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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/orpsocv2/rtl/verilog
    from Rev 456 to Rev 462
    ↔ Reverse comparison
  •

Rev 456 → Rev 462

/include/or1200_defines.v
389,9 → 389,9
//
// Implement HW Single Precision FPU
//
//`define OR1200_FPU_IMPLEMENTED
//
`define OR1200_FPU_IMPLEMENTED
 
 
//
// Clock ratio RISC clock versus WB clock
//
/or1200/or1200_rfram_generic.v
151,6 → 151,48
endfunction // get_gpr
 
// Function to access GPRs (for use by Verilator). No need to hide this one
// from the simulator, since it has an input (as required by IEEE 1364-2001).
function [31:0] set_gpr;
// verilator public
input [aw-1:0] gpr_no;
input [dw-1:0] value;
 
mem[gpr_no*32 + 31] = value[31];
mem[gpr_no*32 + 30] = value[30];
mem[gpr_no*32 + 29] = value[29];
mem[gpr_no*32 + 28] = value[28];
mem[gpr_no*32 + 27] = value[27];
mem[gpr_no*32 + 26] = value[26];
mem[gpr_no*32 + 25] = value[25];
mem[gpr_no*32 + 24] = value[24];
mem[gpr_no*32 + 23] = value[23];
mem[gpr_no*32 + 22] = value[22];
mem[gpr_no*32 + 21] = value[21];
mem[gpr_no*32 + 20] = value[20];
mem[gpr_no*32 + 19] = value[19];
mem[gpr_no*32 + 18] = value[18];
mem[gpr_no*32 + 17] = value[17];
mem[gpr_no*32 + 16] = value[16];
mem[gpr_no*32 + 15] = value[15];
mem[gpr_no*32 + 14] = value[14];
mem[gpr_no*32 + 13] = value[13];
mem[gpr_no*32 + 12] = value[12];
mem[gpr_no*32 + 11] = value[11];
mem[gpr_no*32 + 10] = value[10];
mem[gpr_no*32 + 9] = value[ 9];
mem[gpr_no*32 + 8] = value[ 8];
mem[gpr_no*32 + 7] = value[ 7];
mem[gpr_no*32 + 6] = value[ 6];
mem[gpr_no*32 + 5] = value[ 5];
mem[gpr_no*32 + 4] = value[ 4];
mem[gpr_no*32 + 3] = value[ 3];
mem[gpr_no*32 + 2] = value[ 2];
mem[gpr_no*32 + 1] = value[ 1];
mem[gpr_no*32 + 0] = value[ 0];
endfunction // set_gpr
 
//
// Write port
//
/or1200/or1200_dpram.v
107,6 → 107,15
get_gpr = mem[gpr_no];
endfunction // get_gpr
 
function [31:0] set_gpr;
// verilator public
input [aw-1:0] gpr_no;
input [dw-1:0] value;
 
mem[gpr_no] = value;
endfunction // get_gpr
//
// Data output drivers
/ram_wb/ram_wb_b3.v
35,7 → 35,7
parameter mem_words = (mem_size_bytes/bytes_per_dw);
 
// synthesis attribute ram_style of mem is block
reg [dw-1:0] mem [ 0 : mem_words-1 ] /* synthesis ram_style = no_rw_check */;
reg [dw-1:0] mem [ 0 : mem_words-1 ] /* verilator public */ /* synthesis ram_style = no_rw_check */;
 
// Register to address internal memory array
reg [(mem_adr_width-adr_width_for_num_word_bytes)-1:0] adr;
114,13 → 114,29
adr <= burst_adr_counter;
else if (wb_cyc_i & wb_stb_i)
adr <= wb_adr_i[mem_adr_width-1:2];
 
/* Memory initialisation.
If not Verilator model, always do load, otherwise only load when called
from SystemC testbench.
*/
 
parameter memory_file = "sram.vmem";
 
`ifdef verilator
task do_readmemh;
// verilator public
$readmemh(memory_file, mem);
endtask // do_readmemh
`else
initial
begin
$readmemh(memory_file, mem);
end
`endif // !`ifdef verilator
 
assign wb_rty_o = 0;
 
199,56 → 215,38
// OR in other errors here...
assign wb_err_o = wb_ack_o & (burst_access_wrong_wb_adr | addr_err);
 
`ifdef verilator
task do_readmemh;
// verilator public
$readmemh(memory_file, mem);
endtask // do_readmemh
`else
initial
begin
$readmemh(memory_file, mem);
end
`endif // !`ifdef verilator
 
//
// Access functions
//
// Function to access RAM (for use by Verilator).
function [31:0] get_mem;
function [31:0] get_mem32;
// verilator public
input [aw-1:0] addr;
get_mem = mem[addr[mem_adr_width-1:adr_width_for_num_word_bytes]];
endfunction // get_mem
get_mem32 = mem[addr];
endfunction // get_mem32
 
// Function to access RAM (for use by Verilator).
function [7:0] get_byte;
function [7:0] get_mem8;
// verilator public
input [aw-1:0] addr;
reg [31:0] temp_word;
reg [31:0] temp_word;
begin
temp_word = mem[addr[mem_adr_width-1:adr_width_for_num_word_bytes]];
temp_word = mem[{addr[aw-1:2],2'd0}];
// Big endian mapping.
get_byte = (addr[1:0]==2'b00) ? temp_word[31:24] :
get_mem8 = (addr[1:0]==2'b00) ? temp_word[31:24] :
(addr[1:0]==2'b01) ? temp_word[23:16] :
(addr[1:0]==2'b10) ? temp_word[15:8] : temp_word[7:0];
end
endfunction // get_mem
endfunction // get_mem8
 
// Function to write RAM (for use by Verilator).
function set_mem;
function set_mem32;
// verilator public
input [aw-1:0] addr;
input [dw-1:0] data;
mem[addr[mem_adr_width-1:adr_width_for_num_word_bytes]] = data;
endfunction // set_mem
mem[addr] = data;
endfunction // set_mem32
endmodule // ram_wb_b3
 

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