OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/orpsocv2/rtl/verilog
    from Rev 476 to Rev 477
    ↔ Reverse comparison
  •

Rev 476 → Rev 477

/include/or1200_defines.v
161,12 → 161,14
// (consider available FPGA memory resources)
//
//`define OR1200_IC_1W_512B
//`define OR1200_IC_1W_4KB
`define OR1200_IC_1W_4KB
//`define OR1200_IC_1W_8KB
`define OR1200_IC_1W_16KB
//`define OR1200_DC_1W_4KB
//`define OR1200_IC_1W_16KB
//`define OR1200_IC_1W_32KB
`define OR1200_DC_1W_4KB
//`define OR1200_DC_1W_8KB
`define OR1200_DC_1W_16KB
//`define OR1200_DC_1W_16KB
//`define OR1200_DC_1W_32KB
 
`endif
 
1221,19 → 1223,23
// Insn cache (IC)
//
 
// 3 for 8 bytes, 4 for 16 bytes etc
`define OR1200_ICLS 4
// 4 for 16 byte line, 5 for 32 byte lines.
`ifdef OR1200_IC_1W_32KB
`define OR1200_ICLS 5
`else
`define OR1200_ICLS 4
`endif
 
//
// IC configurations
//
`ifdef OR1200_IC_1W_512B
`define OR1200_ICSIZE 9 // 512
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 7
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 8
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 9
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 5
`define OR1200_ICTAG_W 24
`define OR1200_ICSIZE 9 // 512
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 7
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 8
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 9
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 5
`define OR1200_ICTAG_W 24
`endif
`ifdef OR1200_IC_1W_4KB
`define OR1200_ICSIZE 12 // 4096
1259,6 → 1265,14
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 10
`define OR1200_ICTAG_W 19
`endif
`ifdef OR1200_IC_1W_32KB
`define OR1200_ICSIZE 15 // 32768
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 13
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 14
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 14
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 10
`define OR1200_ICTAG_W 18
`endif
 
 
/////////////////////////////////////////////////
1266,8 → 1280,12
// Data cache (DC)
//
 
// 3 for 8 bytes, 4 for 16 bytes etc
`define OR1200_DCLS 4
// 4 for 16 bytes, 5 for 32 bytes
`ifdef OR1200_DC_1W_32KB
`define OR1200_DCLS 5
`else
`define OR1200_DCLS 4
`endif
 
// Define to enable default behavior of cache as write through
// Turning this off enabled write back statergy
1315,6 → 1333,14
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 10
`define OR1200_DCTAG_W 19
`endif
`ifdef OR1200_DC_1W_32KB
`define OR1200_DCSIZE 15 // 32768
`define OR1200_DCINDX `OR1200_DCSIZE-2 // 13
`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 14
`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 15
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 10
`define OR1200_DCTAG_W 18
`endif
 
 
/////////////////////////////////////////////////
/or1200/or1200_dc_fsm.v
125,7 → 125,7
//
reg [31:0] addr_r;
reg [2:0] state;
reg [2:0] cnt;
reg [`OR1200_DCLS-1:0] cnt;
reg hitmiss_eval;
reg store;
reg load;
150,7 → 150,7
wire tagram_dirty_bit_set;
wire writethrough;
wire cache_inhibit_with_eval;
wire [1:0] next_addr_word;
wire [(`OR1200_DCLS-1)-2:0] next_addr_word;
 
//
// Cache inhibit
268,8 → 268,9
// the line to memory. (1 selects DCRAM)
assign biu_do_sel = (state == `OR1200_DCFSM_LOOP2) & store;
 
// 2-bit wire for calculating next word of burst write
assign next_addr_word = addr_r[3:2] + 1;
// 3-bit wire for calculating next word of burst write, depending on
// line size of data cache.
assign next_addr_word = addr_r[`OR1200_DCLS-1:2] + 1;
// Address to cache RAM (tag address also derived from this)
assign dc_addr =
285,7 → 286,7
// to increment, but it's needed immediately for burst)
// otherwise, output our registered address.
(state==`OR1200_DCFSM_LOOP2 & biudata_valid & store ) ?
{addr_r[31:4], next_addr_word, 2'b00} : addr_r;
{addr_r[31:`OR1200_DCLS], next_addr_word, 2'b00} : addr_r;
`ifdef OR1200_DC_WRITETHROUGH
`ifdef OR1200_DC_NOSTACKWRITETHROUGH
342,9 → 343,9
// tell from value of cnt), and we're loading a line to read from it (not
// loading to write to it, in the case of a write without writethrough.)
assign load_miss_ack = ((state== `OR1200_DCFSM_LOOP2) & load &
(cnt==`OR1200_DCLS-1) & biudata_valid &
(cnt==((1 << `OR1200_DCLS) - 4)) & biudata_valid &
!(dcqmem_we_i & !writethrough));
 
assign load_inhibit_ack = (state == `OR1200_DCFSM_CLOADSTORE) &
load & cache_inhibit & biudata_valid;
362,11 → 363,11
always @(posedge clk or `OR1200_RST_EVENT rst) begin
if (rst == `OR1200_RST_VALUE) begin
state <= `OR1200_DCFSM_IDLE;
addr_r <= 32'b0;
addr_r <= 32'd0;
hitmiss_eval <= 1'b0;
store <= 1'b0;
load <= 1'b0;
cnt <= 3'd0;
cnt <= `OR1200_DCLS'd0;
cache_miss <= 1'b0;
cache_dirty_needs_writeback <= 1'b0;
cache_inhibit <= 1'b0;
430,7 → 431,7
end // else: !if(dirty)
state <= `OR1200_DCFSM_LOOP2;
// Set the counter for the burst accesses
cnt <= `OR1200_DCLS-1;
cnt <= ((1 << `OR1200_DCLS) - 4);
end
else if (// Strobe goes low
!dcqmem_cycstb_i |
453,11 → 454,11
state <= `OR1200_DCFSM_IDLE;
load <= 1'b0;
store <= 1'b0;
cnt <= 3'd0;
cnt <= `OR1200_DCLS'd0;
end
if (biudata_valid & (|cnt)) begin
cnt <= cnt - 3'd1;
addr_r[3:2] <= addr_r[3:2] + 1'b1;
cnt <= cnt - 4;
addr_r[`OR1200_DCLS-1:2] <= addr_r[`OR1200_DCLS-1:2] + 1;
end
else if (biudata_valid & !(|cnt)) begin
state <= `OR1200_DCFSM_LOOP3;
478,7 → 479,7
// Just did store of the dirty line so now load new one
load <= 1'b1;
// Set the counter for the burst accesses
cnt <= `OR1200_DCLS-1;
cnt <= ((1 << `OR1200_DCLS) - 4);
// Address of line to be loaded
addr_r <= lsu_addr;
cache_dirty_needs_writeback <= 1'b0;
526,7 → 527,7
`endif
state <= `OR1200_DCFSM_LOOP2;
// Set the counter for the burst accesses
cnt <= `OR1200_DCLS-1;
cnt <= ((1 << `OR1200_DCLS) - 4);
end
else if (cache_spr_block_flush & !dirty)
begin
/or1200/or1200_ic_tag.v
115,34 → 115,11
//
// Instantiation of TAG RAM block
//
`ifdef OR1200_IC_1W_512B
or1200_spram #
(
.aw(5),
.dw(24)
.aw(`OR1200_ICTAG),
.dw(`OR1200_ICTAG_W)
)
`endif
`ifdef OR1200_IC_1W_4KB
or1200_spram #
(
.aw(8),
.dw(21)
)
`endif
`ifdef OR1200_IC_1W_8KB
or1200_spram #
(
.aw(9),
.dw(20)
)
`endif
`ifdef OR1200_IC_1W_16KB
or1200_spram #
(
.aw(10),
.dw(19)
)
`endif
ic_tag0
(
`ifdef OR1200_BIST
/or1200/or1200_ic_ram.v
105,34 → 105,11
//
// Instantiation of IC RAM block
//
`ifdef OR1200_IC_1W_512B
or1200_spram #
(
.aw(9),
.aw(`OR1200_ICINDX),
.dw(32)
)
`endif
`ifdef OR1200_IC_1W_4KB
or1200_spram #
(
.aw(10),
.dw(32)
)
`endif
`ifdef OR1200_IC_1W_8KB
or1200_spram #
(
.aw(11),
.dw(32)
)
`endif
`ifdef OR1200_IC_1W_16KB
or1200_spram #
(
.aw(12),
.dw(32)
)
`endif
ic_ram0
(
`ifdef OR1200_BIST
/or1200/or1200_wb_biu.v
79,7 → 79,10
 
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
 
parameter bl = 4; /* Can currently be either 4 or 8 - the two optional line
sizes for the OR1200. */
//
// RISC clock, reset and clock control
//
153,7 → 156,7
assign retry_cnt = 1'b0;
`endif
`ifdef OR1200_WB_B3
reg [1:0] burst_len; // burst counter
reg [3:0] burst_len; // burst counter
`endif
 
reg biu_stb_reg; // WB strobe
197,14 → 200,14
//
always @(posedge wb_clk_i or `OR1200_RST_EVENT wb_rst_i) begin
if (wb_rst_i == `OR1200_RST_VALUE) begin
burst_len <= 2'h0;
burst_len <= 0;
end
else begin
// burst counter
if (wb_fsm_state_cur == wb_fsm_idle)
burst_len <= 2'h2;
burst_len <= bl[3:0] - 2;
else if (wb_stb_o & wb_ack)
burst_len <= burst_len - 1'b1;
burst_len <= burst_len - 1;
end
end
 
233,10 → 236,10
wb_stb_nxt = !wb_stb_o | !wb_err_i & !wb_rty_i & !wb_ack |
!wb_err_i & !wb_rty_i & wb_cti_o == 3'b010 /*& !wb_we_o -- Removed to add burst write, JPB*/;
wb_cti_nxt[2] = wb_stb_o & wb_ack & burst_len == 'h0 | wb_cti_o[2];
wb_cti_nxt[1] = 1'b1 ;
wb_cti_nxt[0] = wb_stb_o & wb_ack & burst_len == 'h0 | wb_cti_o[0];
 
//if ((!biu_cyc_i | !biu_stb | !biu_cab_i) & wb_cti_o == 3'b010 |
// biu_sel_i != wb_sel_o | biu_we_i != wb_we_o)
282,7 → 285,7
wb_cyc_o <= 1'b0;
wb_stb_o <= 1'b0;
wb_cti_o <= 3'b111;
wb_bte_o <= 2'b01; // 4-beat wrap burst = constant
wb_bte_o <= (bl==8) ? 2'b10 : (bl==4) ? 2'b01 : 2'b00;
`ifdef OR1200_WB_CAB
wb_cab_o <= 1'b0;
`endif
301,7 → 304,7
else
wb_stb_o <= wb_stb_nxt;
wb_cti_o <= wb_cti_nxt;
wb_bte_o <= 2'b01; // 4-beat wrap burst = constant
wb_bte_o <= (bl==8) ? 2'b10 : (bl==4) ? 2'b01 : 2'b00;
`ifdef OR1200_WB_CAB
wb_cab_o <= biu_cab_i;
`endif
315,7 → 318,12
wb_adr_o <= biu_adr_i;
end
else if (wb_stb_o & wb_ack) begin
wb_adr_o[3:2] <= wb_adr_o[3:2] + 1'b1;
if (bl==4) begin
wb_adr_o[3:2] <= wb_adr_o[3:2] + 1;
end
if (bl==8) begin
wb_adr_o[4:2] <= wb_adr_o[4:2] + 1;
end
end
`ifdef OR1200_NO_DC
// dat - write data changed after avery subsequent write access
/or1200/or1200_dc_tag.v
108,27 → 108,11
// Instantiation of TAG RAM block
//
// Data widths are tag width plus one for valid
`ifdef OR1200_DC_1W_4KB
or1200_spram #
(
.aw(8),
.aw(`OR1200_DCTAG),
.dw(`OR1200_DCTAG_W + 1)
)
`endif
`ifdef OR1200_DC_1W_8KB
or1200_spram #
(
.aw(9),
.dw(`OR1200_DCTAG_W + 1)
)
`endif
`ifdef OR1200_DC_1W_16KB
or1200_spram #
(
.aw(10),
.dw(`OR1200_DCTAG_W + 1)
)
`endif
dc_tag0
(
`ifdef OR1200_BIST
/or1200/or1200_dc_ram.v
104,27 → 104,11
//
// Instantiation of RAM block
//
`ifdef OR1200_DC_1W_4KB
or1200_spram_32_bw #
(
.aw(10),
.dw(32)
.aw(`OR1200_DCINDX),
.dw(dw)
)
`endif
`ifdef OR1200_DC_1W_8KB
or1200_spram_32_bw #
(
.aw(11),
.dw(32)
)
`endif
`ifdef OR1200_DC_1W_16KB
or1200_spram_32_bw #
(
.aw(12),
.dw(32)
)
`endif
dc_ram
(
`ifdef OR1200_BIST
/or1200/or1200_dc_top.v
284,7 → 284,6
// Select between data generated by DCRAM or passed by BIU
//
assign dcqmem_dat_o = dcfsm_first_miss_ack | !dc_en ? dcsb_dat_i : from_dcram;
//assign dcqmem_dat_o = !dc_en ? dcsb_dat_i : from_dcram;
 
//
// Tag comparison
/or1200/or1200_ic_fsm.v
102,7 → 102,7
//
reg [31:0] saved_addr_r;
reg [1:0] state;
reg [2:0] cnt;
reg [`OR1200_ICLS-1:0] cnt;
reg hitmiss_eval;
reg load;
reg cache_inhibit;
147,7 → 147,7
saved_addr_r <= 32'b0;
hitmiss_eval <= 1'b0;
load <= 1'b0;
cnt <= 3'b000;
cnt <= `OR1200_ICLS'd0;
cache_inhibit <= 1'b0;
last_eval_miss <= 0; // JPB
174,8 → 174,7
cache_inhibit <= 1'b1;
if (hitmiss_eval)
saved_addr_r[31:13] <= start_addr[31:13];
saved_addr_r[31:`OR1200_ICTAGL] <= start_addr[31:`OR1200_ICTAGL];
if ((!ic_en) ||
// fetch aborted (usually caused by IMMU)
(hitmiss_eval & !icqmem_cycstb_i) ||
190,9 → 189,10
// fetch missed, wait for first fetch and continue filling line
else if (tagcomp_miss & biudata_valid) begin
state <= `OR1200_ICFSM_LREFILL3;
saved_addr_r[3:2] <= saved_addr_r[3:2] + 1'd1;
saved_addr_r[`OR1200_ICLS-1:2]
<= saved_addr_r[`OR1200_ICLS-1:2] + 1;
hitmiss_eval <= 1'b0;
cnt <= `OR1200_ICLS-2;
cnt <= ((1 << `OR1200_ICLS) - (2 * 4));
cache_inhibit <= 1'b0;
end
// fetch aborted (usually caused by exception)
227,8 → 227,9
end
// refill ack, more fetchs to come
else if (biudata_valid && (|cnt)) begin
cnt <= cnt - 3'd1;
saved_addr_r[3:2] <= saved_addr_r[3:2] + 1'd1;
cnt <= cnt - `OR1200_ICLS'd4;
saved_addr_r[`OR1200_ICLS-1:2]
<= saved_addr_r[`OR1200_ICLS-1:2] + 1;
end
// last fetch of line refill
else if (biudata_valid) begin
/or1200/or1200_top.v
432,7 → 432,9
//
// Instantiation of Instruction WISHBONE BIU
//
or1200_wb_biu iwb_biu(
or1200_wb_biu
#(.bl((1 << (`OR1200_ICLS-2))))
iwb_biu(
// RISC clk, rst and clock control
.clk(clk_i),
.rst(rst_i),
476,7 → 478,9
//
// Instantiation of Data WISHBONE BIU
//
or1200_wb_biu dwb_biu(
or1200_wb_biu
#(.bl((1 << (`OR1200_DCLS-2))))
dwb_biu(
// RISC clk, rst and clock control
.clk(clk_i),
.rst(rst_i),

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.