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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/orpsocv2/rtl/verilog
    from Rev 479 to Rev 482
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  •

Rev 479 → Rev 482

/include/or1200_defines.v
1764,10 → 1764,18
 
///////////////////////////////////////////////////////////////////////////////
// Boot Address Selection //
// This only changes where the initial reset occurs. EPH setting is still //
// used to determine where vectors are located. //
// //
// Allows a definable boot address, potentially different to the usual reset //
// vector to allow for power-on code to be run, if desired. //
// //
// OR1200_BOOT_ADR should be the 32-bit address of the boot location //
// OR1200_BOOT_PCREG_DEFAULT should be ((OR1200_BOOT_ADR-4)>>2) //
// //
// For default reset behavior uncomment the settings under the "Boot 0x100" //
// comment below. //
// //
///////////////////////////////////////////////////////////////////////////////
// Boot from 0xf0000100
// Boot from 0xf0000100
//`define OR1200_BOOT_PCREG_DEFAULT 30'h3c00003f
//`define OR1200_BOOT_ADR 32'hf0000100
// Boot from 0x100
/or1200/or1200_ic_tag.v
135,6 → 135,9
.addr(addr),
.di(datain),
.doq({tag, tag_v})
`ifdef OR1200_RAM_PARITY
, .p_err()
`endif
);
`endif
 
/or1200/or1200_ic_ram.v
125,6 → 125,9
.addr(addr),
.di(datain),
.doq(dataout)
`ifdef OR1200_RAM_PARITY
, .p_err()
`endif
);
`endif
 
/or1200/or1200_parity_chk.v
0,0 → 1,68
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200 Parity Checking ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://opencores.org/project,or1k ////
//// ////
//// Description ////
//// Parity bit checking, combinatorial. Presumes single bit of ////
//// parity supplied to check against. Signals error on parity ////
//// mismatch. ////
//// ////
//// To Do: ////
//// ////
//// Author(s): ////
//// - Julius Baxter, julius@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2011 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_parity_chk
(
d_i,
p_i,
err_o
);
 
// Width of data we check parity for.
parameter dw = 8;
input [dw-1:0] d_i; // Data word in
input p_i; // Parity bit in
output err_o; // Error indicator out
assign err_o = ((^d_i[dw-1:0]) != p_i);
 
endmodule // or1200_parity_chk
 
/or1200/or1200_dmmu_tlb.v
243,6 → 243,9
.addr(tlb_index),
.di(tlb_mr_ram_in),
.doq(tlb_mr_ram_out)
`ifdef OR1200_RAM_PARITY
, .p_err()
`endif
);
//
268,6 → 271,9
.addr(tlb_index),
.di(tlb_tr_ram_in),
.doq(tlb_tr_ram_out)
`ifdef OR1200_RAM_PARITY
, .p_err()
`endif
);
endmodule // or1200_dmmu_tlb
/or1200/or1200_rf.v
299,6 → 299,10
.we_b(rf_we),
.addr_b(rf_addrw),
.di_b(rf_dataw)
`ifdef OR1200_RAM_PARITY
, .p_err()
`endif
);
 
//
323,6 → 327,10
.we_b(rf_we),
.addr_b(rf_addrw),
.di_b(rf_dataw)
`ifdef OR1200_RAM_PARITY
, .p_err()
`endif
 
);
`else
/or1200/or1200_dc_tag.v
127,6 → 127,9
.addr(addr),
.di(datain),
.doq({tag, tag_v, dirty})
`ifdef OR1200_RAM_PARITY
, .p_err()
`endif
);
`endif
 
/or1200/or1200_spram.v
65,6 → 65,9
`endif
// Generic synchronous single-port RAM interface
clk, ce, we, addr, di, doq
`ifdef OR1200_RAM_PARITY
, p_err
`endif
);
//
79,7 → 82,7
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
output mbist_so_o;
`endif
//
88,10 → 91,12
input clk; // Clock
input ce; // Chip enable input
input we; // Write enable input
//input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
`ifdef OR1200_RAM_PARITY
output p_err; // parity error indicator
`endif
//
// Internal wires and registers
104,18 → 109,68
//
// Generic RAM's registers and wires
//
`ifdef OR1200_GENERIC
`ifdef OR1200_RAM_PARITY
reg [(dw+(dw/8))-1:0] mem [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
`else
reg [dw-1:0] mem [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
`endif
reg [aw-1:0] addr_reg; // RAM address register
 
`ifdef OR1200_RAM_PARITY
wire [(dw+(dw/8))-1:0] doq_wire;
wire [(dw/8)-1:0] di_p;
wire [(dw/8)-1:0] do_p;
wire [(dw/8)-1:0] parity_err;
`else
reg [dw-1:0] mem [(1<<aw)-1:0];
wire [dw-1:0] doq_wire;
`endif
reg [aw-1:0] addr_reg; // RAM address register
 
`ifdef OR1200_RAM_PARITY
genvar i;
generate
for (i=0;i<(dw/8);i=i+1) begin: paritygen
or1200_parity_gen pgen(.d_i(di[(i*8)+7:(i*8)]), .p_o(di_p[i]));
or1200_parity_chk pchk(.d_i(doq_wire[(i*8)+7:(i*8)]),
.p_i(do_p[i]), .err_o(parity_err[i]));
end
endgenerate
 
// Extract parity bits of data out
assign do_p = doq_wire[(dw+(dw/8))-1:dw];
// Indicate error
assign p_err = (|parity_err);
 
// Inject a parity error. Can specify GPR number to affect,
// and which parity or data bit to switch.
task gen_parity_err;
input [aw-1:0] gpr_no;
input [31:0] parity_bit_no;
input [31:0] data_bit_no;
reg [(dw+(dw/8))-1:0] do_temp;
begin
do_temp = mem[gpr_no];
// Switch parity bit
if (parity_bit_no > 0 && parity_bit_no <= (dw/8))
do_temp[dw+(parity_bit_no-1)] = ~do_temp[dw+(parity_bit_no-1)];
// Switch data bit
if (data_bit_no > 0 && data_bit_no <= dw)
do_temp[data_bit_no-1] = ~do_temp[data_bit_no-1];
// Write word back
mem[gpr_no] = do_temp;
end
endtask // gen_parity_err
`endif
 
//
// Data output drivers
//
//assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
assign doq = mem[addr_reg];
assign doq_wire = mem[addr_reg];
assign doq = doq_wire[dw-1:0];
//
// RAM read address register
129,6 → 184,10
//
always @(posedge clk)
if (we && ce)
`ifdef OR1200_RAM_PARITY
mem[addr] <= {di_p,di};
`else
mem[addr] <= di;
`endif
endmodule // or1200_spram
/or1200/or1200_dc_ram.v
123,6 → 123,9
.addr(addr),
.di(datain),
.doq(dataout)
`ifdef OR1200_RAM_PARITY
, .p_err()
`endif
);
`endif
 
/or1200/or1200_parity_gen.v
0,0 → 1,64
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200 Parity Generator ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://opencores.org/project,or1k ////
//// ////
//// Description ////
//// Parity bit generation, combinatorial ////
//// ////
//// To Do: ////
//// ////
//// Author(s): ////
//// - Julius Baxter, julius@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2011 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_parity_gen
(
d_i,
p_o
);
 
// Width of data we generate parity for.
parameter dw = 8;
input [dw-1:0] d_i;
output p_o;
// Even parity generation
assign p_o = (^d_i[dw-1:0]);
 
endmodule // or1200_parity_gen
/or1200/or1200_immu_tlb.v
47,44 → 47,6
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Minor update:
// Bugs fixed, coding style changed.
//
// Revision 1.9 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.8 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.6.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.6 2002/10/28 16:34:32 mohor
// RAMs wrong connected to the BIST scan chain.
//
// Revision 1.5 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.4 2002/08/14 06:23:50 lampret
// Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run.
//
// Revision 1.3 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.2 2002/01/28 01:16:00 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
//
 
// synopsys translate_off
`include "timescale.v"
283,6 → 245,9
.addr(tlb_index),
.di(tlb_mr_ram_in),
.doq(tlb_mr_ram_out)
`ifdef OR1200_RAM_PARITY
, .p_err()
`endif
);
 
//
308,6 → 273,9
.addr(tlb_index),
.di(tlb_tr_ram_in),
.doq(tlb_tr_ram_out)
`ifdef OR1200_RAM_PARITY
, .p_err()
`endif
);
endmodule
/or1200/or1200_spram_32_bw.v
66,6 → 66,9
`endif
// Generic synchronous single-port RAM interface
clk, ce, we, addr, di, doq
`ifdef OR1200_RAM_PARITY
, p_err
`endif
);
//
74,6 → 77,9
parameter aw = 10;
parameter dw = 32;
parameter bw = 8;
`ifdef OR1200_BIST
//
// RAM BIST
92,6 → 98,9
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
`ifdef OR1200_RAM_PARITY
output p_err; // parity error indicator
`endif
//
// Internal wires and registers
104,24 → 113,92
//
// Generic RAM's registers and wires
//
`ifdef OR1200_GENERIC
reg [7:0] mem0 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
reg [7:0] mem1 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
reg [7:0] mem2 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
reg [7:0] mem3 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
`ifdef OR1200_RAM_PARITY
reg [bw:0] mem0 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
reg [bw:0] mem1 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
reg [bw:0] mem2 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
reg [bw:0] mem3 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
`else
reg [7:0] mem0 [(1<<aw)-1:0];
reg [7:0] mem1 [(1<<aw)-1:0];
reg [7:0] mem2 [(1<<aw)-1:0];
reg [7:0] mem3 [(1<<aw)-1:0];
reg [bw-1:0] mem0 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
reg [bw-1:0] mem1 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
reg [bw-1:0] mem2 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
reg [bw-1:0] mem3 [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
`endif
reg [aw-1:0] addr_reg; // RAM address register
 
`ifdef OR1200_RAM_PARITY
wire [(dw+(dw/8))-1:0] doq_wire;
wire [bw:0] doq0_wire;
wire [bw:0] doq1_wire;
wire [bw:0] doq2_wire;
wire [bw:0] doq3_wire;
wire [(dw/8)-1:0] di_p;
wire [(dw/8)-1:0] do_p;
wire [(dw/8)-1:0] parity_err;
`else
wire [dw-1:0] doq_wire;
`endif
 
`ifdef OR1200_RAM_PARITY
genvar i;
generate
for (i=0;i<(dw/8);i=i+1) begin: paritygen
or1200_parity_gen pgen(.d_i(di[(i*8)+7:(i*8)]), .p_o(di_p[i]));
or1200_parity_chk pchk(.d_i(doq_wire[(i*8)+7:(i*8)]),
.p_i(do_p[i]), .err_o(parity_err[i]));
end
endgenerate
 
// Extract parity bits of data out
assign do_p = doq_wire[(dw+(dw/8))-1:dw];
// Indicate error
assign p_err = (|parity_err);
 
// Inject a parity error. Can specify GPR number to affect,
// and which parity or data bit to switch.
task gen_parity_err;
input [aw-1:0] gpr_no;
input [31:0] parity_bit_no;
input [31:0] data_bit_no;
reg [(dw+(dw/8))-1:0] do_temp;
begin
// TODO
/*
do_temp = mem[gpr_no];
// Switch parity bit
if (parity_bit_no > 0 && parity_bit_no <= (dw/8))
do_temp[dw+(parity_bit_no-1)] = ~do_temp[dw+(parity_bit_no-1)];
// Switch data bit
if (data_bit_no > 0 && data_bit_no <= dw)
do_temp[data_bit_no-1] = ~do_temp[data_bit_no-1];
// Write word back
mem[gpr_no] = do_temp;
*/
end
endtask // gen_parity_err
`endif
//
// Data output drivers
//
assign doq = {mem0[addr_reg], mem1[addr_reg], mem2[addr_reg], mem3[addr_reg]};
`ifdef OR1200_RAM_PARITY
assign doq0_wire = mem0[addr_reg];
assign doq1_wire = mem1[addr_reg];
assign doq2_wire = mem2[addr_reg];
assign doq3_wire = mem3[addr_reg];
assign doq_wire = {// Parity bits
doq0_wire[bw],doq1_wire[bw],doq2_wire[bw],doq3_wire[bw],
// Data bytes
doq0_wire[bw-1:0],doq1_wire[bw-1:0],
doq2_wire[bw-1:0],doq3_wire[bw-1:0]};
`else
assign doq_wire = {mem0[addr_reg], mem1[addr_reg], mem2[addr_reg], mem3[addr_reg]};
`endif
assign doq = doq_wire[dw-1:0];
//
// RAM read address register
//
134,14 → 211,25
//
always @(posedge clk)
if (ce) begin
if (we[3])
mem0[addr] <= di[31:24];
if (we[2])
mem1[addr] <= di[23:16];
if (we[1])
mem2[addr] <= di[15:08];
if (we[0])
mem3[addr] <= di[07:00];
`ifdef OR1200_RAM_PARITY
if (we[3])
mem0[addr] <= {di_p[3],di[(bw*3)+(bw-1):(bw*3)]};
if (we[2])
mem1[addr] <= {di_p[2],di[(bw*2)+(bw-1):(bw*2)]};
if (we[1])
mem2[addr] <= {di_p[1],di[(bw*1)+(bw-1):(bw*1)]};
if (we[0])
mem3[addr] <= {di_p[0],di[(bw*0)+(bw-1):(bw*0)]};
`else
if (we[3])
mem0[addr] <= di[(bw*3)+(bw-1):(bw*3)];
if (we[2])
mem1[addr] <= di[(bw*2)+(bw-1):(bw*2)];
if (we[1])
mem2[addr] <= di[(bw*1)+(bw-1):(bw*1)];
if (we[0])
mem3[addr] <= di[(bw*0)+(bw-1):(bw*0)];
`endif
end
endmodule // or1200_spram
/or1200/or1200_dpram.v
62,6 → 62,9
// Generic synchronous double-port RAM interface
clk_a, ce_a, addr_a, do_a,
clk_b, ce_b, we_b, addr_b, di_b
`ifdef OR1200_RAM_PARITY
, p_err
`endif
);
//
82,6 → 85,9
input we_b; // Write enable input
input [aw-1:0] addr_b; // address bus inputs
input [dw-1:0] di_b; // input data bus
`ifdef OR1200_RAM_PARITY
output p_err; // parity error indicator
`endif
//
// Internal wires and registers
94,9 → 100,21
//
// Generic RAM's registers and wires
//
`ifdef OR1200_RAM_PARITY
reg [(dw+(dw/8))-1:0] mem [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/; // RAM content
`else
reg [dw-1:0] mem [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/; // RAM content
`endif
reg [aw-1:0] addr_a_reg; // RAM address registered
 
`ifdef OR1200_RAM_PARITY
wire [(dw+(dw/8))-1:0] do_a_wire;
wire [(dw/8)-1:0] di_p;
wire [(dw/8)-1:0] do_p;
wire [(dw/8)-1:0] parity_err;
`else
wire [dw-1:0] do_a_wire;
`endif
 
// Function to access GPRs (for use by Verilator). No need to hide this one
// from the simulator, since it has an input (as required by IEEE 1364-2001).
103,27 → 121,78
function [31:0] get_gpr;
// verilator public
input [aw-1:0] gpr_no;
 
get_gpr = mem[gpr_no];
reg [(dw+(dw/8))-1:0] gpr_temp;
begin
`ifdef OR1200_RAM_PARITY
gpr_temp = mem[gpr_no];
get_gpr = gpr_temp[31:0];
`else
get_gpr = mem[gpr_no];
`endif
end
endfunction // get_gpr
 
function [31:0] set_gpr;
task set_gpr;
// verilator public
input [aw-1:0] gpr_no;
input [dw-1:0] value;
 
mem[gpr_no] = value;
endfunction // get_gpr
mem[gpr_no] =
`ifdef OR1200_RAM_PARITY
{(^value[(8*3)+7:(8*3)]),(^value[(8*2)+7:(8*2)]),
(^value[(8*1)+7:(8*1)]),(^value[(8*0)+7:(8*0)]),
value}
`else
value
`endif
;
endtask // get_gpr
 
`ifdef OR1200_RAM_PARITY
genvar i;
generate
for (i=0;i<(dw/8);i=i+1) begin: paritygen
or1200_parity_gen pgen(.d_i(di_b[(i*8)+7:(i*8)]), .p_o(di_p[i]));
or1200_parity_chk pchk(.d_i(do_a_wire[(i*8)+7:(i*8)]),
.p_i(do_p[i]), .err_o(parity_err[i]));
end
endgenerate
 
// Extract parity bits of data out
assign do_p = do_a_wire[(dw+(dw/8))-1:dw];
// Indicate error
assign p_err = (|parity_err);
 
// Inject a parity error. Can specify GPR number to affect,
// and which parity or data bit to switch.
task gen_parity_err;
input [aw-1:0] gpr_no;
input [31:0] parity_bit_no;
input [31:0] data_bit_no;
reg [(dw+(dw/8))-1:0] do_temp;
begin
do_temp = mem[gpr_no];
// Switch parity bit
if (parity_bit_no > 0)
do_temp[dw+(parity_bit_no-1)] = ~do_temp[dw+(parity_bit_no-1)];
// Switch data bit
if (data_bit_no > 0 && data_bit_no <= dw)
do_temp[data_bit_no-1] = ~do_temp[data_bit_no-1];
// Write word back
mem[gpr_no] = do_temp;
end
endtask // gen_parity_err
`endif
 
//
// Data output drivers
//
//assign do_a = (oe_a) ? mem[addr_a_reg] : {dw{1'b0}};
assign do_a = mem[addr_a_reg];
assign do_a_wire = mem[addr_a_reg];
assign do_a = do_a_wire[dw-1:0];
//
// RAM read
//
136,6 → 205,10
//
always @(posedge clk_b)
if (ce_b & we_b)
`ifdef OR1200_RAM_PARITY
mem[addr_b] <= {di_p,di_b};
`else
mem[addr_b] <= di_b;
`endif
endmodule // or1200_dpram
/orpsoc_top/orpsoc_top.v
668,7 → 668,7
// ROM
//
////////////////////////////////////////////////////////////////////////
`ifdef BOOTROM
rom rom0
(
.wb_dat_o (wbs_i_rom0_dat_o),
682,6 → 682,10
.wb_rst (wb_rst));
 
defparam rom0.addr_width = wbs_i_rom0_addr_width;
`else // !`ifdef BOOTROM
assign wbs_i_rom0_dat_o = 0;
assign wbs_i_rom0_ack_o = 0;
`endif // !`ifdef BOOTROM
 
assign wbs_i_rom0_err_o = 0;
assign wbs_i_rom0_rty_o = 0;
/ethmac/eth_wishbone.v
1257,7 → 1257,7
if(Reset)
TxStartFrm_wb <= 1'b0;
else
if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0))
if(TxBDReady & ~StartOccured & (TxBufferAlmostFull | TxBufferFull| TxLengthEq0))
TxStartFrm_wb <= 1'b1;
else
if(TxStartFrm_syncb2)
/ethmac/eth_fifo.v
113,11 → 113,7
else if (write)
waddr <= waddr + 1;
 
reg read_reg;
always @(posedge clk)
read_reg <= read;
 
always @(posedge clk)
if (reset)
raddr <= 0;
else if (clear)
153,7 → 149,8
assign empty = ~(|cnt);
assign almost_empty = cnt==1;
assign full = {{32-CNT_WIDTH{1'b0}},cnt} == (DEPTH-1);
assign almost_full = &cnt[CNT_WIDTH-1:0];
//assign almost_full = &cnt[CNT_WIDTH-1:0];
assign almost_full = {{32-CNT_WIDTH{1'b0}},cnt} == (DEPTH-2);
 
`else // !`ifdef ETH_FIFO_GENERIC

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