URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
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- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2/rtl/verilog
- from Rev 49 to Rev 51
- ↔ Reverse comparison
Rev 49 → Rev 51
/eth_defines.v
317,8 → 317,11
`define ETH_REGISTERED_OUTPUTS |
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// Settings for TX FIFO |
`define ETH_TX_FIFO_CNT_WIDTH 5 |
`define ETH_TX_FIFO_DEPTH 16 |
//`define ETH_TX_FIFO_CNT_WIDTH 5 |
//`define ETH_TX_FIFO_DEPTH 16 |
// Settings for TX FIFO buffer for a while ethernet packet (1500 bytes) |
`define ETH_TX_FIFO_CNT_WIDTH 9 |
`define ETH_TX_FIFO_DEPTH 375 |
`define ETH_TX_FIFO_DATA_WIDTH 32 |
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// Settings for RX FIFO |
/components/or1200r2/or1200_except.v
225,9 → 225,9
// |
// Internal regs and wires |
// |
reg [`OR1200_EXCEPT_WIDTH-1:0] except_type; |
reg [`OR1200_EXCEPT_WIDTH-1:0] except_type /* verilator public */; |
reg [31:0] id_pc /* verilator public */; |
reg [31:0] ex_pc; |
reg [31:0] ex_pc /* verilator public */; |
reg [31:0] wb_pc /* verilator public */; |
reg [31:0] epcr; |
reg [31:0] eear; |
303,10 → 303,6
get_wb_pc = wb_pc; |
endfunction // get_wb_pc |
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`endif |
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`ifdef verilator |
// Function to access id_pc (for Verilator). Have to hide this from |
// simulator, since functions with no inputs are not allowed in IEEE |
// 1364-2001. |
315,6 → 311,21
get_id_pc = id_pc; |
endfunction // get_id_pc |
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// Function to access ex_pc (for Verilator). Have to hide this from |
// simulator, since functions with no inputs are not allowed in IEEE |
// 1364-2001. |
function [31:0] get_ex_pc; |
// verilator public |
get_ex_pc = ex_pc; |
endfunction // get_ex_pc |
// Function to access except_type[3:0] (for Verilator). Have to hide this from |
// simulator, since functions with no inputs are not allowed in IEEE |
// 1364-2001. |
function [3:0] get_except_type; |
// verilator public |
get_except_type = except_type; |
endfunction // get_except_type |
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`endif |
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// |
/components/or1200r2/or1200_ctrl.v
145,11 → 145,11
input clk; |
input rst; |
input id_freeze; |
input ex_freeze; |
input ex_freeze /* verilator public */; |
input wb_freeze /* verilator public */; |
input flushpipe; |
input [31:0] if_insn; |
output [31:0] ex_insn; |
output [31:0] ex_insn/* verilator public */; |
output [`OR1200_BRANCHOP_WIDTH-1:0] pre_branch_op; |
output [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; |
input branch_taken; |
202,7 → 202,7
reg [`OR1200_SHROTOP_WIDTH-1:0] shrot_op; |
reg [31:0] id_insn /* verilator public */; |
reg [31:0] ex_insn; |
reg [31:0] wb_insn; |
reg [31:0] wb_insn /* verilator public */; |
reg [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw; |
reg [`OR1200_REGFILE_ADDR_WIDTH-1:0] wb_rfaddrw; |
reg [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op; |
277,9 → 277,7
// verilator public |
get_wb_insn = wb_insn; |
endfunction // get_wb_insn |
`endif |
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`ifdef verilator |
// Function to access id_insn (for Verilator). Have to hide this from |
// simulator, since functions with no inputs are not allowed in IEEE |
// 1364-2001. |
287,6 → 285,15
// verilator public |
get_id_insn = id_insn; |
endfunction // get_id_insn |
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// Function to access ex_insn (for Verilator). Have to hide this from |
// simulator, since functions with no inputs are not allowed in IEEE |
// 1364-2001. |
function [31:0] get_ex_insn; |
// verilator public |
get_ex_insn = ex_insn; |
endfunction // get_ex_insn |
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`endif |
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/components/ram_wb/ram_wb_sc_sw.v
10,7 → 10,7
output reg [dat_width-1:0] dat_o; |
input clk; |
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reg [dat_width-1:0] ram [0:mem_size - 1] /* synthesis ram_style = no_rw_check */; |
reg [dat_width-1:0] ram [0:mem_size - 1] /* verilator public */ /* synthesis ram_style = no_rw_check */; |
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// Preload the memory |
// Note! This vmem file must be WORD addressed, not BYTE addressed |
19,12 → 19,40
// @00000008 00000000 00000000 00000000 00000000 |
// @0000000c 00000000 00000000 00000000 00000000 |
// etc.. |
parameter memory_file = "sram.vmem"; |
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parameter memory_file = "sram.vmem"; |
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`ifdef verilator |
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task do_readmemh; |
// verilator public |
$readmemh(memory_file, ram); |
endtask // do_readmemh |
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`else |
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initial |
begin |
$readmemh(memory_file, ram); |
end |
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`endif |
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// Function to access RAM (for use by Verilator). |
function [31:0] get_mem; |
// verilator public |
input [adr_width-1:0] addr; |
get_mem = ram[addr]; |
endfunction // get_mem |
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// Function to write RAM (for use by Verilator). |
function set_mem; |
// verilator public |
input [adr_width-1:0] addr; |
input [dat_width-1:0] data; |
ram[addr] = data; |
endfunction // set_mem |
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always @ (posedge clk) |
begin |
dat_o <= ram[adr_i]; |