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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/orpsocv2/rtl/verilog
    from Rev 505 to Rev 506
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  •

Rev 505 → Rev 506

/include/orpsoc-defines.v
41,6 → 41,7
`define JTAG_DEBUG
`define UART0
`define RAM_WB
`define INTGEN
 
// end of included module defines - keep this comment line here
 
/include/orpsoc-params.v
45,6 → 45,11
parameter uart0_data_width = 8;
parameter uart0_addr_width = 3;
 
// Interrupt generator (intgen) params
parameter intgen_wb_adr = 8'he1;
parameter intgen_data_width = 8;
parameter intgen_addr_width = 1;
 
// ROM
parameter wbs_i_rom0_data_width = 32;
parameter wbs_i_rom0_addr_width = 6;
93,10 → 98,10
// //
///////////////////////////////
parameter bbus_arb_wb_addr_match_width = 8;
parameter bbus_arb_wb_num_slaves = 1; // Update this when changing slaves!
parameter bbus_arb_wb_num_slaves = 2; // Update this when changing slaves!
// Slave addresses
parameter bbus_arb_slave0_adr = uart0_wb_adr;
parameter bbus_arb_slave1_adr = 0 /* UNASSIGNED */;
parameter bbus_arb_slave1_adr = intgen_wb_adr;
parameter bbus_arb_slave2_adr = 0 /* UNASSIGNED */;
parameter bbus_arb_slave3_adr = 0 /* UNASSIGNED */;
parameter bbus_arb_slave4_adr = 0 /* UNASSIGNED */;
/intgen/intgen.v
0,0 → 1,70
/*
*
* Interrupt generation module
*
* A counter is loaded with a value over the Wishbone bus interface, which then
* counts down and issues an interrupt when the value is 1
*
*
* Register 0 - write only - counter value
*
* Register 1 - read/write - interrupt status/clear
*
*/
 
module intgen(
clk_i,
rst_i,
wb_adr_i,
wb_cyc_i,
wb_stb_i,
wb_dat_i,
wb_we_i,
wb_ack_o,
wb_dat_o,
 
irq_o
);
 
 
input clk_i;
input rst_i;
input wb_adr_i;
input wb_cyc_i;
input wb_stb_i;
input [7:0] wb_dat_i;
input wb_we_i;
output wb_ack_o;
output [7:0] wb_dat_o;
output reg irq_o;
reg [7:0] counter;
 
always @(posedge clk_i or posedge rst_i)
if (rst_i)
counter <= 0;
else if (wb_stb_i & wb_cyc_i & wb_we_i & !wb_adr_i)
// Write to adress 0 loads counter
counter <= wb_dat_i;
else if (|counter)
counter <= counter - 1;
always @(posedge clk_i or posedge rst_i)
if (rst_i)
irq_o <= 0;
else if (wb_stb_i & wb_cyc_i & wb_we_i & wb_adr_i)
// Clear on write to reg 1
irq_o <= 0;
else if (counter==8'd1)
irq_o <= 1;
 
assign wb_ack_o = wb_stb_i & wb_cyc_i;
assign wb_dat_o = (wb_adr_i) ? {7'd0,irq_o} : counter;
endmodule // intgen
 
 
/orpsoc_top/orpsoc_top.v
231,7 → 231,22
wire wbs_d_uart0_err_o;
wire wbs_d_uart0_rty_o;
 
// intgen wires
wire [31:0] wbs_d_intgen_adr_i;
wire [7:0] wbs_d_intgen_dat_i;
wire [3:0] wbs_d_intgen_sel_i;
wire wbs_d_intgen_we_i;
wire wbs_d_intgen_cyc_i;
wire wbs_d_intgen_stb_i;
wire [2:0] wbs_d_intgen_cti_i;
wire [1:0] wbs_d_intgen_bte_i;
wire [7:0] wbs_d_intgen_dat_o;
wire wbs_d_intgen_ack_o;
wire wbs_d_intgen_err_o;
wire wbs_d_intgen_rty_o;
 
 
//
// Wishbone instruction bus arbiter
//
408,6 → 423,18
.wbs0_err_o (wbs_d_uart0_err_o),
.wbs0_rty_o (wbs_d_uart0_rty_o),
 
.wbs1_adr_i (wbs_d_intgen_adr_i),
.wbs1_dat_i (wbs_d_intgen_dat_i),
.wbs1_we_i (wbs_d_intgen_we_i),
.wbs1_cyc_i (wbs_d_intgen_cyc_i),
.wbs1_stb_i (wbs_d_intgen_stb_i),
.wbs1_cti_i (wbs_d_intgen_cti_i),
.wbs1_bte_i (wbs_d_intgen_bte_i),
.wbs1_dat_o (wbs_d_intgen_dat_o),
.wbs1_ack_o (wbs_d_intgen_ack_o),
.wbs1_err_o (wbs_d_intgen_err_o),
.wbs1_rty_o (wbs_d_intgen_rty_o),
 
// Clock, reset inputs
.wb_clk (wb_clk),
.wb_rst (wb_rst));
811,7 → 838,31
////////////////////////////////////////////////////////////////////////
`endif // !`ifdef UART0
 
`ifdef INTGEN
 
wire intgen_irq;
 
intgen intgen0
(
.clk_i (wb_clk),
.rst_i (wb_rst),
.wb_adr_i (wbs_d_intgen_adr_i[intgen_addr_width-1:0]),
.wb_cyc_i (wbs_d_intgen_cyc_i),
.wb_stb_i (wbs_d_intgen_stb_i),
.wb_dat_i (wbs_d_intgen_dat_i),
.wb_we_i (wbs_d_intgen_we_i),
.wb_ack_o (wbs_d_intgen_ack_o),
.wb_dat_o (wbs_d_intgen_dat_o),
.irq_o (intgen_irq)
);
 
`endif // `ifdef INTGEN
assign wbs_d_intgen_err_o = 0;
assign wbs_d_intgen_rty_o = 0;
////////////////////////////////////////////////////////////////////////
//
// OR1200 Interrupt assignment
845,7 → 896,11
assign or1200_pic_ints[16] = 0;
assign or1200_pic_ints[17] = 0;
assign or1200_pic_ints[18] = 0;
`ifdef INTGEN
assign or1200_pic_ints[19] = intgen_irq;
`else
assign or1200_pic_ints[19] = 0;
`endif
endmodule // top
 
/arbiter/arbiter_bytebus.v
75,7 → 75,7
wbs0_ack_o,
wbs0_err_o,
wbs0_rty_o,
/*
 
// Slave two
// Wishbone Slave interface
wbs1_adr_i,
89,7 → 89,7
wbs1_ack_o,
wbs1_err_o,
wbs1_rty_o,
 
/*
// Slave three
// Wishbone Slave interface
wbs2_adr_i,
420,7 → 420,7
input wbs0_err_o;
input wbs0_rty_o;
/*
 
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs1_adr_i;
output [wbs_dat_width-1:0] wbs1_dat_i;
434,7 → 434,7
input wbs1_err_o;
input wbs1_rty_o;
 
/*
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs2_adr_i;
output [wbs_dat_width-1:0] wbs2_dat_i;
788,8 → 788,8
 
// Slave selects
assign wb_slave_sel[0] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave0_adr;
assign wb_slave_sel[1] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave1_adr;
/*
assign wb_slave_sel[1] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave1_adr;
assign wb_slave_sel[2] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave2_adr;
assign wb_slave_sel[3] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave3_adr;
assign wb_slave_sel[4] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave4_adr;
826,7 → 826,7
assign wbs_err_o_mux_i[0] = wbs0_err_o & wb_slave_sel[0];
assign wbs_rty_o_mux_i[0] = wbs0_rty_o & wb_slave_sel[0];
 
/*
 
// Slave 1 inputs
assign wbs1_adr_i = wbm_adr_o;
assign wbs1_dat_i = wbm_dat_o;
840,7 → 840,7
assign wbs_err_o_mux_i[1] = wbs1_err_o & wb_slave_sel[1];
assign wbs_rty_o_mux_i[1] = wbs1_rty_o & wb_slave_sel[1];
 
 
/*
// Slave 2 inputs
assign wbs2_adr_i = wbm_adr_o;
assign wbs2_dat_i = wbm_dat_o;
1095,9 → 1095,8
 
// Master out mux from slave in data
assign wbm_dat_byte_i = wb_slave_sel[0] ? wbs_dat_o_mux_i[0] :
/*
wb_slave_sel[1] ? wbs_dat_o_mux_i[1] :
wb_slave_sel[2] ? wbs_dat_o_mux_i[2] :
/* wb_slave_sel[2] ? wbs_dat_o_mux_i[2] :
wb_slave_sel[3] ? wbs_dat_o_mux_i[3] :
wb_slave_sel[4] ? wbs_dat_o_mux_i[4] :
wb_slave_sel[5] ? wbs_dat_o_mux_i[5] :
1118,8 → 1117,8
*/
wbs_dat_o_mux_i[0];
// Master out acks, or together
assign wbm_ack_i = wbs_ack_o_mux_i[0] /* |
wbs_ack_o_mux_i[1] |
assign wbm_ack_i = wbs_ack_o_mux_i[0] |
wbs_ack_o_mux_i[1] /* |
wbs_ack_o_mux_i[2] |
wbs_ack_o_mux_i[3] |
wbs_ack_o_mux_i[4] |
1142,8 → 1141,8
;
 
assign wbm_err_i = wbs_err_o_mux_i[0] |/*
wbs_err_o_mux_i[1] |
assign wbm_err_i = wbs_err_o_mux_i[0] |
wbs_err_o_mux_i[1] |/*
wbs_err_o_mux_i[2] |
wbs_err_o_mux_i[3] |
wbs_err_o_mux_i[4] |
1166,8 → 1165,8
watchdog_err ;
 
assign wbm_rty_i = wbs_rty_o_mux_i[0] /*|
wbs_rty_o_mux_i[1] |
assign wbm_rty_i = wbs_rty_o_mux_i[0] |
wbs_rty_o_mux_i[1] /*|
wbs_rty_o_mux_i[2] |
wbs_rty_o_mux_i[3] |
wbs_rty_o_mux_i[4] |

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