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Rev 362 → Rev 363

/verilog/include/dbg_cpu_defines.v
39,32 → 39,6
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: dbg_cpu_defines.v,v $
// Revision 1.6 2004/04/05 13:52:54 igorm
// CPU_WR_CTRL and CPU_RD_CTRL defines changed.
//
// Revision 1.5 2004/03/31 14:34:09 igorm
// data_cnt_lim length changed to reduce number of warnings.
//
// Revision 1.4 2004/03/28 20:27:02 igorm
// New release of the debug interface (3rd. release).
//
// Revision 1.3 2004/03/22 16:35:46 igorm
// Temp version before changing dbg interface.
//
// Revision 1.2 2004/01/17 17:01:14 mohor
// Almost finished.
//
// Revision 1.1 2004/01/16 14:53:33 mohor
// *** empty log message ***
//
//
//
 
// Defining length of the command
`define DBG_CPU_CMD_LEN 3'd4
71,17 → 45,16
`define DBG_CPU_CMD_CNT_WIDTH 3
 
// Defining length of the access_type field
`define DBG_CPU_ACC_TYPE_LEN 3'd4
`define DBG_CPU_ACC_TYPE_LEN 4
 
// Defining length of the address
`define DBG_CPU_ADR_LEN 6'd32
`define DBG_CPU_ADR_LEN 32
 
// Defining length of the length register
`define DBG_CPU_LEN_LEN 5'd16
`define DBG_CPU_LEN_LEN 16
 
// Defining total length of the DR needed
//define DBG_CPU_DR_LEN (`DBG_CPU_ACC_TYPE_LEN + `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN)
`define DBG_CPU_DR_LEN 52
`define DBG_CPU_DR_LEN (`DBG_CPU_ACC_TYPE_LEN + `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN)
// Defining length of the CRC
`define DBG_CPU_CRC_LEN 6'd32
`define DBG_CPU_CRC_CNT_WIDTH 6
/verilog/include/or1200_defines.v
867,7 → 867,7
//
 
// Define it if you want DU implemented
`define OR1200_DU_IMPLEMENTED
//`define OR1200_DU_IMPLEMENTED
 
//
// Define if you want HW Breakpoints
922,10 → 922,10
`define OR1200_DU_DRR 11'd21
`ifdef OR1200_DU_TB_IMPLEMENTED
`define OR1200_DU_TBADR 11'h0ff
`define OR1200_DU_TBIA 11'h1xx
`define OR1200_DU_TBIM 11'h2xx
`define OR1200_DU_TBAR 11'h3xx
`define OR1200_DU_TBTS 11'h4xx
`define OR1200_DU_TBIA 11'h1??
`define OR1200_DU_TBIM 11'h2??
`define OR1200_DU_TBAR 11'h3??
`define OR1200_DU_TBTS 11'h4??
`endif
 
// Position of offset bits inside SPR address
1631,7 → 1631,7
`else
`define OR1200_DCCFGR_NCW 3'h0 // 1 cache way
`define OR1200_DCCFGR_NCS (`OR1200_DCTAG) // Num cache sets
`define OR1200_DCCFGR_CBS (`OR1200_DCLS-4) // 16 byte cache block
`define OR1200_DCCFGR_CBS `OR1200_DCLS==4 ? 1'b0 : 1'b1 // 16 byte cache block
`ifdef OR1200_DC_WRITETHROUGH
`define OR1200_DCCFGR_CWS 1'b0 // Write-through strategy
`else
1679,7 → 1679,7
`else
`define OR1200_ICCFGR_NCW 3'h0 // 1 cache way
`define OR1200_ICCFGR_NCS (`OR1200_ICTAG) // Num cache sets
`define OR1200_ICCFGR_CBS (`OR1200_ICLS-4) // 16 byte cache block
`define OR1200_ICCFGR_CBS `OR1200_ICLS==4 ? 1'b0: 1'b1 // 16 byte cache block
`define OR1200_ICCFGR_CWS 1'b0 // Irrelevant
`define OR1200_ICCFGR_CCRI 1'b1 // Cache control reg impl.
`define OR1200_ICCFGR_CBIRI 1'b1 // Cache block inv reg impl.
1707,7 → 1707,7
`define OR1200_DCFGR_NDP 4'h0 // Zero DVR/DCR pairs
`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl.
`endif
`define OR1200_DCFGR_RES1 28'h0000000
`define OR1200_DCFGR_RES1 27'd0
 
///////////////////////////////////////////////////////////////////////////////
// Boot Address Selection //
/verilog/include/orpsoc-defines.v
38,7 → 38,7
`define BOARD_CLOCK_PERIOD_NS 20
 
// Included modules: define to include
`define JTAG_DEBUG
//`define JTAG_DEBUG
`define UART0
 
// end of included module defines - keep this comment line here
/verilog/include/dbg_wb_defines.v
69,16 → 69,18
 
// Defining length of the command
`define DBG_WB_CMD_LEN 3'd4
`define DBG_WB_CMD_LEN_INT 4
`define DBG_WB_CMD_CNT_WIDTH 3
 
// Defining length of the access_type field
`define DBG_WB_ACC_TYPE_LEN 3'd4
`define DBG_WB_ACC_TYPE_LEN 4
 
 
// Defining length of the address
`define DBG_WB_ADR_LEN 6'd32
`define DBG_WB_ADR_LEN 32
 
// Defining length of the length register
`define DBG_WB_LEN_LEN 5'd16
`define DBG_WB_LEN_LEN 16
 
// Defining total length of the DR needed
`define DBG_WB_DR_LEN (`DBG_WB_ACC_TYPE_LEN + `DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN)
/verilog/or1200/or1200_freeze.v
158,9 → 158,9
//
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
multicycle_cnt <= 2'b00;
multicycle_cnt <= `OR1200_MULTICYCLE_WIDTH'd0;
else if (|multicycle_cnt)
multicycle_cnt <= multicycle_cnt - 2'd1;
multicycle_cnt <= multicycle_cnt - `OR1200_MULTICYCLE_WIDTH'd1;
else if (|multicycle & !ex_freeze)
multicycle_cnt <= multicycle;
 
/verilog/or1200/or1200_alu.v
148,9 → 148,9
`endif
) begin
`ifdef OR1200_CASE_DEFAULT
casex (alu_op) // synopsys parallel_case
casez (alu_op) // synopsys parallel_case
`else
casex (alu_op) // synopsys full_case parallel_case
casez (alu_op) // synopsys full_case parallel_case
`endif
`OR1200_ALUOP_FF1: begin
result = a[0] ? 1 : a[1] ? 2 : a[2] ? 3 : a[3] ? 4 : a[4] ? 5 : a[5] ? 6 : a[6] ? 7 : a[7] ? 8 : a[8] ? 9 : a[9] ? 10 : a[10] ? 11 : a[11] ? 12 : a[12] ? 13 : a[13] ? 14 : a[14] ? 15 : a[15] ? 16 : a[16] ? 17 : a[17] ? 18 : a[18] ? 19 : a[19] ? 20 : a[20] ? 21 : a[21] ? 22 : a[22] ? 23 : a[23] ? 24 : a[24] ? 25 : a[25] ? 26 : a[26] ? 27 : a[27] ? 28 : a[28] ? 29 : a[29] ? 30 : a[30] ? 31 : a[31] ? 32 : 0;
220,9 → 220,9
// Examples for move byte, set bit and clear bit
//
always @(cust5_op or cust5_limm or a or b) begin
casex (cust5_op) // synopsys parallel_case
casez (cust5_op) // synopsys parallel_case
5'h1 : begin
casex (cust5_limm[1:0])
casez (cust5_limm[1:0])
2'h0: result_cust5 = {a[31:8], b[7:0]};
2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]};
2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]};
250,7 → 250,7
or result_csum
`endif
) begin
casex (alu_op) // synopsys parallel_case
casez (alu_op) // synopsys parallel_case
`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
`OR1200_ALUOP_ADD : begin
flagforw = (result_sum == 32'h0000_0000);
291,7 → 291,7
`endif
`endif
) begin
casex (alu_op) // synopsys parallel_case
casez (alu_op) // synopsys parallel_case
`ifdef OR1200_IMPL_CY
`OR1200_ALUOP_ADD : begin
cyforw = cy_sum;
/verilog/or1200/or1200_sprs.v
365,7 → 365,7
 
function [31:0] get_sr;
// verilator public
get_sr = sr;
get_sr = {{32-`OR1200_SR_WIDTH{1'b0}},sr};
endfunction // get_sr
 
function [31:0] get_epcr;
380,7 → 380,7
 
function [31:0] get_esr;
// verilator public
get_esr = esr;
get_esr = {{32-`OR1200_SR_WIDTH{1'b0}},esr};
endfunction // get_esr
 
`endif
392,7 → 392,7
always @(spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
spr_dat_fpu or
spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin
casex (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
casez (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
`OR1200_SPR_GROUP_SYS:
to_wbmux = sys_data;
`OR1200_SPR_GROUP_TT:
/verilog/or1200/or1200_dc_fsm.v
366,7 → 366,7
hitmiss_eval <= 1'b0;
store <= 1'b0;
load <= 1'b0;
cnt <= 3'b000;
cnt <= 3'd0;
cache_miss <= 1'b0;
cache_dirty_needs_writeback <= 1'b0;
cache_inhibit <= 1'b0;
453,10 → 453,10
state <= `OR1200_DCFSM_IDLE;
load <= 1'b0;
store <= 1'b0;
cnt <= 1'b0;
cnt <= 3'd0;
end
if (biudata_valid & (|cnt)) begin
cnt <= cnt - 1'b1;
cnt <= cnt - 3'd1;
addr_r[3:2] <= addr_r[3:2] + 1'b1;
end
else if (biudata_valid & !(|cnt)) begin
/verilog/or1200/or1200_reg2mem.v
104,7 → 104,7
// Mux to memdata[31:24]
//
always @(lsu_op or addr or regdata) begin
casex({lsu_op, addr[1:0]}) // synopsys parallel_case
casez({lsu_op, addr[1:0]}) // synopsys parallel_case
{`OR1200_LSUOP_SB, 2'b00} : memdata_hh = regdata[7:0];
{`OR1200_LSUOP_SH, 2'b00} : memdata_hh = regdata[15:8];
default : memdata_hh = regdata[31:24];
115,7 → 115,7
// Mux to memdata[23:16]
//
always @(lsu_op or addr or regdata) begin
casex({lsu_op, addr[1:0]}) // synopsys parallel_case
casez({lsu_op, addr[1:0]}) // synopsys parallel_case
{`OR1200_LSUOP_SW, 2'b00} : memdata_hl = regdata[23:16];
default : memdata_hl = regdata[7:0];
endcase
125,7 → 125,7
// Mux to memdata[15:8]
//
always @(lsu_op or addr or regdata) begin
casex({lsu_op, addr[1:0]}) // synopsys parallel_case
casez({lsu_op, addr[1:0]}) // synopsys parallel_case
{`OR1200_LSUOP_SB, 2'b10} : memdata_lh = regdata[7:0];
default : memdata_lh = regdata[15:8];
endcase
/verilog/or1200/or1200_lsu.v
147,7 → 147,7
 
always @(posedge clk or `OR1200_RST_EVENT rst) begin
if (rst == `OR1200_RST_VALUE)
dcpu_adr_r <= {`OR1200_LSUEA_PRECALC{1'b0}};
dcpu_adr_r <= {`OR1200_LSUEA_PRECALC+1{1'b0}};
else if (!ex_freeze)
dcpu_adr_r <= id_precalc_sum;
end
181,7 → 181,12
//
// External I/F assignments
//
assign dcpu_adr_o[31:`OR1200_LSUEA_PRECALC] = ex_addrbase[31:`OR1200_LSUEA_PRECALC] + ex_addrofs[31:`OR1200_LSUEA_PRECALC] + dcpu_adr_r[`OR1200_LSUEA_PRECALC]; // carry
assign dcpu_adr_o[31:`OR1200_LSUEA_PRECALC] =
ex_addrbase[31:`OR1200_LSUEA_PRECALC] +
(ex_addrofs[31:`OR1200_LSUEA_PRECALC] +
// carry from precalc, pad to 30-bits
{{(32-`OR1200_LSUEA_PRECALC)-1{1'b0}},
dcpu_adr_r[`OR1200_LSUEA_PRECALC]});
assign dcpu_adr_o[`OR1200_LSUEA_PRECALC-1:0] = dcpu_adr_r[`OR1200_LSUEA_PRECALC-1:0];
assign dcpu_cycstb_o = du_stall | lsu_unstall | except_align ?
1'b0 : |ex_lsu_op;
188,7 → 193,7
assign dcpu_we_o = ex_lsu_op[3];
assign dcpu_tag_o = dcpu_cycstb_o ? `OR1200_DTAG_ND : `OR1200_DTAG_IDLE;
always @(ex_lsu_op or dcpu_adr_o)
casex({ex_lsu_op, dcpu_adr_o[1:0]})
casez({ex_lsu_op, dcpu_adr_o[1:0]})
{`OR1200_LSUOP_SB, 2'b00} : dcpu_sel_o = 4'b1000;
{`OR1200_LSUOP_SB, 2'b01} : dcpu_sel_o = 4'b0100;
{`OR1200_LSUOP_SB, 2'b10} : dcpu_sel_o = 4'b0010;
/verilog/or1200/or1200_ctrl.v
321,7 → 321,7
// pipeline ID and EX branch target address
always @(posedge clk or `OR1200_RST_EVENT rst) begin
if (rst == `OR1200_RST_VALUE)
ex_branch_addrtarget <= 32'h00000000;
ex_branch_addrtarget <= 0;
else if (!ex_freeze)
ex_branch_addrtarget <= id_branch_addrtarget;
end
471,15 → 471,14
// ALU instructions except the one with immediate
`OR1200_OR32_ALU:
case (id_insn[3:0]) // synopsys parallel_case
4'h6: multicycle = 2'b11; // l.mul
4'h9: multicycle = 2'b10; // l.div
4'hA: multicycle = 2'b10; // l.divu
4'hB: multicycle = 2'b11; // l.mulu
default: multicycle = 2'b00;
endcase
4'h6: multicycle = `OR1200_MULTICYCLE_WIDTH'd3; // l.mul
4'h9: multicycle = `OR1200_MULTICYCLE_WIDTH'd2; // l.div
4'hA: multicycle = `OR1200_MULTICYCLE_WIDTH'd2; // l.divu
4'hB: multicycle = `OR1200_MULTICYCLE_WIDTH'd3; // l.mulu
default: multicycle = `OR1200_MULTICYCLE_WIDTH'd0;
endcase
`OR1200_OR32_MULI:
multicycle = 2'h3;
multicycle = `OR1200_MULTICYCLE_WIDTH'd3;
// Single cycle instructions
default: begin
724,52 → 723,53
`OR1200_OR32_CUST5,
`endif
`OR1200_OR32_NOP:
except_illegal <= 1'b0;
except_illegal <= 1'b0;
`ifdef OR1200_FPU_IMPLEMENTED
`OR1200_OR32_FLOAT:
// Check it's not a double precision instruction
except_illegal <= id_insn[`OR1200_FPUOP_DOUBLE_BIT];
// Check it's not a double precision instruction
except_illegal <= id_insn[`OR1200_FPUOP_DOUBLE_BIT];
`endif
 
`OR1200_OR32_ALU:
except_illegal <= 1'b0
except_illegal <= 1'b0
 
`ifdef OR1200_MULT_IMPLEMENTED
`ifdef OR1200_DIV_IMPLEMENTED
`else
| ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_DIV)
| ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_DIVU)
| (id_insn[3:0] == `OR1200_ALUOP_DIV)
| (id_insn[3:0] == `OR1200_ALUOP_DIVU)
`endif
`else
| ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_DIV)
| ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_DIVU)
| ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_MUL)
| (id_insn[3:0] == `OR1200_ALUOP_DIV)
| (id_insn[3:0] == `OR1200_ALUOP_DIVU)
| (id_insn[3:0] == `OR1200_ALUOP_MUL)
`endif
 
`ifdef OR1200_IMPL_ADDC
`else
| ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_ADDC)
| (id_insn[3:0] == `OR1200_ALUOP_ADDC)
`endif
 
`ifdef OR1200_IMPL_ALU_ROTATE
`else
| (({1'b0, id_insn[3:0]} == `OR1200_ALUOP_SHROT) && (id_insn[7:6] == `OR1200_SHROTOP_ROR))
| ((id_insn[3:0] == `OR1200_ALUOP_SHROT) &
(id_insn[7:6] == `OR1200_SHROTOP_ROR))
`endif
 
`ifdef OR1200_IMPL_SUB
`else
| ({1'b0, id_insn[3:0]} == `OR1200_ALUOP_SUB)
| (id_insn[3:0] == `OR1200_ALUOP_SUB)
`endif
;
;
 
// Illegal and OR1200 unsupported instructions
default:
except_illegal <= 1'b1;
default:
except_illegal <= 1'b1;
 
endcase
end
endcase
end // if (!ex_freeze)
end
 
//
// Decode of alu_op
/verilog/or1200/or1200_wb_biu.v
337,17 → 337,17
end
else begin
// WB ack toggle counter
if (wb_fsm_state_cur == wb_fsm_idle | !clmode)
if (wb_fsm_state_cur == wb_fsm_idle | !(|clmode))
wb_ack_cnt <= 1'b0;
else if (wb_stb_o & wb_ack)
wb_ack_cnt <= !wb_ack_cnt;
// WB err toggle counter
if (wb_fsm_state_cur == wb_fsm_idle | !clmode)
if (wb_fsm_state_cur == wb_fsm_idle | !(|clmode))
wb_err_cnt <= 1'b0;
else if (wb_stb_o & wb_err_i)
wb_err_cnt <= !wb_err_cnt;
// WB rty toggle counter
if (wb_fsm_state_cur == wb_fsm_idle | !clmode)
if (wb_fsm_state_cur == wb_fsm_idle | !(|clmode))
wb_rty_cnt <= 1'b0;
else if (wb_stb_o & wb_rty_i)
wb_rty_cnt <= !wb_rty_cnt;
371,17 → 371,17
else
biu_stb_reg <= biu_stb_i;
// BIU ack toggle counter
if (wb_fsm_state_cur == wb_fsm_idle | !clmode)
if (wb_fsm_state_cur == wb_fsm_idle | !(|clmode))
biu_ack_cnt <= 1'b0 ;
else if (biu_ack_o)
biu_ack_cnt <= !biu_ack_cnt ;
// BIU err toggle counter
if (wb_fsm_state_cur == wb_fsm_idle | !clmode)
if (wb_fsm_state_cur == wb_fsm_idle | !(|clmode))
biu_err_cnt <= 1'b0 ;
else if (wb_err_i & biu_err_o)
biu_err_cnt <= !biu_err_cnt ;
// BIU rty toggle counter
if (wb_fsm_state_cur == wb_fsm_idle | !clmode)
if (wb_fsm_state_cur == wb_fsm_idle | !(|clmode))
biu_rty_cnt <= 1'b0 ;
else if (biu_rty)
biu_rty_cnt <= !biu_rty_cnt ;
/verilog/or1200/or1200_du.v
536,39 → 536,39
//
always @(du_except_stop) begin
except_stop = 14'b00_0000_0000_0000;
casex (du_except_stop)
14'b1x_xxxx_xxxx_xxxx:
casez (du_except_stop)
14'b1?_????_????_????:
except_stop[`OR1200_DU_DRR_TTE] = 1'b1;
14'b01_xxxx_xxxx_xxxx: begin
14'b01_????_????_????: begin
except_stop[`OR1200_DU_DRR_IE] = 1'b1;
end
14'b00_1xxx_xxxx_xxxx: begin
14'b00_1???_????_????: begin
except_stop[`OR1200_DU_DRR_IME] = 1'b1;
end
14'b00_01xx_xxxx_xxxx:
14'b00_01??_????_????:
except_stop[`OR1200_DU_DRR_IPFE] = 1'b1;
14'b00_001x_xxxx_xxxx: begin
14'b00_001?_????_????: begin
except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
end
14'b00_0001_xxxx_xxxx:
14'b00_0001_????_????:
except_stop[`OR1200_DU_DRR_IIE] = 1'b1;
14'b00_0000_1xxx_xxxx: begin
14'b00_0000_1???_????: begin
except_stop[`OR1200_DU_DRR_AE] = 1'b1;
end
14'b00_0000_01xx_xxxx: begin
14'b00_0000_01??_????: begin
except_stop[`OR1200_DU_DRR_DME] = 1'b1;
end
14'b00_0000_001x_xxxx:
14'b00_0000_001?_????:
except_stop[`OR1200_DU_DRR_DPFE] = 1'b1;
14'b00_0000_0001_xxxx:
14'b00_0000_0001_????:
except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
14'b00_0000_0000_1xxx: begin
14'b00_0000_0000_1???: begin
except_stop[`OR1200_DU_DRR_RE] = 1'b1;
end
14'b00_0000_0000_01xx: begin
14'b00_0000_0000_01??: begin
except_stop[`OR1200_DU_DRR_TE] = 1'b1;
end
14'b00_0000_0000_001x: begin
14'b00_0000_0000_001?: begin
except_stop[`OR1200_DU_DRR_FPE] = 1'b1;
end
14'b00_0000_0000_0001:
912,7 → 912,7
or tbar_dat_o or tbts_dat_o
`endif
)
casex (spr_addr[`OR1200_DUOFS_BITS]) // synopsys parallel_case
casez (spr_addr[`OR1200_DUOFS_BITS]) // synopsys parallel_case
`ifdef OR1200_DU_DVR0
`OR1200_DU_DVR0:
spr_dat_o = dvr0;
/verilog/or1200/or1200_mult_mac.v
176,10 → 176,10
// to next instruction and to WB stage
//
always @*
casex(alu_op) // synopsys parallel_case
casez(alu_op) // synopsys parallel_case
`ifdef OR1200_DIV_IMPLEMENTED
`OR1200_ALUOP_DIV: begin
result = a[31] ^ b[31] ? ~mul_prod_r[31:0] + 1'b1 : mul_prod_r[31:0];
result = a[31] ^ b[31] ? ~mul_prod_r[31:0] + 32'd1 : mul_prod_r[31:0];
end
`OR1200_ALUOP_DIVU,
`endif
233,7 → 233,7
mul_prod_r <= {mul_prod_r[62:0], 1'b0};
else
mul_prod_r <= {div_tmp[30:0], mul_prod_r[31:0], 1'b1};
div_cntr <= div_cntr - 1'b1;
div_cntr <= div_cntr - 6'd1;
end
else if (alu_op_div_divu && div_free) begin
mul_prod_r <= {31'b0, x[31:0], 1'b0};
/verilog/or1200/or1200_wbmux.v
113,9 → 113,9
//
always @(muxin_a or muxin_b or muxin_c or muxin_d or muxin_e or rfwb_op) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
case(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case infer_mux
casez(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case infer_mux
`else
case(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case
casez(rfwb_op[`OR1200_RFWBOP_WIDTH-1:1]) // synopsys parallel_case
`endif
`OR1200_RFWBOP_ALU: muxout = muxin_a;
`OR1200_RFWBOP_LSU: begin
151,7 → 151,11
// synopsys translate_on
`endif
end
`endif
`endif
default : begin
muxout = 0;
end
endcase
end
 
/verilog/or1200/or1200_operandmuxes.v
128,9 → 128,9
//
always @(ex_forw or wb_forw or rf_dataa or sel_a) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
casex (sel_a) // synopsys parallel_case infer_mux
casez (sel_a) // synopsys parallel_case infer_mux
`else
casex (sel_a) // synopsys parallel_case
casez (sel_a) // synopsys parallel_case
`endif
`OR1200_SEL_EX_FORW:
muxed_a = ex_forw;
146,9 → 146,9
//
always @(simm or ex_forw or wb_forw or rf_datab or sel_b) begin
`ifdef OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
casex (sel_b) // synopsys parallel_case infer_mux
casez (sel_b) // synopsys parallel_case infer_mux
`else
casex (sel_b) // synopsys parallel_case
casez (sel_b) // synopsys parallel_case
`endif
`OR1200_SEL_IMM:
muxed_b = simm;
/verilog/or1200/or1200_dmmu_top.v
233,7 → 233,7
//
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
dcpu_vpn_r <= {31-`OR1200_DMMU_PS{1'b0}};
dcpu_vpn_r <= {32-`OR1200_DMMU_PS{1'b0}};
else
dcpu_vpn_r <= dcpu_adr_i[31:`OR1200_DMMU_PS];
 
/verilog/or1200/or1200_except.v
466,9 → 466,9
state <= `OR1200_EXCEPTFSM_FLU1;
extend_flush <= 1'b1;
esr <= sr_we ? to_sr : sr;
casex (except_trig)
casez (except_trig)
`ifdef OR1200_EXCEPT_ITLBMISS
14'b1x_xxxx_xxxx_xxxx: begin
14'b1?_????_????_????: begin
except_type <= `OR1200_EXCEPT_ITLBMISS;
eear <= ex_dslot ?
ex_pc : ex_pc;
477,7 → 477,7
end
`endif
`ifdef OR1200_EXCEPT_IPF
14'b01_xxxx_xxxx_xxxx: begin
14'b01_????_????_????: begin
except_type <= `OR1200_EXCEPT_IPF;
eear <= ex_dslot ?
ex_pc : delayed1_ex_dslot ?
490,7 → 490,7
end
`endif
`ifdef OR1200_EXCEPT_BUSERR
14'b00_1xxx_xxxx_xxxx: begin // Insn. Bus Error
14'b00_1???_????_????: begin // Insn. Bus Error
except_type <= `OR1200_EXCEPT_BUSERR;
eear <= ex_dslot ?
wb_pc : ex_pc;
499,7 → 499,7
end
`endif
`ifdef OR1200_EXCEPT_ILLEGAL
14'b00_01xx_xxxx_xxxx: begin
14'b00_01??_????_????: begin
except_type <= `OR1200_EXCEPT_ILLEGAL;
eear <= ex_pc;
epcr <= ex_dslot ?
507,7 → 507,7
end
`endif
`ifdef OR1200_EXCEPT_ALIGN
14'b00_001x_xxxx_xxxx: begin
14'b00_001?_????_????: begin
except_type <= `OR1200_EXCEPT_ALIGN;
eear <= lsu_addr;
epcr <= ex_dslot ?
515,7 → 515,7
end
`endif
`ifdef OR1200_EXCEPT_DTLBMISS
14'b00_0001_xxxx_xxxx: begin
14'b00_0001_????_????: begin
except_type <= `OR1200_EXCEPT_DTLBMISS;
eear <= lsu_addr;
epcr <= ex_dslot ?
524,7 → 524,7
end
`endif
`ifdef OR1200_EXCEPT_TRAP
14'b00_0000_1xxx_xxxx: begin
14'b00_0000_1???_????: begin
except_type <= `OR1200_EXCEPT_TRAP;
epcr <= ex_dslot ?
wb_pc : delayed1_ex_dslot ?
532,7 → 532,7
end
`endif
`ifdef OR1200_EXCEPT_SYSCALL
14'b00_0000_01xx_xxxx: begin
14'b00_0000_01??_????: begin
except_type <= `OR1200_EXCEPT_SYSCALL;
epcr <= ex_dslot ?
wb_pc : delayed1_ex_dslot ?
541,7 → 541,7
end
`endif
`ifdef OR1200_EXCEPT_DPF
14'b00_0000_001x_xxxx: begin
14'b00_0000_001?_????: begin
except_type <= `OR1200_EXCEPT_DPF;
eear <= lsu_addr;
epcr <= ex_dslot ?
550,7 → 550,7
end
`endif
`ifdef OR1200_EXCEPT_BUSERR
14'b00_0000_0001_xxxx: begin // Data Bus Error
14'b00_0000_0001_????: begin // Data Bus Error
except_type <= `OR1200_EXCEPT_BUSERR;
eear <= lsu_addr;
epcr <= ex_dslot ?
559,7 → 559,7
end
`endif
`ifdef OR1200_EXCEPT_RANGE
14'b00_0000_0000_1xxx: begin
14'b00_0000_0000_1???: begin
except_type <= `OR1200_EXCEPT_RANGE;
epcr <= ex_dslot ?
wb_pc : delayed1_ex_dslot ?
568,13 → 568,13
end
`endif
`ifdef OR1200_EXCEPT_FLOAT
14'b00_0000_0000_01xx: begin
14'b00_0000_0000_01??: begin
except_type <= `OR1200_EXCEPT_FLOAT;
epcr <= id_pc;
end
`endif
`ifdef OR1200_EXCEPT_INT
14'b00_0000_0000_001x: begin
14'b00_0000_0000_001?: begin
except_type <= `OR1200_EXCEPT_INT;
epcr <= id_pc;
end
/verilog/or1200/or1200_genpc.v
154,7 → 154,7
or except_start or operand_b or epcr or spr_pc_we or spr_dat_i or
except_prefix)
begin
casex ({spr_pc_we, except_start, branch_op}) // synopsys parallel_case
casez ({spr_pc_we, except_start, branch_op}) // synopsys parallel_case
{2'b00, `OR1200_BRANCHOP_NOP}: begin
pc = {pcreg + 30'd1, 2'b0};
ex_branch_taken = 1'b0;
229,7 → 229,7
pc = epcr;
ex_branch_taken = 1'b1;
end
{2'b01, 3'bxxx}: begin
{2'b01, 3'b???}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("Starting exception: %h.", except_type);
/verilog/or1200/or1200_top.v
258,7 → 258,8
wire [dw-1:0] spr_dat_cpu;
wire [31:0] spr_cs;
wire spr_we;
 
wire mtspr_dc_done;
//
// SB
//
/verilog/orpsoc_top/orpsoc_top.v
72,8 → 72,9
//
// Wires
//
wire wb_clk, wb_rst;
wire dbg_tck;
wire async_rst;
wire wb_clk, wb_rst;
wire dbg_tck;
 
clkgen clkgen0
80,6 → 81,8
(
 
.clk_pad_i (clk_pad_i),
 
.async_rst_o (async_rst),
.wb_clk_o (wb_clk),
.wb_rst_o (wb_rst),
429,7 → 432,7
wire dbg_if_tdo;
wire jtag_tap_tdo;
wire jtag_tap_shift_dr, jtag_tap_pause_dr,
jtag_tap_upate_dr, jtag_tap_capture_dr;
jtag_tap_update_dr, jtag_tap_capture_dr;
//
// Instantiation
//
443,7 → 446,7
.trst_pad_i (async_rst),
.tdi_pad_i (tdi_pad_i),
.tdo_padoe_o (tdo_padoe_o),
.tdo_padoe_o (),
.tdo_o (jtag_tap_tdo),
 
692,7 → 695,7
////////////////////////////////////////////////////////////////////////
 
parameter wb_ram_dat_width = 32;
parameter wb_ram_adr_width = 25;
parameter wb_ram_adr_width = 23;
//parameter ram_wb_mem_size = 2097152; // 8MB
parameter wb_ram_mem_size = 8388608; // 32MB -- for linux test
 
746,8 → 749,10
wb_ram_last_selected <= 2'b10;
// Mux input signals to RAM (default to wbs_d_mc0)
assign wb_ram_adr_i = (wb_ram_mast_select[1]) ? wbs_i_mc0_adr_i :
(wb_ram_mast_select[0]) ? wbs_d_mc0_adr_i : 0;
assign wb_ram_adr_i = (wb_ram_mast_select[1]) ?
wbs_i_mc0_adr_i[wb_ram_adr_width-1:0] :
(wb_ram_mast_select[0]) ?
wbs_d_mc0_adr_i[wb_ram_adr_width-1:0] : 0;
assign wb_ram_bte_i = (wb_ram_mast_select[1]) ? wbs_i_mc0_bte_i :
(wb_ram_mast_select[0]) ? wbs_d_mc0_bte_i : 0;
assign wb_ram_cti_i = (wb_ram_mast_select[1]) ? wbs_i_mc0_cti_i :
/verilog/arbiter/arbiter_ibus.v
299,7 → 299,7
// Slave out assigns
assign wbs0_adr_i = wbm_adr_o;
assign wbs0_dat_i = wbm_dat_o;
assign wbs0_we_i = wbm_dat_o;
assign wbs0_we_i = wbm_we_o;
assign wbs0_sel_i = wbm_sel_o;
assign wbs0_cti_i = wbm_cti_o;
assign wbs0_bte_i = wbm_bte_o;
308,7 → 308,7
 
assign wbs1_adr_i = wbm_adr_o;
assign wbs1_dat_i = wbm_dat_o;
assign wbs1_we_i = wbm_dat_o;
assign wbs1_we_i = wbm_we_o;
assign wbs1_sel_i = wbm_sel_o;
assign wbs1_cti_i = wbm_cti_o;
assign wbs1_bte_i = wbm_bte_o;
/verilog/jtag_tap/jtag_tap.v
505,7 → 505,7
 
always @ (negedge tck_pad_i)
begin
idcode_tdo <= idcode_reg;
idcode_tdo <= idcode_reg[0]; // JB 100911
end
/**********************************************************************************
* *
/verilog/wb_ram_b3/wb_ram_b3.v
15,7 → 15,7
parameter dw = 32;
 
// 32MB memory by default
parameter aw = 25;
parameter aw = 23;
parameter mem_size = 8388608;
 
input [aw-1:0] wb_adr_i;
40,7 → 40,7
reg [dw-1:0] mem [ 0 : mem_size-1 ] /* verilator public */ /* synthesis ram_style = no_rw_check */;
//reg [aw-1:2] wb_adr_i_r;
reg [(aw-2)-1:0] adr;
reg [aw-1:0] adr;
wire [31:0] wr_data;
 
50,7 → 50,7
wire wb_b3_trans_start, wb_b3_trans_stop;
// Register to use for counting the addresses when doing burst accesses
reg [aw-1-2:0] burst_adr_counter;
reg [aw-1:0] burst_adr_counter;
reg [2:0] wb_cti_i_r;
reg [1:0] wb_bte_i_r;
wire using_burst_adr;
78,7 → 78,7
if (wb_rst_i)
burst_adr_counter = 0;
else if (wb_b3_trans_start)
burst_adr_counter = wb_adr_i[aw-1:2];
burst_adr_counter = {2'b00,wb_adr_i[aw-1:2]};
else if ((wb_cti_i_r == 3'b010) & wb_ack_o & wb_b3_trans)
// Incrementing burst
begin
104,7 → 104,7
 
assign using_burst_adr = wb_b3_trans;
assign burst_access_wrong_wb_adr = (using_burst_adr & (adr != wb_adr_i[aw-1:2]));
assign burst_access_wrong_wb_adr = (using_burst_adr & (adr != {2'b00,wb_adr_i[aw-1:2]}));
 
// Address registering logic
always@(posedge wb_clk_i)
113,7 → 113,7
else if (using_burst_adr)
adr <= burst_adr_counter;
else if (wb_cyc_i & wb_stb_i)
adr <= wb_adr_i[aw-1:2];
adr <= {2'b00,wb_adr_i[aw-1:2]};
parameter memory_file = "sram.vmem";
 
/verilog/clkgen/clkgen.v
42,7 → 42,9
(
// Main clocks in, depending on board
clk_pad_i,
 
// Input reset - through a buffer, asynchronous
async_rst_o,
// Wishbone clock and reset out
wb_clk_o,
wb_rst_o,
60,6 → 62,8
 
input clk_pad_i;
output async_rst_o;
output wb_rst_o;
output wb_clk_o;
 
72,7 → 76,6
input rst_n_pad_i;
// First, deal with the asychronous reset
wire async_rst;
wire async_rst_n;
 
// An input buffer is usually instantiated here
79,7 → 82,7
assign async_rst_n = rst_n_pad_i;
// Everyone likes active-high reset signals...
assign async_rst = ~async_rst_n;
assign async_rst_o = ~async_rst_n;
`ifdef JTAG_DEBUG
assign dbg_tck_o = tck_pad_i;
104,8 → 107,8
 
// Reset generation for wishbone
reg [15:0] wb_rst_shr;
always @(posedge wb_clk_o or posedge async_rst)
if (async_rst)
always @(posedge wb_clk_o or posedge async_rst_o)
if (async_rst_o)
wb_rst_shr <= 16'hffff;
else
wb_rst_shr <= {wb_rst_shr[14:0], ~(sync_rst_n)};
/verilog/dbg_if/dbg_cpu.v
39,50 → 39,7
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: dbg_cpu.v,v $
// Revision 1.12 2004/04/08 14:15:10 igorm
// CTRL READ fixed. Stall bit was not shifted out OK. Error appeared in last
// check-in.
//
// Revision 1.11 2004/04/07 19:28:55 igorm
// Zero is shifted out when CTRL_READ command is active.
//
// Revision 1.10 2004/04/01 10:22:45 igorm
// Signals for easier debugging removed.
//
// Revision 1.9 2004/03/31 14:34:09 igorm
// data_cnt_lim length changed to reduce number of warnings.
//
// Revision 1.8 2004/03/28 20:27:01 igorm
// New release of the debug interface (3rd. release).
//
// Revision 1.7 2004/01/25 14:04:18 mohor
// All flipflops are reset.
//
// Revision 1.6 2004/01/22 13:58:53 mohor
// Port signals are all set to zero after reset.
//
// Revision 1.5 2004/01/19 07:32:41 simons
// Reset values width added because of FV, a good sentence changed because some tools can not handle it.
//
// Revision 1.4 2004/01/17 18:38:11 mohor
// cpu_tall_o is set with cpu_stb_o or register.
//
// Revision 1.3 2004/01/17 18:01:24 mohor
// New version.
//
// Revision 1.2 2004/01/17 17:01:14 mohor
// Almost finished.
//
// Revision 1.1 2004/01/16 14:53:31 mohor
// *** empty log message ***
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
285,7 → 242,10
dr[31:0] <= {dr[30:0], 1'b0};
latch_data <= 1'b0;
end
end
end
default: begin
end
endcase
end
else if (enable && (!addr_len_cnt_end))
307,7 → 267,7
else if (update_dr_i)
cmd_cnt <= {`DBG_CPU_CMD_CNT_WIDTH{1'b0}};
else if (cmd_cnt_en)
cmd_cnt <= cmd_cnt + 1'b1;
cmd_cnt <= cmd_cnt + 1;
end
 
 
357,7 → 317,7
else if (update_dr_i)
addr_len_cnt <= 6'h0;
else if (addr_len_cnt_en)
addr_len_cnt <= addr_len_cnt + 1'b1;
addr_len_cnt <= addr_len_cnt + 1;
end
 
 
381,11 → 341,11
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
data_cnt <= {`DBG_CPU_DATA_CNT_WIDTH{1'b0}};
data_cnt <= {`DBG_CPU_DATA_CNT_WIDTH+1{1'b0}};
else if (update_dr_i)
data_cnt <= {`DBG_CPU_DATA_CNT_WIDTH{1'b0}};
data_cnt <= {`DBG_CPU_DATA_CNT_WIDTH+1{1'b0}};
else if (data_cnt_en)
data_cnt <= data_cnt + 1'b1;
data_cnt <= data_cnt + 1;
end
 
 
394,9 → 354,9
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
data_cnt_limit <= {`DBG_CPU_DATA_CNT_LIM_WIDTH{1'b0}};
data_cnt_limit <= {`DBG_CPU_DATA_CNT_LIM_WIDTH+1{1'b0}};
else if (update_dr_i)
data_cnt_limit <= len + 1'b1;
data_cnt_limit <= len + 1;
end
 
 
424,7 → 384,7
if (rst_i)
crc_cnt <= {`DBG_CPU_CRC_CNT_WIDTH{1'b0}};
else if(crc_cnt_en)
crc_cnt <= crc_cnt + 1'b1;
crc_cnt <= crc_cnt + 1;
else if (update_dr_i)
crc_cnt <= {`DBG_CPU_CRC_CNT_WIDTH{1'b0}};
end
462,7 → 422,7
else if (update_dr_i)
status_cnt <= {`DBG_CPU_STATUS_CNT_WIDTH{1'b0}};
else if (status_cnt_en)
status_cnt <= status_cnt + 1'b1;
status_cnt <= status_cnt + 1;
end
 
 
532,11 → 492,11
if (rst_i)
len_var <= {1'b0, {`DBG_CPU_LEN_LEN{1'b0}}};
else if(update_dr_i)
len_var <= len + 1'b1;
len_var <= len + 'd1;
else if (start_rd_tck)
begin
if (len_var > 'd4)
len_var <= len_var - 3'd4;
if (len_var > 4)
len_var <= len_var - 'd4;
else
len_var <= {1'b0, {`DBG_CPU_LEN_LEN{1'b0}}};
end
571,7 → 531,7
if (rst_i)
begin
start_wr_tck <= 1'b0;
cpu_dat_tmp <= 32'h0;
cpu_dat_tmp <= 32'd0;
end
else if (curr_cmd_go && acc_type_write)
begin
686,7 → 646,8
cpu_addr_dsff <= adr;
else if (cpu_ack_i && (!cpu_ack_q))
//cpu_addr_dsff <= cpu_addr_dsff + 3'd4;
cpu_addr_dsff <= cpu_addr_dsff + 3'd1; // Increment by just 1, to allow block reading -- jb 090901
// Increment by just 1, to allow block reading -- jb 090901
cpu_addr_dsff <= cpu_addr_dsff + 'd1;
end
 
 
/verilog/dbg_if/dbg_wb.v
39,81 → 39,6
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: dbg_wb.v,v $
// Revision 1.23 2004/04/01 17:21:22 igorm
// Changes for the FormalPRO.
//
// Revision 1.22 2004/04/01 11:56:59 igorm
// Port names and defines for the supported CPUs changed.
//
// Revision 1.21 2004/03/31 14:34:09 igorm
// data_cnt_lim length changed to reduce number of warnings.
//
// Revision 1.20 2004/03/28 20:27:02 igorm
// New release of the debug interface (3rd. release).
//
// Revision 1.19 2004/03/22 16:35:46 igorm
// Temp version before changing dbg interface.
//
// Revision 1.18 2004/01/25 14:04:18 mohor
// All flipflops are reset.
//
// Revision 1.17 2004/01/22 13:58:53 mohor
// Port signals are all set to zero after reset.
//
// Revision 1.16 2004/01/19 07:32:41 simons
// Reset values width added because of FV, a good sentence changed because some tools can not handle it.
//
// Revision 1.15 2004/01/17 18:01:24 mohor
// New version.
//
// Revision 1.14 2004/01/16 14:51:33 mohor
// cpu registers added.
//
// Revision 1.13 2004/01/15 12:09:43 mohor
// Working.
//
// Revision 1.12 2004/01/14 22:59:18 mohor
// Temp version.
//
// Revision 1.11 2004/01/14 12:29:40 mohor
// temp version. Resets will be changed in next version.
//
// Revision 1.10 2004/01/13 11:28:14 mohor
// tmp version.
//
// Revision 1.9 2004/01/10 07:50:24 mohor
// temp version.
//
// Revision 1.8 2004/01/09 12:48:44 mohor
// tmp version.
//
// Revision 1.7 2004/01/08 17:53:36 mohor
// tmp version.
//
// Revision 1.6 2004/01/07 11:58:56 mohor
// temp4 version.
//
// Revision 1.5 2004/01/06 17:15:19 mohor
// temp3 version.
//
// Revision 1.4 2004/01/05 12:16:00 mohor
// tmp2 version.
//
// Revision 1.3 2003/12/23 16:22:46 mohor
// Tmp version.
//
// Revision 1.2 2003/12/23 15:26:26 mohor
// Small fix.
//
// Revision 1.1 2003/12/23 15:09:04 mohor
// New directory structure. New version of the debug interface.
//
//
//
 
// synopsys translate_off
`include "timescale.v"
262,7 → 187,7
reg [2:0] mem_ptr_dsff;
reg wishbone_ce_csff;
reg mem_ptr_init;
reg [`DBG_WB_CMD_LEN -1: 0] curr_cmd;
reg [`DBG_WB_CMD_LEN_INT -1: 0] curr_cmd;
wire curr_cmd_go;
reg curr_cmd_go_q;
wire curr_cmd_wr_comm;
393,7 → 318,7
else if (update_dr_i)
cmd_cnt <= {`DBG_WB_CMD_CNT_WIDTH{1'b0}};
else if (cmd_cnt_en)
cmd_cnt <= cmd_cnt + 1'b1;
cmd_cnt <= cmd_cnt + `DBG_WB_CMD_CNT_WIDTH'd1;
end
 
 
401,11 → 326,11
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
curr_cmd <= {`DBG_WB_CMD_LEN{1'b0}};
curr_cmd <= {`DBG_WB_CMD_LEN_INT{1'b0}};
else if (update_dr_i)
curr_cmd <= {`DBG_WB_CMD_LEN{1'b0}};
else if (cmd_cnt == (`DBG_WB_CMD_LEN -1))
curr_cmd <= {dr[`DBG_WB_CMD_LEN-2 :0], tdi_i};
curr_cmd <= {`DBG_WB_CMD_LEN_INT{1'b0}};
else if (cmd_cnt == (`DBG_WB_CMD_LEN_INT -1))
curr_cmd <= {dr[`DBG_WB_CMD_LEN_INT-2 :0], tdi_i};
end
 
 
439,11 → 364,11
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
addr_len_cnt <= 6'h0;
addr_len_cnt <= 6'd0;
else if (update_dr_i)
addr_len_cnt <= 6'h0;
addr_len_cnt <= 6'd0;
else if (addr_len_cnt_en)
addr_len_cnt <= addr_len_cnt + 1'b1;
addr_len_cnt <= addr_len_cnt + 6'd1;
end
 
 
467,11 → 392,11
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
data_cnt <= {`DBG_WB_DATA_CNT_WIDTH{1'b0}};
data_cnt <= {`DBG_WB_DATA_CNT_WIDTH+1{1'b0}};
else if (update_dr_i)
data_cnt <= {`DBG_WB_DATA_CNT_WIDTH{1'b0}};
data_cnt <= {`DBG_WB_DATA_CNT_WIDTH+1{1'b0}};
else if (data_cnt_en)
data_cnt <= data_cnt + 1'b1;
data_cnt <= data_cnt + 1;
end
 
 
480,9 → 405,9
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
data_cnt_limit <= {`DBG_WB_DATA_CNT_LIM_WIDTH{1'b0}};
data_cnt_limit <= {`DBG_WB_DATA_CNT_LIM_WIDTH+1{1'b0}};
else if (update_dr_i)
data_cnt_limit <= len + 1'b1;
data_cnt_limit <= len + 1;
end
 
 
510,7 → 435,7
if (rst_i)
crc_cnt <= {`DBG_WB_CRC_CNT_WIDTH{1'b0}};
else if(crc_cnt_en)
crc_cnt <= crc_cnt + 1'b1;
crc_cnt <= crc_cnt + 1;
else if (update_dr_i)
crc_cnt <= {`DBG_WB_CRC_CNT_WIDTH{1'b0}};
end
548,7 → 473,7
else if (update_dr_i)
status_cnt <= {`DBG_WB_STATUS_CNT_WIDTH{1'b0}};
else if (status_cnt_en)
status_cnt <= status_cnt + 1'b1;
status_cnt <= status_cnt + `DBG_WB_STATUS_CNT_WIDTH'd1;
end
 
 
615,23 → 540,23
if (rst_i)
len_var <= {1'b0, {`DBG_WB_LEN_LEN{1'b0}}};
else if(update_dr_i)
len_var <= len + 1'b1;
len_var <= len + 1;
else if (start_rd_tck)
begin
case (acc_type) // synthesis parallel_case
`DBG_WB_READ8 :
if (len_var > 'd1)
len_var <= len_var - 1'd1;
len_var <= len_var - 1;
else
len_var <= {1'b0, {`DBG_WB_LEN_LEN{1'b0}}};
`DBG_WB_READ16:
if (len_var > 'd2)
len_var <= len_var - 2'd2;
len_var <= len_var - 2;
else
len_var <= {1'b0, {`DBG_WB_LEN_LEN{1'b0}}};
`DBG_WB_READ32:
if (len_var > 'd4)
len_var <= len_var - 3'd4;
len_var <= len_var - 4;
else
len_var <= {1'b0, {`DBG_WB_LEN_LEN{1'b0}}};
default: len_var <= {1'bx, {`DBG_WB_LEN_LEN{1'bx}}};
640,7 → 565,8
end
 
 
assign len_eq_0 = len_var == 'h0;
assign len_eq_0 = !(|len_var);
 
 
assign byte = data_cnt[2:0] == 3'd7;
708,7 → 634,10
begin
start_wr_tck <= 1'b0;
end
end
end
default: begin
 
end
endcase
end
else
800,17 → 729,17
always @ (posedge wb_clk_i or posedge rst_i)
begin
if (rst_i)
wb_adr_dsff <= 32'h0;
wb_adr_dsff <= 32'd0;
else if (set_addr_wb && (!set_addr_wb_q)) // Setting starting address
wb_adr_dsff <= adr;
else if (wb_ack_i)
begin
if ((acc_type == `DBG_WB_WRITE8) || (acc_type == `DBG_WB_READ8))
wb_adr_dsff <= wb_adr_dsff + 1'd1;
wb_adr_dsff <= wb_adr_dsff + 32'd1;
else if ((acc_type == `DBG_WB_WRITE16) || (acc_type == `DBG_WB_READ16))
wb_adr_dsff <= wb_adr_dsff + 2'd2;
wb_adr_dsff <= wb_adr_dsff + 32'd2;
else
wb_adr_dsff <= wb_adr_dsff + 3'd4;
wb_adr_dsff <= wb_adr_dsff + 32'd4;
end
end
 
1021,9 → 950,9
else if (wb_ack_i)
begin
if (acc_type == `DBG_WB_READ8)
mem_ptr_dsff <= mem_ptr_dsff + 1'd1;
mem_ptr_dsff <= mem_ptr_dsff + 3'd1;
else if (acc_type == `DBG_WB_READ16)
mem_ptr_dsff <= mem_ptr_dsff + 2'd2;
mem_ptr_dsff <= mem_ptr_dsff + 3'd2;
end
end
 
1082,8 → 1011,8
else if (wb_end_tck && (!wb_end_tck_q) && (!latch_data) && (!fifo_full)) // incrementing
begin
case (acc_type) // synthesis parallel_case
`DBG_WB_READ8 : fifo_cnt <= fifo_cnt + 1'd1;
`DBG_WB_READ16: fifo_cnt <= fifo_cnt + 2'd2;
`DBG_WB_READ8 : fifo_cnt <= fifo_cnt + 3'd1;
`DBG_WB_READ16: fifo_cnt <= fifo_cnt + 3'd2;
`DBG_WB_READ32: fifo_cnt <= fifo_cnt + 3'd4;
default: fifo_cnt <= 3'bxxx;
endcase
1091,8 → 1020,8
else if (!(wb_end_tck && (!wb_end_tck_q)) && latch_data && (!fifo_empty)) // decrementing
begin
case (acc_type) // synthesis parallel_case
`DBG_WB_READ8 : fifo_cnt <= fifo_cnt - 1'd1;
`DBG_WB_READ16: fifo_cnt <= fifo_cnt - 2'd2;
`DBG_WB_READ8 : fifo_cnt <= fifo_cnt - 3'd1;
`DBG_WB_READ16: fifo_cnt <= fifo_cnt - 3'd2;
`DBG_WB_READ32: fifo_cnt <= fifo_cnt - 3'd4;
default: fifo_cnt <= 3'bxxx;
endcase
/verilog/dbg_if/dbg_if.v
396,7 → 396,7
if (rst_i)
data_cnt <= {`DBG_TOP_DATA_CNT{1'b0}};
else if(shift_dr_i & (~data_cnt_end))
data_cnt <= data_cnt + 1'b1;
data_cnt <= data_cnt + 1;
else if (update_dr_i)
data_cnt <= {`DBG_TOP_DATA_CNT{1'b0}};
end
411,7 → 411,7
if (rst_i)
crc_cnt <= {`DBG_TOP_CRC_CNT{1'b0}};
else if(shift_dr_i & data_cnt_end & (~crc_cnt_end) & module_select)
crc_cnt <= crc_cnt + 1'b1;
crc_cnt <= crc_cnt + 1;
else if (update_dr_i)
crc_cnt <= {`DBG_TOP_CRC_CNT{1'b0}};
end
434,7 → 434,7
if (rst_i)
status_cnt <= {`DBG_TOP_STATUS_CNT_WIDTH{1'b0}};
else if(shift_dr_i & crc_cnt_end & (~status_cnt_end))
status_cnt <= status_cnt + 1'b1;
status_cnt <= status_cnt + 1;
else if (update_dr_i)
status_cnt <= {`DBG_TOP_STATUS_CNT_WIDTH{1'b0}};
end
502,7 → 502,7
always @ (posedge tck_i or posedge rst_i)
begin
if (rst_i)
module_dr <= `DBG_TOP_MODULE_DATA_LEN'h0;
module_dr <= 0;
else if (data_shift_en)
module_dr[`DBG_TOP_MODULE_DATA_LEN -1:0] <= {module_dr[`DBG_TOP_MODULE_DATA_LEN -2:0], tdi_i};
end
/verilog/uart16550/uart_regs.v
352,29 → 352,31
assign dtr_pad_o = mcr[`UART_MC_DTR];
 
// Interrupt signals
wire rls_int; // receiver line status interrupt
wire rda_int; // receiver data available interrupt
wire ti_int; // timeout indicator interrupt
wire thre_int; // transmitter holding register empty interrupt
wire ms_int; // modem status interrupt
wire rls_int; // receiver line status interrupt
wire rda_int; // receiver data available interrupt
wire ti_int; // timeout indicator interrupt
wire thre_int; // transmitter holding register empty interrupt
wire ms_int; // modem status interrupt
 
// FIFO signals
reg tf_push;
reg rf_pop;
wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
wire rf_error_bit; // an error (parity or framing) is inside the fifo
wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
wire [2:0] tstate;
wire [3:0] rstate;
wire [9:0] counter_t;
reg tf_push;
reg rf_pop;
wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
wire rf_error_bit; // an error (parity or framing) is inside the fifo
wire rf_overrun;
wire rf_push_pulse;
wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
wire [2:0] tstate;
wire [3:0] rstate;
wire [9:0] counter_t;
 
wire thre_set_en; // THRE status is delayed one character time when a character is written to fifo.
reg [7:0] block_cnt; // While counter counts, THRE status is blocked (delayed one character cycle)
reg [7:0] block_value; // One character length minus stop bit
wire thre_set_en; // THRE status is delayed one character time when a character is written to fifo.
reg [7:0] block_cnt; // While counter counts, THRE status is blocked (delayed one character cycle)
reg [7:0] block_value; // One character length minus stop bit
 
// Transmitter Instance
wire serial_out;
wire serial_out;
 
uart_transmitter transmitter(clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, serial_out, tstate, tf_count, tx_reset, lsr_mask);
 
392,7 → 394,7
defparam i_uart_sync_flops.init_value = 1'b1;
 
// handle loopback
wire serial_in = loopback ? serial_out : srx_pad;
wire serial_in = loopback ? serial_out : srx_pad;
assign stx_pad_o = loopback ? 1'b1 : serial_out;
 
// Receiver Instance
406,7 → 408,7
begin
case (wb_addr_i)
`UART_REG_RB : wb_dat_o = dlab ? dl[`UART_DL1] : rf_data_out[10:3];
`UART_REG_IE : wb_dat_o = dlab ? dl[`UART_DL2] : ier;
`UART_REG_IE : wb_dat_o = dlab ? dl[`UART_DL2] : {4'd0,ier};
`UART_REG_II : wb_dat_o = {4'b1100,iir};
`UART_REG_LC : wb_dat_o = lcr;
`UART_REG_LS : wb_dat_o = lsr;
498,7 → 500,7
`ifdef PRESCALER_PRESET_HARD
dl[`UART_DL2];
`else
wb_dat_i;
wb_dat_i;
`endif
end
else
/verilog/uart16550/uart_receiver.v
257,7 → 257,7
wire rcounter16_eq_0 = (rcounter16 == 4'd0);
wire rcounter16_eq_1 = (rcounter16 == 4'd1);
 
wire [3:0] rcounter16_minus_1 = rcounter16 - 1'b1;
wire [3:0] rcounter16_minus_1 = rcounter16 - 3'd1;
 
parameter sr_idle = 4'd0;
parameter sr_rec_start = 4'd1;
351,7 → 351,7
else // else we have more bits to read
begin
rstate <= sr_rec_bit;
rbit_counter <= rbit_counter - 1'b1;
rbit_counter <= rbit_counter - 3'd1;
end
rcounter16 <= 4'b1110;
end
/verilog/uart16550/uart_rfifo.v
192,7 → 192,7
reg [fifo_counter_w-1:0] count;
reg overrun;
 
wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1;
wire [fifo_pointer_w-1:0] top_plus_1 = top + 4'h1;
 
raminfr #(fifo_pointer_w,8,fifo_depth) rfifo
(.clk(clk),
208,7 → 208,7
if (wb_rst_i)
begin
top <= 0;
bottom <= 1'b0;
bottom <= 0;
count <= 0;
fifo[0] <= 0;
fifo[1] <= 0;
230,7 → 230,7
else
if (fifo_reset) begin
top <= 0;
bottom <= 1'b0;
bottom <= 0;
count <= 0;
fifo[0] <= 0;
fifo[1] <= 0;
256,16 → 256,16
begin
top <= top_plus_1;
fifo[top] <= data_in[2:0];
count <= count + 1'b1;
count <= count + 5'd1;
end
2'b01 : if(count>0)
begin
fifo[bottom] <= 0;
bottom <= bottom + 1'b1;
count <= count - 1'b1;
bottom <= bottom + 4'd1;
count <= count - 5'd1;
end
2'b11 : begin
bottom <= bottom + 1'b1;
bottom <= bottom + 4'd1;
top <= top_plus_1;
fifo[top] <= data_in[2:0];
end
/verilog/uart16550/uart_tfifo.v
180,7 → 180,7
 
reg [fifo_counter_w-1:0] count;
reg overrun;
wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1;
wire [fifo_pointer_w-1:0] top_plus_1 = top + 4'd1;
 
raminfr #(fifo_pointer_w,fifo_width,fifo_depth) tfifo
(.clk(clk),
197,13 → 197,13
if (wb_rst_i)
begin
top <= 0;
bottom <= 1'b0;
bottom <= 0;
count <= 0;
end
else
if (fifo_reset) begin
top <= 0;
bottom <= 1'b0;
bottom <= 0;
count <= 0;
end
else
212,15 → 212,15
2'b10 : if (count<fifo_depth) // overrun condition
begin
top <= top_plus_1;
count <= count + 1'b1;
count <= count + 5'd1;
end
2'b01 : if(count>0)
begin
bottom <= bottom + 1'b1;
count <= count - 1'b1;
bottom <= bottom + 4'd1;
count <= count - 5'd1;
end
2'b11 : begin
bottom <= bottom + 1'b1;
bottom <= bottom + 4'd1;
top <= top_plus_1;
end
default: ;
/verilog/uart16550/uart_transmitter.v
269,7 → 269,7
tstate <= s_send_byte;
end
else
counter <= counter - 1'b1;
counter <= counter - 5'd1;
stx_o_tmp <= 1'b0;
end
s_send_byte : begin
280,7 → 280,7
begin
if (bit_counter > 3'b0)
begin
bit_counter <= bit_counter - 1'b1;
bit_counter <= bit_counter - 3'd1;
{shift_out[5:0],bit_out } <= {shift_out[6:1], shift_out[0]};
tstate <= s_send_byte;
end
302,7 → 302,7
counter <= 0;
end
else
counter <= counter - 1'b1;
counter <= counter - 5'd1;
stx_o_tmp <= bit_out; // set output pin
end
s_send_parity : begin
311,18 → 311,18
else
if (counter == 5'b00001)
begin
counter <= 4'b0;
counter <= 5'd0;
tstate <= s_send_stop;
end
else
counter <= counter - 1'b1;
counter <= counter - 5'd1;
stx_o_tmp <= bit_out;
end
s_send_stop : begin
if (~|counter)
begin
casex ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]})
3'b0xx: counter <= 5'b01101; // 1 stop bit ok igor
casez ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]})
3'b0??: counter <= 5'b01101; // 1 stop bit ok igor
3'b100: counter <= 5'b10101; // 1.5 stop bit
default: counter <= 5'b11101; // 2 stop bits
endcase
334,7 → 334,7
tstate <= s_idle;
end
else
counter <= counter - 1'b1;
counter <= counter - 5'd1;
stx_o_tmp <= 1'b1;
end
 

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