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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/orpsocv2/rtl
    from Rev 412 to Rev 415
    ↔ Reverse comparison
  •

Rev 412 → Rev 415

/verilog/include/orpsoc-defines.v
40,6 → 40,7
// Included modules: define to include
`define JTAG_DEBUG
`define UART0
`define RAM_WB
 
// end of included module defines - keep this comment line here
 
/verilog/or1200/or1200_immu_top.v
3,7 → 3,7
//// OR1200's Instruction MMU top level ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// http://www.opencores.org/project,or1k ////
//// ////
//// Description ////
//// Instantiation of all IMMU blocks. ////
40,81 → 40,6
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_immu_top.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Major update:
// Structure reordered and bugs fixed.
//
// Revision 1.15 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.14 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.12.4.2 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.12.4.1 2003/07/08 15:36:37 lampret
// Added embedded memory QMEM.
//
// Revision 1.12 2003/06/06 02:54:47 lampret
// When OR1200_NO_IMMU and OR1200_NO_IC are not both defined or undefined at the same time, results in a IC bug. Fixed.
//
// Revision 1.11 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.10 2002/09/16 03:08:56 lampret
// Disabled cache inhibit atttribute.
//
// Revision 1.9 2002/08/18 19:54:17 lampret
// Added store buffer.
//
// Revision 1.8 2002/08/14 06:23:50 lampret
// Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run.
//
// Revision 1.7 2002/08/12 05:31:30 lampret
// Delayed external access at page crossing.
//
// Revision 1.6 2002/03/29 15:16:56 lampret
// Some of the warnings fixed.
//
// Revision 1.5 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.4 2002/02/01 19:56:54 lampret
// Fixed combinational loops.
//
// Revision 1.3 2002/01/28 01:16:00 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.2 2002/01/14 06:18:22 lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.6 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.5 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.1 2001/08/17 08:03:35 lampret
// *** empty log message ***
//
// Revision 1.2 2001/07/22 03:31:53 lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
254,27 → 179,35
always @(`OR1200_RST_EVENT rst or posedge clk)
// default value
if (rst == `OR1200_RST_VALUE) begin
// select async. value due to reset state
icpu_adr_default <= 32'h0000_0100;
icpu_adr_select <= 1'b1; // select async. value due to reset state
icpu_adr_select <= 1'b1;
end
// selected value (different from default) is written into FF after reset state
// selected value (different from default) is written
// into FF after reset state
else if (icpu_adr_select) begin
icpu_adr_default <= icpu_adr_boot; // dynamic value can only be assigned to FF out of reset!
icpu_adr_select <= 1'b0; // select FF value
// dynamic value can only be assigned to FF out of reset!
icpu_adr_default <= icpu_adr_boot;
// select FF value
icpu_adr_select <= 1'b0;
end
else begin
icpu_adr_default <= icpu_adr_i;
end
 
// select async. value for boot address after reset - PC jumps to the address selected after boot!
//assign icpu_adr_boot = {(boot_adr_sel_i ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), 12'h100} ;
// select async. value for boot address after reset - PC jumps to the address
// selected after boot!
//assign icpu_adr_boot = {(boot_adr_sel_i ? `OR1200_EXCEPT_EPH1_P :
// `OR1200_EXCEPT_EPH0_P), 12'h100} ;
assign icpu_adr_boot = `OR1200_BOOT_ADR; // jb
 
always @(icpu_adr_boot or icpu_adr_default or icpu_adr_select)
if (icpu_adr_select)
icpu_adr_o = icpu_adr_boot ; // async. value is selected due to reset state
// async. value is selected due to reset state
icpu_adr_o = icpu_adr_boot ;
else
icpu_adr_o = icpu_adr_default ; // FF value is selected 2nd clock after reset state
// FF value is selected 2nd clock after reset state
icpu_adr_o = icpu_adr_default ;
`else
Unsupported !!!
`endif
/verilog/or1200/or1200_ic_top.v
1,6 → 1,6
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Data Cache top level ////
//// OR1200's Instruction Cache top level ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://opencores.org/project,or1k ////
51,7 → 51,7
`include "or1200_defines.v"
 
//
// Data cache
// Instruction cache top
//
module or1200_ic_top(
// Rst, clk and clock control
58,13 → 58,12
clk, rst,
 
// External i/f
icbiu_dat_o, icbiu_adr_o, icbiu_cyc_o, icbiu_stb_o, icbiu_we_o, icbiu_sel_o, icbiu_cab_o,
icbiu_dat_i, icbiu_ack_i, icbiu_err_i,
icbiu_dat_o, icbiu_adr_o, icbiu_cyc_o, icbiu_stb_o, icbiu_we_o,
icbiu_sel_o, icbiu_cab_o, icbiu_dat_i, icbiu_ack_i, icbiu_err_i,
 
// Internal i/f
ic_en,
icqmem_adr_i, icqmem_cycstb_i, icqmem_ci_i,
icqmem_sel_i, icqmem_tag_i,
icqmem_adr_i, icqmem_cycstb_i, icqmem_ci_i, icqmem_sel_i, icqmem_tag_i,
icqmem_dat_o, icqmem_ack_o, icqmem_rty_o, icqmem_err_o, icqmem_tag_o,
 
`ifdef OR1200_BIST
145,7 → 144,9
wire ictag_we;
wire [31:0] ic_addr;
wire icfsm_biu_read;
/* verilator lint_off UNOPTFLAT */
reg tagcomp_miss;
/* verilator lint_on UNOPTFLAT */
wire [`OR1200_ICINDXH:`OR1200_ICLS] ictag_addr;
wire ictag_en;
wire ictag_v;
155,6 → 156,8
wire icfsm_first_miss_err;
wire icfsm_burst;
wire icfsm_tag_we;
reg ic_inv_q;
`ifdef OR1200_BIST
//
// RAM BIST
217,13 → 220,25
assign icqmem_dat_o = icfsm_first_miss_ack | !ic_en ? icbiu_dat_i : from_icram;
 
//
// Detect falling edge of IC invalidate signal
//
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst==`OR1200_RST_VALUE)
ic_inv_q <= 1'b0;
else
ic_inv_q <= ic_inv;
//
// Tag comparison
//
// During line invalidate, ensure it stays the same
// /* TODO - do this properly! */
always @(tag or saved_addr or tag_v) begin
if ((tag != saved_addr[31:`OR1200_ICTAGL]) || !tag_v)
tagcomp_miss = 1'b1;
else
tagcomp_miss = 1'b0;
if ((tag != saved_addr[31:`OR1200_ICTAGL]) | !tag_v)
tagcomp_miss = (ic_inv | ic_inv_q) ? tagcomp_miss : 1'b1;
else
tagcomp_miss = (ic_inv | ic_inv_q) ? tagcomp_miss : 1'b0;
end
 
//
/verilog/or1200/or1200_ic_fsm.v
58,7 → 58,7
`define OR1200_ICFSM_IFETCH 2'd3
 
//
// Data cache FSM for cache line of 16 bytes (4x singleword)
// Instruction cache FSM
//
 
module or1200_ic_fsm(
67,9 → 67,13
 
// Internal i/f to top level IC
ic_en, icqmem_cycstb_i, icqmem_ci_i,
tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,
icram_we, biu_read, first_hit_ack, first_miss_ack, first_miss_err,
burst, tag_we
tagcomp_miss,
biudata_valid, biudata_error,
start_addr, saved_addr,
icram_we, tag_we,
biu_read,
first_hit_ack, first_miss_ack, first_miss_err,
burst
);
 
//
102,7 → 106,7
reg hitmiss_eval;
reg load;
reg cache_inhibit;
reg waiting_for_first_fill_ack; // JPB
reg last_eval_miss; // JPB
//
// Generate of ICRAM write enables
145,7 → 149,7
load <= 1'b0;
cnt <= 3'b000;
cache_inhibit <= 1'b0;
waiting_for_first_fill_ack <= 0; // JPB
last_eval_miss <= 0; // JPB
end
else
157,7 → 161,7
hitmiss_eval <= 1'b1;
load <= 1'b1;
cache_inhibit <= icqmem_ci_i;
waiting_for_first_fill_ack <= 0; // JPB
last_eval_miss <= 0; // JPB
end
else begin // idle
hitmiss_eval <= 1'b0;
182,9 → 186,8
hitmiss_eval <= 1'b0;
load <= 1'b0;
cache_inhibit <= 1'b0;
waiting_for_first_fill_ack <= 0;
end // if ((!ic_en) ||...
// fetch missed, finish current external fetch and refill
// fetch missed, wait for first fetch and continue filling line
else if (tagcomp_miss & biudata_valid) begin
state <= `OR1200_ICFSM_LREFILL3;
saved_addr_r[3:2] <= saved_addr_r[3:2] + 1'd1;
191,22 → 194,18
hitmiss_eval <= 1'b0;
cnt <= `OR1200_ICLS-2;
cache_inhibit <= 1'b0;
waiting_for_first_fill_ack <= 0; // JPB
end
// fetch aborted (usually caused by exception)
else if (!icqmem_cycstb_i) begin
else if (!icqmem_cycstb_i
& !last_eval_miss // JPB
) begin
state <= `OR1200_ICFSM_IDLE;
hitmiss_eval <= 1'b0;
load <= 1'b0;
cache_inhibit <= 1'b0;
waiting_for_first_fill_ack <= 0; // JPB
end
// fetch hit, finish immediately
else if (!tagcomp_miss & !icqmem_ci_i &
!waiting_for_first_fill_ack) begin
state <= `OR1200_ICFSM_IDLE; // JPB
load <= 1'b0; // JPB
hitmiss_eval <= 1'b0; // JPB
// fetch hit, wait in this state for now
else if (!tagcomp_miss & !icqmem_ci_i) begin
saved_addr_r <= start_addr;
cache_inhibit <= 1'b0;
end
213,8 → 212,8
else // fetch in-progress
hitmiss_eval <= 1'b0;
 
if (hitmiss_eval & tagcomp_miss) // JPB
waiting_for_first_fill_ack <= 1;
if (hitmiss_eval & !tagcomp_miss) // JPB
last_eval_miss <= 1; // JPB
end
`OR1200_ICFSM_LREFILL3 : begin
/verilog/orpsoc_top/orpsoc_top.v
688,6 → 688,7
////////////////////////////////////////////////////////////////////////
 
`ifdef RAM_WB
////////////////////////////////////////////////////////////////////////
//
// Generic main RAM
807,7 → 808,7
.wb_rst_i (wb_rst));
////////////////////////////////////////////////////////////////////////
`endif
`ifdef UART0
////////////////////////////////////////////////////////////////////////
//

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