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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/orpsocv2/rtl
    from Rev 479 to Rev 485
    ↔ Reverse comparison
  •

Rev 479 → Rev 485

/verilog/include/or1200_defines.v
1764,10 → 1764,18
 
///////////////////////////////////////////////////////////////////////////////
// Boot Address Selection //
// This only changes where the initial reset occurs. EPH setting is still //
// used to determine where vectors are located. //
// //
// Allows a definable boot address, potentially different to the usual reset //
// vector to allow for power-on code to be run, if desired. //
// //
// OR1200_BOOT_ADR should be the 32-bit address of the boot location //
// OR1200_BOOT_PCREG_DEFAULT should be ((OR1200_BOOT_ADR-4)>>2) //
// //
// For default reset behavior uncomment the settings under the "Boot 0x100" //
// comment below. //
// //
///////////////////////////////////////////////////////////////////////////////
// Boot from 0xf0000100
// Boot from 0xf0000100
//`define OR1200_BOOT_PCREG_DEFAULT 30'h3c00003f
//`define OR1200_BOOT_ADR 32'hf0000100
// Boot from 0x100
/verilog/or1200/or1200_dpram.v
112,9 → 112,10
// verilator public
input [aw-1:0] gpr_no;
input [dw-1:0] value;
 
mem[gpr_no] = value;
begin
mem[gpr_no] = value;
set_gpr = 0;
end
endfunction // get_gpr
//
/verilog/orpsoc_top/orpsoc_top.v
668,7 → 668,7
// ROM
//
////////////////////////////////////////////////////////////////////////
`ifdef BOOTROM
rom rom0
(
.wb_dat_o (wbs_i_rom0_dat_o),
682,6 → 682,10
.wb_rst (wb_rst));
 
defparam rom0.addr_width = wbs_i_rom0_addr_width;
`else // !`ifdef BOOTROM
assign wbs_i_rom0_dat_o = 0;
assign wbs_i_rom0_ack_o = 0;
`endif // !`ifdef BOOTROM
 
assign wbs_i_rom0_err_o = 0;
assign wbs_i_rom0_rty_o = 0;
725,14 → 729,14
.wbm1_err_o (wbs_d_mc0_err_o),
.wbm1_rty_o (wbs_d_mc0_rty_o),
// Wishbone slave interface 2
.wbm2_dat_i (0),
.wbm2_adr_i (0),
.wbm2_sel_i (0),
.wbm2_cti_i (0),
.wbm2_bte_i (0),
.wbm2_we_i (0),
.wbm2_cyc_i (0),
.wbm2_stb_i (0),
.wbm2_dat_i (32'd0),
.wbm2_adr_i (32'd0),
.wbm2_sel_i (4'd0),
.wbm2_cti_i (3'd0),
.wbm2_bte_i (2'd0),
.wbm2_we_i (1'd0),
.wbm2_cyc_i (1'd0),
.wbm2_stb_i (1'd0),
.wbm2_dat_o (),
.wbm2_ack_o (),
.wbm2_err_o (),
/verilog/ethmac/eth_wishbone.v
1257,7 → 1257,7
if(Reset)
TxStartFrm_wb <= 1'b0;
else
if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0))
if(TxBDReady & ~StartOccured & (TxBufferAlmostFull | TxBufferFull| TxLengthEq0))
TxStartFrm_wb <= 1'b1;
else
if(TxStartFrm_syncb2)
/verilog/ethmac/eth_fifo.v
64,9 → 64,9
output [CNT_WIDTH-1:0] cnt;
 
 
 
reg [CNT_WIDTH-1:0] read_pointer;
reg [CNT_WIDTH-1:0] cnt;
reg final_read;
reg final_read;
always @ (posedge clk or posedge reset)
begin
113,11 → 113,7
else if (write)
waddr <= waddr + 1;
 
reg read_reg;
always @(posedge clk)
read_reg <= read;
 
always @(posedge clk)
if (reset)
raddr <= 0;
else if (clear)
153,11 → 149,27
assign empty = ~(|cnt);
assign almost_empty = cnt==1;
assign full = {{32-CNT_WIDTH{1'b0}},cnt} == (DEPTH-1);
assign almost_full = &cnt[CNT_WIDTH-1:0];
//assign almost_full = &cnt[CNT_WIDTH-1:0];
assign almost_full = {{32-CNT_WIDTH{1'b0}},cnt} == (DEPTH-2);
 
 
 
always @ (posedge clk or posedge reset)
begin
if(reset)
read_pointer <= 0;
else
if(clear)
// Begin read pointer at 1
read_pointer <= { {(CNT_WIDTH-1){1'b0}}, 1'b1};
else
if(read & ~empty)
read_pointer <= read_pointer + 1'b1;
end
 
 
`else // !`ifdef ETH_FIFO_GENERIC
reg [CNT_WIDTH-1:0] read_pointer;
 
reg [CNT_WIDTH-1:0] write_pointer;
 
 
167,8 → 179,7
read_pointer <= 0;
else
if(clear)
//read_pointer <= { {(CNT_WIDTH-1){1'b0}}, read};
read_pointer <= { {(CNT_WIDTH-1){1'b0}}, 1'b1};
read_pointer <= { {(CNT_WIDTH-1){1'b0}}, read};
else
if(read & ~empty)
read_pointer <= read_pointer + 1'b1;
186,15 → 197,81
write_pointer <= write_pointer + 1'b1;
end
 
`ifdef ETH_FIFO_XILINX
xilinx_dist_ram_16x32 fifo
( .data_out(data_out),
.we(write & ~full),
.data_in(data_in),
.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer),
.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer),
.wclk(clk)
);
`ifdef ETH_FIFO_XILINX
generate
if (CNT_WIDTH==4)
begin
xilinx_dist_ram_16x32 fifo
( .data_out(data_out),
.we(write & ~full),
.data_in(data_in),
.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]),
.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]),
.wclk(clk)
);
end // if (CNT_WIDTH==4)
else if (CNT_WIDTH==6)
begin
 
wire [DATA_WIDTH-1:0] data_out0;
wire [DATA_WIDTH-1:0] data_out1;
wire [DATA_WIDTH-1:0] data_out2;
wire [DATA_WIDTH-1:0] data_out3;
wire ramsel0,ramsel1,ramsel2,ramsel3;
 
assign ramsel0 = (read_pointer[5:4]==2'b00);
assign ramsel1 = (read_pointer[5:4]==2'b01);
assign ramsel2 = (read_pointer[5:4]==2'b10);
assign ramsel3 = (read_pointer[5:4]==2'b11);
assign data_out = ramsel3 ? data_out3 :
ramsel2 ? data_out2 :
ramsel1 ? data_out1 : data_out0;
xilinx_dist_ram_16x32 fifo0
( .data_out(data_out0),
.we((write & ~full) & ramsel0),
.data_in(data_in),
.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]),
.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]),
.wclk(clk)
);
xilinx_dist_ram_16x32 fifo1
( .data_out(data_out1),
.we(write & ~full & ramsel1),
.data_in(data_in),
.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]),
.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]),
.wclk(clk)
);
 
xilinx_dist_ram_16x32 fifo2
( .data_out(data_out2),
.we(write & ~full & ramsel2),
.data_in(data_in),
.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]),
.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]),
.wclk(clk)
);
xilinx_dist_ram_16x32 fifo3
( .data_out(data_out3),
.we(write & ~full & ramsel3),
.data_in(data_in),
.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]),
.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]),
.wclk(clk)
);
end // if (CNT_WIDTH==6)
endgenerate
 
`else // !ETH_FIFO_XILINX
`ifdef ETH_ALTERA_ALTSYNCRAM
altera_dpram_16x32 altera_dpram_16x32_inst

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