URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2/rtl
- from Rev 506 to Rev 530
- ↔ Reverse comparison
Rev 506 → Rev 530
/verilog/ethmac/eth_wishbone.v
142,22 → 142,22
|
// Rx Status signals |
input InvalidSymbol; // Invalid symbol was received during |
// reception in 100 Mbps mode |
// reception in 100 Mbps mode |
input LatchedCrcError; // CRC error |
input RxLateCollision; // Late collision occured while receiving |
// frame |
// frame |
input ShortFrame; // Frame shorter then the minimum size |
// (r_MinFL) was received while small |
// packets are enabled (r_RecSmall) |
// (r_MinFL) was received while small |
// packets are enabled (r_RecSmall) |
input DribbleNibble; // Extra nibble received |
input ReceivedPacketTooBig;// Received packet is bigger than |
// r_MaxFL |
// r_MaxFL |
input [15:0] RxLength; // Length of the incoming frame |
input LoadRxStatus; // Rx status was loaded |
input ReceivedPacketGood;// Received packet's length and CRC are |
// good |
// good |
input AddressMiss; // When a packet is received AddressMiss |
// status is written to the Rx BD |
// status is written to the Rx BD |
input r_RxFlow; |
input r_PassAll; |
input ReceivedPauseFrm; |
165,13 → 165,13
// Tx Status signals |
input [3:0] RetryCntLatched; // Latched Retry Counter |
input RetryLimit; // Retry limit reached (Retry Max value + |
// 1 attempts were made) |
// 1 attempts were made) |
input LateCollLatched; // Late collision occured |
input DeferLatched; // Defer indication (Frame was defered |
// before sucessfully sent) |
// before sucessfully sent) |
output RstDeferLatched; |
input CarrierSenseLost; // Carrier Sense was lost during the |
// frame transmission |
// frame transmission |
|
// Tx |
input MTxClk; // Transmit clock (from PHY) |
193,7 → 193,7
input RxStartFrm; // |
input RxEndFrm; // |
input RxAbort; // This signal is set when address doesn't |
// match. |
// match. |
output RxStatusWriteLatched_sync2; |
|
//Register |
360,83 → 360,188
reg RxPointerRead/* synthesis syn_allow_retiming=0*/; |
|
// RX shift ending signals |
reg ShiftEnded_rck; |
reg ShiftEndedSync1; |
reg ShiftEndedSync2; |
reg ShiftEndedSync3; |
reg ShiftEndedSync_c1; |
reg ShiftEndedSync_c2; |
reg ShiftEnded_rck; |
reg ShiftEndedSync1; |
reg ShiftEndedSync2; |
reg ShiftEndedSync3; |
reg ShiftEndedSync_c1; |
reg ShiftEndedSync_c2; |
|
wire StartShiftWillEnd; |
wire StartShiftWillEnd; |
|
// Pulse for wishbone side having finished writing back |
reg rx_wb_writeback_finished; |
reg rx_wb_writeback_finished; |
// Indicator of last set of writes from the Wishbone master coming up |
reg rx_wb_last_writes; |
reg rx_wb_last_writes; |
|
|
reg StartOccured; |
reg TxStartFrm_sync1; |
reg TxStartFrm_sync2; |
reg TxStartFrm_syncb1; |
reg TxStartFrm_syncb2; |
reg StartOccured; |
reg TxStartFrm_sync1; |
reg TxStartFrm_sync2; |
reg TxStartFrm_syncb1; |
reg TxStartFrm_syncb2; |
|
|
wire TxFifoClear; |
wire TxBufferAlmostFull; |
wire TxBufferFull; |
wire TxBufferEmpty; |
wire TxBufferAlmostEmpty; |
wire SetReadTxDataFromMemory; |
reg BlockReadTxDataFromMemory/* synthesis syn_allow_retiming=0*/; |
wire TxFifoClear; |
wire TxBufferAlmostFull; |
wire TxBufferFull; |
wire TxBufferEmpty; |
wire TxBufferAlmostEmpty; |
wire SetReadTxDataFromMemory; |
reg BlockReadTxDataFromMemory/* synthesis syn_allow_retiming=0*/; |
|
reg tx_burst_en; |
reg rx_burst_en; |
reg [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt; |
reg tx_burst_en; |
reg rx_burst_en; |
reg [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt; |
|
wire ReadTxDataFromMemory_2; |
wire tx_burst; |
wire ReadTxDataFromMemory_2; |
wire tx_burst; |
|
wire [31:0] TxData_wb; |
wire ReadTxDataFromFifo_wb; |
wire [31:0] TxData_wb; |
wire ReadTxDataFromFifo_wb; |
|
wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt; |
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt; |
wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt; |
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt; |
|
reg [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt; |
reg [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt; |
|
wire rx_burst; |
wire enough_data_in_rxfifo_for_burst; |
wire enough_data_in_rxfifo_for_burst_plus1; |
wire rx_burst; |
wire enough_data_in_rxfifo_for_burst; |
wire enough_data_in_rxfifo_for_burst_plus1; |
|
reg ReadTxDataFromMemory/* synthesis syn_allow_retiming=0*/; |
wire WriteRxDataToMemory; |
reg WriteRxDataToMemory_r ; |
reg ReadTxDataFromMemory/* synthesis syn_allow_retiming=0*/; |
wire WriteRxDataToMemory; |
reg WriteRxDataToMemory_r ; |
|
reg MasterWbTX; |
reg MasterWbRX; |
reg MasterWbTX; |
reg MasterWbRX; |
|
reg [29:0] m_wb_adr_o; |
reg m_wb_cyc_o; |
reg [3:0] m_wb_sel_o; |
reg m_wb_we_o; |
reg [29:0] m_wb_adr_o; |
reg m_wb_cyc_o; |
reg [3:0] m_wb_sel_o; |
reg m_wb_we_o; |
|
wire TxLengthEq0; |
wire TxLengthLt4; |
wire TxLengthEq0; |
wire TxLengthLt4; |
|
reg BlockingIncrementTxPointer; |
reg [31:2] TxPointerMSB; |
reg [1:0] TxPointerLSB; |
reg [1:0] TxPointerLSB_rst; |
reg [31:2] RxPointerMSB; |
reg [1:0] RxPointerLSB_rst; |
reg BlockingIncrementTxPointer; |
reg [31:2] TxPointerMSB; |
reg [1:0] TxPointerLSB; |
reg [1:0] TxPointerLSB_rst; |
reg [31:2] RxPointerMSB; |
reg [1:0] RxPointerLSB_rst; |
|
wire RxBurstAcc; |
wire RxWordAcc; |
wire RxHalfAcc; |
wire RxByteAcc; |
wire RxBurstAcc; |
wire RxWordAcc; |
wire RxHalfAcc; |
wire RxByteAcc; |
|
|
|
wire ResetTxBDReady; |
reg BlockingTxStatusWrite_sync1; |
reg BlockingTxStatusWrite_sync2; |
reg BlockingTxStatusWrite_sync3; |
|
reg cyc_cleared; |
reg IncrTxPointer; |
|
reg [3:0] RxByteSel; |
wire MasterAccessFinished; |
|
reg LatchValidBytes; |
reg LatchValidBytes_q; |
|
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I |
reg ReadTxDataFromFifo_sync1; |
reg ReadTxDataFromFifo_sync2; |
reg ReadTxDataFromFifo_sync3; |
reg ReadTxDataFromFifo_syncb1; |
reg ReadTxDataFromFifo_syncb2; |
reg ReadTxDataFromFifo_syncb3; |
|
reg RxAbortSync1; |
reg RxAbortSync2; |
reg RxAbortSync3; |
reg RxAbortSync4; |
reg RxAbortSyncb1; |
reg RxAbortSyncb2; |
|
reg RxEnableWindow; |
|
wire SetWriteRxDataToFifo; |
|
|
reg WriteRxDataToFifoSync1; |
reg WriteRxDataToFifoSync2; |
reg WriteRxDataToFifoSync3; |
|
wire WriteRxDataToFifo_wb; |
// Receive fifo selection register - JB |
reg [3:0] rx_shift_ended_wb_shr; |
reg rx_ethside_fifo_sel /* synthesis syn_allow_retiming=0; syn_noprune=1; syn_keep=1 */; |
reg rx_wbside_fifo_sel /* synthesis syn_allow_retiming=0; syn_noprune=1; syn_keep=1 */; |
reg rx_discard_packet; |
|
|
reg LatchedRxStartFrm; |
reg SyncRxStartFrm; |
reg SyncRxStartFrm_q; |
reg SyncRxStartFrm_q2; |
wire RxFifoReset; |
|
wire [31:0] rx_fifo0_data_out; |
wire rx_fifo0_write; |
wire rx_fifo0_read; |
wire rx_fifo0_clear; |
wire rx_fifo0_full; |
wire rx_fifo0_afull; |
wire rx_fifo0_empty; |
wire rx_fifo0_aempty; |
|
|
wire [31:0] rx_fifo1_data_out; |
wire rx_fifo1_write; |
wire rx_fifo1_read; |
wire rx_fifo1_clear; |
wire rx_fifo1_full; |
wire rx_fifo1_afull; |
wire rx_fifo1_empty; |
wire rx_fifo1_aempty; |
|
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rx_fifo0_cnt; |
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rx_fifo1_cnt; |
|
|
wire TxError; |
wire RxError; |
|
wire write_rx_data_to_memory_wait; |
wire write_rx_data_to_memory_go; |
|
reg RxStatusWriteLatched; |
reg RxStatusWriteLatched_sync1; |
reg RxStatusWriteLatched_sync2; |
reg RxStatusWriteLatched_syncb1; |
reg RxStatusWriteLatched_syncb2; |
reg busy_wb; |
|
reg overflow_bug_reset; |
|
// Fix bug when overflow causes things to become a bit confused |
always @ (posedge WB_CLK_I) |
if (Reset) |
overflow_bug_reset <= 0; |
else |
overflow_bug_reset <= (rx_fifo1_empty & rx_fifo0_empty & |
!RxEnableWindow & !rx_wb_writeback_finished & |
!rx_wb_last_writes & RxEn & RxEn_q & |
(rx_ethside_fifo_sel != rx_wbside_fifo_sel)); |
|
always @(posedge overflow_bug_reset) |
$display("%t: %m overflow_bug_reset posedge",$time); |
|
|
`ifdef ETH_WISHBONE_B3 |
`ifndef BURST_4BEAT |
assign m_wb_bte_o = 2'b00; // Linear burst |
613,7 → 718,6
Flop <= ~Flop; |
end |
|
wire ResetTxBDReady; |
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse; |
|
// Latching READY status of the Tx buffer descriptor |
685,10 → 789,6
end |
|
|
reg BlockingTxStatusWrite_sync1; |
reg BlockingTxStatusWrite_sync2; |
reg BlockingTxStatusWrite_sync3; |
|
// Synchronizing BlockingTxStatusWrite to MTxClk |
always @ (posedge MTxClk or posedge Reset) |
begin |
768,27 → 868,21
begin |
if(TxLengthLt4) |
TxLength <= 16'h0; |
else |
if(TxPointerLSB_rst==2'h0) |
TxLength <= TxLength - 16'd4; // Length is subtracted at |
else if(TxPointerLSB_rst==2'h0) |
TxLength <= TxLength - 16'd4; // Length is subtracted at |
// the data request |
else |
if(TxPointerLSB_rst==2'h1) |
TxLength <= TxLength - 16'd3; // Length is subtracted |
else if(TxPointerLSB_rst==2'h1) |
TxLength <= TxLength - 16'd3; // Length is subtracted |
// at the data request |
else |
if(TxPointerLSB_rst==2'h2) |
TxLength <= TxLength - 16'd2; // Length is subtracted |
else if(TxPointerLSB_rst==2'h2) |
TxLength <= TxLength - 16'd2; // Length is subtracted |
// at the data request |
else |
if(TxPointerLSB_rst==2'h3) |
TxLength <= TxLength - 16'd1; // Length is subtracted |
else if(TxPointerLSB_rst==2'h3) |
TxLength <= TxLength - 16'd1; // Length is subtracted |
// at the data request |
end |
end |
|
|
|
//Latching length from the buffer descriptor; |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
802,10 → 896,7
assign TxLengthEq0 = TxLength == 0; |
assign TxLengthLt4 = TxLength < 4; |
|
reg cyc_cleared; |
reg IncrTxPointer; |
|
|
// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are |
// latched because TxPointerMSB is only used for word-aligned accesses. |
always @ (posedge WB_CLK_I or posedge Reset) |
854,10 → 945,6
end |
|
|
reg [3:0] RxByteSel; |
wire MasterAccessFinished; |
|
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
1344,9 → 1431,6
// Marks which bytes are valid within the word. |
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0; |
|
reg LatchValidBytes; |
reg LatchValidBytes_q; |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
1392,7 → 1476,9
|
|
// Temporary Tx and Rx buffer descriptor address |
assign TempTxBDAddress[7:1] = {7{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 1) ; // Tx BD increment or wrap (last BD) |
assign TempTxBDAddress[7:1] = {7{ TxStatusWrite & ~WrapTxStatusBit}} & |
(TxBDAddress + 1) ; // Tx BD increment or wrap |
// (last BD) |
|
assign TempRxBDAddress[7:1] = {7{ WrapRxStatusBit}} & (r_TxBDNum[6:0]) | // Using first Rx BD |
{7{~WrapRxStatusBit}} & (RxBDAddress + 1) ; // Using next Rx BD (incremenrement address) |
1746,15 → 1832,6
end |
|
|
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I |
reg ReadTxDataFromFifo_sync1; |
reg ReadTxDataFromFifo_sync2; |
reg ReadTxDataFromFifo_sync3; |
reg ReadTxDataFromFifo_syncb1; |
reg ReadTxDataFromFifo_syncb2; |
reg ReadTxDataFromFifo_syncb3; |
|
|
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
1877,13 → 1954,6
end |
|
|
reg RxAbortSync1; |
reg RxAbortSync2; |
reg RxAbortSync3; |
reg RxAbortSync4; |
reg RxAbortSyncb1; |
reg RxAbortSyncb2; |
|
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4 | |
r_RxEn & ~r_RxEn_q; |
|
1960,13 → 2030,11
begin |
if(Reset) |
RxBDOK <= 1'b0; |
else |
if(rx_wb_writeback_finished | RxAbortSync2 & ~RxAbortSync3 | |
~r_RxEn & r_RxEn_q) |
RxBDOK <= 1'b0; |
else |
if(RxBDReady) |
RxBDOK <= 1'b1; |
else if(rx_wb_writeback_finished | RxAbortSync2 & ~RxAbortSync3 | |
~r_RxEn & r_RxEn_q) |
RxBDOK <= 1'b0; |
else if(RxBDReady) |
RxBDOK <= 1'b1; |
end |
|
// Reading Rx BD pointer |
2033,12 → 2101,10
begin |
if(Reset) |
RxEn_needed <= 1'b0; |
else |
if(/*~RxReady &*/ r_RxEn & WbEn & ~WbEn_q) |
RxEn_needed <= 1'b1; |
else |
if(RxPointerRead & RxEn & RxEn_q) |
RxEn_needed <= 1'b0; |
else if(/*~RxReady &*/ r_RxEn & WbEn & ~WbEn_q) |
RxEn_needed <= 1'b1; |
else if(RxPointerRead & RxEn & RxEn_q) |
RxEn_needed <= 1'b0; |
end |
|
|
2046,8 → 2112,6
// of frame is detected. |
assign RxStatusWrite = rx_wb_writeback_finished & RxEn & RxEn_q; |
|
reg RxEnableWindow; |
|
// Indicating that last byte is being reveived |
always @ (posedge MRxClk or posedge Reset) |
begin |
2146,8 → 2210,6
end |
end |
|
wire SetWriteRxDataToFifo; |
|
// Assembling data that will be written to the rx_fifo |
always @ (posedge MRxClk or posedge Reset) |
begin |
2169,11 → 2231,6
end |
|
|
reg WriteRxDataToFifoSync1; |
reg WriteRxDataToFifoSync2; |
reg WriteRxDataToFifoSync3; |
|
|
// Indicating start of the reception process |
assign SetWriteRxDataToFifo = (RxValid & ~RxStartFrm & |
RxEnableWindow & (&RxByteCnt)) |
2222,14 → 2279,24
WriteRxDataToFifoSync3 <= WriteRxDataToFifoSync2; |
end |
|
wire WriteRxDataToFifo_wb; |
|
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 & |
~WriteRxDataToFifoSync3; |
// Receive fifo selection register - JB |
reg [3:0] rx_shift_ended_wb_shr; |
reg rx_ethside_fifo_sel /* synthesis syn_allow_retiming=0; syn_noprune=1; syn_keep=1 */; |
reg rx_wbside_fifo_sel /* synthesis syn_allow_retiming=0; syn_noprune=1; syn_keep=1 */; |
|
|
// Signal to indicate data in current buffer should be discarded as we had |
// no open buffer for it. |
// Goes high when rx_wb_last_writes goes off and we still haven't gotten a |
// RX buffer for it. |
always @(posedge WB_CLK_I) |
if (Reset) |
rx_discard_packet <= 0; |
else if (rx_shift_ended_wb_shr[3:2] == 2'b01) |
rx_discard_packet <= 0; |
else if (rx_wb_last_writes & RxBDRead) |
rx_discard_packet <= 1; |
|
|
// Shift in this - our detection of end of data RX |
always @(posedge WB_CLK_I) |
rx_shift_ended_wb_shr <= {rx_shift_ended_wb_shr[2:0], |
2239,8 → 2306,9
always @ (posedge WB_CLK_I or posedge Reset) |
if(Reset) |
rx_ethside_fifo_sel <= 0; |
else |
if(rx_shift_ended_wb_shr[3:2] == 2'b01) |
else if (rx_discard_packet | overflow_bug_reset) |
rx_ethside_fifo_sel <= 0; |
else if(rx_shift_ended_wb_shr[3:2] == 2'b01 & !rx_discard_packet) |
// Switch over whenever we've finished receiving last frame's data |
rx_ethside_fifo_sel <= ~rx_ethside_fifo_sel; |
|
2249,17 → 2317,12
always @ (posedge WB_CLK_I or posedge Reset) |
if(Reset) |
rx_wbside_fifo_sel <= 0; |
else |
if(rx_wb_writeback_finished & RxEn & RxEn_q) |
// Switch over whenever we've finished receiving last frame's data |
rx_wbside_fifo_sel <= ~rx_wbside_fifo_sel; |
else if (rx_discard_packet | overflow_bug_reset) |
rx_wbside_fifo_sel <= 0; |
else if(rx_wb_writeback_finished & RxEn & RxEn_q) |
// Switch over whenever we've finished receiving last frame's data |
rx_wbside_fifo_sel <= ~rx_wbside_fifo_sel; |
|
reg LatchedRxStartFrm; |
reg SyncRxStartFrm; |
reg SyncRxStartFrm_q; |
reg SyncRxStartFrm_q2; |
wire RxFifoReset; |
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
2304,31 → 2367,9
assign rx_startfrm_wb = SyncRxStartFrm_q & ~SyncRxStartFrm_q2; |
|
|
assign RxFifoReset = rx_startfrm_wb; |
assign RxFifoReset = rx_startfrm_wb | rx_discard_packet | overflow_bug_reset; |
|
|
|
wire [31:0] rx_fifo0_data_out; |
wire rx_fifo0_write; |
wire rx_fifo0_read; |
wire rx_fifo0_clear; |
wire rx_fifo0_full; |
wire rx_fifo0_afull; |
wire rx_fifo0_empty; |
wire rx_fifo0_aempty; |
|
|
wire [31:0] rx_fifo1_data_out; |
wire rx_fifo1_write; |
wire rx_fifo1_read; |
wire rx_fifo1_clear; |
wire rx_fifo1_full; |
wire rx_fifo1_afull; |
wire rx_fifo1_empty; |
wire rx_fifo1_aempty; |
|
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rx_fifo0_cnt; |
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rx_fifo1_cnt; |
|
// RX FIFO buffer 0 controls |
assign rx_fifo0_write = (!rx_ethside_fifo_sel) & WriteRxDataToFifo_wb & |
~rx_fifo0_full; |
2406,13 → 2447,9
rx_fifo1_full : rx_fifo0_full; |
|
|
|
|
|
wire write_rx_data_to_memory_wait; |
assign write_rx_data_to_memory_wait = !RxBDOK | RxPointerRead; |
wire write_rx_data_to_memory_go; |
|
|
`ifdef ETH_RX_BURST_EN |
assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=(`ETH_BURST_LENGTH); |
assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>(`ETH_BURST_LENGTH - 1); |
2471,6 → 2508,8
rx_wb_last_writes <= ShiftEndedSync1 & ~ShiftEndedSync2; |
else if (rx_wb_writeback_finished & RxEn & RxEn_q) |
rx_wb_last_writes <= 0; |
else if (rx_discard_packet | overflow_bug_reset) |
rx_wb_last_writes <= 0; |
|
// Pulse indicating last of RX data has been written out |
always @ (posedge WB_CLK_I or posedge Reset) |
2504,12 → 2543,10
begin |
if(Reset) |
RxEnableWindow <= 1'b0; |
else |
if(RxStartFrm) |
RxEnableWindow <= 1'b1; |
else |
if(RxEndFrm | RxAbort) |
RxEnableWindow <= 1'b0; |
else if(RxStartFrm) |
RxEnableWindow <= 1'b1; |
else if(RxEndFrm | RxAbort) |
RxEnableWindow <= 1'b0; |
end |
|
|
2585,7 → 2622,15
end |
|
|
assign RxStatusIn = {ReceivedPauseFrm, AddressMiss, RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision}; |
assign RxStatusIn = {ReceivedPauseFrm, |
AddressMiss, |
RxOverrun, |
InvalidSymbol, |
DribbleNibble, |
ReceivedPacketTooBig, |
ShortFrame, |
LatchedCrcError, |
RxLateCollision}; |
|
always @ (posedge MRxClk or posedge Reset) |
begin |
2602,20 → 2647,17
begin |
if(Reset) |
RxOverrun <= 1'b0; |
else |
if(RxStatusWrite) |
RxOverrun <= 1'b0; |
else |
if(RxBufferFull & WriteRxDataToFifo_wb) |
RxOverrun <= 1'b1; |
else if(RxStatusWrite | rx_discard_packet | overflow_bug_reset) |
RxOverrun <= 1'b0; |
else if(RxBufferFull & WriteRxDataToFifo_wb) |
RxOverrun <= 1'b1; |
end |
|
|
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | |
CarrierSenseLost; |
|
wire TxError; |
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost; |
|
wire RxError; |
|
// ShortFrame (RxStatusInLatched[2]) can not set an error because short |
// frames are aborted when signal r_RecSmall is set to 0 in MODER register. |
2624,14 → 2666,6
assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]); |
|
|
|
reg RxStatusWriteLatched; |
reg RxStatusWriteLatched_sync1; |
reg RxStatusWriteLatched_sync2; |
reg RxStatusWriteLatched_syncb1; |
reg RxStatusWriteLatched_syncb2; |
|
|
// Latching and synchronizing RxStatusWrite signal. This signal is used for |
// clearing the ReceivedPauseFrm signal |
always @ (posedge WB_CLK_I or posedge Reset) |
2746,7 → 2780,6
|
|
|
reg busy_wb; |
always @ (posedge WB_CLK_I or posedge Reset) |
if(Reset) |
busy_wb <= 0; |
2783,21 → 2816,25
assign dbg_dat0[26:24] = tx_burst_cnt; |
|
// Third byte |
assign dbg_dat0[23] = 0; |
assign dbg_dat0[22] = 0; |
assign dbg_dat0[21] = rx_burst; |
assign dbg_dat0[20] = rx_burst_en; |
assign dbg_dat0[19] = 0; |
assign dbg_dat0[18] = 0; |
assign dbg_dat0[17] = tx_burst; |
assign dbg_dat0[16] = tx_burst_en; |
assign dbg_dat0[23] = rx_ethside_fifo_sel; |
assign dbg_dat0[22] = rx_wbside_fifo_sel; |
assign dbg_dat0[21] = rx_fifo0_empty; |
assign dbg_dat0[20] = rx_fifo1_empty; |
assign dbg_dat0[19] = overflow_bug_reset; |
assign dbg_dat0[18] = RxBDOK; |
assign dbg_dat0[17] = write_rx_data_to_memory_go; |
assign dbg_dat0[16] = rx_wb_last_writes; |
// Second byte - TxBDAddress - or TX BD address pointer |
assign dbg_dat0[15:8] = { 1'b0, TxBDAddress}; |
assign dbg_dat0[15:8] = { BlockingTxBDRead , TxBDAddress}; |
// Bottom byte - FSM controlling vector |
assign dbg_dat0[7:0] = {MasterWbTX,MasterWbRX, |
ReadTxDataFromMemory_2,WriteRxDataToMemory, |
MasterAccessFinished,cyc_cleared, |
tx_burst,rx_burst}; |
assign dbg_dat0[7:0] = {MasterWbTX, |
MasterWbRX, |
ReadTxDataFromMemory_2, |
WriteRxDataToMemory, |
MasterAccessFinished, |
cyc_cleared, |
tx_burst, |
rx_burst}; |
|
`endif |
|
/verilog/ethmac/eth_fifo.v
45,44 → 45,49
module eth_fifo (data_in, data_out, clk, reset, write, read, clear, |
almost_full, full, almost_empty, empty, cnt); |
|
parameter DATA_WIDTH = 32; |
parameter DEPTH = 8; |
parameter CNT_WIDTH = 3; |
parameter DATA_WIDTH = 32; |
parameter DEPTH = 8; |
parameter CNT_WIDTH = 3; |
|
input clk; |
input reset; |
input write; |
input read; |
input clear; |
input [DATA_WIDTH-1:0] data_in; |
input clk; |
input reset; |
input write; |
input read; |
input clear; |
input [DATA_WIDTH-1:0] data_in; |
|
output [DATA_WIDTH-1:0] data_out; |
output almost_full; |
output full; |
output almost_empty; |
output empty; |
output [CNT_WIDTH-1:0] cnt; |
output [DATA_WIDTH-1:0] data_out; |
output almost_full; |
output full; |
output almost_empty; |
output empty; |
output [CNT_WIDTH-1:0] cnt; |
|
|
reg [CNT_WIDTH-1:0] read_pointer; |
reg [CNT_WIDTH-1:0] cnt; |
reg final_read; |
reg [CNT_WIDTH-1:0] read_pointer; |
reg [CNT_WIDTH-1:0] cnt; |
|
always @ (posedge clk or posedge reset) |
begin |
if(reset) |
cnt <= 0; |
else |
if(clear) |
cnt <= { {(CNT_WIDTH-1){1'b0}}, read^write}; |
else |
if(read ^ write) |
if(read) |
cnt <= cnt - 1; |
else |
cnt <= cnt + 1; |
end |
always @ (posedge clk or posedge reset) |
begin |
if(reset) |
cnt <= 0; |
else |
if(clear) |
cnt <= { {(CNT_WIDTH-1){1'b0}}, read^write}; |
else |
if(read ^ write) |
if(read) |
cnt <= cnt - 1; |
else |
cnt <= cnt + 1; |
end |
|
|
assign empty = ~(|cnt); |
assign almost_empty = cnt==1; |
assign full = {{32-CNT_WIDTH{1'b0}},cnt} == (DEPTH-1); |
assign almost_full = {{32-CNT_WIDTH{1'b0}},cnt} == (DEPTH-2); |
|
|
`ifdef ETH_FIFO_GENERIC |
|
90,11 → 95,11
|
|
// This should make the synthesis tool infer a RAM |
reg [CNT_WIDTH-1:0] waddr, raddr, raddr_reg; |
reg clear_reg; // Register the clear pulse |
reg [CNT_WIDTH-1:0] waddr, raddr, raddr_reg; |
reg clear_reg; // Register the clear pulse |
|
reg fallthrough_read; |
reg [CNT_WIDTH-1:0] fallthrough_read_addr; |
reg fallthrough_read; |
reg [CNT_WIDTH-1:0] fallthrough_read_addr; |
|
|
always @(posedge clk) |
106,7 → 111,7
always @(posedge clk) |
if (empty & write) |
fallthrough_read_addr <= waddr; |
|
|
always @(posedge clk) |
if (reset) |
waddr <= 0; |
137,163 → 142,231
|
assign data_out = fifo[raddr_reg]; |
|
always @ (posedge clk or posedge reset) |
begin |
if(reset) |
read_pointer <= 0; |
else |
if(clear) |
// Begin read pointer at 1 |
read_pointer <= { {(CNT_WIDTH-1){1'b0}}, 1'b1}; |
else |
if(read & ~empty) |
read_pointer <= read_pointer + 1'b1; |
end |
|
always @(posedge clk) |
if (reset) |
final_read <= 0; |
else if (final_read & read & !write) |
final_read <= ~final_read; |
else if ((cnt == 1) & read & !write) |
final_read <= 1; // Indicate last read data has been output |
|
assign empty = ~(|cnt); |
assign almost_empty = cnt==1; |
assign full = {{32-CNT_WIDTH{1'b0}},cnt} == (DEPTH-1); |
//assign almost_full = &cnt[CNT_WIDTH-1:0]; |
assign almost_full = {{32-CNT_WIDTH{1'b0}},cnt} == (DEPTH-2); |
|
`else // !`ifdef ETH_FIFO_GENERIC |
|
reg [CNT_WIDTH-1:0] write_pointer; |
|
always @ (posedge clk or posedge reset) |
begin |
if(reset) |
read_pointer <= 0; |
else |
if(clear) |
// Begin read pointer at 1 |
read_pointer <= { {(CNT_WIDTH-1){1'b0}}, 1'b1}; |
else |
if(read & ~empty) |
read_pointer <= read_pointer + 1'b1; |
end |
|
always @ (posedge clk or posedge reset) |
begin |
if(reset) |
read_pointer <= 0; |
else |
if(clear) |
read_pointer <= { {(CNT_WIDTH-1){1'b0}}, read}; |
else |
if(read & ~empty) |
read_pointer <= read_pointer + 1'b1; |
end |
|
`else // !`ifdef ETH_FIFO_GENERIC |
always @ (posedge clk or posedge reset) |
begin |
if(reset) |
write_pointer <= 0; |
else |
if(clear) |
write_pointer <= { {(CNT_WIDTH-1){1'b0}}, write}; |
else |
if(write & ~full) |
write_pointer <= write_pointer + 1'b1; |
end // always @ (posedge clk or posedge reset) |
|
reg [CNT_WIDTH-1:0] write_pointer; |
`endif // !`ifdef ETH_FIFO_GENERIC |
|
`ifdef ETH_FIFO_XILINX |
|
generate |
if (CNT_WIDTH==4) |
begin |
xilinx_dist_ram_16x32 fifo |
( .data_out(data_out), |
.we(write & ~full), |
.data_in(data_in), |
.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]), |
.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]), |
.wclk(clk) |
); |
end // if (CNT_WIDTH==4) |
else if (CNT_WIDTH==6) |
begin |
|
always @ (posedge clk or posedge reset) |
begin |
if(reset) |
read_pointer <= 0; |
else |
if(clear) |
read_pointer <= { {(CNT_WIDTH-1){1'b0}}, read}; |
else |
if(read & ~empty) |
read_pointer <= read_pointer + 1'b1; |
end |
wire [DATA_WIDTH-1:0] data_out0; |
wire [DATA_WIDTH-1:0] data_out1; |
wire [DATA_WIDTH-1:0] data_out2; |
wire [DATA_WIDTH-1:0] data_out3; |
|
wire we_ram0,we_ram1,we_ram2,we_ram3; |
|
always @ (posedge clk or posedge reset) |
begin |
if(reset) |
write_pointer <= 0; |
else |
if(clear) |
write_pointer <= { {(CNT_WIDTH-1){1'b0}}, write}; |
else |
if(write & ~full) |
write_pointer <= write_pointer + 1'b1; |
end |
assign we_ram0 = (write_pointer[5:4]==2'b00); |
assign we_ram1 = (write_pointer[5:4]==2'b01); |
assign we_ram2 = (write_pointer[5:4]==2'b10); |
assign we_ram3 = (write_pointer[5:4]==2'b11); |
|
assign data_out = (read_pointer[5:4]==2'b11) ? data_out3 : |
(read_pointer[5:4]==2'b10) ? data_out2 : |
(read_pointer[5:4]==2'b01) ? data_out1 : data_out0; |
|
xilinx_dist_ram_16x32 fifo0 |
( .data_out(data_out0), |
.we(write & ~full & we_ram0), |
.data_in(data_in), |
.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]), |
.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]), |
.wclk(clk) |
); |
|
xilinx_dist_ram_16x32 fifo1 |
( .data_out(data_out1), |
.we(write & ~full & we_ram1), |
.data_in(data_in), |
.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]), |
.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]), |
.wclk(clk) |
); |
|
`ifdef ETH_FIFO_XILINX |
|
generate |
if (CNT_WIDTH==4) |
begin |
xilinx_dist_ram_16x32 fifo |
( .data_out(data_out), |
.we(write & ~full), |
.data_in(data_in), |
.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]), |
.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]), |
.wclk(clk) |
); |
end // if (CNT_WIDTH==4) |
else if (CNT_WIDTH==6) |
begin |
xilinx_dist_ram_16x32 fifo2 |
( .data_out(data_out2), |
.we(write & ~full & we_ram2), |
.data_in(data_in), |
.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]), |
.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]), |
.wclk(clk) |
); |
|
xilinx_dist_ram_16x32 fifo3 |
( .data_out(data_out3), |
.we(write & ~full & we_ram3), |
.data_in(data_in), |
.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]), |
.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]), |
.wclk(clk) |
); |
end // if (CNT_WIDTH==6) |
|
endgenerate |
`endif // `ifdef ETH_FIFO_XILINX |
|
wire [DATA_WIDTH-1:0] data_out0; |
wire [DATA_WIDTH-1:0] data_out1; |
wire [DATA_WIDTH-1:0] data_out2; |
wire [DATA_WIDTH-1:0] data_out3; |
|
wire we_ram0,we_ram1,we_ram2,we_ram3; |
`ifdef ETH_FIFO_RAMB18 |
|
assign we_ram0 = (write_pointer[5:4]==2'b00); |
assign we_ram1 = (write_pointer[5:4]==2'b01); |
assign we_ram2 = (write_pointer[5:4]==2'b10); |
assign we_ram3 = (write_pointer[5:4]==2'b11); |
|
assign data_out = (read_pointer[5:4]==2'b11) ? data_out3 : |
(read_pointer[5:4]==2'b10) ? data_out2 : |
(read_pointer[5:4]==2'b01) ? data_out1 : data_out0; |
|
xilinx_dist_ram_16x32 fifo0 |
( .data_out(data_out0), |
.we(write & ~full & we_ram0), |
.data_in(data_in), |
.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]), |
.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]), |
.wclk(clk) |
); |
|
xilinx_dist_ram_16x32 fifo1 |
( .data_out(data_out1), |
.we(write & ~full & we_ram1), |
.data_in(data_in), |
.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]), |
.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]), |
.wclk(clk) |
); |
|
xilinx_dist_ram_16x32 fifo2 |
( .data_out(data_out2), |
.we(write & ~full & we_ram2), |
.data_in(data_in), |
.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]), |
.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]), |
.wclk(clk) |
); |
|
xilinx_dist_ram_16x32 fifo3 |
( .data_out(data_out3), |
.we(write & ~full & we_ram3), |
.data_in(data_in), |
.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]), |
.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]), |
.wclk(clk) |
); |
end // if (CNT_WIDTH==6) |
endgenerate |
wire [8:0] read_pointer_to_xilinx_ram; |
wire [8:0] read_pointer_preincremented; |
assign read_pointer_preincremented = read_pointer + 1; |
|
assign read_pointer_to_xilinx_ram = (read) ? |
read_pointer_preincremented : |
read_pointer; |
|
|
|
wire [8:0] write_pointer_to_xilinx_ram; |
assign write_pointer_to_xilinx_ram = {{(9-CNT_WIDTH){1'b0}},write_pointer}; |
|
`else // !ETH_FIFO_XILINX |
`ifdef ETH_ALTERA_ALTSYNCRAM |
altera_dpram_16x32 altera_dpram_16x32_inst |
( |
.data (data_in), |
.wren (write & ~full), |
.wraddress (clear ? {CNT_WIDTH-1{1'b0}} : write_pointer), |
.rdaddress (clear ? {CNT_WIDTH-1{1'b0}} : read_pointer ), |
.clock (clk), |
.q (data_out) |
); //exemplar attribute altera_dpram_16x32_inst NOOPT TRUE |
`endif // `ifdef ETH_ALTERA_ALTSYNCRAM |
`endif // !`ifdef ETH_FIFO_XILINX |
|
// synthesis translate_off |
// Port A - Write |
// Port B - Rread |
BLK_MEM_GEN_V3_1 #( |
.C_ADDRA_WIDTH(9), |
.C_ADDRB_WIDTH(9), |
.C_ALGORITHM(1), |
.C_BYTE_SIZE(9), |
.C_COMMON_CLK(0), |
.C_DEFAULT_DATA("0"), |
.C_DISABLE_WARN_BHV_COLL(0), |
.C_DISABLE_WARN_BHV_RANGE(0), |
.C_FAMILY("virtex5"), |
.C_HAS_ENA(0), |
.C_HAS_ENB(0), |
.C_HAS_INJECTERR(0), |
.C_HAS_MEM_OUTPUT_REGS_A(0), |
.C_HAS_MEM_OUTPUT_REGS_B(0), |
.C_HAS_MUX_OUTPUT_REGS_A(0), |
.C_HAS_MUX_OUTPUT_REGS_B(0), |
.C_HAS_REGCEA(0), |
.C_HAS_REGCEB(0), |
.C_HAS_RSTA(0), |
.C_HAS_RSTB(0), |
.C_INITA_VAL("0"), |
.C_INITB_VAL("0"), |
.C_INIT_FILE_NAME("no_coe_file_loaded"), |
.C_LOAD_INIT_FILE(0), |
.C_MEM_TYPE(1), |
.C_MUX_PIPELINE_STAGES(0), |
.C_PRIM_TYPE(1), |
.C_READ_DEPTH_A(512), |
.C_READ_DEPTH_B(512), |
.C_READ_WIDTH_A(32), |
.C_READ_WIDTH_B(32), |
.C_RSTRAM_A(0), |
.C_RSTRAM_B(0), |
.C_RST_PRIORITY_A("CE"), |
.C_RST_PRIORITY_B("CE"), |
.C_RST_TYPE("SYNC"), |
.C_SIM_COLLISION_CHECK("WARNING_ONLY"), |
.C_USE_BYTE_WEA(0), |
.C_USE_BYTE_WEB(0), |
.C_USE_DEFAULT_DATA(0), |
.C_USE_ECC(0), |
.C_WEA_WIDTH(1), |
.C_WEB_WIDTH(1), |
.C_WRITE_DEPTH_A(512), |
.C_WRITE_DEPTH_B(512), |
.C_WRITE_MODE_A("WRITE_FIRST"), |
.C_WRITE_MODE_B("READ_FIRST"), |
.C_WRITE_WIDTH_A(32), |
.C_WRITE_WIDTH_B(32), |
.C_XDEVICEFAMILY("virtex5")) |
inst ( |
.CLKA(clk), |
.WEA(write), |
.ADDRA(write_pointer_to_xilinx_ram), |
.DINA(data_in), |
.CLKB(clk), |
.ADDRB(read_pointer_to_xilinx_ram), |
.DOUTB(data_out), |
.RSTA(reset), |
.ENA(), |
.REGCEA(), |
.DOUTA(), |
.RSTB(), |
.ENB(), |
.REGCEB(), |
.WEB(), |
.DINB(), |
.INJECTSBITERR(), |
.INJECTDBITERR(), |
.SBITERR(), |
.DBITERR(), |
.RDADDRECC() |
); |
// synthesis translate_on |
`endif // `ifdef ETH_FIFO_RAMB18 |
|
assign empty = ~(|cnt); |
assign almost_empty = cnt == 1; |
assign full = cnt == (DEPTH-1); |
assign almost_full = &cnt[CNT_WIDTH-1:0]; |
|
`endif // !`ifdef ETH_FIFO_GENERIC |
|
`ifdef ETH_ALTERA_ALTSYNCRAM |
altera_dpram_16x32 altera_dpram_16x32_inst |
( |
.data (data_in), |
.wren (write & ~full), |
.wraddress (clear ? {CNT_WIDTH-1{1'b0}} : write_pointer), |
.rdaddress (clear ? {CNT_WIDTH-1{1'b0}} : read_pointer ), |
.clock (clk), |
.q (data_out) |
); //exemplar attribute altera_dpram_16x32_inst NOOPT TRUE |
`endif // `ifdef ETH_ALTERA_ALTSYNCRAM |
|
|
endmodule // eth_fifo |
|
endmodule |