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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/orpsocv2/rtl
    from Rev 58 to Rev 63
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  •

Rev 58 → Rev 63

/verilog/or1200_defines.v
514,7 → 514,7
//
// To implement divide, multiplier needs to be implemented.
//
//`define OR1200_IMPL_DIV
`define OR1200_IMPL_DIV
 
//
// Implement rotate in the ALU
572,7 → 572,7
//
// Implement HW Single Precision FPU
//
//`define OR1200_FPU_IMPLEMENTED
`define OR1200_FPU_IMPLEMENTED
 
//
// Clock ratio RISC clock versus WB clock
751,7 → 751,11
//
`ifdef OR1200_FPU_IMPLEMENTED
`define OR1200_FPUOP_WIDTH 8
/* FPU unit from Usselman takes 5 cycles from decode, so 4 ex. cycles */
`define OR1200_FPUOP_CYCLES 3'd4
/* FP instruction is double precision if bit 4 is set. We're a 32-bit
implementation thus do not support double precision FP */
`define OR1200_FPUOP_DOUBLE_BIT 4
`define OR1200_FPUOP_ADD 8'b0000_0000
`define OR1200_FPUOP_SUB 8'b0000_0001
`define OR1200_FPUOP_MUL 8'b0000_0010
/verilog/components/wb_conbus/wb_conbus_top.v
369,7 → 369,7
//
 
wire [`mselectw -1:0] i_gnt_arb;
wire [2:0] gnt;
wire [2:0] gnt/* verilator public */;
reg [`sselectw -1:0] i_ssel_dec;
`ifdef WB_USE_TRISTATE
wire [`mbusw -1:0] i_bus_m;
639,7 → 639,7
//////////////////////////////////
// address decode logic
//
wire [7:0] m0_ssel_dec, m1_ssel_dec, m2_ssel_dec, m3_ssel_dec, m4_ssel_dec, m5_ssel_dec, m6_ssel_dec, m7_ssel_dec;
wire [7:0] m0_ssel_dec, m1_ssel_dec, m2_ssel_dec, m3_ssel_dec, m4_ssel_dec, m5_ssel_dec, m6_ssel_dec, m7_ssel_dec ;
always @(gnt, m0_ssel_dec, m1_ssel_dec, m2_ssel_dec, m3_ssel_dec, m4_ssel_dec, m5_ssel_dec, m6_ssel_dec, m7_ssel_dec)
case(gnt)
3'h0: i_ssel_dec = m0_ssel_dec;
762,4 → 762,170
//assign i_ssel_dec[7] = (i_bus_m[`mbusw -1 : `mbusw - s27_addr_w ] == s7_addr);
 
 
`ifdef verilator
// Access functions for verilator, hardcoded to dw=32, aw=32
 
// Master Signal Access functions
wire [`dw-1:0] m_dat_i[0:`mselectw-1] /* verilator public */;
assign m_dat_i[0] = m0_dat_i;
assign m_dat_i[1] = m1_dat_i;
assign m_dat_i[2] = m2_dat_i;
assign m_dat_i[3] = m3_dat_i;
assign m_dat_i[4] = m4_dat_i;
assign m_dat_i[5] = m5_dat_i;
assign m_dat_i[6] = m6_dat_i;
assign m_dat_i[7] = m7_dat_i;
wire [`dw-1:0] m_dat_o[0:`mselectw-1]/* verilator public */;
assign m_dat_o[0] = m0_dat_o;
assign m_dat_o[1] = m1_dat_o;
assign m_dat_o[2] = m2_dat_o;
assign m_dat_o[3] = m3_dat_o;
assign m_dat_o[4] = m4_dat_o;
assign m_dat_o[5] = m5_dat_o;
assign m_dat_o[6] = m6_dat_o;
assign m_dat_o[7] = m7_dat_o;
wire [`aw-1:0] m_adr_i[0:`mselectw-1]/* verilator public */;
assign m_adr_i[0] = m0_adr_i;
assign m_adr_i[1] = m1_adr_i;
assign m_adr_i[2] = m2_adr_i;
assign m_adr_i[3] = m3_adr_i;
assign m_adr_i[4] = m4_adr_i;
assign m_adr_i[5] = m5_adr_i;
assign m_adr_i[6] = m6_adr_i;
assign m_adr_i[7] = m7_adr_i;
wire [`sw-1:0] m_sel_i[0:`mselectw-1]/* verilator public */;
assign m_sel_i[0] = m0_sel_i;
assign m_sel_i[1] = m1_sel_i;
assign m_sel_i[2] = m2_sel_i;
assign m_sel_i[3] = m3_sel_i;
assign m_sel_i[4] = m4_sel_i;
assign m_sel_i[5] = m5_sel_i;
assign m_sel_i[6] = m6_sel_i;
assign m_sel_i[7] = m7_sel_i;
wire [`mselectw-1:0] m_we_i/* verilator public */;
assign m_we_i[0] = m0_we_i;
assign m_we_i[1] = m1_we_i;
assign m_we_i[2] = m2_we_i;
assign m_we_i[3] = m3_we_i;
assign m_we_i[4] = m4_we_i;
assign m_we_i[5] = m5_we_i;
assign m_we_i[6] = m6_we_i;
assign m_we_i[7] = m7_we_i;
wire [`mselectw-1:0] m_cyc_i/* verilator public */;
assign m_cyc_i[0] = m0_cyc_i;
assign m_cyc_i[1] = m1_cyc_i;
assign m_cyc_i[2] = m2_cyc_i;
assign m_cyc_i[3] = m3_cyc_i;
assign m_cyc_i[4] = m4_cyc_i;
assign m_cyc_i[5] = m5_cyc_i;
assign m_cyc_i[6] = m6_cyc_i;
assign m_cyc_i[7] = m7_cyc_i;
wire [`mselectw-1:0] m_stb_i/* verilator public */;
assign m_stb_i[0] = m0_stb_i;
assign m_stb_i[1] = m1_stb_i;
assign m_stb_i[2] = m2_stb_i;
assign m_stb_i[3] = m3_stb_i;
assign m_stb_i[4] = m4_stb_i;
assign m_stb_i[5] = m5_stb_i;
assign m_stb_i[6] = m6_stb_i;
assign m_stb_i[7] = m7_stb_i;
wire [`mselectw-1:0] m_ack_o/* verilator public */;
assign m_ack_o[0] = m0_ack_o;
assign m_ack_o[1] = m1_ack_o;
assign m_ack_o[2] = m2_ack_o;
assign m_ack_o[3] = m3_ack_o;
assign m_ack_o[4] = m4_ack_o;
assign m_ack_o[5] = m5_ack_o;
assign m_ack_o[6] = m6_ack_o;
assign m_ack_o[7] = m7_ack_o;
wire [`mselectw-1:0] m_err_o/* verilator public */;
assign m_err_o[0] = m0_err_o;
assign m_err_o[1] = m1_err_o;
assign m_err_o[2] = m2_err_o;
assign m_err_o[3] = m3_err_o;
assign m_err_o[4] = m4_err_o;
assign m_err_o[5] = m5_err_o;
assign m_err_o[6] = m6_err_o;
assign m_err_o[7] = m7_err_o;
 
wire [7:0] m_ssel_dec [0:7]/* verilator public*/;
assign m_ssel_dec[0] = m0_ssel_dec;
assign m_ssel_dec[1] = m1_ssel_dec;
assign m_ssel_dec[2] = m2_ssel_dec;
assign m_ssel_dec[3] = m3_ssel_dec;
assign m_ssel_dec[4] = m4_ssel_dec;
assign m_ssel_dec[5] = m5_ssel_dec;
assign m_ssel_dec[6] = m6_ssel_dec;
assign m_ssel_dec[7] = m7_ssel_dec;
 
// Arbiter's grant signal
function [2:0] get_gnt;
// verilator public
get_gnt = gnt;
endfunction
 
function [31:0] get_m_dat_i;
// verilator public
input [2:0] mast_no;
get_m_dat_i = m_dat_i[mast_no];
endfunction // get_m_dat_i
function [31:0] get_m_dat_o;
// verilator public
input [2:0] mast_no;
get_m_dat_o = m_dat_o[mast_no];
endfunction // get_m_dat_o
function [31:0] get_m_adr_i;
// verilator public
input [2:0] mast_no;
get_m_adr_i = m_adr_i[mast_no];
endfunction // get_m_adr_i
function [3:0] get_m_sel_i;
// verilator public
input [2:0] mast_no;
get_m_sel_i = m_sel_i[mast_no];
endfunction // get_m_sel_i
function get_m_we_i;
// verilator public
input [2:0] mast_no;
get_m_we_i = m_we_i[mast_no];
endfunction // get_m_we_i
function get_m_cyc_i;
// verilator public
input [2:0] mast_no;
get_m_cyc_i = m_cyc_i[mast_no];
endfunction // get_m_cyc_i
function get_m_stb_i;
// verilator public
input [2:0] mast_no;
get_m_stb_i = m_stb_i[mast_no];
endfunction // get_m_stb_i
function get_m_ack_o;
// verilator public
input [2:0] mast_no;
get_m_ack_o = m_ack_o[mast_no];
endfunction // get_m_ack_o
function get_m_err_o;
// verilator public
input [2:0] mast_no;
get_m_err_o = m_err_o[mast_no];
endfunction // get_m_err_o
// Decoded slave for each master's access
function [7:0] get_m_ssel_dec;
// verilator public
input [2:0] mast_no;
get_m_ssel_dec = m_ssel_dec[mast_no];
endfunction
`endif
endmodule
/verilog/components/debug_if/dbg_cpu.v
280,7 → 280,7
dr[31:0] <= #1 input_data[31:0];
latch_data <= #1 1'b1;
end
else
else if (enable)
begin
dr[31:0] <= #1 {dr[30:0], 1'b0};
latch_data <= #1 1'b0;
/verilog/components/or1200r2/or1200_du.v
1111,6 → 1111,10
case (dcr0[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b000: match_cond0_stb = 1'b0; //comparison disabled
3'b001: match_cond0_stb = 1'b1; // insn fetch EA
3'b010: match_cond0_stb = dcpu_cycstb_i & ~dcpu_we_i;// load
3'b011: match_cond0_stb = dcpu_cycstb_i & dcpu_we_i;// store
3'b100: match_cond0_stb = dcpu_cycstb_i & ~dcpu_we_i;// load
3'b101: match_cond0_stb = dcpu_cycstb_i & dcpu_we_i;// store
default:match_cond0_stb = dcpu_cycstb_i; // any load/store
endcase
 
1185,7 → 1189,11
case (dcr1[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b000: match_cond1_stb = 1'b0; //comparison disabled
3'b001: match_cond1_stb = 1'b1; // insn fetch EA
default:match_cond1_stb = dcpu_cycstb_i; // any load/store
3'b010: match_cond1_stb = dcpu_cycstb_i & ~dcpu_we_i;// load
3'b011: match_cond1_stb = dcpu_cycstb_i & dcpu_we_i;// store
3'b100: match_cond1_stb = dcpu_cycstb_i & ~dcpu_we_i;// load
3'b101: match_cond1_stb = dcpu_cycstb_i & dcpu_we_i;// store
default:match_cond1_stb = dcpu_cycstb_i; // any load/store
endcase
 
//
1252,6 → 1260,11
case (dcr2[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b000: match_cond2_stb = 1'b0; //comparison disabled
3'b001: match_cond2_stb = 1'b1; // insn fetch EA
3'b010: match_cond2_stb = dcpu_cycstb_i & ~dcpu_we_i;// load
3'b011: match_cond2_stb = dcpu_cycstb_i & dcpu_we_i;// store
3'b100: match_cond2_stb = dcpu_cycstb_i & ~dcpu_we_i;// load
3'b101: match_cond2_stb = dcpu_cycstb_i & dcpu_we_i;// store
 
default:match_cond2_stb = dcpu_cycstb_i; // any load/store
endcase
 
1320,6 → 1333,11
case (dcr3[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b000: match_cond3_stb = 1'b0; //comparison disabled
3'b001: match_cond3_stb = 1'b1; // insn fetch EA
3'b010: match_cond3_stb = dcpu_cycstb_i & ~dcpu_we_i;// load
3'b011: match_cond3_stb = dcpu_cycstb_i & dcpu_we_i;// store
3'b100: match_cond3_stb = dcpu_cycstb_i & ~dcpu_we_i;// load
3'b101: match_cond3_stb = dcpu_cycstb_i & dcpu_we_i;// store
 
default:match_cond3_stb = dcpu_cycstb_i; // any load/store
endcase
 
1388,6 → 1406,11
case (dcr4[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b000: match_cond4_stb = 1'b0; //comparison disabled
3'b001: match_cond4_stb = 1'b1; // insn fetch EA
3'b010: match_cond4_stb = dcpu_cycstb_i & ~dcpu_we_i;// load
3'b011: match_cond4_stb = dcpu_cycstb_i & dcpu_we_i;// store
3'b100: match_cond4_stb = dcpu_cycstb_i & ~dcpu_we_i;// load
3'b101: match_cond4_stb = dcpu_cycstb_i & dcpu_we_i;// store
 
default:match_cond4_stb = dcpu_cycstb_i; // any load/store
endcase
 
1457,6 → 1480,11
case (dcr5[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b000: match_cond5_stb = 1'b0; //comparison disabled
3'b001: match_cond5_stb = 1'b1; // insn fetch EA
3'b010: match_cond5_stb = dcpu_cycstb_i & ~dcpu_we_i;// load
3'b011: match_cond5_stb = dcpu_cycstb_i & dcpu_we_i;// store
3'b100: match_cond5_stb = dcpu_cycstb_i & ~dcpu_we_i;// load
3'b101: match_cond5_stb = dcpu_cycstb_i & dcpu_we_i;// store
 
default:match_cond5_stb = dcpu_cycstb_i; // any load/store
endcase
 
1525,6 → 1553,11
case (dcr6[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b000: match_cond6_stb = 1'b0; //comparison disabled
3'b001: match_cond6_stb = 1'b1; // insn fetch EA
3'b010: match_cond6_stb = dcpu_cycstb_i & ~dcpu_we_i;// load
3'b011: match_cond6_stb = dcpu_cycstb_i & dcpu_we_i;// store
3'b100: match_cond6_stb = dcpu_cycstb_i & ~dcpu_we_i;// load
3'b101: match_cond6_stb = dcpu_cycstb_i & dcpu_we_i;// store
 
default:match_cond6_stb = dcpu_cycstb_i; // any load/store
endcase
 
1594,6 → 1627,11
case (dcr7[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b000: match_cond7_stb = 1'b0; //comparison disabled
3'b001: match_cond7_stb = 1'b1; // insn fetch EA
3'b010: match_cond7_stb = dcpu_cycstb_i & ~dcpu_we_i;// load
3'b011: match_cond7_stb = dcpu_cycstb_i & dcpu_we_i;// store
3'b100: match_cond7_stb = dcpu_cycstb_i & ~dcpu_we_i;// load
3'b101: match_cond7_stb = dcpu_cycstb_i & dcpu_we_i;// store
 
default:match_cond7_stb = dcpu_cycstb_i; // any load/store
endcase
/verilog/components/or1200r2/or1200_ctrl.v
684,9 → 684,6
`ifdef OR1200_MAC_IMPLEMENTED
`OR1200_OR32_MACMSB,
`endif
`ifdef OR1200_FPU_IMPLEMENTED
`OR1200_OR32_FLOAT,
`endif
`OR1200_OR32_SW,
`OR1200_OR32_SB,
`OR1200_OR32_SH,
697,7 → 694,13
`endif
`OR1200_OR32_NOP:
except_illegal <= #1 1'b0;
`ifdef OR1200_FPU_IMPLEMENTED
`OR1200_OR32_FLOAT:
/* Check it's not a double instruction */
except_illegal <= #1 id_insn[`OR1200_FPUOP_DOUBLE_BIT];
`endif
 
 
// Illegal and OR1200 unsupported instructions
default:
except_illegal <= #1 1'b1;
1115,6 → 1118,9
sig_trap <= #1 (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b010})
| du_hwbkpt;
end
else if (!sig_trap)
sig_trap <= #1 du_hwbkpt; // Added jb 091220 - because hw data load/store EA bkpts weren't getting triggered
end
 
endmodule
/verilog/orpsoc_top.v
679,7 → 679,7
`else // !`ifdef USE_SDRAM
parameter ram_wb_dat_width = 32;
parameter ram_wb_adr_width = 24;
parameter ram_wb_adr_width = 25;
//parameter ram_wb_mem_size = 2097152; // 8MB
parameter ram_wb_mem_size = 8388608; // 32MB -- for linux test
 

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