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verilog/components/ethernet/BUGS Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: verilog/components/ethernet/eth_cop.v =================================================================== --- verilog/components/ethernet/eth_cop.v (revision 67) +++ verilog/components/ethernet/eth_cop.v (nonexistent) @@ -1,403 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// eth_cop.v //// -//// //// -//// This file is part of the Ethernet IP core project //// -//// http://www.opencores.org/projects/ethmac/ //// -//// //// -//// Author(s): //// -//// - Igor Mohor (igorM@opencores.org) //// -//// //// -//// All additional information is avaliable in the Readme.txt //// -//// file. //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001, 2002 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: eth_cop.v,v $ -// Revision 1.4 2003/06/13 11:55:37 mohor -// Define file in eth_cop.v is changed to eth_defines.v. Some defines were -// moved from tb_eth_defines.v to eth_defines.v. -// -// Revision 1.3 2002/10/10 16:43:59 mohor -// Minor $display change. -// -// Revision 1.2 2002/09/09 12:54:13 mohor -// error acknowledge cycle termination added to display. -// -// Revision 1.1 2002/08/14 17:16:07 mohor -// Traffic cop with 2 wishbone master interfaces and 2 wishbona slave -// interfaces: -// - Host connects to the master interface -// - Ethernet master (DMA) connects to the second master interface -// - Memory interface connects to the slave interface -// - Ethernet slave interface (access to registers and BDs) connects to second -// slave interface -// -// -// -// -// - -`include "eth_defines.v" -`include "timescale.v" - -module eth_cop -( - // WISHBONE common - wb_clk_i, wb_rst_i, - - // WISHBONE MASTER 1 - m1_wb_adr_i, m1_wb_sel_i, m1_wb_we_i, m1_wb_dat_o, - m1_wb_dat_i, m1_wb_cyc_i, m1_wb_stb_i, m1_wb_ack_o, - m1_wb_err_o, - - // WISHBONE MASTER 2 - m2_wb_adr_i, m2_wb_sel_i, m2_wb_we_i, m2_wb_dat_o, - m2_wb_dat_i, m2_wb_cyc_i, m2_wb_stb_i, m2_wb_ack_o, - m2_wb_err_o, - - // WISHBONE slave 1 - s1_wb_adr_o, s1_wb_sel_o, s1_wb_we_o, s1_wb_cyc_o, - s1_wb_stb_o, s1_wb_ack_i, s1_wb_err_i, s1_wb_dat_i, - s1_wb_dat_o, - - // WISHBONE slave 2 - s2_wb_adr_o, s2_wb_sel_o, s2_wb_we_o, s2_wb_cyc_o, - s2_wb_stb_o, s2_wb_ack_i, s2_wb_err_i, s2_wb_dat_i, - s2_wb_dat_o -); - -parameter Tp=1; - -// WISHBONE common -input wb_clk_i, wb_rst_i; - -// WISHBONE MASTER 1 -input [31:0] m1_wb_adr_i, m1_wb_dat_i; -input [3:0] m1_wb_sel_i; -input m1_wb_cyc_i, m1_wb_stb_i, m1_wb_we_i; -output [31:0] m1_wb_dat_o; -output m1_wb_ack_o, m1_wb_err_o; - -// WISHBONE MASTER 2 -input [31:0] m2_wb_adr_i, m2_wb_dat_i; -input [3:0] m2_wb_sel_i; -input m2_wb_cyc_i, m2_wb_stb_i, m2_wb_we_i; -output [31:0] m2_wb_dat_o; -output m2_wb_ack_o, m2_wb_err_o; - -// WISHBONE slave 1 -input [31:0] s1_wb_dat_i; -input s1_wb_ack_i, s1_wb_err_i; -output [31:0] s1_wb_adr_o, s1_wb_dat_o; -output [3:0] s1_wb_sel_o; -output s1_wb_we_o, s1_wb_cyc_o, s1_wb_stb_o; - -// WISHBONE slave 2 -input [31:0] s2_wb_dat_i; -input s2_wb_ack_i, s2_wb_err_i; -output [31:0] s2_wb_adr_o, s2_wb_dat_o; -output [3:0] s2_wb_sel_o; -output s2_wb_we_o, s2_wb_cyc_o, s2_wb_stb_o; - -reg m1_in_progress; -reg m2_in_progress; -reg [31:0] s1_wb_adr_o; -reg [3:0] s1_wb_sel_o; -reg s1_wb_we_o; -reg [31:0] s1_wb_dat_o; -reg s1_wb_cyc_o; -reg s1_wb_stb_o; -reg [31:0] s2_wb_adr_o; -reg [3:0] s2_wb_sel_o; -reg s2_wb_we_o; -reg [31:0] s2_wb_dat_o; -reg s2_wb_cyc_o; -reg s2_wb_stb_o; - -reg m1_wb_ack_o; -reg [31:0] m1_wb_dat_o; -reg m2_wb_ack_o; -reg [31:0] m2_wb_dat_o; - -reg m1_wb_err_o; -reg m2_wb_err_o; - - // Added to allow compilation with Verilator - wire M1_ADDRESSED_S1_wire; - assign M1_ADDRESSED_S1_wire = `M1_ADDRESSED_S1; - wire M1_ADDRESSED_S2_wire; - assign M1_ADDRESSED_S2_wire = `M1_ADDRESSED_S2; - wire M2_ADDRESSED_S1_wire; - assign M2_ADDRESSED_S1_wire = `M2_ADDRESSED_S1; - wire M2_ADDRESSED_S2_wire; - assign M2_ADDRESSED_S2_wire = `M2_ADDRESSED_S2; - - -wire m_wb_access_finished; -wire m1_req = m1_wb_cyc_i & m1_wb_stb_i & (M1_ADDRESSED_S1_wire | M1_ADDRESSED_S2_wire); -wire m2_req = m2_wb_cyc_i & m2_wb_stb_i & (M2_ADDRESSED_S1_wire | M2_ADDRESSED_S2_wire); - -always @ (posedge wb_clk_i or posedge wb_rst_i) -begin - if(wb_rst_i) - begin - m1_in_progress <=#Tp 0; - m2_in_progress <=#Tp 0; - s1_wb_adr_o <=#Tp 0; - s1_wb_sel_o <=#Tp 0; - s1_wb_we_o <=#Tp 0; - s1_wb_dat_o <=#Tp 0; - s1_wb_cyc_o <=#Tp 0; - s1_wb_stb_o <=#Tp 0; - s2_wb_adr_o <=#Tp 0; - s2_wb_sel_o <=#Tp 0; - s2_wb_we_o <=#Tp 0; - s2_wb_dat_o <=#Tp 0; - s2_wb_cyc_o <=#Tp 0; - s2_wb_stb_o <=#Tp 0; - end - else - begin - case({m1_in_progress, m2_in_progress, m1_req, m2_req, m_wb_access_finished}) // synopsys_full_case synopsys_paralel_case - 5'b00_10_0, 5'b00_11_0 : - begin - m1_in_progress <=#Tp 1'b1; // idle: m1 or (m1 & m2) want access: m1 -> m - if(M1_ADDRESSED_S1_wire) - begin - s1_wb_adr_o <=#Tp m1_wb_adr_i; - s1_wb_sel_o <=#Tp m1_wb_sel_i; - s1_wb_we_o <=#Tp m1_wb_we_i; - s1_wb_dat_o <=#Tp m1_wb_dat_i; - s1_wb_cyc_o <=#Tp 1'b1; - s1_wb_stb_o <=#Tp 1'b1; - end - else if(M1_ADDRESSED_S2_wire) - begin - s2_wb_adr_o <=#Tp m1_wb_adr_i; - s2_wb_sel_o <=#Tp m1_wb_sel_i; - s2_wb_we_o <=#Tp m1_wb_we_i; - s2_wb_dat_o <=#Tp m1_wb_dat_i; - s2_wb_cyc_o <=#Tp 1'b1; - s2_wb_stb_o <=#Tp 1'b1; - end - else - $display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time); - end - 5'b00_01_0 : - begin - m2_in_progress <=#Tp 1'b1; // idle: m2 wants access: m2 -> m - if(M2_ADDRESSED_S1_wire) - begin - s1_wb_adr_o <=#Tp m2_wb_adr_i; - s1_wb_sel_o <=#Tp m2_wb_sel_i; - s1_wb_we_o <=#Tp m2_wb_we_i; - s1_wb_dat_o <=#Tp m2_wb_dat_i; - s1_wb_cyc_o <=#Tp 1'b1; - s1_wb_stb_o <=#Tp 1'b1; - end - else if(M2_ADDRESSED_S2_wire) - begin - s2_wb_adr_o <=#Tp m2_wb_adr_i; - s2_wb_sel_o <=#Tp m2_wb_sel_i; - s2_wb_we_o <=#Tp m2_wb_we_i; - s2_wb_dat_o <=#Tp m2_wb_dat_i; - s2_wb_cyc_o <=#Tp 1'b1; - s2_wb_stb_o <=#Tp 1'b1; - end - else - $display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time); - end - 5'b10_10_1, 5'b10_11_1 : - begin - m1_in_progress <=#Tp 1'b0; // m1 in progress. Cycle is finished. Send ack or err to m1. - if(M1_ADDRESSED_S1_wire) - begin - s1_wb_cyc_o <=#Tp 1'b0; - s1_wb_stb_o <=#Tp 1'b0; - end - else if(M1_ADDRESSED_S2_wire) - begin - s2_wb_cyc_o <=#Tp 1'b0; - s2_wb_stb_o <=#Tp 1'b0; - end - end - 5'b01_01_1, 5'b01_11_1 : - begin - m2_in_progress <=#Tp 1'b0; // m2 in progress. Cycle is finished. Send ack or err to m2. - if(M2_ADDRESSED_S1_wire) - begin - s1_wb_cyc_o <=#Tp 1'b0; - s1_wb_stb_o <=#Tp 1'b0; - end - else if(M2_ADDRESSED_S2_wire) - begin - s2_wb_cyc_o <=#Tp 1'b0; - s2_wb_stb_o <=#Tp 1'b0; - end - end - endcase - end -end - -// Generating Ack for master 1 -always @ (m1_in_progress or m1_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or M1_ADDRESSED_S1_wire or M1_ADDRESSED_S2_wire) -begin - if(m1_in_progress) - begin - if(M1_ADDRESSED_S1_wire) begin - m1_wb_ack_o <= s1_wb_ack_i; - m1_wb_dat_o <= s1_wb_dat_i; - end - else if(M1_ADDRESSED_S2_wire) begin - m1_wb_ack_o <= s2_wb_ack_i; - m1_wb_dat_o <= s2_wb_dat_i; - end - end - else - m1_wb_ack_o <= 0; -end - - -// Generating Ack for master 2 -always @ (m2_in_progress or m2_wb_adr_i or s1_wb_ack_i or s2_wb_ack_i or s1_wb_dat_i or s2_wb_dat_i or M2_ADDRESSED_S1_wire or M2_ADDRESSED_S2_wire) -begin - if(m2_in_progress) - begin - if(M2_ADDRESSED_S1_wire) begin - m2_wb_ack_o <= s1_wb_ack_i; - m2_wb_dat_o <= s1_wb_dat_i; - end - else if(M2_ADDRESSED_S2_wire) begin - m2_wb_ack_o <= s2_wb_ack_i; - m2_wb_dat_o <= s2_wb_dat_i; - end - end - else - m2_wb_ack_o <= 0; -end - - -// Generating Err for master 1 -always @ (m1_in_progress or m1_wb_adr_i or s1_wb_err_i or s2_wb_err_i or M2_ADDRESSED_S1_wire or M2_ADDRESSED_S2_wire or - m1_wb_cyc_i or m1_wb_stb_i) -begin - if(m1_in_progress) begin - if(M1_ADDRESSED_S1_wire) - m1_wb_err_o <= s1_wb_err_i; - else if(M1_ADDRESSED_S2_wire) - m1_wb_err_o <= s2_wb_err_i; - end - else if(m1_wb_cyc_i & m1_wb_stb_i & ~M1_ADDRESSED_S1_wire & ~M1_ADDRESSED_S2_wire) - m1_wb_err_o <= 1'b1; - else - m1_wb_err_o <= 1'b0; -end - - -// Generating Err for master 2 -always @ (m2_in_progress or m2_wb_adr_i or s1_wb_err_i or s2_wb_err_i or M2_ADDRESSED_S1_wire or M2_ADDRESSED_S2_wire or - m2_wb_cyc_i or m2_wb_stb_i) -begin - if(m2_in_progress) begin - if(M2_ADDRESSED_S1_wire) - m2_wb_err_o <= s1_wb_err_i; - else if(M2_ADDRESSED_S2_wire) - m2_wb_err_o <= s2_wb_err_i; - end - else if(m2_wb_cyc_i & m2_wb_stb_i & ~M2_ADDRESSED_S1_wire & ~M2_ADDRESSED_S2_wire) - m2_wb_err_o <= 1'b1; - else - m2_wb_err_o <= 1'b0; -end - - -assign m_wb_access_finished = m1_wb_ack_o | m1_wb_err_o | m2_wb_ack_o | m2_wb_err_o; - - -// Activity monitor -integer cnt; -always @ (posedge wb_clk_i or posedge wb_rst_i) -begin - if(wb_rst_i) - cnt <=#Tp 0; - else - if(s1_wb_ack_i | s1_wb_err_i | s2_wb_ack_i | s2_wb_err_i) - cnt <=#Tp 0; - else - if(s1_wb_cyc_o | s2_wb_cyc_o) - cnt <=#Tp cnt+1; -end - -always @ (posedge wb_clk_i) -begin - if(cnt==1000) begin - $display("(%0t)(%m) ERROR: WB activity ??? ", $time); - if(s1_wb_cyc_o) begin - $display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o); - $display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o); - $display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o); - $display("s1_wb_we_o = 0x%0x", s1_wb_we_o); - end - else if(s2_wb_cyc_o) begin - $display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o); - $display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o); - $display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o); - $display("s2_wb_we_o = 0x%0x", s2_wb_we_o); - end - - $stop; - end -end - - -always @ (posedge wb_clk_i) -begin - if(s1_wb_err_i & s1_wb_cyc_o) begin - $display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time); - $display("s1_wb_dat_o = 0x%0x", s1_wb_dat_o); - $display("s1_wb_adr_o = 0x%0x", s1_wb_adr_o); - $display("s1_wb_sel_o = 0x%0x", s1_wb_sel_o); - $display("s1_wb_we_o = 0x%0x", s1_wb_we_o); - $stop; - end - if(s2_wb_err_i & s2_wb_cyc_o) begin - $display("(%0t) ERROR: WB cycle finished with error acknowledge ", $time); - $display("s2_wb_dat_o = 0x%0x", s2_wb_dat_o); - $display("s2_wb_adr_o = 0x%0x", s2_wb_adr_o); - $display("s2_wb_sel_o = 0x%0x", s2_wb_sel_o); - $display("s2_wb_we_o = 0x%0x", s2_wb_we_o); - $stop; - end -end - - - -endmodule

verilog/components/ethernet/eth_cop.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: verilog/components/ethernet/eth_defines.v =================================================================== --- verilog/components/ethernet/eth_defines.v (revision 67) +++ verilog/components/ethernet/eth_defines.v (nonexistent) @@ -1,357 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// eth_defines.v //// -//// //// -//// This file is part of the Ethernet IP core project //// -//// http://www.opencores.org/projects/ethmac/ //// -//// //// -//// Author(s): //// -//// - Igor Mohor (igorM@opencores.org) //// -//// //// -//// All additional information is available in the Readme.txt //// -//// file. //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001, 2002 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: eth_defines.v,v $ -// Revision 1.34 2005/02/21 12:48:06 igorm -// Warning fixes. -// -// Revision 1.33 2003/11/12 18:24:58 tadejm -// WISHBONE slave changed and tested from only 32-bit accesss to byte access. -// -// Revision 1.32 2003/10/17 07:46:13 markom -// mbist signals updated according to newest convention -// -// Revision 1.31 2003/08/14 16:42:58 simons -// Artisan ram instance added. -// -// Revision 1.30 2003/06/13 11:55:37 mohor -// Define file in eth_cop.v is changed to eth_defines.v. Some defines were -// moved from tb_eth_defines.v to eth_defines.v. -// -// Revision 1.29 2002/11/19 18:13:49 mohor -// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. -// -// Revision 1.28 2002/11/15 14:27:15 mohor -// Since r_Rst bit is not used any more, default value is changed to 0xa000. -// -// Revision 1.27 2002/11/01 18:19:34 mohor -// Defines fixed to use generic RAM by default. -// -// Revision 1.26 2002/10/24 18:53:03 mohor -// fpga define added. -// -// Revision 1.3 2002/10/11 16:57:54 igorm -// eth_defines.v tagged with rel_5 used. -// -// Revision 1.25 2002/10/10 16:47:44 mohor -// Defines changed to have ETH_ prolog. -// ETH_WISHBONE_B# define added. -// -// Revision 1.24 2002/10/10 16:33:11 mohor -// Bist added. -// -// Revision 1.23 2002/09/23 18:22:48 mohor -// Virtual Silicon RAM might be used in the ASIC implementation of the ethernet -// core. -// -// Revision 1.22 2002/09/04 18:36:49 mohor -// Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL). -// -// Revision 1.21 2002/08/16 22:09:47 mohor -// Defines for register width added. mii_rst signal in MIIMODER register -// changed. -// -// Revision 1.20 2002/08/14 19:31:48 mohor -// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No -// need to multiply or devide any more. -// -// Revision 1.19 2002/07/23 15:28:31 mohor -// Ram , used for BDs changed from generic_spram to eth_spram_256x32. -// -// Revision 1.18 2002/05/03 10:15:50 mohor -// Outputs registered. Reset changed for eth_wishbone module. -// -// Revision 1.17 2002/04/24 08:52:19 mohor -// Compiler directives added. Tx and Rx fifo size incremented. A "late collision" -// bug fixed. -// -// Revision 1.16 2002/03/19 12:53:29 mohor -// Some defines that are used in testbench only were moved to tb_eth_defines.v -// file. -// -// Revision 1.15 2002/02/26 16:11:32 mohor -// Number of interrupts changed -// -// Revision 1.14 2002/02/16 14:03:44 mohor -// Registered trimmed. Unused registers removed. -// -// Revision 1.13 2002/02/16 13:06:33 mohor -// EXTERNAL_DMA used instead of WISHBONE_DMA. -// -// Revision 1.12 2002/02/15 10:58:31 mohor -// Changed that were lost with last update put back to the file. -// -// Revision 1.11 2002/02/14 20:19:41 billditt -// Modified for Address Checking, -// addition of eth_addrcheck.v -// -// Revision 1.10 2002/02/12 17:01:19 mohor -// HASH0 and HASH1 registers added. - -// Revision 1.9 2002/02/08 16:21:54 mohor -// Rx status is written back to the BD. -// -// Revision 1.8 2002/02/05 16:44:38 mohor -// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200 -// MHz. Statuses, overrun, control frame transmission and reception still need -// to be fixed. -// -// Revision 1.7 2002/01/23 10:28:16 mohor -// Link in the header changed. -// -// Revision 1.6 2001/12/05 15:00:16 mohor -// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors -// instead of the number of RX descriptors). -// -// Revision 1.5 2001/12/05 10:21:37 mohor -// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. -// -// Revision 1.4 2001/11/13 14:23:56 mohor -// Generic memory model is used. Defines are changed for the same reason. -// -// Revision 1.3 2001/10/18 12:07:11 mohor -// Status signals changed, Adress decoding changed, interrupt controller -// added. -// -// Revision 1.2 2001/09/24 15:02:56 mohor -// Defines changed (All precede with ETH_). Small changes because some -// tools generate warnings when two operands are together. Synchronization -// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC -// demands). -// -// Revision 1.1 2001/08/06 14:44:29 mohor -// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). -// Include files fixed to contain no path. -// File names and module names changed ta have a eth_ prologue in the name. -// File eth_timescale.v is used to define timescale -// All pin names on the top module are changed to contain _I, _O or _OE at the end. -// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O -// and Mdo_OE. The bidirectional signal must be created on the top level. This -// is done due to the ASIC tools. -// -// Revision 1.1 2001/07/30 21:23:42 mohor -// Directory structure changed. Files checked and joind together. -// -// -// -// -// - - - -//`define ETH_BIST // Bist for usage with Virtual Silicon RAMS - -`define ETH_MBIST_CTRL_WIDTH 3 // width of MBIST control bus - -// Ethernet implemented in Xilinx Chips (uncomment following lines) -// `define ETH_FIFO_XILINX // Use Xilinx distributed ram for tx and rx fifo -// `define ETH_XILINX_RAMB4 // Selection of the used memory for Buffer descriptors - // Core is going to be implemented in Virtex FPGA and contains Virtex - // specific elements. - -// Ethernet implemented in Altera Chips (uncomment following lines) -//`define ETH_ALTERA_ALTSYNCRAM - -// Ethernet implemented in ASIC with Virtual Silicon RAMs -// `define ETH_VIRTUAL_SILICON_RAM // Virtual Silicon RAMS used storing buffer decriptors (ASIC implementation) - -// Ethernet implemented in ASIC with Artisan RAMs -// `define ETH_ARTISAN_RAM // Artisan RAMS used storing buffer decriptors (ASIC implementation) - -// Uncomment when Avalon bus is used -//`define ETH_AVALON_BUS - -`define ETH_MODER_ADR 8'h0 // 0x0 -`define ETH_INT_SOURCE_ADR 8'h1 // 0x4 -`define ETH_INT_MASK_ADR 8'h2 // 0x8 -`define ETH_IPGT_ADR 8'h3 // 0xC -`define ETH_IPGR1_ADR 8'h4 // 0x10 -`define ETH_IPGR2_ADR 8'h5 // 0x14 -`define ETH_PACKETLEN_ADR 8'h6 // 0x18 -`define ETH_COLLCONF_ADR 8'h7 // 0x1C -`define ETH_TX_BD_NUM_ADR 8'h8 // 0x20 -`define ETH_CTRLMODER_ADR 8'h9 // 0x24 -`define ETH_MIIMODER_ADR 8'hA // 0x28 -`define ETH_MIICOMMAND_ADR 8'hB // 0x2C -`define ETH_MIIADDRESS_ADR 8'hC // 0x30 -`define ETH_MIITX_DATA_ADR 8'hD // 0x34 -`define ETH_MIIRX_DATA_ADR 8'hE // 0x38 -`define ETH_MIISTATUS_ADR 8'hF // 0x3C -`define ETH_MAC_ADDR0_ADR 8'h10 // 0x40 -`define ETH_MAC_ADDR1_ADR 8'h11 // 0x44 -`define ETH_HASH0_ADR 8'h12 // 0x48 -`define ETH_HASH1_ADR 8'h13 // 0x4C -`define ETH_TX_CTRL_ADR 8'h14 // 0x50 -`define ETH_RX_CTRL_ADR 8'h15 // 0x54 - -// Define to exclude ascosiated register and set signal static -`define ETH_IPGT -`define ETH_IPGR1 -`define ETH_IPGR2 -`define ETH_PACKETLEN -`define ETH_COLLCONF -`define ETH_MAC_ADDR -`define ETH_HASH0 -`define ETH_HASH1 - -`define ETH_MODER_DEF_0 8'h00 -`define ETH_MODER_DEF_1 8'hA0 -`define ETH_MODER_DEF_2 1'h0 -`define ETH_INT_MASK_DEF_0 7'h0 -`define ETH_IPGT_DEF_0 7'h15 -`define ETH_IPGR1_DEF_0 7'h0C -`define ETH_IPGR2_DEF_0 7'h12 -`define ETH_PACKETLEN_DEF_0 8'h00 -`define ETH_PACKETLEN_DEF_1 8'h06 -`define ETH_PACKETLEN_DEF_2 8'h40 -`define ETH_PACKETLEN_DEF_3 8'h00 -`define ETH_COLLCONF_DEF_0 6'h3f -`define ETH_COLLCONF_DEF_2 4'hF -`define ETH_TX_BD_NUM_DEF_0 8'h40 -`define ETH_CTRLMODER_DEF_0 3'h0 -`define ETH_MIIMODER_DEF_0 8'h64 -`define ETH_MIIMODER_DEF_1 1'h0 -`define ETH_MIIADDRESS_DEF_0 5'h00 -`define ETH_MIIADDRESS_DEF_1 5'h00 -`define ETH_MIITX_DATA_DEF_0 8'h00 -`define ETH_MIITX_DATA_DEF_1 8'h00 -`define ETH_MIIRX_DATA_DEF 16'h0000 // not written from WB -`define ETH_MAC_ADDR0_DEF_0 8'h00 -`define ETH_MAC_ADDR0_DEF_1 8'h00 -`define ETH_MAC_ADDR0_DEF_2 8'h00 -`define ETH_MAC_ADDR0_DEF_3 8'h00 -`define ETH_MAC_ADDR1_DEF_0 8'h00 -`define ETH_MAC_ADDR1_DEF_1 8'h00 -`define ETH_HASH0_DEF_0 8'h00 -`define ETH_HASH0_DEF_1 8'h00 -`define ETH_HASH0_DEF_2 8'h00 -`define ETH_HASH0_DEF_3 8'h00 -`define ETH_HASH1_DEF_0 8'h00 -`define ETH_HASH1_DEF_1 8'h00 -`define ETH_HASH1_DEF_2 8'h00 -`define ETH_HASH1_DEF_3 8'h00 -`define ETH_TX_CTRL_DEF_0 8'h00 // -`define ETH_TX_CTRL_DEF_1 8'h00 // -`define ETH_TX_CTRL_DEF_2 1'h0 // -`define ETH_RX_CTRL_DEF_0 8'h00 -`define ETH_RX_CTRL_DEF_1 8'h00 - - -`define ETH_MODER_WIDTH_0 8 -`define ETH_MODER_WIDTH_1 8 -`define ETH_MODER_WIDTH_2 1 -`define ETH_INT_SOURCE_WIDTH_0 7 -`define ETH_INT_MASK_WIDTH_0 7 -`define ETH_IPGT_WIDTH_0 7 -`define ETH_IPGR1_WIDTH_0 7 -`define ETH_IPGR2_WIDTH_0 7 -`define ETH_PACKETLEN_WIDTH_0 8 -`define ETH_PACKETLEN_WIDTH_1 8 -`define ETH_PACKETLEN_WIDTH_2 8 -`define ETH_PACKETLEN_WIDTH_3 8 -`define ETH_COLLCONF_WIDTH_0 6 -`define ETH_COLLCONF_WIDTH_2 4 -`define ETH_TX_BD_NUM_WIDTH_0 8 -`define ETH_CTRLMODER_WIDTH_0 3 -`define ETH_MIIMODER_WIDTH_0 8 -`define ETH_MIIMODER_WIDTH_1 1 -`define ETH_MIICOMMAND_WIDTH_0 3 -`define ETH_MIIADDRESS_WIDTH_0 5 -`define ETH_MIIADDRESS_WIDTH_1 5 -`define ETH_MIITX_DATA_WIDTH_0 8 -`define ETH_MIITX_DATA_WIDTH_1 8 -`define ETH_MIIRX_DATA_WIDTH 16 // not written from WB -`define ETH_MIISTATUS_WIDTH 3 // not written from WB -`define ETH_MAC_ADDR0_WIDTH_0 8 -`define ETH_MAC_ADDR0_WIDTH_1 8 -`define ETH_MAC_ADDR0_WIDTH_2 8 -`define ETH_MAC_ADDR0_WIDTH_3 8 -`define ETH_MAC_ADDR1_WIDTH_0 8 -`define ETH_MAC_ADDR1_WIDTH_1 8 -`define ETH_HASH0_WIDTH_0 8 -`define ETH_HASH0_WIDTH_1 8 -`define ETH_HASH0_WIDTH_2 8 -`define ETH_HASH0_WIDTH_3 8 -`define ETH_HASH1_WIDTH_0 8 -`define ETH_HASH1_WIDTH_1 8 -`define ETH_HASH1_WIDTH_2 8 -`define ETH_HASH1_WIDTH_3 8 -`define ETH_TX_CTRL_WIDTH_0 8 -`define ETH_TX_CTRL_WIDTH_1 8 -`define ETH_TX_CTRL_WIDTH_2 1 -`define ETH_RX_CTRL_WIDTH_0 8 -`define ETH_RX_CTRL_WIDTH_1 8 - - -// Outputs are registered (uncomment when needed) -`define ETH_REGISTERED_OUTPUTS - -// Settings for TX FIFO -`define ETH_TX_FIFO_CNT_WIDTH 5 -`define ETH_TX_FIFO_DEPTH 16 -`define ETH_TX_FIFO_DATA_WIDTH 32 - -// Settings for RX FIFO -`define ETH_RX_FIFO_CNT_WIDTH 5 -`define ETH_RX_FIFO_DEPTH 16 -`define ETH_RX_FIFO_DATA_WIDTH 32 - -// Burst length -`define ETH_BURST_LENGTH 4 // Change also ETH_BURST_CNT_WIDTH -`define ETH_BURST_CNT_WIDTH 3 // The counter must be width enough to count to ETH_BURST_LENGTH - -// WISHBONE interface is Revision B3 compliant (uncomment when needed) -`define ETH_WISHBONE_B3 - - -// Following defines are needed when eth_cop.v is used. Otherwise they may be deleted. -`define ETH_BASE 32'hd0000000 -`define ETH_WIDTH 32'h800 -`define MEMORY_BASE 32'h2000 -`define MEMORY_WIDTH 32'h10000 - -`define M1_ADDRESSED_S1 ( (m1_wb_adr_i >= `ETH_BASE) & (m1_wb_adr_i < (`ETH_BASE + `ETH_WIDTH )) ) -`define M1_ADDRESSED_S2 ( (m1_wb_adr_i >= `MEMORY_BASE) & (m1_wb_adr_i < (`MEMORY_BASE + `MEMORY_WIDTH)) ) -`define M2_ADDRESSED_S1 ( (m2_wb_adr_i >= `ETH_BASE) & (m2_wb_adr_i < (`ETH_BASE + `ETH_WIDTH )) ) -`define M2_ADDRESSED_S2 ( (m2_wb_adr_i >= `MEMORY_BASE) & (m2_wb_adr_i < (`MEMORY_BASE + `MEMORY_WIDTH)) ) -// Previous defines are only needed for eth_cop.v -

verilog/components/ethernet/eth_defines.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: verilog/components/ethernet/filer =================================================================== --- verilog/components/ethernet/filer (revision 67) +++ verilog/components/ethernet/filer (nonexistent) @@ -1,31 +0,0 @@ -BUGS -CVS -TODO -eth_clockgen.v -eth_cop.v -eth_crc.v -eth_defines.v -eth_fifo.v -eth_maccontrol.v -eth_macstatus.v -eth_miim.v -eth_outputcontrol.v -eth_random.v -eth_receivecontrol.v -eth_register.v -eth_registers.v -eth_rxaddrcheck.v -eth_rxcounters.v -eth_rxethmac.v -eth_rxstatem.v -eth_shiftreg.v -eth_spram_256x32.v -eth_top.v -eth_transmitcontrol.v -eth_txcounters.v -eth_txethmac.v -eth_txstatem.v -eth_wishbone.v -filer -timescale.v -xilinx_dist_ram_16x32.v

verilog/components/ethernet/filer Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: verilog/components/ethernet/TODO =================================================================== --- verilog/components/ethernet/TODO (revision 67) +++ verilog/components/ethernet/TODO (nonexistent) @@ -1,68 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// TODO //// -//// //// -//// This file is part of the Ethernet IP core project //// -//// http://www.opencores.org/projects/ethmac/ //// -//// //// -//// Author(s): //// -//// - Igor Mohor (igorM@opencores.org) //// -//// //// -//// All additional information is available in the Readme.txt //// -//// file. //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2001, 2002 Authors //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -// -// CVS Revision History -// -// $Log: TODO,v $ -// Revision 1.3 2003/01/23 09:14:12 mohor -// Fix MTxErr or prevent sending too big frames. -// -// Revision 1.2 2002/11/21 00:33:32 mohor -// In loopback rx_clk is not looped back. Possible CRC error. Consider if usage -// of additional logic is necessery (FIFO for looping the data). -// -// Revision 1.1 2002/09/10 10:42:06 mohor -// HASH improvement needed. -// - - -- Add logic for easier use of the HASH table: First write MAC address to some - register. Then issue a command. CRC is calculated from this MAC and appropriate - bit written to the HASH register. - -- In loopback rx_clk is not looped back. Possible CRC error. Consider if usage of - additional logic is necessery (FIFO for looping the data). - -- When sending frames bigger than MaxFL, MaxFL is sent, BD marked as finished, - TxB_IRQ interrupt is set and MTxErr is set for a short period. Fix MTxErr or - prevent sending too big frames or set TxE_IRQ instead. - - -

verilog/components/ethernet/TODO Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: verilog/components/ethernet/Makefile =================================================================== --- verilog/components/ethernet/Makefile (revision 67) +++ verilog/components/ethernet/Makefile (nonexistent) @@ -1,10 +0,0 @@ -spram: - vppp --simple eth_spram_256x32.v > spram_256x32.v - -fifo: - vppp --simple eth_fifo.v > fifo.v - -eth: - cat eth_clockgen.v eth_crc.v eth_fifo.v eth_maccontrol.v eth_macstatus.v eth_miim.v eth_outputcontrol.v eth_random.v eth_receivecontrol.v eth_register.v eth_registers.v eth_rxaddrcheck.v eth_rxcounters.v eth_rxethmac.v eth_rxstatem.v eth_shiftreg.v eth_spram_256x32.v eth_transmitcontrol.v eth_txcounters.v eth_txethmac.v eth_txstatem.v eth_wishbone.v eth_top.v > eth_top_ip.v - -all: eth

verilog/components/ethernet/Makefile Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: verilog/components/ethernet/eth_wishbone.v =================================================================== --- verilog/components/ethernet/eth_wishbone.v (revision 67) +++ verilog/components/ethernet/eth_wishbone.v (revision 69) @@ -334,8 +334,14 @@ output m_wb_stb_o; // input [31:0] m_wb_dat_i; // input m_wb_ack_i; // -input m_wb_err_i; // +input m_wb_err_i; // +`ifdef POLL_TXBDS + reg [31:0] TxBDReadySamples; // -- jb + wire TxBDNotReady; // -- jb +`endif + + `ifdef ETH_WISHBONE_B3 output [2:0] m_wb_cti_o; // Cycle Type Identifier output [1:0] m_wb_bte_o; // Burst Type Extension @@ -717,7 +723,29 @@ TxBDReady <=#Tp 1'b0; end +`ifdef POLL_TXBDS + // Register TxBDReady 4 times, when all are low we know this one is not good to transmit + always @(posedge WB_CLK_I or posedge Reset) // -- jb + begin + if (Reset) TxBDReadySamples <= 32'hffffffff; + else begin + if (r_TxEn) + begin + if (TxBDNotReady) + TxBDReadySamples <= 32'hffffffff; + else + TxBDReadySamples[31:0] <= {TxBDReadySamples[30:0],TxBDReady}; + end + else + TxBDReadySamples <= 32'hffffffff; + end // else: !if(Reset) + end // always @ (posedge WB_CLK_I or posedge Reset) + + + assign TxBDNotReady = ~(|TxBDReadySamples); // When all low, this goes high // -- jb +`endif // `ifdef POLL_TXBDS + // Reading the Tx buffer descriptor assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady; @@ -1359,8 +1387,12 @@ assign WrapRxStatusBit = RxStatus[13]; -// Temporary Tx and Rx buffer descriptor address -assign TempTxBDAddress[7:1] = {7{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 1'b1) ; // Tx BD increment or wrap (last BD) +// Temporary Tx and Rx buffer descriptor address +`ifdef POLL_TXBDS +assign TempTxBDAddress[7:1] = {7{ (TxStatusWrite|TxBDNotReady) & ~WrapTxStatusBit}} & (TxBDAddress + 1'b1) ; // Tx BD increment or wrap (last BD) +`else +assign TempTxBDAddress[7:1] = {7{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 1'b1) ; // Tx BD increment or wrap (last BD) +`endif assign TempRxBDAddress[7:1] = {7{ WrapRxStatusBit}} & (r_TxBDNum[6:0]) | // Using first Rx BD {7{~WrapRxStatusBit}} & (RxBDAddress + 1'b1) ; // Using next Rx BD (incremenrement address) @@ -1372,7 +1404,11 @@ TxBDAddress <=#Tp 7'h0; else if (r_TxEn & (~r_TxEn_q)) TxBDAddress <=#Tp 7'h0; +`ifdef POLL_TXBDS + else if (TxStatusWrite | TxBDNotReady) +`else else if (TxStatusWrite) +`endif TxBDAddress <=#Tp TempTxBDAddress; end