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URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

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  • This comparison shows the changes necessary to convert path
    /openrisc/trunk/orpsocv2/scripts
    from Rev 558 to Rev 560
    Reverse comparison

Rev 558 → Rev 560

/make/Makefile-board-modelsim.inc
3,13 → 3,13
#
# Modelsim-specific settings
#
VOPT_ARGS=$(QUIET) -suppress 2241
VOPT_ARGS+=$(QUIET) -suppress 2241
 
# If VCD dump is desired, tell Modelsim not to optimise
# away everything.
ifeq ($(VCD), 1)
#VOPT_ARGS=-voptargs="+acc=rnp"
VOPT_ARGS=+acc=rnpqv
VOPT_ARGS+=+acc=rnpqv
endif
 
# VSIM commands
16,7 → 16,7
# Suppressed warnings - 3009: Failed to open $readmemh() file
# Suppressed warnings - 3009: Module 'blah' does not have a `timescale directive in effect, but previous modules do.
# Suppressed warnings - 8598: Non-positive replication multiplier inside concat. Replication will be ignored
VSIM_ARGS= -suppress 7 -suppress 3009 -suppress 8598 -c $(QUIET) -do "set StdArithNoWarnings 1; run -all; exit"
VSIM_ARGS+= -suppress 7 -suppress 3009 -suppress 8598 -c $(QUIET) -do "set StdArithNoWarnings 1; run -all; exit"
 
# VPI debugging interface set up
VPI_SRC_C_DIR=$(COMMON_BENCH_VERILOG_DIR)/vpi/c
62,8 → 62,8
echo "+libext+.vm" >> $@; \
fi
ifeq ($(FPGA_VENDOR), xilinx)
$(Q)echo "-y "$(XILINX_PATH)"/verilog/src/unisims" >> $@;
$(Q)echo "-y "$(XILINX_PATH)"/verilog/src/XilinxCoreLib" >> $@;
$(Q)echo "-y "$(TECHNOLOGY_LIBRARY_VERILOG_DIR)"/src/unisims" >> $@;
$(Q)echo "-y "$(TECHNOLOGY_LIBRARY_VERILOG_DIR)"/src/XilinxCoreLib" >> $@;
endif
$(Q)echo >> $@
 
77,7 → 77,7
$(Q)for vsrc in $(BOARD_BENCH_VERILOG_SRC); do echo $$vsrc >> $@; done
$(Q)for vsrc in $(COMMON_BENCH_VERILOG_SRC); do echo $$vsrc >> $@; done
ifeq ($(FPGA_VENDOR), xilinx)
$(Q)echo "+incdir+"$(XILINX_PATH)"/verilog/src" >> $@;
$(Q)echo "+incdir+"$(TECHNOLOGY_LIBRARY_VERILOG_DIR)"/src" >> $@;
endif
$(Q)echo >> $@
 
121,6 → 121,9
ifeq ($(FPGA_VENDOR), xilinx)
$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(VPI_LIBS) work
$(Q)echo; echo "\t### Compiling Xilinx support libs, user design & testbench ###"; echo
ifeq ($(DO_XILINX_COMPXLIB), 1)
$(Q)$(TECHNOLOGY_BACKEND_BIN_DIR)/compxlib $(XLIB_ARGS)
endif
$(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP_FILE) -f $<
$(Q)vopt $(QUIET) glbl $(RTL_TESTBENCH_TOP_NAME) $(VOPT_ARGS) -o tb
$(Q)echo; echo "\t### Launching simulation ###"; echo

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