URL
https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
Subversion Repositories openrisc_me
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- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2/sim/bin
- from Rev 42 to Rev 43
- ↔ Reverse comparison
Rev 42 → Rev 43
/Makefile
165,7 → 165,7
# and into SDRAM before it is executed. Although this more closely mimics the |
# behaviour of the hardware, for simulation purposes it is purely time-consuming |
# however it may be useful to track down any problems with this boot-loading |
# process. Therefore, becuase it enables SDRAM memory, ir also enables the flash |
# process. Therefore, becuase it enables SDRAM memory, it also enables the flash |
# memory model and SPI controller inside ORPSoC. |
# |
# Ethernet |
386,7 → 386,7
fi; \ |
echo "\`define TEST_NAME_STRING \"$$TEST\"" > $(SIM_RUN_DIR)/test_define.v; \ |
echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v; \ |
if [ ! -z $$SIM_LOGGING ]; then \ |
if [ -z $$NO_SIM_LOGGING ]; then \ |
echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; \ |
fi; \ |
echo ; \ |