URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2/sim/bin
- from Rev 53 to Rev 54
- ↔ Reverse comparison
Rev 53 → Rev 54
/icarus.scr
12,6 → 12,7
+incdir+$RTL_DIR/components/smii |
+incdir+$RTL_DIR/components/debug_if |
+incdir+$RTL_DIR/components/wb_sdram_ctrl |
+incdir+$RTL_DIR/components/wb_conbus |
|
-y $BENCH_DIR |
-y $BENCH_DIR/vpi/verilog |
27,6 → 28,7
-y $RTL_DIR/components/debug_if |
-y $RTL_DIR/components/wb_sdram_ctrl |
-y $RTL_DIR/components/ram_wb |
-y $RTL_DIR/components/wb_conbus |
|
// RTL files (top) |
$BENCH_DIR/orpsoc_testbench.v |
/Makefile
301,7 → 301,7
@cd $(RTL_VERILOG_DIR) && sed '/defparam/!s/\([a-zA-Z0-9_]\)\.//g' intercon.vm > intercon.v |
|
.PHONY: prepare_rtl |
prepare_rtl: $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm.v $(RTL_VERILOG_DIR)/intercon.v |
prepare_rtl: $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm.v #$(RTL_VERILOG_DIR)/intercon.v |
|
|
ifdef UART_PRINTF |
584,6 → 584,10
SYSC_MODELS_BUILD=$(SYSC_MODELS) $(VLT_TRACEOBJ) |
|
prepare_vlt: prepare_rtl vlt_model_links $(SIM_VLT_DIR)/Vorpsoc_top |
@echo;echo "\tCycle-accurate model compiled successfully" |
@echo;echo "\tRun the executable with the -h option for usage instructions:";echo |
$(SIM_VLT_DIR)/Vorpsoc_top -h |
@echo;echo |
|
$(SIM_VLT_DIR)/Vorpsoc_top: $(SIM_VLT_DIR)/libVorpsoc_top.a $(SIM_VLT_DIR)/OrpsocMain.o |
# Final linking of the simulation executable. Order of libraries here is important! |
/verilator.scr
12,6 → 12,7
+incdir+$RTL_DIR/components/smii |
+incdir+$RTL_DIR/components/debug_if |
+incdir+$RTL_DIR/components/wb_sdram_ctrl |
+incdir+$RTL_DIR/components/wb_conbus |
|
-y $BENCH_DIR |
-y $BACKEND_DIR |
26,6 → 27,7
-y $RTL_DIR/components/debug_if |
-y $RTL_DIR/components/wb_sdram_ctrl |
-y $RTL_DIR/components/ram_wb |
-y $RTL_DIR/components/wb_conbus |
|
// RTL files (top) |
$RTL_DIR/orpsoc_top.v |