URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2/sw/bootrom
- from Rev 403 to Rev 415
- ↔ Reverse comparison
Rev 403 → Rev 415
/bootrom.S
42,6 → 42,8
#ifdef BOOTROM_SPI_FLASH |
|
/* Assembly program to go into the boot ROM */ |
/* For use with simple_spi SPI master core and standard SPI flash |
interface-compatible parts (ST M25P16 for example.)*/ |
/* Currently just loads a program from SPI flash into RAM */ |
/* Assuming address at RAM_LOAD_BASE gets clobbered, we need |
a byte writable address somewhere!*/ |
67,52 → 69,75
l.movhi r4, hi(SPI_BASE) |
|
spi_init: |
l.ori r2, r0, SPI_SPCR_XFER_GO /* Setup SPCR with enable bit set */ |
l.sb SPI_SPCR(r4), r2 |
l.sb SPI_SPSS(r4), r0 /* Clear SPI slave selects */ |
l.ori r6, r0, SPI_SPSS_INIT |
l.sb SPI_SPSS(r4), r6 /* Now put in appropriate slave select */ |
l.jal spi_xfer |
l.ori r3, r0, 0x3 /* READ command opcode for SPI device */ |
l.jal spi_xfer |
l.or r3, r0, r0 |
l.jal spi_xfer |
l.or r3, r0, r0 |
l.jal spi_xfer |
l.or r3, r0, r0 |
l.ori r2, r0, SPI_SPCR_XFER_GO /* Setup SPCR with enable bit set */ |
l.sb SPI_SPCR(r4), r2 |
l.sb SPI_SPSS(r4), r0 /* Clear SPI slave selects */ |
l.ori r6, r0, SPI_SPSS_INIT |
l.sb SPI_SPSS(r4), r6 /* Set appropriate slave select */ |
l.jal spi_xfer |
l.ori r3, r0, 0x3 /* READ command opcode for SPI device*/ |
l.jal spi_xfer |
#ifdef BOOTROM_ADDR_BYTE2 |
l.ori r3, r0, BOOTROM_ADDR_BYTE2 /* Use addr if defined. MSB first */ |
#else |
l.or r3, r0, r0 |
#endif |
l.jal spi_xfer |
#ifdef BOOTROM_ADDR_BYTE1 |
l.ori r3, r0, BOOTROM_ADDR_BYTE1 |
#else |
l.or r3, r0, r0 |
#endif |
l.jal spi_xfer |
#ifdef BOOTROM_ADDR_BYTE0 |
l.ori r3, r0, BOOTROM_ADDR_BYTE0 |
#else |
l.or r3, r0, r0 |
#endif |
l.movhi r6, 0 |
l.movhi r7, 0xffff |
|
copy: |
l.jal spi_xfer /* Read a byte into r3 */ |
l.add r8, r1, r6 /* Calculate store address */ |
l.sb 0(r8), r3 /* Write byte to memory */ |
l.addi r6, r6, 1 /* Increment counter */ |
l.sfeqi r6, 0x4 /* Is this the first word */ |
l.bf store_sizeword /* put sizeword in the register */ |
l.sfeq r6, r7 /* Check if we've finished loading the words */ |
l.bnf copy /* Continue copying if not last word */ |
l.jal spi_xfer /* Read a byte into r3 */ |
l.add r8, r1, r6 /* Calculate store address */ |
l.sb 0(r8), r3 /* Write byte to memory */ |
l.addi r6, r6, 1 /* Increment counter */ |
l.sfeqi r6, 0x4 /* Is this the first word ?*/ |
l.bf store_sizeword /* put sizeword in the register */ |
l.sfeq r6, r7 /* Check if we've finished loading the words */ |
l.bnf copy /* Continue copying if not last word */ |
l.nop |
|
goto_reset: |
l.ori r1, r1, RESET_ADDR |
l.jr r1 |
l.sb SPI_SPSS(r4), r0 /* Clear SPI slave selects */ |
l.ori r1, r1, RESET_ADDR |
l.jr r1 |
l.sb SPI_SPSS(r4), r0 /* Clear SPI slave selects */ |
|
store_sizeword: |
l.j copy |
l.lwz r7, 0(r1) /* Size word is in first word of SDRAM */ |
#ifdef SPI_RETRY_IF_INSANE_SIZEWORD |
l.lwz r7, 0(r1) /* Size word is in first word of SDRAM */ |
l.srli r10, r7, 16 /* Chop the sizeword we read in half */ |
l.sfgtui r10, 0x0200 /* It's unlikely we'll ever load > 32MB */ |
l.bf boot_init |
l.nop |
l.j copy |
l.nop |
|
#else |
l.j copy |
l.lwz r7, 0(r1) /* Size word is in first word of SDRAM */ |
#endif |
|
spi_xfer: |
l.sb SPI_SPDR(r4), r3 /* Dummy write what's in r3 */ |
l.ori r3, r0, SPI_SPSR_RX_CHECK /* r3 = , ensure loop just once */ |
l.sb SPI_SPDR(r4), r3 /* Dummy write what's in r3 */ |
l.ori r3, r0, SPI_SPSR_RX_CHECK /* r3 = , ensure loop just once */ |
spi_xfer_poll: |
l.andi r3, r3, SPI_SPSR_RX_CHECK /* AND read fifo bit empty */ |
l.andi r3, r3, SPI_SPSR_RX_CHECK /* AND read fifo bit empty */ |
l.sfeqi r3, SPI_SPSR_RX_CHECK /* is bit set? ... */ |
l.bf spi_xfer_poll /* ... if so, rxfifo empty, keep polling */ |
l.lbz r3, SPI_SPSR(r4) /* Read SPSR */ |
l.jr r9 |
l.lbz r3, SPI_SPDR(r4) /* Get data byte */ |
l.bf spi_xfer_poll /* ... if so, rxfifo empty, keep polling */ |
l.lbz r3, SPI_SPSR(r4) /* Read SPSR */ |
l.jr r9 |
l.lbz r3, SPI_SPDR(r4) /* Get data byte */ |
|
|
#endif |
121,8 → 146,8
/* Jump to reset vector in the SDRAM */ |
l.movhi r0, 0 |
l.movhi r4, SDRAM_BASE |
l.ori r4, r4, 0x100 |
l.jr r4 |
l.ori r4, r4, 0x100 |
l.jr r4 |
l.nop |
|
#endif |
134,13 → 159,13
*/ |
l.movhi r0, 0 |
l.movhi r4, SDRAM_BASE |
l.sw 0x0(r4), r0 |
l.sw 0x0(r4), r0 |
l.movhi r5, hi(0x15000001) /* A l.nop 1 so sim exits if this enabled */ |
l.ori r5, r5, lo(0x15000001) |
l.sw 0x4(r4), r5 |
l.sw 0x8(r4), r5 |
l.sw 0xc(r4), r5 |
l.jr r4 |
l.ori r5, r5, lo(0x15000001) |
l.sw 0x4(r4), r5 |
l.sw 0x8(r4), r5 |
l.sw 0xc(r4), r5 |
l.jr r4 |
l.nop |
|
|
153,11 → 178,8
of memory and jump there. |
*/ |
l.movhi r0, 0 |
l.nop 0x1 |
l.j 0 |
l.nop 0x1 |
l.j 0 |
l.nop |
l.nop |
|
|
|
#endif |