URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2/sw/drivers/or1200
- from Rev 505 to Rev 530
- ↔ Reverse comparison
Rev 505 → Rev 530
/cache.S
0,0 → 1,114
#include "spr-defs.h" |
/* Cache init. To be called during init ONLY */ |
|
.global _cache_init |
.type _cache_init,@function |
|
_cache_init: |
/* Instruction cache enable */ |
/* Check if IC present and skip enabling otherwise */ |
l.mfspr r3,r0,SPR_UPR |
l.andi r4,r3,SPR_UPR_ICP |
l.sfeq r4,r0 |
l.bf .L8 |
l.nop |
|
/* Disable IC */ |
l.mfspr r6,r0,SPR_SR |
l.addi r5,r0,-1 |
l.xori r5,r5,SPR_SR_ICE |
l.and r5,r6,r5 |
l.mtspr r0,r5,SPR_SR |
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/* Establish cache block size |
If BS=0, 16; |
If BS=1, 32; |
r14 contain block size |
*/ |
l.mfspr r3,r0,SPR_ICCFGR |
l.andi r4,r3,SPR_ICCFGR_CBS |
l.srli r5,r4,7 |
l.ori r6,r0,16 |
l.sll r14,r6,r5 |
|
/* Establish number of cache sets |
r7 contains number of cache sets |
r5 contains log(# of cache sets) |
*/ |
l.andi r4,r3,SPR_ICCFGR_NCS |
l.srli r5,r4,3 |
l.ori r6,r0,1 |
l.sll r7,r6,r5 |
|
/* Invalidate IC */ |
l.addi r6,r0,0 |
l.sll r5,r14,r5 |
|
.L7: |
l.mtspr r0,r6,SPR_ICBIR |
l.sfne r6,r5 |
l.bf .L7 |
l.add r6,r6,r14 |
|
/* Enable IC */ |
l.mfspr r6,r0,SPR_SR |
l.ori r6,r6,SPR_SR_ICE |
l.mtspr r0,r6,SPR_SR |
l.nop |
l.nop |
l.nop |
l.nop |
l.nop |
l.nop |
l.nop |
l.nop |
|
.L8: |
/* Data cache enable */ |
/* Check if DC present and skip enabling otherwise */ |
l.mfspr r3,r0,SPR_UPR |
l.andi r4,r3,SPR_UPR_DCP |
l.sfeq r4,r0 |
l.bf .L10 |
l.nop |
/* Disable DC */ |
l.mfspr r6,r0,SPR_SR |
l.addi r5,r0,-1 |
l.xori r5,r5,SPR_SR_DCE |
l.and r5,r6,r5 |
l.mtspr r0,r5,SPR_SR |
/* Establish cache block size |
If BS=0, 16; |
If BS=1, 32; |
r14 contain block size |
*/ |
l.mfspr r3,r0,SPR_DCCFGR |
l.andi r4,r3,SPR_DCCFGR_CBS |
l.srli r5,r4,7 |
l.ori r6,r0,16 |
l.sll r14,r6,r5 |
/* Establish number of cache sets |
r7 contains number of cache sets |
r5 contains log(# of cache sets) |
*/ |
l.andi r4,r3,SPR_DCCFGR_NCS |
l.srli r5,r4,3 |
l.ori r6,r0,1 |
l.sll r7,r6,r5 |
/* Invalidate DC */ |
l.addi r6,r0,0 |
l.sll r5,r14,r5 |
.L9: |
l.mtspr r0,r6,SPR_DCBIR |
l.sfne r6,r5 |
l.bf .L9 |
l.add r6,r6,r14 |
/* Enable DC */ |
l.mfspr r6,r0,SPR_SR |
l.ori r6,r6,SPR_SR_DCE |
l.mtspr r0,r6,SPR_SR |
|
.L10: |
/* Return */ |
l.jr r9 |
l.nop |
/crt0.S
65,6 → 65,7
l.movhi r29, 0 |
l.movhi r30, 0 |
l.movhi r31, 0 |
|
/* Clear status register, set supervisor mode */ |
l.ori r1, r0, SPR_SR_SM |
l.mtspr r0, r1, SPR_SR |
196,125 → 197,18
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ENTRY(_start) |
|
|
|
/* Instruction cache enable */ |
/* Check if IC present and skip enabling otherwise */ |
l.mfspr r24,r0,SPR_UPR |
l.andi r26,r24,SPR_UPR_ICP |
l.sfeq r26,r0 |
l.bf .L8 |
/* Cache initialisation */ |
l.jal _cache_init |
l.nop |
|
/* Disable IC */ |
l.mfspr r6,r0,SPR_SR |
l.addi r5,r0,-1 |
l.xori r5,r5,SPR_SR_ICE |
l.and r5,r6,r5 |
l.mtspr r0,r5,SPR_SR |
|
/* Establish cache block size |
If BS=0, 16; |
If BS=1, 32; |
r14 contain block size |
*/ |
l.mfspr r24,r0,SPR_ICCFGR |
l.andi r26,r24,SPR_ICCFGR_CBS |
l.srli r28,r26,7 |
l.ori r30,r0,16 |
l.sll r14,r30,r28 |
|
/* Establish number of cache sets |
r16 contains number of cache sets |
r28 contains log(# of cache sets) |
*/ |
l.andi r26,r24,SPR_ICCFGR_NCS |
l.srli r28,r26,3 |
l.ori r30,r0,1 |
l.sll r16,r30,r28 |
|
/* Invalidate IC */ |
l.addi r6,r0,0 |
l.sll r5,r14,r28 |
|
.L7: |
l.mtspr r0,r6,SPR_ICBIR |
l.sfne r6,r5 |
l.bf .L7 |
l.add r6,r6,r14 |
|
/* Enable IC */ |
l.mfspr r6,r0,SPR_SR |
l.ori r6,r6,SPR_SR_ICE |
l.mtspr r0,r6,SPR_SR |
l.nop |
l.nop |
l.nop |
l.nop |
l.nop |
l.nop |
l.nop |
l.nop |
|
.L8: |
/* Data cache enable */ |
/* Check if DC present and skip enabling otherwise */ |
l.mfspr r24,r0,SPR_UPR |
l.andi r26,r24,SPR_UPR_DCP |
l.sfeq r26,r0 |
l.bf .L10 |
l.nop |
/* Disable DC */ |
l.mfspr r6,r0,SPR_SR |
l.addi r5,r0,-1 |
l.xori r5,r5,SPR_SR_DCE |
l.and r5,r6,r5 |
l.mtspr r0,r5,SPR_SR |
/* Establish cache block size |
If BS=0, 16; |
If BS=1, 32; |
r14 contain block size |
*/ |
l.mfspr r24,r0,SPR_DCCFGR |
l.andi r26,r24,SPR_DCCFGR_CBS |
l.srli r28,r26,7 |
l.ori r30,r0,16 |
l.sll r14,r30,r28 |
/* Establish number of cache sets |
r16 contains number of cache sets |
r28 contains log(# of cache sets) |
*/ |
l.andi r26,r24,SPR_DCCFGR_NCS |
l.srli r28,r26,3 |
l.ori r30,r0,1 |
l.sll r16,r30,r28 |
/* Invalidate DC */ |
l.addi r6,r0,0 |
l.sll r5,r14,r28 |
.L9: |
l.mtspr r0,r6,SPR_DCBIR |
l.sfne r6,r5 |
l.bf .L9 |
l.add r6,r6,r14 |
/* Enable DC */ |
l.mfspr r6,r0,SPR_SR |
l.ori r6,r6,SPR_SR_DCE |
l.mtspr r0,r6,SPR_SR |
|
.L10: |
|
/* Clear BSS */ |
LOAD_SYMBOL_2_GPR(r28, _bss_start) |
LOAD_SYMBOL_2_GPR(r30, _bss_end) |
LOAD_SYMBOL_2_GPR(r5, _bss_start) |
LOAD_SYMBOL_2_GPR(r6, _bss_end) |
1: |
l.sw (0)(r28), r0 |
l.sfltu r28, r30 |
l.sw (0)(r5), r0 |
l.sfltu r5, r6 |
l.bf 1b |
l.addi r28, r28, 4 |
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/* Initialise UART in a C function */ |
/*l.jal _uart_init |
l.nop*/ |
l.addi r5, r5, 4 |
|
/* Jump to main program entry point (argc = argv = 0) */ |
CLEAR_GPR(r3) |
360,7 → 254,7
l.sw 0x70(r1), r30 |
l.sw 0x74(r1), r31 |
l.sw 0x78(r1), r32 |
|
|
l.jal default_exception_handler_c |
l.nop |
|
/int.c
25,37 → 25,37
} |
|
/* Add interrupt handler */ |
int int_add(unsigned long vect, void (* handler)(void *), void *arg) |
int int_add(unsigned long irq, void (* handler)(void *), void *arg) |
{ |
if(vect >= MAX_INT_HANDLERS) |
if(irq >= MAX_INT_HANDLERS) |
return -1; |
|
int_handlers[vect].handler = handler; |
int_handlers[vect].arg = arg; |
int_handlers[irq].handler = handler; |
int_handlers[irq].arg = arg; |
|
mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << vect)); |
mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << irq)); |
|
return 0; |
} |
|
/* Disable interrupt */ |
int int_disable(unsigned long vect) |
int int_disable(unsigned long irq) |
{ |
if(vect >= MAX_INT_HANDLERS) |
if(irq >= MAX_INT_HANDLERS) |
return -1; |
|
mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(0x00000001L << vect)); |
mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(0x00000001L << irq)); |
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return 0; |
} |
|
/* Enable interrupt */ |
int int_enable(unsigned long vect) |
int int_enable(unsigned long irq) |
{ |
if(vect >= MAX_INT_HANDLERS) |
if(irq >= MAX_INT_HANDLERS) |
return -1; |
|
mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << vect)); |
mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << irq)); |
|
return 0; |
} |
71,7 → 71,12
while(i < 32) { |
if((picsr & (0x01L << i)) && (int_handlers[i].handler != 0)) { |
(*int_handlers[i].handler)(int_handlers[i].arg); |
mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(0x00000001L << i)); |
#ifdef OR1200_INT_CHECK_BIT_CLEARED |
// Ensure PICSR bit is cleared, incase it takes some time for the |
// IRQ line going low to propagate back to PIC |
while (mfspr(SPR_PICSR) & (0x00000001L << i)) |
#endif |
mtspr(SPR_PICSR, mfspr(SPR_PICSR) & ~(0x00000001L << i)); |
} |
i++; |
} |
/link.ld
72,14 → 72,10
/* ensure there is enough room for stack */ |
.stack (NOLOAD): { |
. = ALIGN(4); |
sstack = . ; |
_sstack = . ; |
. = . + _min_stack ; |
. = . + _min_stack ; |
. = ALIGN(4); |
stack = . ; |
_stack = . ; |
estack = . ; |
_estack = . ; |
} > ram |
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.stab 0 (NOLOAD) : |
/Makefile
1,7 → 1,7
SW_ROOT=../.. |
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# Sources to go into the liborpsoc.a support library |
COMPILE_SRCS=exceptions.c int.c or1200-mmu.S or1200-utils.c |
COMPILE_SRCS=exceptions.c int.c or1200-mmu.S or1200-utils.c cache.S |
|
include $(SW_ROOT)/Makefile.inc |
|