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    /openrisc/trunk/orpsocv2/sw/drivers
    from Rev 408 to Rev 409
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Rev 408 → Rev 409

/ethmac/ethmac.c
0,0 → 1,46
//////////////////////////////////////////////////////////////////////
//// ////
//// Ethernet MAC driver functions ////
//// ////
//// Description ////
//// A collection of functions to help control the OpenCores ////
//// 10/100 ethernet mac (ethmac) core. ////
//// ////
//// ////
//// Author(s): ////
//// - Julius Baxter, julius@opencores.org ////
//// - Parts taken from Linux kernel's open_eth driver. ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009,2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
/* Dummy function for now, just to make the driver compile */
void ethmac_init()
{
return;
}
/ethmac/include/eth-phy-mii.h
0,0 → 1,149
#ifndef _ETH_PHY_MII_H_
#define _ETH_PHY_MII_H_
/* Generic MII registers. */
 
#define MII_BMCR 0x00 /* Basic mode control register */
#define MII_BMSR 0x01 /* Basic mode status register */
#define MII_PHYSID1 0x02 /* PHYS ID 1 */
#define MII_PHYSID2 0x03 /* PHYS ID 2 */
#define MII_ADVERTISE 0x04 /* Advertisement control reg */
#define MII_LPA 0x05 /* Link partner ability reg */
#define MII_EXPANSION 0x06 /* Expansion register */
#define MII_CTRL1000 0x09 /* 1000BASE-T control */
#define MII_STAT1000 0x0a /* 1000BASE-T status */
#define MII_ESTATUS 0x0f /* Extended Status */
#define MII_DCOUNTER 0x12 /* Disconnect counter */
#define MII_FCSCOUNTER 0x13 /* False carrier counter */
#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
#define MII_RERRCOUNTER 0x15 /* Receive error counter */
#define MII_SREVISION 0x16 /* Silicon revision */
#define MII_RESV1 0x17 /* Reserved... */
#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
#define MII_PHYADDR 0x19 /* PHY address */
#define MII_RESV2 0x1a /* Reserved... */
#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
#define MII_NCONFIG 0x1c /* Network interface config */
 
/* Basic mode control register. */
#define BMCR_SPD2 0x0040 /* Gigabit enable? (bcm5411) */
#define BMCR_RESV 0x003f /* Unused... */
#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
#define BMCR_CTST 0x0080 /* Collision test */
#define BMCR_FULLDPLX 0x0100 /* Full duplex */
#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
#define BMCR_SPEED100 0x2000 /* Select 100Mbps */
#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
#define BMCR_RESET 0x8000 /* Reset the DP83840 */
 
/* Basic mode status register. */
#define BMSR_ERCAP 0x0001 /* Ext-reg capability */
#define BMSR_JCD 0x0002 /* Jabber detected */
#define BMSR_LSTATUS 0x0004 /* Link status */
#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
#define BMSR_RFAULT 0x0010 /* Remote fault detected */
#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
#define BMSR_RESV 0x00c0 /* Unused... */
#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */
#define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
#define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */
#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
 
/* Advertisement control register. */
#define ADVERTISE_SLCT 0x001f /* Selector bits */
#define ADVERTISE_CSMA 0x0001 /* Only selector supported */
#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
#define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */
#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
#define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */
#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
#define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */
#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
#define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */
#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */
#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */
#define ADVERTISE_RESV 0x1000 /* Unused... */
#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
#define ADVERTISE_NPAGE 0x8000 /* Next page bit */
 
#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
ADVERTISE_CSMA)
#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
ADVERTISE_100HALF | ADVERTISE_100FULL)
 
/* Link partner ability register. */
#define LPA_SLCT 0x001f /* Same as advertise selector */
#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
#define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */
#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
#define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */
#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
#define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */
#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
#define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym*/
#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
#define LPA_PAUSE_CAP 0x0400 /* Can pause */
#define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */
#define LPA_RESV 0x1000 /* Unused... */
#define LPA_RFAULT 0x2000 /* Link partner faulted */
#define LPA_LPACK 0x4000 /* Link partner acked us */
#define LPA_NPAGE 0x8000 /* Next page bit */
 
#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
 
/* Expansion register for auto-negotiation. */
#define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */
#define EXPANSION_LCWP 0x0002 /* Got new RX page code word */
#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */
#define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */
#define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */
#define EXPANSION_RESV 0xffe0 /* Unused... */
 
#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */
#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */
 
/* N-way test register. */
#define NWAYTEST_RESV1 0x00ff /* Unused... */
#define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */
#define NWAYTEST_RESV2 0xfe00 /* Unused... */
 
/* 1000BASE-T Control register */
#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */
#define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */
 
/* 1000BASE-T Status register */
#define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */
#define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */
#define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */
#define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */
 
/* 1000BT control (Marvell & BCM54xx at least) */
#define MII_1000BASETCONTROL 0x09
#define MII_1000BASETCONTROL_FULLDUPLEXCAP 0x0200
#define MII_1000BASETCONTROL_HALFDUPLEXCAP 0x0100
 
/* Marvell 88E1011 PHY control */
#define MII_M1011_PHY_SPEC_CONTROL 0x10
#define MII_M1011_PHY_SPEC_CONTROL_MANUAL_MDIX 0x20
#define MII_M1011_PHY_SPEC_CONTROL_AUTO_MDIX 0x40
 
/* Marvell 88E1011 PHY status */
#define MII_M1011_PHY_SPEC_STATUS 0x11
#define MII_M1011_PHY_SPEC_STATUS_1000 0x8000
#define MII_M1011_PHY_SPEC_STATUS_100 0x4000
#define MII_M1011_PHY_SPEC_STATUS_SPD_MASK 0xc000
#define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX 0x2000
#define MII_M1011_PHY_SPEC_STATUS_RESOLVED 0x0800
#define MII_M1011_PHY_SPEC_STATUS_TX_PAUSE 0x0008
#define MII_M1011_PHY_SPEC_STATUS_RX_PAUSE 0x0004
 
#endif
/ethmac/include/ethmac.h
0,0 → 1,195
//////////////////////////////////////////////////////////////////////
//// ////
//// Ethernet MAC driver functions ////
//// ////
//// Description ////
//// A collection of functions to help control the OpenCores ////
//// 10/100 ethernet mac (ethmac) core. ////
//// ////
//// ////
//// Author(s): ////
//// - Julius Baxter, julius@opencores.org ////
//// - Parts taken from Linux kernel's open_eth driver. ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009,2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
#ifndef _ETHMAC_H_
#define _ETHMAC_H
typedef unsigned int uint;
 
/* Ethernet configuration registers */
typedef struct _oeth_regs {
uint moder; /* Mode Register */
uint int_src; /* Interrupt Source Register */
uint int_mask; /* Interrupt Mask Register */
uint ipgt; /* Back to Bak Inter Packet Gap Register */
uint ipgr1; /* Non Back to Back Inter Packet Gap Register 1 */
uint ipgr2; /* Non Back to Back Inter Packet Gap Register 2 */
uint packet_len; /* Packet Length Register (min. and max.) */
uint collconf; /* Collision and Retry Configuration Register */
uint tx_bd_num; /* Transmit Buffer Descriptor Number Register */
uint ctrlmoder; /* Control Module Mode Register */
uint miimoder; /* MII Mode Register */
uint miicommand; /* MII Command Register */
uint miiaddress; /* MII Address Register */
uint miitx_data; /* MII Transmit Data Register */
uint miirx_data; /* MII Receive Data Register */
uint miistatus; /* MII Status Register */
uint mac_addr0; /* MAC Individual Address Register 0 */
uint mac_addr1; /* MAC Individual Address Register 1 */
uint hash_addr0; /* Hash Register 0 */
uint hash_addr1; /* Hash Register 1 */
} oeth_regs;
 
/* Ethernet buffer descriptor */
typedef struct _oeth_bd {
#if 0
ushort len; /* Buffer length */
ushort status; /* Buffer status */
#else
uint len_status;
#endif
uint addr; /* Buffer address */
} oeth_bd;
 
// From board.h
#define ETH_BASE_ADD ETH0_BASE
 
#define OETH_REG_BASE ETH_BASE_ADD
#define OETH_BD_BASE (ETH_BASE_ADD + 0x400)
#define OETH_TOTAL_BD 128
#define OETH_MAXBUF_LEN 0x600
/* Tx BD */
#define OETH_TX_BD_READY 0x8000 /* Tx BD Ready */
#define OETH_TX_BD_IRQ 0x4000 /* Tx BD IRQ Enable */
#define OETH_TX_BD_WRAP 0x2000 /* Tx BD Wrap (last BD) */
#define OETH_TX_BD_PAD 0x1000 /* Tx BD Pad Enable */
#define OETH_TX_BD_CRC 0x0800 /* Tx BD CRC Enable */
#define OETH_TX_BD_UNDERRUN 0x0100 /* Tx BD Underrun Status */
#define OETH_TX_BD_RETRY 0x00F0 /* Tx BD Retry Status */
#define OETH_TX_BD_RETLIM 0x0008 /* Tx BD Retransmission Limit Status */
#define OETH_TX_BD_LATECOL 0x0004 /* Tx BD Late Collision Status */
#define OETH_TX_BD_DEFER 0x0002 /* Tx BD Defer Status */
#define OETH_TX_BD_CARRIER 0x0001 /* Tx BD Carrier Sense Lost Status */
#define OETH_TX_BD_STATS (OETH_TX_BD_UNDERRUN | \
OETH_TX_BD_RETRY | \
OETH_TX_BD_RETLIM | \
OETH_TX_BD_LATECOL | \
OETH_TX_BD_DEFER | \
OETH_TX_BD_CARRIER)
/* Rx BD */
#define OETH_RX_BD_EMPTY 0x8000 /* Rx BD Empty */
#define OETH_RX_BD_IRQ 0x4000 /* Rx BD IRQ Enable */
#define OETH_RX_BD_WRAP 0x2000 /* Rx BD Wrap (last BD) */
#define OETH_RX_BD_MISS 0x0080 /* Rx BD Miss Status */
#define OETH_RX_BD_OVERRUN 0x0040 /* Rx BD Overrun Status */
#define OETH_RX_BD_INVSIMB 0x0020 /* Rx BD Invalid Symbol Status */
#define OETH_RX_BD_DRIBBLE 0x0010 /* Rx BD Dribble Nibble Status */
#define OETH_RX_BD_TOOLONG 0x0008 /* Rx BD Too Long Status */
#define OETH_RX_BD_SHORT 0x0004 /* Rx BD Too Short Frame Status */
#define OETH_RX_BD_CRCERR 0x0002 /* Rx BD CRC Error Status */
#define OETH_RX_BD_LATECOL 0x0001 /* Rx BD Late Collision Status */
#define OETH_RX_BD_STATS (OETH_RX_BD_MISS | \
OETH_RX_BD_OVERRUN | \
OETH_RX_BD_INVSIMB | \
OETH_RX_BD_DRIBBLE | \
OETH_RX_BD_TOOLONG | \
OETH_RX_BD_SHORT | \
OETH_RX_BD_CRCERR | \
OETH_RX_BD_LATECOL)
 
/* MODER Register */
#define OETH_MODER_RXEN 0x00000001 /* Receive Enable */
#define OETH_MODER_TXEN 0x00000002 /* Transmit Enable */
#define OETH_MODER_NOPRE 0x00000004 /* No Preamble */
#define OETH_MODER_BRO 0x00000008 /* Reject Broadcast */
#define OETH_MODER_IAM 0x00000010 /* Use Individual Hash */
#define OETH_MODER_PRO 0x00000020 /* Promiscuous (receive all) */
#define OETH_MODER_IFG 0x00000040 /* Min. IFG not required */
#define OETH_MODER_LOOPBCK 0x00000080 /* Loop Back */
#define OETH_MODER_NOBCKOF 0x00000100 /* No Backoff */
#define OETH_MODER_EXDFREN 0x00000200 /* Excess Defer */
#define OETH_MODER_FULLD 0x00000400 /* Full Duplex */
#define OETH_MODER_RST 0x00000800 /* Reset MAC */
#define OETH_MODER_DLYCRCEN 0x00001000 /* Delayed CRC Enable */
#define OETH_MODER_CRCEN 0x00002000 /* CRC Enable */
#define OETH_MODER_HUGEN 0x00004000 /* Huge Enable */
#define OETH_MODER_PAD 0x00008000 /* Pad Enable */
#define OETH_MODER_RECSMALL 0x00010000 /* Receive Small */
/* Interrupt Source Register */
#define OETH_INT_TXB 0x00000001 /* Transmit Buffer IRQ */
#define OETH_INT_TXE 0x00000002 /* Transmit Error IRQ */
#define OETH_INT_RXF 0x00000004 /* Receive Frame IRQ */
#define OETH_INT_RXE 0x00000008 /* Receive Error IRQ */
#define OETH_INT_BUSY 0x00000010 /* Busy IRQ */
#define OETH_INT_TXC 0x00000020 /* Transmit Control Frame IRQ */
#define OETH_INT_RXC 0x00000040 /* Received Control Frame IRQ */
 
/* Interrupt Mask Register */
#define OETH_INT_MASK_TXB 0x00000001 /* Transmit Buffer IRQ Mask */
#define OETH_INT_MASK_TXE 0x00000002 /* Transmit Error IRQ Mask */
#define OETH_INT_MASK_RXF 0x00000004 /* Receive Frame IRQ Mask */
#define OETH_INT_MASK_RXE 0x00000008 /* Receive Error IRQ Mask */
#define OETH_INT_MASK_BUSY 0x00000010 /* Busy IRQ Mask */
#define OETH_INT_MASK_TXC 0x00000020 /* Transmit Control Frame IRQ Mask */
#define OETH_INT_MASK_RXC 0x00000040 /* Received Control Frame IRQ Mask */
/* Control Module Mode Register */
#define OETH_CTRLMODER_PASSALL 0x00000001 /* Pass Control Frames */
#define OETH_CTRLMODER_RXFLOW 0x00000002 /* Receive Control Flow Enable */
#define OETH_CTRLMODER_TXFLOW 0x00000004 /* Transmit Control Flow Enable */
/* MII Mode Register */
#define OETH_MIIMODER_CLKDIV 0x000000FF /* Clock Divider */
#define OETH_MIIMODER_NOPRE 0x00000100 /* No Preamble */
#define OETH_MIIMODER_RST 0x00000200 /* MIIM Reset */
/* MII Command Register */
#define OETH_MIICOMMAND_SCANSTAT 0x00000001 /* Scan Status */
#define OETH_MIICOMMAND_RSTAT 0x00000002 /* Read Status */
#define OETH_MIICOMMAND_WCTRLDATA 0x00000004 /* Write Control Data */
/* MII Address Register */
#define OETH_MIIADDRESS_FIAD 0x0000001F /* PHY Address */
#define OETH_MIIADDRESS_RGAD 0x00001F00 /* RGAD Address */
/* MII Status Register */
#define OETH_MIISTATUS_LINKFAIL 0x00000001 /* Link Fail */
#define OETH_MIISTATUS_BUSY 0x00000002 /* MII Busy */
#define OETH_MIISTATUS_NVALID 0x00000004 /* Data in MII Status Register is invalid */
 
/* Dummy function for now, just to make the driver compile */
void ethmac_init();
 
#endif
/ethmac/Makefile
0,0 → 1,8
SW_ROOT=../..
 
COMPILE_SRCS=ethmac.c
 
include $(SW_ROOT)/Makefile.inc
 
clean:
$(Q)rm -f *.a *.o

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