URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2/sw/drivers
- from Rev 486 to Rev 488
- ↔ Reverse comparison
Rev 486 → Rev 488
/or1200/exceptions.c
40,6 → 40,7
}; |
|
extern void int_main(); |
extern void cpu_timer_tick(); |
|
void (*except_handlers[]) (void ) = {0, // 0 |
0, // 1 |
46,7 → 47,7
0, // 2 |
0, // 3 |
0, // 4 |
0, // 5 |
cpu_timer_tick, // 5 |
0, // 6 |
0, // 7 |
int_main, // 8 |
/or1200/or1200-utils.c
75,12 → 75,13
} |
|
/* Timer increment - called by interrupt routine */ |
/* Now actually done in interrupt vector code in crt0.S */ |
void |
cpu_timer_tick(void) |
{ |
timer_ticks++; |
mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT | ((IN_CLK/TICKS_PER_SEC) & SPR_TTMR_PERIOD)); |
// Reset timer mode register to interrupt with same interval |
mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT | |
((IN_CLK/TICKS_PER_SEC) & SPR_TTMR_PERIOD)); |
} |
|
/* Reset tick counter */ |
/or1200/crt0.S
93,29 → 93,10
.org 0x400 |
EXCEPTION_HANDLER |
|
|
/* ---[ 0x500: Timer exception ]----------------------------------------- */ |
.org 0x500 |
#define TIMER_RELOAD_VALUE (SPR_TTMR_IE | SPR_TTMR_RT | ((IN_CLK/TICKS_PER_SEC) & SPR_TTMR_PERIOD)) |
//EXCEPTION_HANDLER |
/* Simply load timer_ticks variable and increment */ |
.extern timer_ticks |
l.addi r1, r1, -136 |
l.sw 0(r1), r25 |
l.sw 4(r1), r26 |
l.movhi r25, hi(timer_ticks) |
l.ori r25, r25, lo(timer_ticks) |
l.lwz r26, 0(r25) /* Load variable addr.*/ |
l.addi r26, r26, 1 /* Increment variable */ |
l.sw 0(r25), r26 /* Store variable */ |
l.movhi r25, hi(TIMER_RELOAD_VALUE) /* Load timer value */ |
l.ori r25, r25, lo(TIMER_RELOAD_VALUE) |
l.mtspr r0, r25, SPR_TTMR /* Reset timer */ |
l.lwz r25, 0(r1) |
l.lwz r26, 4(r1) |
l.addi r1, r1, 136 |
l.rfe |
|
EXCEPTION_HANDLER |
|
/* ---[ 0x600: Aligment exception ]-------------------------------------- */ |
.org 0x600 |
EXCEPTION_HANDLER |