URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2/sw/drivers
- from Rev 488 to Rev 489
- ↔ Reverse comparison
Rev 488 → Rev 489
/or1200/exceptions.c
39,10 → 39,10
"A Custom", // 1f |
}; |
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extern void int_main(); |
extern void cpu_timer_tick(); |
extern void int_main(void); |
extern void cpu_timer_tick(void); |
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void (*except_handlers[]) (void ) = {0, // 0 |
void (*except_handlers[]) (void) = {0, // 0 |
0, // 1 |
0, // 2 |
0, // 3 |
65,20 → 65,22
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void |
add_handler(unsigned long vector, void (*handler) (void *)) |
add_handler(unsigned long vector, void (*handler) (void)) |
{ |
except_handlers[vector] = handler; |
} |
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void default_exception_handler_c(unsigned exception_address,unsigned epc) |
void |
default_exception_handler_c(unsigned exception_address,unsigned epc) |
{ |
int exception_no = (exception_address >> 8) & 0x1f; |
if (except_handlers[exception_no]) |
{ |
return (*except_handlers[exception_no])(); |
(*except_handlers[exception_no])(); |
return; |
} |
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// Init uart here, incase it hasn't been |
// init uart here, incase it hasn't been |
uart_init(DEFAULT_UART); |
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printf("EPC = 0x%.8x\n", exception_address); |
/or1200/include/int.h
14,7 → 14,7
int int_add(unsigned long vect, void (* handler)(void *), void *arg); |
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/* Add exception vector handler */ |
void add_handler(unsigned long vector, void (* handler) (void *)); |
void add_handler(unsigned long vector, void (* handler) (void)); |
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/* Initialize routine */ |
int int_init(); |
/or1200/include/or1200-utils.h
1,6 → 1,9
#ifndef _OR1200_UTILS_H_ |
#define _OR1200_UTILS_H_ |
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// Pull in interrupt defines here |
#include "int.h" |
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/* Register access macros */ |
#define REG8(add) *((volatile unsigned char *)(add)) |
#define REG16(add) *((volatile unsigned short *)(add)) |
/or1200/crt0.S
31,7 → 31,6
/* =================================================== [ exceptions ] === */ |
.section .vectors, "ax" |
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/* ---[ 0x100: RESET exception ]----------------------------------------- */ |
.org 0x100 |
l.movhi r0, 0 |
197,6 → 196,8
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ENTRY(_start) |
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/* Instruction cache enable */ |
/* Check if IC present and skip enabling otherwise */ |
l.mfspr r24,r0,SPR_UPR |