OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/orpsocv2/sw/drivers
    from Rev 545 to Rev 655
    ↔ Reverse comparison
  •

Rev 545 → Rev 655

/cfi-ctrl/include/cfi_ctrl.h
0,0 → 1,38
/* cfi_ctrl driver header */
 
#define CFI_CTRL_UNLOCKBLOCK_OFFSET 0x04000000
#define CFI_CTRL_ERASEBLOCK_OFFSET 0x08000000
#define CFI_CTRL_REGS_OFFSET 0x0c000000
#define CFI_CTRL_DEVICEIDENT_OFFSET 0x0e000000
#define CFI_CTRL_CFIQUERY_OFFSET 0x0e010000
 
#define CFI_CTRL_SCR_OFFSET (CFI_CTRL_REGS_OFFSET + 0)
#define CFI_CTRL_FSR_OFFSET (CFI_CTRL_REGS_OFFSET + 4)
 
#define CFI_CTRL_SCR_CONTROLLER_BUSY (1 << 0)
#define CFI_CTRL_SCR_CLEAR_FSR (1 << 1)
#define CFI_CTRL_SCR_RESET_DEVICE (1 << 2)
 
/* Flash status register (FSR) bit meanings - from CFI standard */
#define CFI_FSR_DWS (1<<7) /* Device write status. 0 - busy, 1 - ready */
#define CFI_FSR_ERR (1<<6) /* Erase suspend status - N/A here */
#define CFI_FSR_ES (1<<5) /* Erase status. 0 - successful, 1 - fail/seq err. */
#define CFI_FSR_PS (1<<4) /* Program status. 0 - successful, 1 - fail/seq err*/
#define CFI_FSR_VPPS (1<<3) /* VPP status. N/A here */
#define CFI_FSR_PSS (1<<2) /* Program suspend status. N/A here */
#define CFI_FSR_BLS (1<<1) /* Block-locked status */
#define CFI_FSR_BWS (1<<0) /* Buffer-enhanced programming status - N/A here */
 
 
/* Driver function prototypes */
void cfi_ctrl_reset_flash(void);
void cfi_ctrl_clear_status(void);
int cfi_ctrl_busy(void);
unsigned char cfi_ctrl_get_status(void);
void cfi_ctrl_unlock_block(unsigned int addr);
int cfi_ctrl_erase_block(unsigned int addr);
void cfi_ctrl_erase_block_no_wait(unsigned int addr);
int cfi_ctrl_write_short(short data, unsigned int addr);
short cfi_ctrl_read_identifier(unsigned int addr);
short cfi_ctrl_query_info(unsigned int addr);
void cfi_ctrl_enable_data_read(void);
/cfi-ctrl/cfi_ctrl.c
0,0 → 1,112
/* Driver functions for cfi_ctrl module which is to control
CFI flash devices.
*/
 
#include "board.h"
#include "cpu-utils.h"
#include "cfi_ctrl.h"
 
void cfi_ctrl_reset_flash(void)
{
//REG32((CFI_CTRL_BASE + CFI_CTRL_SCR_OFFSET)) = CFI_CTRL_SCR_RESET_DEVICE;
// Put in array read mode, like reset would
REG16(CFI_CTRL_BASE) = 0x00ff;
}
 
int cfi_ctrl_busy(void)
{
// return REG32((CFI_CTRL_BASE + CFI_CTRL_SCR_OFFSET)) &
//CFI_CTRL_SCR_CONTROLLER_BUSY;
return 0;
}
 
void cfi_ctrl_clear_status(void)
{
//REG32((CFI_CTRL_BASE + CFI_CTRL_SCR_OFFSET)) = CFI_CTRL_SCR_CLEAR_FSR;
REG16(CFI_CTRL_BASE) = 0x0050;
}
 
unsigned char cfi_ctrl_get_status(void)
{
//return (unsigned char) (REG32((CFI_CTRL_BASE + CFI_CTRL_FSR_OFFSET)) & 0xff);
REG16(CFI_CTRL_BASE) = 0x0070;
return (unsigned char) REG16(CFI_CTRL_BASE);
}
 
void cfi_ctrl_unlock_block(unsigned int addr)
{
//REG32((CFI_CTRL_BASE + CFI_CTRL_UNLOCKBLOCK_OFFSET + addr)) = 0;
REG16(CFI_CTRL_BASE + addr) = 0x0060;
REG16(CFI_CTRL_BASE + addr) = 0x00d0;
}
 
int cfi_ctrl_erase_block(unsigned int addr)
{
cfi_ctrl_clear_status();
 
/* Unlock block first */
cfi_ctrl_unlock_block(addr);
//REG32((CFI_CTRL_BASE + CFI_CTRL_ERASEBLOCK_OFFSET + addr)) = 0;
REG16(CFI_CTRL_BASE + addr) = 0x0020;
REG16(CFI_CTRL_BASE + addr) = 0x00d0;
 
/* Wait for device to be finished erasing */
while(!(cfi_ctrl_get_status() & CFI_FSR_DWS));
 
/* Check if programming was successful */
return !!(cfi_ctrl_get_status() & CFI_FSR_ES);
}
 
void cfi_ctrl_erase_block_no_wait(unsigned int addr)
{
cfi_ctrl_clear_status();
 
/* Unlock block first */
cfi_ctrl_unlock_block(addr);
/* Now erase the block */
REG16(CFI_CTRL_BASE + addr) = 0x0020;
REG16(CFI_CTRL_BASE + addr) = 0x00d0;
// REG32((CFI_CTRL_BASE + CFI_CTRL_ERASEBLOCK_OFFSET + addr)) = 0;
return;
}
 
int cfi_ctrl_write_short(short data, unsigned int addr)
{
 
cfi_ctrl_clear_status();
 
REG16(CFI_CTRL_BASE + addr) = 0x0040;
REG16(CFI_CTRL_BASE + addr) = data;
/* Wait for device to write */
while(!(cfi_ctrl_get_status() & CFI_FSR_DWS));
 
/* Check if programming was successful */
return !!(cfi_ctrl_get_status() & CFI_FSR_PS);
}
 
void cfi_ctrl_enable_data_read(void)
{
REG16(CFI_CTRL_BASE) = 0x00ff;
}
 
short cfi_ctrl_read_identifier(unsigned int addr)
{
//return REG16(CFI_CTRL_BASE + CFI_CTRL_DEVICEIDENT_OFFSET + (addr<<1));
REG16(CFI_CTRL_BASE) = 0x0090;
return REG16(CFI_CTRL_BASE + (addr<<1));
}
 
short cfi_ctrl_query_info(unsigned int addr)
{
REG16(CFI_CTRL_BASE) = 0x0098;
return REG16(CFI_CTRL_BASE + (addr<<1));
}
 
 
/cfi-ctrl/Makefile
0,0 → 1,8
SW_ROOT=../..
 
COMPILE_SRCS=cfi_ctrl.c
 
include $(SW_ROOT)/Makefile.inc
 
clean:
$(Q)rm -f *.a *.o

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.