URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2/sw/tests
- from Rev 415 to Rev 425
- ↔ Reverse comparison
Rev 415 → Rev 425
/ethmac/board/ethmac-ping.c
100,8 → 100,8
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/* Buffer number (must be 2^n) |
*/ |
#define OETH_RXBD_NUM 32 |
#define OETH_TXBD_NUM 32 |
#define OETH_RXBD_NUM 64 |
#define OETH_TXBD_NUM 64 |
#define OETH_RXBD_NUM_MASK (OETH_RXBD_NUM-1) |
#define OETH_TXBD_NUM_MASK (OETH_TXBD_NUM-1) |
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1790,9 → 1790,10
} |
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if (bad) { |
printf("RXE: 0x%x\n",rx_bdp[i].len_status & OETH_RX_BD_STATS); |
rx_bdp[i].len_status &= ~OETH_RX_BD_STATS; |
rx_bdp[i].len_status |= OETH_RX_BD_EMPTY; |
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bad = 0; |
continue; |
} |
else { |
1844,6 → 1845,9
tx_bd[i].len_status &= ~OETH_TX_BD_IRQ; |
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/* Probably good to check for TX errors here */ |
// Check if either carrier sense lost or colission indicated |
if (tx_bd[i].len_status & OETH_TX_BD_STATS) |
printf("TXER: 0x%x\n",(tx_bd[i].len_status & OETH_TX_BD_STATS)); |
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if (print_packet_contents) |
printf("T%d",i); |
/or1200/sim/or1200-mac.S
240,6 → 240,8
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l.movhi r3, 0x8000 |
l.ori r3, r3, 0x000d |
l.nop 0x2 |
l.ori r3, r0, 0 |
l.nop 0x1 |
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fail: |
/or1200/sim/or1200-cbasic.c
195,7 → 195,8
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// gives us 8000000d (goooood) |
report(result3+0x3474E142); |
//exit(result3-0x6cdd401e); |
exit(result3+0x3474E142); |
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if (result3+0x3474E142 == 0x8000000d) |
exit(0); |
else |
exit(1); |
} |
/or1200/sim/or1200-fp.S
2614,7 → 2614,7
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l.movhi r3,hi(ALL_DONE) |
l.ori r3,r3,lo(ALL_DONE) |
l.nop NOP_REPORT /* Should be 0xdeaddead */ |
l.nop NOP_REPORT |
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l.addi r3,r0,0 |
l.nop NOP_EXIT |
/or1200/sim/or1200-dctest.c
29,11 → 29,12
{ |
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// Check data cache is present and enabled |
if (!(mfspr(SPR_UPR)& SPR_UPR_DCP)) |
return 0x8000000d; |
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if (!(mfspr(SPR_SR) & SPR_SR_DCE)) |
return 0x8000000d; |
if (!(mfspr(SPR_UPR)& SPR_UPR_DCP) | !(mfspr(SPR_SR) & SPR_SR_DCE)) |
{ |
// Not really a pass, but not really a fail, either. |
report(0x8000000d); |
return 0; |
} |
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volatile char* ptr = (volatile char*) 0xe00000; |
int i; |
150,7 → 151,9
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report(next_rand()); |
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return 0x8000000d; |
report(0x8000000d); |
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exit(0); |
} |
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/or1200/sim/or1200-maci.S
125,4 → 125,8
l.mfspr r3,r0,SPR_MACLO |
l.nop 0x2 |
l.nop |
l.nop 0x1 |
l.movhi r3, hi(0x8000000d) |
l.ori r3, r3, lo(0x8000000d) |
l.nop 0x2 |
l.ori r3, r0, 0 |
l.nop 0x1 |
/or1200/sim/or1200-mmu.c
1532,6 → 1532,5
printf("Tests completed\n"); |
report (0xdeaddead); |
report (0x8000000d); |
exit (0x8000000d); |
return 0; |
exit (0); |
} |
/or1200/sim/or1200-basic.S
1095,8 → 1095,9
l.add r3,r8,r3 /* Should be 0xdeaddead */ |
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l.movhi r4, 0x5ead |
l.ori r4, r4, 0xdea0 |
l.sub r3, r3, r4 /* Should now be 0x8000000d */ |
l.ori r4, r4, 0xdea0 |
l.sub r3, r3, r4 /* Should now be 0x8000000d */ |
l.nop 0x2 |
l.ori r3, r0, 0 /* Clear R3 */ |
l.nop 0x1 /* Exit simulation */ |
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l.nop 0x1 /* Exit simulation */ |
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/or1200/sim/or1200-float.c
39,6 → 39,8
if (*int_ptr != 0x45388615) |
exit(3); |
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exit(0x8000000d); |
report(0x8000000d); |
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exit(0); |
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} |
/or1200/sim/or1200-ticksyscall.S
333,6 → 333,8
l.nop |
l.movhi r3, hi(0x8000000d) |
l.ori r3, r3, lo(0x8000000d) |
l.nop 2 |
l.ori r3, r0, 0 |
l.nop 1 |
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_fail: |
/or1200/sim/or1200-except.S
514,8 → 514,10
l.movhi r5, hi(0x44004800) /* Put "l.jr r9" instruction in r5 */ |
l.ori r5, r5, lo(0x44004800) |
l.sw 0x0(r0), r5 /* Write "l.j r9" to address 0x0 in RAM */ |
l.movhi r5, 0xff00 /* Put an illegal instruction in r5 */ |
l.sw 0x4(r0), r5 /* Write illegal instruction to RAM addr 0x4 */ |
l.movhi r5, 0xee00 /* Put an illegal instruction in r5 */ |
l.sw 0x4(r0), r5 /* Write illegal instruction to RAM addr 0x4 */ |
l.movhi r5, 0x1500 /* l.nop after illegal instruction */ |
l.sw 0x8(r0), r5 /* Write nop to RAM addr 0x8 */ |
l.mtspr r0,r0,SPR_ICBIR /* Invalidate line 0 of cache */ |
/* Call 0x4, illegal opcode instruction */ |
l.ori r6, r0, 0x4 |
/or1200/sim/or1200-ffl1.S
271,7 → 271,7
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fl1_error: |
l.movhi r3, hi(0xbaaadf11) |
l.ori r3, r3, lo(0xbaaadf11) |
l.ori r3, r3, lo(0xbaaadf11) |
l.nop 0x1 |
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278,6 → 278,8
ffl1_ok: |
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l.movhi r3, hi(0x8000000d) |
l.ori r3, r3, lo(0x8000000d) |
l.nop 0x1 |
l.ori r3, r3, lo(0x8000000d) |
l.nop 0x2 /* Report */ |
l.ori r3, r0, 0 /* Return 0 */ |
l.nop 0x1 |
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/or1200/sim/or1200-linkregtest.S
94,16 → 94,20
l.nop |
l.movhi r3, hi(0x8000000d) |
l.ori r3, r3, lo(0x8000000d) |
/* Try writing to r9 during delay slot... */ |
/* Setup some code at address 0x0 */ |
l.movhi r4, hi(0x15000000) /* standard l.nop */ |
l.ori r5, r4, 0x2 /* l.nop that will report value in r3 */ |
l.sw 0x0(r0), r5 /* Write "l.nop 0x2" to 0x0 */ |
l.movhi r6, hi(0xa8600000) /*Assemble register with l.ori r3,r0,0 */ |
l.sw 0x4(r0), r6 /* Write "l.ori r3,r0,0" to 0x4*/ |
l.ori r5, r4, 0x1 /* l.nop that will exit simulation */ |
l.sw 0(r0), r4 /* Write l.nop to 0x0 */ |
l.sw 4(r0), r4 /* Write l.nop to 0x4 */ |
l.sw 8(r0), r5 /* Write l.nop 0x1 to 0x9 */ |
l.sw 12(r0), r4 /* Write l.nop to 0xc */ |
l.sw 0x8(r0), r5 /* Write l.nop 0x1 to 0x8 */ |
l.sw 0xc(r0), r0 /* Write "l.j 0" to address 0xc */ |
l.sw 0x10(r0), r4 /* Write l.nop to 0xc */ |
l.nop |
/* Try writing to r9 during delay slot... */ |
l.jal _testjalfunc |
l.or r9, r0, r0 /* Clear r9 */ |
l.or r9, r0, r0 /* Clear r9 - cause jump to 0 on return */ |
l.nop 1 |
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