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URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/orpsocv2/sw
    from Rev 397 to Rev 403
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  •

Rev 397 → Rev 403

/bootrom/bootrom.S
39,7 → 39,7
#include "board.h"
 
#ifdef BOOTLOADER_SPI_FLASH
#ifdef BOOTROM_SPI_FLASH
/* Assembly program to go into the boot ROM */
/* Currently just loads a program from SPI flash into RAM */
117,7 → 117,7
 
#endif
 
#ifdef BOOTLOADER_GOTO_RESET
#ifdef BOOTROM_GOTO_RESET
/* Jump to reset vector in the SDRAM */
l.movhi r0, 0
l.movhi r4, SDRAM_BASE
127,7 → 127,7
#endif
 
#ifdef BOOTLOADER_LOOP_AT_ZERO
#ifdef BOOTROM_LOOP_AT_ZERO
 
/* Don't load app via SPI, instead just put an infinite loop into bottom
of memory and jump there.
147,7 → 147,7
 
#endif
 
#ifdef BOOTLOADER_LOOP_IN_ROM
#ifdef BOOTROM_LOOP_IN_ROM
 
/* Don't load app via SPI, instead just put an infinite loop into bottom
of memory and jump there.
/tests/eth/sim/Makefile
1,5 → 1,7
include ../Makefile.inc
SW_ROOT=../../..
 
include $(SW_ROOT)/Makefile.inc
 
%.dis: %.elf
$(Q)$(OR32_OBJDUMP) -d $< > $@
 
8,3 → 10,4
 
clean:
$(Q)rm -f *.elf *.bin *.vmem *.flashin *.dis
 
/tests/or1200/sim/or1200-ffl1.S
0,0 → 1,283
/*
OR1200 Find First/Last '1' Test
 
Checks l.ff1 and l.fl1 outputs for every bit position
 
Julius Baxter, julius.baxter@orsoc.se
*/
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
#include "spr-defs.h"
#include "board.h"
#include "or1200-defines.h"
 
// Check MAC unit is enabled before trying to run this test
#ifndef OR1200_IMPL_ALU_FFL1
# error
# error Find First/Last '1' isntructions not enabled.
# error
#endif
 
/* =================================================== [ exceptions ] === */
.section .vectors, "ax"
 
 
/* ---[ 0x100: RESET exception ]----------------------------------------- */
.org 0x100
l.movhi r0, 0
/* Clear status register */
l.ori r1, r0, SPR_SR_SM
l.mtspr r0, r1, SPR_SR
/* Clear timer */
l.mtspr r0, r0, SPR_TTMR
 
/* Jump to program initialisation code */
.global _start
l.movhi r4, hi(_start)
l.ori r4, r4, lo(_start)
l.jr r4
l.nop
 
 
/* =================================================== [ text ] === */
.section .text
 
/* =================================================== [ start ] === */
 
.global _start
_start:
 
/* Instruction cache enable */
/* Check if IC present and skip enabling otherwise */
l.mfspr r24,r0,SPR_UPR
l.andi r26,r24,SPR_UPR_ICP
l.sfeq r26,r0
l.bf .L8
l.nop
/* Disable IC */
l.mfspr r6,r0,SPR_SR
l.addi r5,r0,-1
l.xori r5,r5,SPR_SR_ICE
l.and r5,r6,r5
l.mtspr r0,r5,SPR_SR
/* Establish cache block size
If BS=0, 16;
If BS=1, 32;
r14 contain block size
*/
l.mfspr r24,r0,SPR_ICCFGR
l.andi r26,r24,SPR_ICCFGR_CBS
l.srli r28,r26,7
l.ori r30,r0,16
l.sll r14,r30,r28
/* Establish number of cache sets
r16 contains number of cache sets
r28 contains log(# of cache sets)
*/
l.andi r26,r24,SPR_ICCFGR_NCS
l.srli r28,r26,3
l.ori r30,r0,1
l.sll r16,r30,r28
/* Invalidate IC */
l.addi r6,r0,0
l.sll r5,r14,r28
.L7:
l.mtspr r0,r6,SPR_ICBIR
l.sfne r6,r5
l.bf .L7
l.add r6,r6,r14
/* Enable IC */
l.mfspr r6,r0,SPR_SR
l.ori r6,r6,SPR_SR_ICE
l.mtspr r0,r6,SPR_SR
l.nop
l.nop
l.nop
l.nop
l.nop
l.nop
l.nop
l.nop
 
.L8:
/* Data cache enable */
/* Check if DC present and skip enabling otherwise */
l.mfspr r24,r0,SPR_UPR
l.andi r26,r24,SPR_UPR_DCP
l.sfeq r26,r0
l.bf .L10
l.nop
/* Disable DC */
l.mfspr r6,r0,SPR_SR
l.addi r5,r0,-1
l.xori r5,r5,SPR_SR_DCE
l.and r5,r6,r5
l.mtspr r0,r5,SPR_SR
/* Establish cache block size
If BS=0, 16;
If BS=1, 32;
r14 contain block size
*/
l.mfspr r24,r0,SPR_DCCFGR
l.andi r26,r24,SPR_DCCFGR_CBS
l.srli r28,r26,7
l.ori r30,r0,16
l.sll r14,r30,r28
/* Establish number of cache sets
r16 contains number of cache sets
r28 contains log(# of cache sets)
*/
l.andi r26,r24,SPR_DCCFGR_NCS
l.srli r28,r26,3
l.ori r30,r0,1
l.sll r16,r30,r28
/* Invalidate DC */
l.addi r6,r0,0
l.sll r5,r14,r28
.L9:
l.mtspr r0,r6,SPR_DCBIR
l.sfne r6,r5
l.bf .L9
l.add r6,r6,r14
/* Enable DC */
l.mfspr r6,r0,SPR_SR
l.ori r6,r6,SPR_SR_DCE
l.mtspr r0,r6,SPR_SR
.L10:
// Kick off test
l.jal _main
l.nop
 
 
/* =================================================== [ main ] === */
.global _main
_main:
l.movhi r3, 0
l.movhi r4, 0 // Bit we're checking works
l.movhi r5, 0
l.ori r6, r0, 32
l.movhi r7, 0 // Register we'll put a value in to check with l.ff1
 
#define REPORT(reg) l.or r3, reg, r0 ; \
l.nop 0x2
ff1_loop:
// Set a loop going, creating a register with a '1' in a known position
// and checking the output of the l.ff1
l.ori r7, r0, 1 // Put 1 in bit 0
l.sll r7, r7, r4 // Shift '1' by r4
REPORT(r7) // Report value
l.ff1 r5, r7 // Do Find First '1' op
l.fl1 r8, r7 // Do Find Last '1' op
REPORT(r5) // Report value
REPORT(r8) // Report value
l.addi r4, r4, 1 // Increment bit we're checking (will also be
// result from l.ff1)
REPORT(r4) // Report value
l.sfne r5, r4 // r5 should = r4
l.bf ff1_error
l.sfne r8, r4 // r8 should = r4
l.bf fl1_error
l.sfne r6, r4 // Check if loop is finished
l.bf ff1_loop // Keep checking
l.nop
l.j ffl1_test2 // All OK, next test
l.nop
 
ffl1_test2:
// Try 3 values - all '0', all '1' and a block of values in between
l.movhi r4, 0
l.movhi r5, 0xffff
l.ori r5, r5, 0xffff
l.movhi r6, 0x00ff
l.ori r6, r6, 0xff00
// Test '0'
REPORT(r4)
l.ff1 r7, r4
l.fl1 r8, r4
REPORT(r7)
REPORT(r8)
l.sfnei r7, 0
l.bf ff1_error
l.sfnei r8, 0
l.bf fl1_error
 
// Test '0xffffffff'
REPORT(r5)
l.ff1 r7, r5
l.fl1 r8, r5
REPORT(r7)
REPORT(r8)
l.sfnei r7, 1
l.bf ff1_error
l.sfnei r8, 32
l.bf fl1_error
 
// Test '0x00ffff00'
REPORT(r6)
l.ff1 r7, r6
l.fl1 r8, r6
REPORT(r7)
REPORT(r8)
l.sfnei r7, 9
l.bf ff1_error
l.sfnei r8, 24
l.bf fl1_error
l.nop
l.j ffl1_ok // Tests OK
 
ff1_error:
l.movhi r3, hi(0xbaaadff1)
l.ori r3, r3, lo(0xbaaadff1)
l.nop 0x1
 
 
fl1_error:
l.movhi r3, hi(0xbaaadf11)
l.ori r3, r3, lo(0xbaaadf11)
l.nop 0x1
ffl1_ok:
l.movhi r3, hi(0x8000000d)
l.ori r3, r3, lo(0x8000000d)
l.nop 0x1
/tests/sdram/sim/sdram-rows.c
5,7 → 5,7
*
*/
 
#include "or32-utils.h"
#include "cpu-utils.h"
#include "board.h"
#include "sdram.h"
 
/tests/spi/sim/spi-simple.c
6,15 → 6,15
 
Nothing much actually gets tested here.
 
Ensure the slave selects for the spi are enabled in design-defines.v
Ensure the slave selects for the spi are enabled in orpsoc-defines.v
 
*/
 
 
#include "or32-utils.h"
#include "cpu-utils.h"
#include "simple-spi.h"
 
#include "design-defines.h"
#include "orpsoc-defines.h"
 
// Detect which of the SPI cores are enabled, tailor the test for that
#ifndef SPI1
/tests/spi/sim/spi-interrupt.c
1,6 → 1,6
#include "board.h"
#include "spr-defs.h"
#include "or32-utils.h"
#include "cpu-utils.h"
#include "simple-spi.h"
#include "int.h"
 
7,7 → 7,7
#include "simple-spi.h"
 
 
#include "design-defines.h"
#include "orpsoc-defines.h"
 
// Detect which of the SPI cores are enabled, tailor the test for that
#ifndef SPI1
/tests/spi/sim/Makefile
1,5 → 1,7
include ../Makefile.inc
SW_ROOT=../../..
 
include $(SW_ROOT)/Makefile.inc
 
%.dis: %.elf
$(Q)$(OR32_OBJDUMP) -d $< > $@
 
/Makefile.inc
46,29 → 46,47
# Special case for CPU drivers
CPU_DRIVER ?=$(SW_ROOT)/drivers/or1200
 
# Rest of drivers, check if we have any that we should use board-specific
# versions of.
# Expecting BOARD_SPECIFIC_DRIVERS and BOARD_PATH to be set
# If BOARD_PATH is set, we'll first scan that path for which drivers they have
# and will override any locally named driver directories here.
ifdef BOARD_PATH
#$(info BOARD_PATH is being used: $(BOARD_PATH))
BOARD_SPECIFIC_DRIVERS=$(shell if [ -e $(BOARD_PATH)/sw/drivers ]; then ls $(BOARD_PATH)/sw/drivers; fi)
endif
 
COMMON_SW_DRIVERS=$(shell ls $(SW_ROOT)/drivers )
COMMON_SW_DRIVERS_EXCLUDE_BOARD_DRIVERS_CMD=$(shell for driver in $(BOARD_SPECIFIC_DRIVERS); do echo -n "grep -v $$driver"; done)
COMMON_SW_DRIVERS_WITHOUT_BOARD_DRIVERS=$(shell echo $(COMMON_SW_DRIVERS) $(COMMON_SW_DRIVERS_EXCLUDE_BOARD_DRIVERS_CMD))
COMMON_SW_DRIVERS_WITHOUT_BOARD_DRIVERS=$(filter-out $(BOARD_SPECIFIC_DRIVERS),$(COMMON_SW_DRIVERS))
 
# Add paths to the common drivers
SW_DRIVER_PATHS=$(shell for driver in $(COMMON_SW_DRIVERS_WITHOUT_BOARD_DRIVERS); do echo $(SW_ROOT)/drivers/$$driver; done)
# If anything in BOARD_SPECIFIC_DRIVERS, add it to SW_DRIVER_PATHS
# It's expected BOARD_PATH points to the board's path and the heirarchy of
# sw/drivers exists
SW_DRIVER_PATHS += $(shell for driver in $(BOARD_SPECIFIC_DRIVERS); do echo $(BOARD_PATH)/sw/drivers/$$driver; done)
#
# Create paths pointing to each driver directory
#
SW_DRIVER_PATHS=$(addprefix $(SW_ROOT)/drivers/,$(COMMON_SW_DRIVERS_WITHOUT_BOARD_DRIVERS))
# If any board paths add them here
SW_DRIVER_PATHS += $(addprefix $(BOARD_PATH)/sw/drivers/,$(BOARD_SPECIFIC_DRIVERS))
 
# Now assemble all of the include paths for the drivers, prefix with -I for GCC
DRIVER_INCLUDE_PATHS=$(shell for driverpath in $(SW_DRIVER_PATHS); do echo "-I$$driverpath/include"; done)
 
# Add /include to each path - the expected include directories
SW_DRIVER_INCLUDE_PATHS=$(addsuffix /include,$(SW_DRIVER_PATHS))
# Now add the -I to the front of each so we can pass this to GCC
INCLUDE_FLAGS=$(addprefix -I,$(SW_DRIVER_INCLUDE_PATHS))
 
 
print-driver-paths:
$(Q)echo "\tDrivers in use from common sw path"; echo;
@echo $(COMMON_SW_DRIVERS); echo; echo
$(Q)echo "\tDrivers in use from board sw path"; echo;
@echo $(BOARD_SPECIFIC_DRIVERS); echo; echo;
$(Q)echo "\tCommon sw drivers without board drivers"; echo;
@echo $(COMMON_SW_DRIVERS_WITHOUT_BOARD_DRIVERS); echo; echo;
$(Q)echo "\tAll drivers and their paths"; echo;
@echo $(SW_DRIVER_PATHS); echo; echo
 
 
# If BOARD_PATH isn't set, then we're not compiling for a board, so use the
# generic board.h include path, otherwise, use that board's
ifeq ($(BOARD_PATH),)
DRIVER_INCLUDE_PATHS +=-I$(SW_ROOT)/board/include
ifdef BOARD_PATH
INCLUDE_FLAGS +=-I$(BOARD_PATH)/sw/board/include
else
DRIVER_INCLUDE_PATHS +=-I$(BOARD_PATH)/sw/board/include
INCLUDE_FLAGS +=-I$(SW_ROOT)/board/include
endif
 
# For now, only apps path is in root sw directory
93,7 → 111,7
MARCH_FLAGS ?=-mhard-mul -mhard-div -msoft-float
 
OR32_CFLAGS ?=-g -nostdlib -O2 $(MARCH_FLAGS) \
$(DRIVER_INCLUDE_PATHS) \
$(INCLUDE_FLAGS) \
-I$(SW_ROOT)/lib/include
 
OR32_LDFLAGS ?=-lgcc -T$(CPU_DRIVER)/link.ld -e 256
187,17 → 205,25
$(VECTORS_OBJ):
$(Q)$(MAKE) -C $(CPU_DRIVER) crt0.o
 
# This relies on the local clean rule of each makefile
clean-all: distclean
 
clean-support:
$(Q)$(MAKE) -C ../support clean
# Get a list of the tests
SW_TESTS=$(shell ls $(SW_ROOT)/tests)
# A list of the directories in each test directory (not always the same) and
# get a list of what's in them.
SW_TESTS_SUBDIRS=$(shell for test in $(SW_TESTS); do ls -d $(SW_ROOT)/tests/$$test/*; done)
 
# List of software directories, exclude include/
SWDIRS=$(shell ls ../ | grep -v include)
print-sw-tests:
$(Q)echo; echo "\tSoftware tests"; echo;
$(Q)echo $(SW_TESTS); echo
 
distclean:
$(Q)for dir in $(SWDIRS); do if [ -d ../$$dir ]; then $(MAKE) -C ../$$dir clean; fi; done
print-sw-tests-subdirs:
$(Q)echo; echo "\tSoftware tests subdirs"; echo;
$(Q)echo $(SW_TESTS_SUBDIRS); echo
 
# This relies on the local clean rule of each makefile
clean-all: clean
$(Q)for testssubdir in $(SW_TESTS_SUBDIRS); do $(MAKE) -C $$testssubdir clean; done
$(Q)for dir in $(SW_DRIVER_PATHS); do $(MAKE) -C $$dir clean; done
$(Q)for dir in `ls $(SW_APPS_PATH)`; do $(MAKE) -C $(SW_ROOT)/apps/$$dir clean; done
$(Q)for dir in `ls $(SW_APPS_PATH)`; do $(MAKE) -C $(SW_ROOT)/apps/$$dir clean; done
$(Q)rm -f $(PROCESSED_DEFINES)
/board/include/board.h
3,6 → 3,7
 
#define IN_CLK 50000000 // Hz
 
 
//
// Defines for each core (memory map base, OR1200 interrupt line number, etc.)
//
/drivers/i2c_host_slave/Makefile File deleted
/drivers/i2c_host_slave/include/i2c_master_slave.h File deleted
/drivers/i2c_host_slave/i2c_master_slave.c File deleted
/drivers/i2c_master_slave/i2c_master_slave.c
0,0 → 1,256
/*************************************************************
* I2C functions for the Herveille i2c controller *
* *
* Provides functions to read from and write to the I2C bus. *
* Master and slave mode are both supported *
* *
* Julius Baxter, julius@opencores.org *
* *
************************************************************/
 
#include "board.h"
#include "cpu-utils.h"
#include "i2c_master_slave.h"
 
inline unsigned char i2c_master_slave_read_reg(int core, unsigned char addr)
{
return REG8((i2c_base_adr[core] + addr));
}
 
inline void i2c_master_slave_write_reg(int core, unsigned char addr,
unsigned char data)
{
REG8((i2c_base_adr[core] + addr)) = data;
}
 
int i2c_master_slave_wait_for_busy(int core)
{
while (1) {
// Check for busy flag in i2c status reg
if (!
(i2c_master_slave_read_reg(core, I2C_MASTER_SLAVE_SR) &
I2C_MASTER_SLAVE_SR_BUSY))
return 0;
}
}
 
int i2c_master_slave_wait_for_transfer(int core)
{
volatile unsigned char status;
// Wait for ongoing transmission to finish
while (1) {
status = i2c_master_slave_read_reg(core, I2C_MASTER_SLAVE_SR);
// If arbitration lost
if ((status & I2C_MASTER_SLAVE_SR_ARB_LOST) ==
I2C_MASTER_SLAVE_SR_ARB_LOST)
return 2;
// If TIP bit = o , stop waiting
else if (!(status & I2C_MASTER_SLAVE_SR_TRANSFER_IN_PRG))
return 0;
}
}
 
/***********************************************************
* i2c_master_slave_init_core *
* *
* Setup i2c core: *
* Write prescaler register with parmeter passed, enable *
* core in control register, optionally enable interrupts *
************************************************************/
int i2c_master_slave_init_core(int core, unsigned short prescaler,
int interrupt_enable)
{
 
// Setup I2C prescaler,
i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_PRERlo,
prescaler & 0xff);
i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_PRERhi,
(prescaler >> 8) & 0xff);
 
// Enable I2C controller and optionally interrupts
if (interrupt_enable)
i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CTR,
I2C_MASTER_SLAVE_CTR_CORE_ENABLE |
I2C_MASTER_SLAVE_CTR_INTR_ENABLE);
else
i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CTR,
I2C_MASTER_SLAVE_CTR_CORE_ENABLE);
 
return 0;
 
}
 
/***********************************************************
* i2c_master_slave_deact_core *
* *
* Deactivate i2c core: *
* Clear core enable and interrupt enable bits *
************************************************************/
int i2c_master_slave_deact_core(int core)
{
 
i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CTR,
i2c_master_slave_read_reg(core,
I2C_MASTER_SLAVE_CTR) &
~(I2C_MASTER_SLAVE_CTR_CORE_ENABLE |
I2C_MASTER_SLAVE_CTR_INTR_ENABLE));
 
 
return 0;
 
}
 
/***********************************************************
* i2c_master_slave_init_as_slave *
* *
* Setup i2c core to service slave accesses *
* OR in slave enable bit to control register *
* Set slave address *
************************************************************/
int i2c_master_slave_init_as_slave(int core, char addr)
{
 
// Set slave enable bit
i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CTR,
i2c_master_slave_read_reg(core,
I2C_MASTER_SLAVE_CTR)
| I2C_MASTER_SLAVE_CTR_SLAVE_ENABLE);
// Set slave address
i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_SLADR, addr);
 
return 0;
 
}
 
/***********************************************************
* i2c_master_slave_deact_as_slave *
* *
* Disable slave mode for this I2C core *
* Deassert slave eanble bit in control register *
************************************************************/
int i2c_master_slave_deact_as_slave(int core)
{
// Clear slave enable bit
i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CTR,
i2c_master_slave_read_reg(core,
I2C_MASTER_SLAVE_CTR)
& ~I2C_MASTER_SLAVE_CTR_SLAVE_ENABLE);
 
return 0;
}
 
/***********************************************************
* i2c_master_slave_master_start *
* *
* Get the i2c bus. *
************************************************************/
int i2c_master_slave_master_start(int core, unsigned char addr, int read)
{
 
i2c_master_slave_wait_for_busy(core);
 
// Set address in transfer register
i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_TXR,
(addr << 1) | read);
 
// Start and write the address
i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CR,
I2C_MASTER_SLAVE_CR_START |
I2C_MASTER_SLAVE_CR_WRITE);
 
i2c_master_slave_wait_for_transfer(core);
 
return 0;
}
 
/***********************************************************
* i2c_master_slave_master_write *
* *
* Send 1 byte of data *
************************************************************/
int i2c_master_slave_master_write(int core, unsigned char data,
int check_prev_ack, int stop)
{
if (i2c_master_slave_wait_for_transfer(core))
return 1;
// present data
i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_TXR, data);
 
if (!stop)
// set command (write)
i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CR,
I2C_MASTER_SLAVE_CR_WRITE);
else
// set command (write) and stop
i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CR,
I2C_MASTER_SLAVE_CR_WRITE |
I2C_MASTER_SLAVE_CR_STOP);
 
return 0;
}
 
/***********************************************************
* i2c_master_slave_master_stop *
* *
* Send stop condition *
************************************************************/
int i2c_master_slave_master_stop(int core)
{
unsigned char status;
unsigned char ready = 0;
 
// Make I2C controller wait at end of finished byte
if (i2c_master_slave_wait_for_transfer(core))
return 1;
 
// Send stop condition
i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CR,
I2C_MASTER_SLAVE_CR_STOP);
 
return 0;
}
 
/***********************************************************
* i2c_master_slave_master_read *
* *
* Read 1 byte of data *
************************************************************/
int i2c_master_slave_master_read(int core, int check_prev_ack,
int stop, char *data)
{
 
// Make I2C controller wait at end of finished byte
if (i2c_master_slave_wait_for_transfer(core))
return 1;
 
if (stop)
i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CR,
I2C_MASTER_SLAVE_CR_READ |
I2C_MASTER_SLAVE_CR_STOP);
else
i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CR,
I2C_MASTER_SLAVE_CR_READ);
 
if (i2c_master_slave_wait_for_transfer(core))
return 1;
 
*data = i2c_master_slave_read_reg(core, I2C_MASTER_SLAVE_RXR);
 
return 0;
}
 
/***********************************************************
* i2c_master_slave_ack_interrupt *
* *
* Acknowledge interrupt has been serviced *
************************************************************/
int i2c_master_slave_ack_interrupt(int core)
{
 
i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CR,
I2C_MASTER_SLAVE_CR_IACK);
 
return 0;
}
/drivers/i2c_master_slave/include/i2c_master_slave.h
0,0 → 1,58
/*************************************************************
* I2C functions for Herveille i2c master_slave core *
* *
* Provides functions to read from and write to the I2C bus. *
* Master and slave mode are both supported *
* *
* *
************************************************************/
 
#ifndef _I2C_MASTER_SLAVE_H_
#define _I2C_MASTER_SLAVE_H_
 
extern const int i2c_base_adr[4];
//Memory mapping adresses
 
#define I2C_MASTER_SLAVE_PRERlo 0x0 // Clock prescaler register
#define I2C_MASTER_SLAVE_PRERhi 0x1 // Clock prescaler register
#define I2C_MASTER_SLAVE_CTR 0x2 // Control register
#define I2C_MASTER_SLAVE_TXR 0x3 // Transmit register
#define I2C_MASTER_SLAVE_RXR 0x3 // Recive register
#define I2C_MASTER_SLAVE_CR 0x4 // Control register
#define I2C_MASTER_SLAVE_SR 0x4 // Status register
#define I2C_MASTER_SLAVE_SLADR 0x7 // Slave address register
 
#define I2C_MASTER_SLAVE_CTR_CORE_ENABLE 0x80
#define I2C_MASTER_SLAVE_CTR_INTR_ENABLE 0x40
#define I2C_MASTER_SLAVE_CTR_SLAVE_ENABLE 0x20
 
#define I2C_MASTER_SLAVE_CR_START 0x80
#define I2C_MASTER_SLAVE_CR_STOP 0x40
#define I2C_MASTER_SLAVE_CR_READ 0x20
#define I2C_MASTER_SLAVE_CR_WRITE 0x10
#define I2C_MASTER_SLAVE_CR_ACK 0x08
#define I2C_MASTER_SLAVE_CR_SL_CONT 0x02
#define I2C_MASTER_SLAVE_CR_IACK 0x01
 
#define I2C_MASTER_SLAVE_SR_RXACK 0x80
#define I2C_MASTER_SLAVE_SR_BUSY 0x40
#define I2C_MASTER_SLAVE_SR_ARB_LOST 0x20
#define I2C_MASTER_SLAVE_SR_SLAVE_MODE 0x10
#define I2C_MASTER_SLAVE_SR_SLAVE_DATA_AVAIL 0x08
#define I2C_MASTER_SLAVE_SR_SLAVE_DATA_REQ 0x04
#define I2C_MASTER_SLAVE_SR_TRANSFER_IN_PRG 0x02
#define I2C_MASTER_SLAVE_SR_IRQ_FLAG 0x01
 
int i2c_master_slave_init_core(int core, unsigned short prescaler,
int interrupt_enable);
int i2c_master_slave_deact_core(int core);
int i2c_master_slave_init_as_slave(int core, char addr);
int i2c_master_slave_deact_as_slave(int core);
int i2c_master_slave_master_start(int core, unsigned char addr, int read);
int i2c_master_slave_master_write(int core, unsigned char data,
int check_prev_ack, int stop);
int i2c_master_slave_master_stop(int core);
int i2c_master_slave_master_read(int core, int check_prev_ack, int stop,
char *data);
int i2c_master_slave_ack_interrupt(int core);
#endif
/drivers/i2c_master_slave/Makefile
0,0 → 1,8
SW_ROOT=../..
 
COMPILE_SRCS=i2c_master_slave.c
 
include $(SW_ROOT)/Makefile.inc
 
clean:
$(Q)rm -f *.a *.o

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