URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2/sw
- from Rev 485 to Rev 486
- ↔ Reverse comparison
Rev 485 → Rev 486
/Makefile.inc
250,3 → 250,4
$(Q)$(MAKE) -C $(SW_ROOT)/lib clean |
$(Q)$(MAKE) -C $(SW_ROOT)/bootrom clean |
$(Q)rm -f $(PROCESSED_DEFINES) |
$(Q)$(MAKE) -C $(SW_ROOT)/utils clean |
/drivers/i2c_master_slave/i2c_master_slave.c
12,15 → 12,29
#include "cpu-utils.h" |
#include "i2c_master_slave.h" |
|
|
// Ensure board.h defines I2C_MASTER_SLAVE_NUM_CORES and |
// I2C_MASTER_SLAVE_BASE_ADDRESSES_CSV which should be the base address values |
// separated with commas |
#ifdef I2C_MASTER_SLAVE_NUM_CORES |
|
const int I2C_MASTER_SLAVE_BASE_ADR[I2C_MASTER_SLAVE_NUM_CORES] = { |
I2C_MASTER_SLAVE_BASE_ADDRESSES_CSV }; |
#else |
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const int I2C_MASTER_SLAVE_BASE_ADR[1] = {-1}; |
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#endif |
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inline unsigned char i2c_master_slave_read_reg(int core, unsigned char addr) |
{ |
return REG8((i2c_base_adr[core] + addr)); |
return REG8((I2C_MASTER_SLAVE_BASE_ADR[core] + addr)); |
} |
|
inline void i2c_master_slave_write_reg(int core, unsigned char addr, |
unsigned char data) |
{ |
REG8((i2c_base_adr[core] + addr)) = data; |
REG8((I2C_MASTER_SLAVE_BASE_ADR[core] + addr)) = data; |
} |
|
int i2c_master_slave_wait_for_busy(int core) |
171,10 → 185,10
************************************************************/ |
int i2c_master_slave_master_write(int core, unsigned char data, |
int check_prev_ack, int stop) |
{ |
{ |
if (i2c_master_slave_wait_for_transfer(core)) |
return 1; |
|
|
// present data |
i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_TXR, data); |
|
188,7 → 202,8
I2C_MASTER_SLAVE_CR_WRITE | |
I2C_MASTER_SLAVE_CR_STOP); |
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return 0; |
return i2c_master_slave_wait_for_transfer(core); |
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} |
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/*********************************************************** |
238,7 → 253,7
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*data = i2c_master_slave_read_reg(core, I2C_MASTER_SLAVE_RXR); |
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return 0; |
return i2c_master_slave_wait_for_transfer(core); |
} |
|
/*********************************************************** |
/drivers/i2c_master_slave/include/i2c_master_slave.h
10,7 → 10,6
#ifndef _I2C_MASTER_SLAVE_H_ |
#define _I2C_MASTER_SLAVE_H_ |
|
extern const int i2c_base_adr[4]; |
//Memory mapping adresses |
|
#define I2C_MASTER_SLAVE_PRERlo 0x0 // Clock prescaler register |
/drivers/or1200/int.c
1,5 → 1,8
/* This file is part of test microkernel for OpenRISC 1000. */ |
/* (C) 2001 Simon Srot, srot@opencores.org */ |
/* |
* |
* User interrupt handler software for OR1200 |
* |
*/ |
|
#include "or1200-utils.h" |
#include "spr-defs.h" |