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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/orpsocv2
    from Rev 363 to Rev 364
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Rev 363 → Rev 364

/rtl/verilog/or1200/or1200_fpu.v
143,7 → 143,7
fpu_comp_done;
wire [width-1:0] result_arith, result_conv;
reg [`OR1200_FPUOP_WIDTH:0] fpu_op_r;
reg [`OR1200_FPUOP_WIDTH-1:0] fpu_op_r;
reg [`OR1200_FPCSR_WIDTH-1:0] fpcsr_r;
wire fpu_op_valid;
reg fpu_op_valid_re;
/rtl/verilog/or1200/or1200_fpu_pre_norm_div.v
109,62 → 109,62
// count leading zeros
//s_dvd_zeros <= count_l_zeros( s_fracta_24 );
always @(s_fracta_24)
casex(s_fracta_24) // synopsys full_case parallel_case
24'b1???????????????????????: s_dvd_zeros <= 0;
24'b01??????????????????????: s_dvd_zeros <= 1;
24'b001?????????????????????: s_dvd_zeros <= 2;
24'b0001????????????????????: s_dvd_zeros <= 3;
24'b00001???????????????????: s_dvd_zeros <= 4;
24'b000001??????????????????: s_dvd_zeros <= 5;
24'b0000001?????????????????: s_dvd_zeros <= 6;
24'b00000001????????????????: s_dvd_zeros <= 7;
24'b000000001???????????????: s_dvd_zeros <= 8;
24'b0000000001??????????????: s_dvd_zeros <= 9;
24'b00000000001?????????????: s_dvd_zeros <= 10;
24'b000000000001????????????: s_dvd_zeros <= 11;
24'b0000000000001???????????: s_dvd_zeros <= 12;
24'b00000000000001??????????: s_dvd_zeros <= 13;
24'b000000000000001?????????: s_dvd_zeros <= 14;
24'b0000000000000001????????: s_dvd_zeros <= 15;
24'b00000000000000001???????: s_dvd_zeros <= 16;
24'b000000000000000001??????: s_dvd_zeros <= 17;
24'b0000000000000000001?????: s_dvd_zeros <= 18;
24'b00000000000000000001????: s_dvd_zeros <= 19;
24'b000000000000000000001???: s_dvd_zeros <= 20;
24'b0000000000000000000001??: s_dvd_zeros <= 21;
24'b00000000000000000000001?: s_dvd_zeros <= 22;
24'b000000000000000000000001: s_dvd_zeros <= 23;
24'b000000000000000000000000: s_dvd_zeros <= 24;
casez(s_fracta_24) // synopsys full_case parallel_case
24'b1???????????????????????: s_dvd_zeros = 0;
24'b01??????????????????????: s_dvd_zeros = 1;
24'b001?????????????????????: s_dvd_zeros = 2;
24'b0001????????????????????: s_dvd_zeros = 3;
24'b00001???????????????????: s_dvd_zeros = 4;
24'b000001??????????????????: s_dvd_zeros = 5;
24'b0000001?????????????????: s_dvd_zeros = 6;
24'b00000001????????????????: s_dvd_zeros = 7;
24'b000000001???????????????: s_dvd_zeros = 8;
24'b0000000001??????????????: s_dvd_zeros = 9;
24'b00000000001?????????????: s_dvd_zeros = 10;
24'b000000000001????????????: s_dvd_zeros = 11;
24'b0000000000001???????????: s_dvd_zeros = 12;
24'b00000000000001??????????: s_dvd_zeros = 13;
24'b000000000000001?????????: s_dvd_zeros = 14;
24'b0000000000000001????????: s_dvd_zeros = 15;
24'b00000000000000001???????: s_dvd_zeros = 16;
24'b000000000000000001??????: s_dvd_zeros = 17;
24'b0000000000000000001?????: s_dvd_zeros = 18;
24'b00000000000000000001????: s_dvd_zeros = 19;
24'b000000000000000000001???: s_dvd_zeros = 20;
24'b0000000000000000000001??: s_dvd_zeros = 21;
24'b00000000000000000000001?: s_dvd_zeros = 22;
24'b000000000000000000000001: s_dvd_zeros = 23;
24'b000000000000000000000000: s_dvd_zeros = 24;
endcase
 
//s_div_zeros <= count_l_zeros( s_fractb_24 );
always @(s_fractb_24)
casex(s_fractb_24) // synopsys full_case parallel_case
24'b1???????????????????????: s_div_zeros <= 0;
24'b01??????????????????????: s_div_zeros <= 1;
24'b001?????????????????????: s_div_zeros <= 2;
24'b0001????????????????????: s_div_zeros <= 3;
24'b00001???????????????????: s_div_zeros <= 4;
24'b000001??????????????????: s_div_zeros <= 5;
24'b0000001?????????????????: s_div_zeros <= 6;
24'b00000001????????????????: s_div_zeros <= 7;
24'b000000001???????????????: s_div_zeros <= 8;
24'b0000000001??????????????: s_div_zeros <= 9;
24'b00000000001?????????????: s_div_zeros <= 10;
24'b000000000001????????????: s_div_zeros <= 11;
24'b0000000000001???????????: s_div_zeros <= 12;
24'b00000000000001??????????: s_div_zeros <= 13;
24'b000000000000001?????????: s_div_zeros <= 14;
24'b0000000000000001????????: s_div_zeros <= 15;
24'b00000000000000001???????: s_div_zeros <= 16;
24'b000000000000000001??????: s_div_zeros <= 17;
24'b0000000000000000001?????: s_div_zeros <= 18;
24'b00000000000000000001????: s_div_zeros <= 19;
24'b000000000000000000001???: s_div_zeros <= 20;
24'b0000000000000000000001??: s_div_zeros <= 21;
24'b00000000000000000000001?: s_div_zeros <= 22;
24'b000000000000000000000001: s_div_zeros <= 23;
24'b000000000000000000000000: s_div_zeros <= 24;
casez(s_fractb_24) // synopsys full_case parallel_case
24'b1???????????????????????: s_div_zeros = 0;
24'b01??????????????????????: s_div_zeros = 1;
24'b001?????????????????????: s_div_zeros = 2;
24'b0001????????????????????: s_div_zeros = 3;
24'b00001???????????????????: s_div_zeros = 4;
24'b000001??????????????????: s_div_zeros = 5;
24'b0000001?????????????????: s_div_zeros = 6;
24'b00000001????????????????: s_div_zeros = 7;
24'b000000001???????????????: s_div_zeros = 8;
24'b0000000001??????????????: s_div_zeros = 9;
24'b00000000001?????????????: s_div_zeros = 10;
24'b000000000001????????????: s_div_zeros = 11;
24'b0000000000001???????????: s_div_zeros = 12;
24'b00000000000001??????????: s_div_zeros = 13;
24'b000000000000001?????????: s_div_zeros = 14;
24'b0000000000000001????????: s_div_zeros = 15;
24'b00000000000000001???????: s_div_zeros = 16;
24'b000000000000000001??????: s_div_zeros = 17;
24'b0000000000000000001?????: s_div_zeros = 18;
24'b00000000000000000001????: s_div_zeros = 19;
24'b000000000000000000001???: s_div_zeros = 20;
24'b0000000000000000000001??: s_div_zeros = 21;
24'b00000000000000000000001?: s_div_zeros = 22;
24'b000000000000000000000001: s_div_zeros = 23;
24'b000000000000000000000000: s_div_zeros = 24;
endcase
 
// left-shift the dividend and divisor
/rtl/verilog/or1200/or1200_fpu_post_norm_addsub.v
132,35 → 132,35
reg [5:0] lzeroes;
always @(s_fract_28_i)
casex(s_fract_28_i[26:0]) // synopsys full_case parallel_case
27'b1??????????????????????????: lzeroes <= 0;
27'b01?????????????????????????: lzeroes <= 1;
27'b001????????????????????????: lzeroes <= 2;
27'b0001???????????????????????: lzeroes <= 3;
27'b00001??????????????????????: lzeroes <= 4;
27'b000001?????????????????????: lzeroes <= 5;
27'b0000001????????????????????: lzeroes <= 6;
27'b00000001???????????????????: lzeroes <= 7;
27'b000000001??????????????????: lzeroes <= 8;
27'b0000000001?????????????????: lzeroes <= 9;
27'b00000000001????????????????: lzeroes <= 10;
27'b000000000001???????????????: lzeroes <= 11;
27'b0000000000001??????????????: lzeroes <= 12;
27'b00000000000001?????????????: lzeroes <= 13;
27'b000000000000001????????????: lzeroes <= 14;
27'b0000000000000001???????????: lzeroes <= 15;
27'b00000000000000001??????????: lzeroes <= 16;
27'b000000000000000001?????????: lzeroes <= 17;
27'b0000000000000000001????????: lzeroes <= 18;
27'b00000000000000000001???????: lzeroes <= 19;
27'b000000000000000000001??????: lzeroes <= 20;
27'b0000000000000000000001?????: lzeroes <= 21;
27'b00000000000000000000001????: lzeroes <= 22;
27'b000000000000000000000001???: lzeroes <= 23;
27'b0000000000000000000000001??: lzeroes <= 24;
27'b00000000000000000000000001?: lzeroes <= 25;
27'b000000000000000000000000001: lzeroes <= 26;
27'b000000000000000000000000000: lzeroes <= 27;
casez(s_fract_28_i[26:0]) // synopsys full_case parallel_case
27'b1??????????????????????????: lzeroes = 0;
27'b01?????????????????????????: lzeroes = 1;
27'b001????????????????????????: lzeroes = 2;
27'b0001???????????????????????: lzeroes = 3;
27'b00001??????????????????????: lzeroes = 4;
27'b000001?????????????????????: lzeroes = 5;
27'b0000001????????????????????: lzeroes = 6;
27'b00000001???????????????????: lzeroes = 7;
27'b000000001??????????????????: lzeroes = 8;
27'b0000000001?????????????????: lzeroes = 9;
27'b00000000001????????????????: lzeroes = 10;
27'b000000000001???????????????: lzeroes = 11;
27'b0000000000001??????????????: lzeroes = 12;
27'b00000000000001?????????????: lzeroes = 13;
27'b000000000000001????????????: lzeroes = 14;
27'b0000000000000001???????????: lzeroes = 15;
27'b00000000000000001??????????: lzeroes = 16;
27'b000000000000000001?????????: lzeroes = 17;
27'b0000000000000000001????????: lzeroes = 18;
27'b00000000000000000001???????: lzeroes = 19;
27'b000000000000000000001??????: lzeroes = 20;
27'b0000000000000000000001?????: lzeroes = 21;
27'b00000000000000000000001????: lzeroes = 22;
27'b000000000000000000000001???: lzeroes = 23;
27'b0000000000000000000000001??: lzeroes = 24;
27'b00000000000000000000000001?: lzeroes = 25;
27'b000000000000000000000000001: lzeroes = 26;
27'b000000000000000000000000000: lzeroes = 27;
endcase
 
assign s_zeros = s_fract_28_i[27] ? 0 : lzeroes;
/rtl/verilog/or1200/or1200_fpu_arith.v
396,27 → 396,27
begin
if (s_rmode_i==2'd0 | s_div_zero_o | s_infa | s_infb | s_qnan_o |
s_qnan_o) // Round to nearest even
s_output_o <= s_output1;
s_output_o = s_output1;
else if (s_rmode_i==2'd1 & (&s_output1[30:23]))
// In round-to-zero: the sum of two non-infinity operands is never
// infinity,even if an overflow occures
s_output_o <= {s_output1[31], 31'b1111111_01111111_11111111_11111111};
s_output_o = {s_output1[31], 31'b1111111_01111111_11111111_11111111};
else if (s_rmode_i==2'd2 & (&s_output1[31:23]))
// In round-up: the sum of two non-infinity operands is never
// negative infinity,even if an overflow occures
s_output_o <= {32'b11111111_01111111_11111111_11111111};
s_output_o = {32'b11111111_01111111_11111111_11111111};
else if (s_rmode_i==2'd3) begin
if (((s_fpu_op_i==3'd0) | (s_fpu_op_i==3'd1)) & s_zero_o &
(s_opa_i[31] | (s_fpu_op_i[0] ^ s_opb_i[31])))
// In round-down: a-a= -0
s_output_o <= {1'b1,s_output1[30:0]};
s_output_o = {1'b1,s_output1[30:0]};
else if (s_output1[31:23]==9'b0_11111111)
s_output_o <= 32'b01111111011111111111111111111111;
s_output_o = 32'b01111111011111111111111111111111;
else
s_output_o <= s_output1;
s_output_o = s_output1;
end
else
s_output_o <= s_output1;
s_output_o = s_output1;
end // always @ *
 
// Exception generation
423,7 → 423,7
assign s_underflow_o = (s_output1[30:23]==8'h00) & s_ine_o;
assign s_overflow_o = (s_output1[30:23]==8'hff) & s_ine_o;
assign s_div_zero_o = serial_div_div_zero & fpu_op_i==3'd3;
assign s_inf_o = s_output1[31:23]==8'hff & !(s_qnan_o | s_snan_o);
assign s_inf_o = s_output1[30:23]==8'hff & !(s_qnan_o | s_snan_o);
assign s_zero_o = !(|s_output1[30:0]);
assign s_qnan_o = s_output1[30:0]==QNAN;
assign s_snan_o = s_output1[30:0]==SNAN;
/rtl/verilog/or1200/or1200_fpu_post_norm_div.v
150,7 → 150,7
wire [9:0] v_shl;
assign v_shr = (s_exp_10b[9] | !(|s_exp_10b)) ?
(10'd1 - s_exp_10b) - s_qutdn : 0;
(10'd1 - s_exp_10b) - {9'd0,s_qutdn} : 0;
assign v_shl = (s_exp_10b[9] | !(|s_exp_10b)) ?
0 :
183,35 → 183,35
//s_r_zeros <= count_r_zeros(s_qutnt_i);
always @(s_qutnt_i)
casex(s_qutnt_i) // synopsys full_case parallel_case
27'b??????????????????????????1: s_r_zeros <= 0;
27'b?????????????????????????10: s_r_zeros <= 1;
27'b????????????????????????100: s_r_zeros <= 2;
27'b???????????????????????1000: s_r_zeros <= 3;
27'b??????????????????????10000: s_r_zeros <= 4;
27'b?????????????????????100000: s_r_zeros <= 5;
27'b????????????????????1000000: s_r_zeros <= 6;
27'b???????????????????10000000: s_r_zeros <= 7;
27'b??????????????????100000000: s_r_zeros <= 8;
27'b?????????????????1000000000: s_r_zeros <= 9;
27'b????????????????10000000000: s_r_zeros <= 10;
27'b???????????????100000000000: s_r_zeros <= 11;
27'b??????????????1000000000000: s_r_zeros <= 12;
27'b?????????????10000000000000: s_r_zeros <= 13;
27'b????????????100000000000000: s_r_zeros <= 14;
27'b???????????1000000000000000: s_r_zeros <= 15;
27'b??????????10000000000000000: s_r_zeros <= 16;
27'b?????????100000000000000000: s_r_zeros <= 17;
27'b????????1000000000000000000: s_r_zeros <= 18;
27'b???????10000000000000000000: s_r_zeros <= 19;
27'b??????100000000000000000000: s_r_zeros <= 20;
27'b?????1000000000000000000000: s_r_zeros <= 21;
27'b????10000000000000000000000: s_r_zeros <= 22;
27'b???100000000000000000000000: s_r_zeros <= 23;
27'b??1000000000000000000000000: s_r_zeros <= 24;
27'b?10000000000000000000000000: s_r_zeros <= 25;
27'b100000000000000000000000000: s_r_zeros <= 26;
27'b000000000000000000000000000: s_r_zeros <= 27;
casez(s_qutnt_i) // synopsys full_case parallel_case
27'b??????????????????????????1: s_r_zeros = 0;
27'b?????????????????????????10: s_r_zeros = 1;
27'b????????????????????????100: s_r_zeros = 2;
27'b???????????????????????1000: s_r_zeros = 3;
27'b??????????????????????10000: s_r_zeros = 4;
27'b?????????????????????100000: s_r_zeros = 5;
27'b????????????????????1000000: s_r_zeros = 6;
27'b???????????????????10000000: s_r_zeros = 7;
27'b??????????????????100000000: s_r_zeros = 8;
27'b?????????????????1000000000: s_r_zeros = 9;
27'b????????????????10000000000: s_r_zeros = 10;
27'b???????????????100000000000: s_r_zeros = 11;
27'b??????????????1000000000000: s_r_zeros = 12;
27'b?????????????10000000000000: s_r_zeros = 13;
27'b????????????100000000000000: s_r_zeros = 14;
27'b???????????1000000000000000: s_r_zeros = 15;
27'b??????????10000000000000000: s_r_zeros = 16;
27'b?????????100000000000000000: s_r_zeros = 17;
27'b????????1000000000000000000: s_r_zeros = 18;
27'b???????10000000000000000000: s_r_zeros = 19;
27'b??????100000000000000000000: s_r_zeros = 20;
27'b?????1000000000000000000000: s_r_zeros = 21;
27'b????10000000000000000000000: s_r_zeros = 22;
27'b???100000000000000000000000: s_r_zeros = 23;
27'b??1000000000000000000000000: s_r_zeros = 24;
27'b?10000000000000000000000000: s_r_zeros = 25;
27'b100000000000000000000000000: s_r_zeros = 26;
27'b000000000000000000000000000: s_r_zeros = 27;
endcase // casex (s_qutnt_i)
assign s_lost = (s_shr1+{5'd0,s_shr2}) > s_r_zeros;
/rtl/verilog/or1200/or1200_fpu_fcmp.v
120,7 → 120,7
always @( qnan or snan or opa_inf or opb_inf or signa or signb or exp_eq or exp_gt or
exp_lt or fract_eq or fract_gt or fract_lt or all_zero)
 
casex( {qnan, snan, opa_inf, opb_inf, signa, signb, exp_eq, exp_gt, exp_lt, fract_eq, fract_gt, fract_lt, all_zero})
casez( {qnan, snan, opa_inf, opb_inf, signa, signb, exp_eq, exp_gt, exp_lt, fract_eq, fract_gt, fract_lt, all_zero})
//13'b??_??_??_???_???_?: {altb, blta, aeqb} = 3'b000;
 
13'b1?_??_??_???_???_?: {altb, blta, aeqb} = 3'b000; // qnan
/rtl/verilog/or1200/or1200_fpu_post_norm_mul.v
139,7 → 139,7
always @(posedge clk_i)
if (!s_fract_48_i[47])
casex(s_fract_48_i[46:1]) // synopsys full_case parallel_case
casez(s_fract_48_i[46:1]) // synopsys full_case parallel_case
46'b1?????????????????????????????????????????????: s_zeros <= 0;
46'b01????????????????????????????????????????????: s_zeros <= 1;
46'b001???????????????????????????????????????????: s_zeros <= 2;
193,7 → 193,7
 
 
always @(posedge clk_i)
casex(s_fract_48_i) // synopsys full_case parallel_case
casez(s_fract_48_i) // synopsys full_case parallel_case
48'b???????????????????????????????????????????????1: s_r_zeros <= 0;
48'b??????????????????????????????????????????????10: s_r_zeros <= 1;
48'b?????????????????????????????????????????????100: s_r_zeros <= 2;
271,7 → 271,7
if ((s_exp_10a[9] | !(|s_exp_10a)))
s_expo1 <= 9'd1;
else if (s_exp_10b[9] | !(|s_exp_10b))
s_expo1 <= 1'd1;
s_expo1 <= 9'd1;
else if (s_exp_10b[8])
s_expo1 <= 9'b011111111;
else
/rtl/verilog/or1200/or1200_fpu_post_norm_intfloat_conv.v
137,7 → 137,7
// Count Leading zeros in fraction
 
always @(/*fract_in*/ posedge clk)
casex(fract_in) // synopsys full_case parallel_case
casez(fract_in) // synopsys full_case parallel_case
48'b1???????????????????????????????????????????????: fi_ldz <= 1;
48'b01??????????????????????????????????????????????: fi_ldz <= 2;
48'b001?????????????????????????????????????????????: fi_ldz <= 3;
294,7 → 294,8
assign exp_in_mi1 = exp_in - 1; // 9 bits - includes carry out
assign exp_out1_mi1 = exp_out1 - 1;
 
assign exp_next_mi = exp_in_pl1 - fi_ldz_mi1; // 9 bits - includes carry out
assign exp_next_mi = exp_in_pl1 -
{3'd0,fi_ldz_mi1}; // 9 bits - includes carry out
 
assign {exp_out1_co, exp_out1} = fract_in[47] ? exp_in_pl1 : exp_next_mi;
309,7 → 310,7
?
0 :opas;
 
assign exp_i2f = fract_in_00 ? (opas ? 8'h9e : 0) : (8'h9e-fi_ldz);
assign exp_i2f = fract_in_00 ? (opas ? 8'h9e : 0) : (8'h9e-{2'd0,fi_ldz});
assign exp_f2i_1 = {{8{fract_in[47]}}, fract_in }<<f2i_shft;
assign exp_f2i = f2i_zero ? 0 : f2i_max ? 8'hff : exp_f2i_1[55:48];
assign conv_exp = op_f2i ? exp_f2i : exp_i2f;
319,7 → 320,7
exp_out <= conv_exp;
 
assign ldz_all = fi_ldz;
assign ldz_all = {1'b0,fi_ldz};
assign fi_ldz_2a = 6'd23 - fi_ldz;
assign fi_ldz_2 = {fi_ldz_2a[6], fi_ldz_2a[6:0]};
 
/rtl/verilog/or1200/or1200_gmultp2_32x32.v
103,16 → 103,15
//
// Conversion unsigned to signed
//
/* verilator lint_off COMBDLY */
always @(X)
xi <= X;
xi = X;
 
//
// Conversion unsigned to signed
//
always @(Y)
yi <= Y;
/* verilator lint_on COMBDLY */
yi = Y;
 
//
// First multiply stage
//
/rtl/verilog/or1200/or1200_fpu_pre_norm_addsub.v
152,39 → 152,39
 
// count the zeros from right to check if result is inexact
always @(s_fract_sm_28)
casex(s_fract_sm_28) // synopsys full_case parallel_case
28'b???????????????????????????1: s_rzeros <= 0;
28'b??????????????????????????10: s_rzeros <= 1;
28'b?????????????????????????100: s_rzeros <= 2;
28'b????????????????????????1000: s_rzeros <= 3;
28'b???????????????????????10000: s_rzeros <= 4;
28'b??????????????????????100000: s_rzeros <= 5;
28'b?????????????????????1000000: s_rzeros <= 6;
28'b????????????????????10000000: s_rzeros <= 7;
28'b???????????????????100000000: s_rzeros <= 8;
28'b??????????????????1000000000: s_rzeros <= 9;
28'b?????????????????10000000000: s_rzeros <= 10;
28'b????????????????100000000000: s_rzeros <= 11;
28'b???????????????1000000000000: s_rzeros <= 12;
28'b??????????????10000000000000: s_rzeros <= 13;
28'b?????????????100000000000000: s_rzeros <= 14;
28'b????????????1000000000000000: s_rzeros <= 15;
28'b???????????10000000000000000: s_rzeros <= 16;
28'b??????????100000000000000000: s_rzeros <= 17;
28'b?????????1000000000000000000: s_rzeros <= 18;
28'b????????10000000000000000000: s_rzeros <= 19;
28'b???????100000000000000000000: s_rzeros <= 20;
28'b??????1000000000000000000000: s_rzeros <= 21;
28'b?????10000000000000000000000: s_rzeros <= 22;
28'b????100000000000000000000000: s_rzeros <= 23;
28'b???1000000000000000000000000: s_rzeros <= 24;
28'b??10000000000000000000000000: s_rzeros <= 25;
28'b?100000000000000000000000000: s_rzeros <= 26;
28'b1000000000000000000000000000: s_rzeros <= 27;
28'b0000000000000000000000000000: s_rzeros <= 28;
casez(s_fract_sm_28) // synopsys full_case parallel_case
28'b???????????????????????????1: s_rzeros = 0;
28'b??????????????????????????10: s_rzeros = 1;
28'b?????????????????????????100: s_rzeros = 2;
28'b????????????????????????1000: s_rzeros = 3;
28'b???????????????????????10000: s_rzeros = 4;
28'b??????????????????????100000: s_rzeros = 5;
28'b?????????????????????1000000: s_rzeros = 6;
28'b????????????????????10000000: s_rzeros = 7;
28'b???????????????????100000000: s_rzeros = 8;
28'b??????????????????1000000000: s_rzeros = 9;
28'b?????????????????10000000000: s_rzeros = 10;
28'b????????????????100000000000: s_rzeros = 11;
28'b???????????????1000000000000: s_rzeros = 12;
28'b??????????????10000000000000: s_rzeros = 13;
28'b?????????????100000000000000: s_rzeros = 14;
28'b????????????1000000000000000: s_rzeros = 15;
28'b???????????10000000000000000: s_rzeros = 16;
28'b??????????100000000000000000: s_rzeros = 17;
28'b?????????1000000000000000000: s_rzeros = 18;
28'b????????10000000000000000000: s_rzeros = 19;
28'b???????100000000000000000000: s_rzeros = 20;
28'b??????1000000000000000000000: s_rzeros = 21;
28'b?????10000000000000000000000: s_rzeros = 22;
28'b????100000000000000000000000: s_rzeros = 23;
28'b???1000000000000000000000000: s_rzeros = 24;
28'b??10000000000000000000000000: s_rzeros = 25;
28'b?100000000000000000000000000: s_rzeros = 26;
28'b1000000000000000000000000000: s_rzeros = 27;
28'b0000000000000000000000000000: s_rzeros = 28;
endcase // casex (s_fract_sm_28)
assign s_sticky = (s_exp_diff > s_rzeros) & (|s_fract_sm_28);
assign s_sticky = (s_exp_diff > {2'b00,s_rzeros}) & (|s_fract_sm_28);
assign s_fracta_28_o = s_expa_gt_expb ?
s_fracta_28 :
/rtl/verilog/uart16550/uart_defines.v File deleted
rtl/verilog/uart16550/uart_defines.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property

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