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/backend/generic_buffers.v File deleted

backend/generic_buffers.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Deleted: svn:mergeinfo ## -0,0 +0,0 ## Index: backend/sim_lib.v =================================================================== --- backend/sim_lib.v (revision 397) +++ backend/sim_lib.v (nonexistent) @@ -1,777 +0,0 @@ -`timescale 1 ns / 100 ps -module GND - ( - output Y - ); - assign Y = 1'b0; -endmodule // GND -`timescale 1 ns / 100 ps -module VCC - ( - output Y - ); - assign Y = 1'b1; -endmodule // VCC -`timescale 1 ns / 100 ps -module CLKDLY - ( - output GL, - input CLK, DLYGL0, DLYGL1, DLYGL2,DLYGL3,DLYGL4 - ); - assign GL = ({DLYGL0,DLYGL1,DLYGL2,DLYGL3,DLYGL4}==5'b00000) ? CLK : 1'b0; -endmodule // CLKDLY - -`timescale 1 ns / 100 ps -module AND2 - ( - input A,B, - output Y - ); - - assign #1 Y = A & B; - -endmodule // AND2 -`timescale 1 ns / 100 ps -module AND2A - ( - input A,B, - output Y - ); - - assign #1 Y = !A & B; - -endmodule // AND2A -`timescale 1 ns / 100 ps -module AND2B - ( - input A,B, - output Y - ); - - assign #1 Y = !A & !B; - -endmodule // AND2B -`timescale 1 ns / 100 ps -module AND3 - ( - input A,B,C, - output Y - ); - - assign #1 Y = A & B & C; - -endmodule // AND3 -`timescale 1 ns / 100 ps -module AND3A - ( - input A,B,C, - output Y - ); - - assign #1 Y = !A & B & C; - -endmodule // AND3A -`timescale 1 ns / 100 ps -`timescale 1 ns / 100 ps -module AND3B - ( - input A,B,C, - output Y - ); - - assign #1 Y = !A & !B & C; - -endmodule // AND3B -`timescale 1 ns / 100 ps -module AND3C - ( - input A,B,C, - output Y - ); - - assign #1 Y = !A & !B & !C; - -endmodule // AND3C -`timescale 1 ns / 100 ps -module NAND2 - ( - input A,B, - output Y - ); - - assign #1 Y = !(A & B); - -endmodule // NAND2 -`timescale 1 ns / 100 ps -module NAND2A - ( - input A,B, - output Y - ); - - assign #1 Y = !(!A & B); - -endmodule // NAND2A -`timescale 1 ns / 100 ps -module NAND2B - ( - input A,B, - output Y - ); - - assign #1 Y = !(!A & !B); - -endmodule // NAND2B -`timescale 1 ns / 100 ps -module NAND3 - ( - input A,B,C, - output Y - ); - - assign #1 Y = !(A & B & C); - -endmodule // NAND3 -`timescale 1 ns / 100 ps -module NAND3A - ( - input A,B,C, - output Y - ); - - assign #1 Y = !(!A & B & C); - -endmodule // NAND3A -`timescale 1 ns / 100 ps -module NAND3B - ( - input A,B,C, - output Y - ); - - assign #1 Y = !(!A & !B & C); - -endmodule // NAND3B -`timescale 1 ns / 100 ps -module NAND3C - ( - input A,B,C, - output Y - ); - - assign #1 Y = !(!A & !B & !C); - -endmodule // NAND3C -`timescale 1 ns / 100 ps -module OR2 - ( - input A,B, - output Y - ); - - assign #1 Y = A | B; - -endmodule // OR2 -`timescale 1 ns / 100 ps -module OR2A - ( - input A,B, - output Y - ); - - assign #1 Y = !A | B; - -endmodule // OR2A -`timescale 1 ns / 100 ps -module OR2B - ( - input A,B, - output Y - ); - - assign #1 Y = !A | !B; - -endmodule // OR2B -`timescale 1 ns / 100 ps -module OR3 - ( - input A,B,C, - output Y - ); - - assign #1 Y = A | B | C; - -endmodule // OR3 -`timescale 1 ns / 100 ps -module OR3A - ( - input A,B,C, - output Y - ); - - assign #1 Y = !A | B | C; - -endmodule // OR3A -`timescale 1 ns / 100 ps -module OR3B - ( - input A,B,C, - output Y - ); - - assign #1 Y = !A | !B | C; - -endmodule // OR3B -`timescale 1 ns / 100 ps -module OR3C - ( - input A,B,C, - output Y - ); - - assign #1 Y = !A | !B | !C; - -endmodule // OR3C -`timescale 1 ns / 100 ps -module NOR2 - ( - input A,B, - output Y - ); - - assign #1 Y = !(A | B); - -endmodule // NOR2 -`timescale 1 ns / 100 ps -module NOR2A - ( - input A,B, - output Y - ); - - assign #1 Y = !(!A | B); - -endmodule // NOR2A -module NOR2B - ( - input A,B, - output Y - ); - - assign #1 Y = !(!A | !B); - -endmodule // NOR2B -`timescale 1 ns / 100 ps -module NOR3 - ( - input A,B,C, - output Y - ); - - assign #1 Y = !(A | B | C); - -endmodule // NOR2 -`timescale 1 ns / 100 ps -module NOR3A - ( - input A,B,C, - output Y - ); - - assign #1 Y = !(!A | B | C); - -endmodule // NOR3A -`timescale 1 ns / 100 ps -module NOR3B - ( - input A,B,C, - output Y - ); - - assign #1 Y = !(!A | !B | C); - -endmodule // NOR3B -`timescale 1 ns / 100 ps -module NOR3C - ( - input A,B,C, - output Y - ); - - assign #1 Y = !(!A | !B | !C); - -endmodule // NOR3C -`timescale 1 ns / 100 ps -module XOR2 - ( - input A,B, - output Y - ); - - assign #1 Y = A ^ B; - -endmodule // XOR2 -`timescale 1 ns / 100 ps -module XOR2A - ( - input A,B, - output Y - ); - - assign #1 Y = !A ^ B; - -endmodule // XOR2A -`timescale 1 ns / 100 ps -module XOR2B - ( - input A,B, - output Y - ); - - assign #1 Y = !A ^ !B; - -endmodule // XOR2B -`timescale 1 ns / 100 ps -module XOR3 - ( - input A,B,C, - output Y - ); - - assign #1 Y = A ^ B ^ C; - -endmodule // XOR3 -`timescale 1 ns / 100 ps -module XOR3A - ( - input A,B,C, - output Y - ); - - assign #1 Y = !A ^ B ^ C; - -endmodule // XOR3A -module XOR3B - ( - input A,B,C, - output Y - ); - - assign #1 Y = !A ^ !B ^ C; - -endmodule // XOR3B -`timescale 1 ns / 100 ps -module XOR3C - ( - input A,B,C, - output Y - ); - - assign #1 Y = !A ^ !B ^ !C; - -endmodule // XOR3C -`timescale 1 ns / 100 ps -module XNOR2 - ( - input A,B, - output Y - ); - - assign #1 Y = !(A ^ B); - -endmodule // XNOR2 -`timescale 1 ns / 100 ps -module XNOR2A - ( - input A,B, - output Y - ); - - assign #1 Y = !(!A ^ B); - -endmodule // XNOR2A -`timescale 1 ns / 100 ps -module XNOR2B - ( - input A,B, - output Y - ); - - assign #1 Y = !(!A ^ !B); - -endmodule // XNOR2B -`timescale 1 ns / 100 ps -module XNOR3 - ( - input A,B,C, - output Y - ); - - assign #1 Y = !(A ^ B ^ C); - -endmodule // XNOR3 -`timescale 1 ns / 100 ps -module XNOR3A - ( - input A,B,C, - output Y - ); - - assign #1 Y = !(!A ^ B ^ C); - -endmodule // XNOR3A -`timescale 1 ns / 100 ps -module XNOR3B - ( - input A,B,C, - output Y - ); - - assign #1 Y = !(!A ^ !B ^ C); - -endmodule // XNOR3B -`timescale 1 ns / 100 ps -module XNOR3C - ( - input A,B,C, - output Y - ); - - assign #1 Y = !(!A ^ !B ^ !C); - -endmodule // XNOR3C -`timescale 1 ns / 100 ps -module MX2 - ( - input A,B,S, - output Y - ); - assign #1 Y = !S ? A : B; -endmodule // MX2 -module MX2A - ( - input A,B,S, - output Y - ); - assign #1 Y = !S ? !A : B; -endmodule // MX2A -`timescale 1 ns / 100 ps -module MX2B - ( - input A,B,S, - output Y - ); - assign #1 Y = !S ? A : !B; -endmodule // MX2B -`timescale 1 ns / 100 ps -module MX2C - ( - input A,B,S, - output Y - ); - assign #1 Y = !S ? !A : !B; -endmodule // MX2C -`timescale 1 ns / 100 ps -module AO1 - ( - input A,B,C, - output Y - ); - assign #1 Y = (A & B) | C; -endmodule // AO1 -`timescale 1 ns / 100 ps -module AO1A - ( - input A,B,C, - output Y - ); - assign #1 Y = (!A & B) | C; -endmodule // AO1A -`timescale 1 ns / 100 ps -module AO1B - ( - input A,B,C, - output Y - ); - assign #1 Y = (A & B) | !C; -endmodule // AO1B -`timescale 1 ns / 100 ps -module AO1C - ( - input A,B,C, - output Y - ); - assign #1 Y = (!A & B) | !C; -endmodule // AO1C -`timescale 1 ns / 100 ps -module AO1D - ( - input A,B,C, - output Y - ); - assign #1 Y = (!A & !B) | C; -endmodule // AO1D -`timescale 1 ns / 100 ps -module AO1E - ( - input A,B,C, - output Y - ); - assign #1 Y = (!A & !B) | !C; -endmodule // AO1E -`timescale 1 ns / 100 ps -module AOI1 - ( - input A,B,C, - output Y - ); - assign #1 Y = !((A & B) | C); -endmodule // AOI1 -`timescale 1 ns / 100 ps -module AOI1A - ( - input A,B,C, - output Y - ); - assign #1 Y = !((!A & B) | C); -endmodule // AOI1A -`timescale 1 ns / 100 ps -module AOI1B - ( - input A,B,C, - output Y - ); - assign #1 Y = !((A & B) | !C); -endmodule // AOI1B -`timescale 1 ns / 100 ps -module AOI1C - ( - input A,B,C, - output Y - ); - assign #1 Y = !((!A & B) | !C); -endmodule // AOI1C -module AOI1D - ( - input A,B,C, - output Y - ); - assign #1 Y = !((!A & !B) | C); -endmodule // AOI1D -`timescale 1 ns / 100 ps -module AOI1E - ( - input A,B,C, - output Y - ); - assign #1 Y = !((!A & !B) | !C); -endmodule // AOI1E -`timescale 1 ns / 100 ps -module AX1 - ( - input A,B,C, - output Y - ); - assign #1 Y = (!A & B) ^ C; -endmodule // AX1 -`timescale 1 ns / 100 ps -module AX1A - ( - input A,B,C, - output Y - ); - assign #1 Y = !((!A & B) ^ C); -endmodule // AX1A -module AX1B - ( - input A,B,C, - output Y - ); - assign #1 Y = (!A & !B) ^ C; -endmodule // AX1B -`timescale 1 ns / 100 ps -module AX1C - ( - input A,B,C, - output Y - ); - assign #1 Y = (A & B) ^ C; -endmodule // AX1C -`timescale 1 ns / 100 ps -module AX1D - ( - input A,B,C, - output Y - ); - assign #1 Y = !((!A & !B) ^ C); -endmodule // AX1D -`timescale 1 ns / 100 ps -module AX1E - ( - input A,B,C, - output Y - ); - assign #1 Y = !((A & B) ^ C); -endmodule // AX1E -`timescale 1 ns / 100 ps -module OA1 - ( - input A,B,C, - output Y - ); - assign #1 Y = (A | B) & C; -endmodule // OA1 -`timescale 1 ns / 100 ps -module OA1A - ( - input A,B,C, - output Y - ); - assign #1 Y = (!A | B) & C; -endmodule // OA1A -`timescale 1 ns / 100 ps -module OA1B - ( - input A,B,C, - output Y - ); - assign #1 Y = (A | B) & !C; -endmodule // OA1B -`timescale 1 ns / 100 ps -module OA1C - ( - input A,B,C, - output Y - ); - assign #1 Y = (!A | B) & !C; -endmodule // OA1C -`timescale 1 ns / 100 ps -module CLKINT - ( - input A, - output Y - ); - assign #1 Y = A; -endmodule // CLKINT -`timescale 1 ns / 100 ps -module OAI1 - ( - input A,B,C, - output Y - ); - assign #1 Y = !((A | B) & C); -endmodule // OAI1 -`timescale 1 ns / 100 ps -module XA1B - ( - input A,B,C, - output Y - ); - assign #1 Y = (A ^ B) & !C; -endmodule // XA1B -`timescale 1 ns / 100 ps -module XAI1 - ( - input A,B,C, - output Y - ); - assign #1 Y = !((A ^ B) & C); -endmodule // XAI1 -///////////////////////////////////////////////////////////////////////////////// -// DFF -`timescale 1 ns / 100 ps -module DFN1C0 - ( - output reg Q, - input D,CLR,CLK - ); - always @ (posedge CLK or negedge CLR) - if (!CLR) - Q <= #1 1'b0; - else - Q <= #1 D; -endmodule // DFN1C0 -`timescale 1 ns / 100 ps -module DFN1C1 - ( - output reg Q, - input D,CLR,CLK - ); - always @ (posedge CLK or posedge CLR) - if (CLR) - Q <= #1 1'b0; - else - Q <= #1 D; -endmodule // DFN1C1 -`timescale 1 ns / 100 ps -module DFN1P0 - ( - output reg Q, - input D,PRE,CLK - ); - always @ (posedge CLK or negedge PRE) - if (!PRE) - Q <= #1 1'b1; - else - Q <= #1 D; -endmodule // DFN1P1 -`timescale 1 ns / 100 ps -module DFN1P1 - ( - output reg Q, - input D,PRE,CLK - ); - always @ (posedge CLK or posedge PRE) - if (PRE) - Q <= #1 1'b1; - else - Q <= #1 D; -endmodule // DFN1P1 -`timescale 1 ns / 100 ps -module DFN1E0C1 - ( - output reg Q, - input D,E,CLR,CLK - ); - always @ (posedge CLK or posedge CLR) - if (CLR) - Q <= #1 1'b0; - else if (!E) - Q <= #1 D; -endmodule // DFN1E0C1 -`timescale 1 ns / 100 ps -module DFN1E1C1 - ( - output reg Q, - input D,E,CLR,CLK - ); - always @ (posedge CLK or posedge CLR) - if (CLR) - Q <= #1 1'b0; - else if (E) - Q <= #1 D; -endmodule // DFN1E0C1 -`timescale 1 ns / 100 ps -module DFN1E0P1 - ( - output reg Q, - input D,E,PRE,CLK - ); - always @ (posedge CLK or posedge PRE) - if (PRE) - Q <= #1 1'b1; - else if (!E) - Q <= #1 D; -endmodule // DFN1E0P1 -`timescale 1 ns / 100 ps -module DFN1E1P1 - ( - output reg Q, - input D,E,PRE,CLK - ); - always @ (posedge CLK or posedge PRE) - if (PRE) - Q <= #1 1'b1; - else if (E) - Q <= #1 D; -endmodule // DFN1E1P1

backend/sim_lib.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: backend/generic_gbuf.v =================================================================== --- backend/generic_gbuf.v (revision 397) +++ backend/generic_gbuf.v (nonexistent) @@ -1,50 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// SMII //// -//// //// -//// Description //// -//// Low pin count serial MII ethernet interface //// -//// //// -//// To Do: //// -//// - //// -//// //// -//// Author(s): //// -//// - Michael Unneback, unneback@opencores.org //// -//// ORSoC AB michael.unneback@orsoc.se //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2009 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -`timescale 1 ns/100 ps -module gbuf - ( - output GL, - input CLK - ); - - assign GL = CLK; - -endmodule

backend/generic_gbuf.v Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Deleted: svn:mergeinfo ## -0,0 +0,0 ## Index: backend/generic_pll.v =================================================================== --- backend/generic_pll.v (revision 397) +++ backend/generic_pll.v (nonexistent) @@ -1,166 +0,0 @@ -////////////////////////////////////////////////////////////////////// -//// //// -//// Generic simple PLL model //// -//// //// -//// Description //// -//// Basic PLL model, with clkx2, clkdiv, locked, outputs //// -//// //// -//// To Do: //// -//// A clkmult output //// -//// //// -//// Author(s): //// -//// - Julius Baxter julius@opencores.org //// -//// //// -////////////////////////////////////////////////////////////////////// -//// //// -//// Copyright (C) 2009 Authors and OPENCORES.ORG //// -//// //// -//// This source file may be used and distributed without //// -//// restriction provided that this copyright statement is not //// -//// removed from the file and that any derivative work contains //// -//// the original copyright notice and the associated disclaimer. //// -//// //// -//// This source file is free software; you can redistribute it //// -//// and/or modify it under the terms of the GNU Lesser General //// -//// Public License as published by the Free Software Foundation; //// -//// either version 2.1 of the License, or (at your option) any //// -//// later version. //// -//// //// -//// This source is distributed in the hope that it will be //// -//// useful, but WITHOUT ANY WARRANTY; without even the implied //// -//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// -//// PURPOSE. See the GNU Lesser General Public License for more //// -//// details. //// -//// //// -//// You should have received a copy of the GNU Lesser General //// -//// Public License along with this source; if not, download it //// -//// from http://www.opencores.org/lgpl.shtml //// -//// //// -////////////////////////////////////////////////////////////////////// -`timescale 1 ps / 1 ps -//Generic model of a PLL -//All outputs are synchronous with clk_in -//Divide for clkdiv output set by divider parameter -//Locked signal goes high 8 clocks after reset -//Note the timescale ^^^^^ - cannot be changed! -module generic_pll(/*AUTOARG*/ - // Outputs - clk1x, clk2x, clkdiv, locked, - // Inputs - clk_in, rst_in - ); -`ifndef verilator - input clk_in; - input rst_in; - output reg clk1x; - output reg clk2x; - output reg clkdiv; - output reg locked; - - parameter DIVIDER = 8; - - - - // Locked shiftreg will hold locked low until 8 cycles after reset - // Clocks should start outputting a few clocks before hand - reg [7:0] locked_shiftreg; - always @(posedge clk_in or negedge rst_in) - begin - if (rst_in) locked_shiftreg <= 8'h0; - else locked_shiftreg <= {1'b1, locked_shiftreg[7:1]}; - end - - always @(posedge clk_in or posedge rst_in) - begin - if (rst_in) locked <= 1'b0; - else - locked <= locked_shiftreg[0]; - - end - - integer clk_in_edge; //variable to store the times at which we get our edges - integer clk_in_period [3:0]; // array to store 4 calculated periods - integer period; //period value used to generate output clocks - - // determine clock period - always @(posedge clk_in or posedge rst_in) - begin - if (rst_in == 1) begin - clk_in_period[0] <= 0; - clk_in_period[1] <= 0; - clk_in_period[2] <= 0; - clk_in_period[3] <= 0; - clk_in_edge <= 0; - end - else begin - clk_in_edge <= $time; - clk_in_period[3] <= clk_in_period[2]; - clk_in_period[2] <= clk_in_period[1]; - clk_in_period[1] <= clk_in_period[0]; - if (clk_in_edge != 0) - clk_in_period[0] <= $time - clk_in_edge; - end // else: !if(rst_in == 1) - end // always @ (posedge clk_in or posedge rst_in) - - // Calculate average of our clk_in period - always @(clk_in_period[3] or clk_in_period[2] or - clk_in_period[1] or clk_in_period[0]) begin - period <= ((clk_in_period[3] + clk_in_period[2] + - clk_in_period[1] + clk_in_period[0])/4); - end - - // generate clk1x out - always @(posedge clk_in or posedge rst_in) - if (rst_in) - clk1x <= 0; - else begin - if (clk_in == 1 && locked_shiftreg[4]) begin - clk1x <= 1; - #(period / 2) clk1x <= 0; - end - else - clk1x <= 0; - end - // generate clk2x out - always @(posedge clk_in or posedge rst_in) - if (rst_in) - clk2x <= 0; - else begin - if (clk_in == 1 && locked_shiftreg[4]) begin - clk2x <= 1; - #(period / 4) clk2x <= 0; - #(period / 4) clk2x <= 1; - #(period / 4) clk2x <= 0; - end - else - clk2x <= 0; - end - - //generate clkdiv out - always @(posedge clk_in or posedge rst_in) - if (rst_in) - clkdiv <= 1'b0; - else begin - if (clk_in == 1 && locked_shiftreg[4]) begin - clkdiv <= 1'b1; - #(DIVIDER*period/2) clkdiv <= 1'b0; - #(DIVIDER*period/2); - end - end -`else // !`ifndef verilator - input clk_in; - input rst_in; - output clk1x; - output clk2x; - output clkdiv; - output reg locked; - - parameter DIVIDER = 8; - - always @(posedge clk_in) locked <= ~rst_in; - assign clk1x = clk_in; - assign clk2x = 0; - assign clkdiv= 0; -`endif // !`ifndef verilator - -endmodule // generic_pll