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https://opencores.org/ocsvn/openrisc/openrisc/trunk
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- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2
- from Rev 408 to Rev 409
- ↔ Reverse comparison
Rev 408 → Rev 409
/rtl/verilog/eth/xilinx_dist_ram_16x32.v
File deleted
rtl/verilog/eth/xilinx_dist_ram_16x32.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: rtl/verilog/eth/eth_maccontrol.v
===================================================================
--- rtl/verilog/eth/eth_maccontrol.v (revision 408)
+++ rtl/verilog/eth/eth_maccontrol.v (nonexistent)
@@ -1,271 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_maccontrol.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.6 2002/11/22 01:57:06 mohor
-// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
-// synchronized.
-//
-// Revision 1.5 2002/11/21 00:14:39 mohor
-// TxDone and TxAbort changed so they're not propagated to the wishbone
-// module when control frame is transmitted.
-//
-// Revision 1.4 2002/11/19 17:37:32 mohor
-// When control frame (PAUSE) was sent, status was written in the
-// eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
-// Only TXC interrupt is set.
-//
-// Revision 1.3 2002/01/23 10:28:16 mohor
-// Link in the header changed.
-//
-// Revision 1.2 2001/10/19 08:43:51 mohor
-// eth_timescale.v changed to timescale.v This is done because of the
-// simulation of the few cores in a one joined project.
-//
-// Revision 1.1 2001/08/06 14:44:29 mohor
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
-// Include files fixed to contain no path.
-// File names and module names changed ta have a eth_ prologue in the name.
-// File eth_timescale.v is used to define timescale
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
-// and Mdo_OE. The bidirectional signal must be created on the top level. This
-// is done due to the ASIC tools.
-//
-// Revision 1.1 2001/07/30 21:23:42 mohor
-// Directory structure changed. Files checked and joind together.
-//
-// Revision 1.1 2001/07/03 12:51:54 mohor
-// Initial release of the MAC Control module.
-//
-//
-//
-//
-
-
-`include "timescale.v"
-
-
-module eth_maccontrol (MTxClk, MRxClk, TxReset, RxReset, TPauseRq, TxDataIn, TxStartFrmIn, TxUsedDataIn,
- TxEndFrmIn, TxDoneIn, TxAbortIn, RxData, RxValid, RxStartFrm, RxEndFrm, ReceiveEnd,
- ReceivedPacketGood, ReceivedLengthOK, TxFlow, RxFlow, DlyCrcEn, TxPauseTV,
- MAC, PadIn, PadOut, CrcEnIn, CrcEnOut, TxDataOut, TxStartFrmOut, TxEndFrmOut,
- TxDoneOut, TxAbortOut, TxUsedDataOut, WillSendControlFrame, TxCtrlEndFrm,
- ReceivedPauseFrm, ControlFrmAddressOK, SetPauseTimer, r_PassAll, RxStatusWriteLatched_sync2
- );
-
-
-parameter Tp = 1;
-
-
-input MTxClk; // Transmit clock (from PHY)
-input MRxClk; // Receive clock (from PHY)
-input TxReset; // Transmit reset
-input RxReset; // Receive reset
-input TPauseRq; // Transmit control frame (from host)
-input [7:0] TxDataIn; // Transmit packet data byte (from host)
-input TxStartFrmIn; // Transmit packet start frame input (from host)
-input TxUsedDataIn; // Transmit packet used data (from TxEthMAC)
-input TxEndFrmIn; // Transmit packet end frame input (from host)
-input TxDoneIn; // Transmit packet done (from TxEthMAC)
-input TxAbortIn; // Transmit packet abort (input from TxEthMAC)
-input PadIn; // Padding (input from registers)
-input CrcEnIn; // Crc append (input from registers)
-input [7:0] RxData; // Receive Packet Data (from RxEthMAC)
-input RxValid; // Received a valid packet
-input RxStartFrm; // Receive packet start frame (input from RxEthMAC)
-input RxEndFrm; // Receive packet end frame (input from RxEthMAC)
-input ReceiveEnd; // End of receiving of the current packet (input from RxEthMAC)
-input ReceivedPacketGood; // Received packet is good
-input ReceivedLengthOK; // Length of the received packet is OK
-input TxFlow; // Tx flow control (from registers)
-input RxFlow; // Rx flow control (from registers)
-input DlyCrcEn; // Delayed CRC enabled (from registers)
-input [15:0] TxPauseTV; // Transmit Pause Timer Value (from registers)
-input [47:0] MAC; // MAC address (from registers)
-input RxStatusWriteLatched_sync2;
-input r_PassAll;
-
-output [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC)
-output TxStartFrmOut; // Transmit packet start frame (output to TxEthMAC)
-output TxEndFrmOut; // Transmit packet end frame (output to TxEthMAC)
-output TxDoneOut; // Transmit packet done (to host)
-output TxAbortOut; // Transmit packet aborted (to host)
-output TxUsedDataOut; // Transmit packet used data (to host)
-output PadOut; // Padding (output to TxEthMAC)
-output CrcEnOut; // Crc append (output to TxEthMAC)
-output WillSendControlFrame;
-output TxCtrlEndFrm;
-output ReceivedPauseFrm;
-output ControlFrmAddressOK;
-output SetPauseTimer;
-
-reg TxUsedDataOutDetected;
-reg TxAbortInLatched;
-reg TxDoneInLatched;
-reg MuxedDone;
-reg MuxedAbort;
-
-wire Pause;
-wire TxCtrlStartFrm;
-wire [7:0] ControlData;
-wire CtrlMux;
-wire SendingCtrlFrm; // Sending Control Frame (enables padding and CRC)
-wire BlockTxDone;
-
-
-// Signal TxUsedDataOut was detected (a transfer is already in progress)
-always @ (posedge MTxClk or posedge TxReset)
-begin
- if(TxReset)
- TxUsedDataOutDetected <= 1'b0;
- else
- if(TxDoneIn | TxAbortIn)
- TxUsedDataOutDetected <= 1'b0;
- else
- if(TxUsedDataOut)
- TxUsedDataOutDetected <= 1'b1;
-end
-
-
-// Latching variables
-always @ (posedge MTxClk or posedge TxReset)
-begin
- if(TxReset)
- begin
- TxAbortInLatched <= 1'b0;
- TxDoneInLatched <= 1'b0;
- end
- else
- begin
- TxAbortInLatched <= TxAbortIn;
- TxDoneInLatched <= TxDoneIn;
- end
-end
-
-
-
-// Generating muxed abort signal
-always @ (posedge MTxClk or posedge TxReset)
-begin
- if(TxReset)
- MuxedAbort <= 1'b0;
- else
- if(TxStartFrmIn)
- MuxedAbort <= 1'b0;
- else
- if(TxAbortIn & ~TxAbortInLatched & TxUsedDataOutDetected)
- MuxedAbort <= 1'b1;
-end
-
-
-// Generating muxed done signal
-always @ (posedge MTxClk or posedge TxReset)
-begin
- if(TxReset)
- MuxedDone <= 1'b0;
- else
- if(TxStartFrmIn)
- MuxedDone <= 1'b0;
- else
- if(TxDoneIn & (~TxDoneInLatched) & TxUsedDataOutDetected)
- MuxedDone <= 1'b1;
-end
-
-
-// TxDoneOut
-assign TxDoneOut = CtrlMux? ((~TxStartFrmIn) & (~BlockTxDone) & MuxedDone) :
- ((~TxStartFrmIn) & (~BlockTxDone) & TxDoneIn);
-
-// TxAbortOut
-assign TxAbortOut = CtrlMux? ((~TxStartFrmIn) & (~BlockTxDone) & MuxedAbort) :
- ((~TxStartFrmIn) & (~BlockTxDone) & TxAbortIn);
-
-// TxUsedDataOut
-assign TxUsedDataOut = ~CtrlMux & TxUsedDataIn;
-
-// TxStartFrmOut
-assign TxStartFrmOut = CtrlMux? TxCtrlStartFrm : (TxStartFrmIn & ~Pause);
-
-
-// TxEndFrmOut
-assign TxEndFrmOut = CtrlMux? TxCtrlEndFrm : TxEndFrmIn;
-
-
-// TxDataOut[7:0]
-assign TxDataOut[7:0] = CtrlMux? ControlData[7:0] : TxDataIn[7:0];
-
-
-// PadOut
-assign PadOut = PadIn | SendingCtrlFrm;
-
-
-// CrcEnOut
-assign CrcEnOut = CrcEnIn | SendingCtrlFrm;
-
-
-
-// Connecting receivecontrol module
-eth_receivecontrol receivecontrol1
-(
- .MTxClk(MTxClk), .MRxClk(MRxClk), .TxReset(TxReset), .RxReset(RxReset), .RxData(RxData),
- .RxValid(RxValid), .RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm), .RxFlow(RxFlow),
- .ReceiveEnd(ReceiveEnd), .MAC(MAC), .DlyCrcEn(DlyCrcEn), .TxDoneIn(TxDoneIn),
- .TxAbortIn(TxAbortIn), .TxStartFrmOut(TxStartFrmOut), .ReceivedLengthOK(ReceivedLengthOK),
- .ReceivedPacketGood(ReceivedPacketGood), .TxUsedDataOutDetected(TxUsedDataOutDetected),
- .Pause(Pause), .ReceivedPauseFrm(ReceivedPauseFrm), .AddressOK(ControlFrmAddressOK),
- .r_PassAll(r_PassAll), .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2), .SetPauseTimer(SetPauseTimer)
-);
-
-
-eth_transmitcontrol transmitcontrol1
-(
- .MTxClk(MTxClk), .TxReset(TxReset), .TxUsedDataIn(TxUsedDataIn), .TxUsedDataOut(TxUsedDataOut),
- .TxDoneIn(TxDoneIn), .TxAbortIn(TxAbortIn), .TxStartFrmIn(TxStartFrmIn), .TPauseRq(TPauseRq),
- .TxUsedDataOutDetected(TxUsedDataOutDetected), .TxFlow(TxFlow), .DlyCrcEn(DlyCrcEn), .TxPauseTV(TxPauseTV),
- .MAC(MAC), .TxCtrlStartFrm(TxCtrlStartFrm), .TxCtrlEndFrm(TxCtrlEndFrm), .SendingCtrlFrm(SendingCtrlFrm),
- .CtrlMux(CtrlMux), .ControlData(ControlData), .WillSendControlFrame(WillSendControlFrame), .BlockTxDone(BlockTxDone)
-);
-
-
-
-endmodule
rtl/verilog/eth/eth_maccontrol.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: rtl/verilog/eth/eth_outputcontrol.v
===================================================================
--- rtl/verilog/eth/eth_outputcontrol.v (revision 408)
+++ rtl/verilog/eth/eth_outputcontrol.v (nonexistent)
@@ -1,147 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_outputcontrol.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.3 2002/01/23 10:28:16 mohor
-// Link in the header changed.
-//
-// Revision 1.2 2001/10/19 08:43:51 mohor
-// eth_timescale.v changed to timescale.v This is done because of the
-// simulation of the few cores in a one joined project.
-//
-// Revision 1.1 2001/08/06 14:44:29 mohor
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
-// Include files fixed to contain no path.
-// File names and module names changed ta have a eth_ prologue in the name.
-// File eth_timescale.v is used to define timescale
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
-// and Mdo_OE. The bidirectional signal must be created on the top level. This
-// is done due to the ASIC tools.
-//
-// Revision 1.1 2001/07/30 21:23:42 mohor
-// Directory structure changed. Files checked and joind together.
-//
-// Revision 1.3 2001/06/01 22:28:56 mohor
-// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
-//
-//
-
-`include "timescale.v"
-
-module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn);
-
-parameter Tp = 1;
-
-input Clk; // Host Clock
-input Reset; // General Reset
-input WriteOp; // Write Operation Latch (When asserted, write operation is in progress)
-input NoPre; // No Preamble (no 32-bit preamble)
-input InProgress; // Operation in progress
-input ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
-input [6:0] BitCounter; // Bit Counter
-input MdcEn_n; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc falls.
-
-output Mdo; // MII Management Data Output
-output MdoEn; // MII Management Data Output Enable
-
-wire SerialEn;
-
-reg MdoEn_2d;
-reg MdoEn_d;
-reg MdoEn;
-
-reg Mdo_2d;
-reg Mdo_d;
-reg Mdo; // MII Management Data Output
-
-
-
-// Generation of the Serial Enable signal (enables the serialization of the data)
-assign SerialEn = WriteOp & InProgress & ( BitCounter>31 | ( ( BitCounter == 0 ) & NoPre ) )
- | ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) | ( ( BitCounter == 0 ) & NoPre ));
-
-
-// Generation of the MdoEn signal
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- begin
- MdoEn_2d <= 1'b0;
- MdoEn_d <= 1'b0;
- MdoEn <= 1'b0;
- end
- else
- begin
- if(MdcEn_n)
- begin
- MdoEn_2d <= SerialEn | InProgress & BitCounter<32;
- MdoEn_d <= MdoEn_2d;
- MdoEn <= MdoEn_d;
- end
- end
-end
-
-
-// Generation of the Mdo signal.
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- begin
- Mdo_2d <= 1'b0;
- Mdo_d <= 1'b0;
- Mdo <= 1'b0;
- end
- else
- begin
- if(MdcEn_n)
- begin
- Mdo_2d <= ~SerialEn & BitCounter<32;
- Mdo_d <= ShiftedBit | Mdo_2d;
- Mdo <= Mdo_d;
- end
- end
-end
-
-
-
-endmodule
rtl/verilog/eth/eth_outputcontrol.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: rtl/verilog/eth/eth_top.v
===================================================================
--- rtl/verilog/eth/eth_top.v (revision 408)
+++ rtl/verilog/eth/eth_top.v (nonexistent)
@@ -1,971 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_top.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// ////
-//// All additional information is available in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001, 2002 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: eth_top.v,v $
-// Revision 1.52 2005/03/21 20:07:18 igorm
-// Some small fixes + some troubles fixed.
-//
-// Revision 1.51 2005/02/21 11:13:17 igorm
-// Defer indication fixed.
-//
-// Revision 1.50 2004/04/26 15:26:23 igorm
-// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
-// previous update of the core.
-// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
-// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
-// register. (thanks to Mathias and Torbjorn)
-// - Multicast reception was fixed. Thanks to Ulrich Gries
-//
-// Revision 1.49 2003/11/12 18:24:59 tadejm
-// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
-//
-// Revision 1.48 2003/10/17 07:46:16 markom
-// mbist signals updated according to newest convention
-//
-// Revision 1.47 2003/10/06 15:43:45 knguyen
-// Update RxEnSync only when mrxdv_pad_i is inactive (LOW).
-//
-// Revision 1.46 2003/01/30 13:30:22 tadejm
-// Defer indication changed.
-//
-// Revision 1.45 2003/01/22 13:49:26 tadejm
-// When control packets were received, they were ignored in some cases.
-//
-// Revision 1.44 2003/01/21 12:09:40 mohor
-// When receiving normal data frame and RxFlow control was switched on, RXB
-// interrupt was not set.
-//
-// Revision 1.43 2002/11/22 01:57:06 mohor
-// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
-// synchronized.
-//
-// Revision 1.42 2002/11/21 00:09:19 mohor
-// TPauseRq synchronized to tx_clk.
-//
-// Revision 1.41 2002/11/19 18:13:49 mohor
-// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
-//
-// Revision 1.40 2002/11/19 17:34:25 mohor
-// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
-// that a frame was received because of the promiscous mode.
-//
-// Revision 1.39 2002/11/18 17:31:55 mohor
-// wb_rst_i is used for MIIM reset.
-//
-// Revision 1.38 2002/11/14 18:37:20 mohor
-// r_Rst signal does not reset any module any more and is removed from the design.
-//
-// Revision 1.37 2002/11/13 22:25:36 tadejm
-// All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.
-//
-// Revision 1.36 2002/10/18 17:04:20 tadejm
-// Changed BIST scan signals.
-//
-// Revision 1.35 2002/10/11 13:36:58 mohor
-// Typo error fixed. (When using Bist)
-//
-// Revision 1.34 2002/10/10 16:49:50 mohor
-// Signals for WISHBONE B3 compliant interface added.
-//
-// Revision 1.33 2002/10/10 16:29:30 mohor
-// BIST added.
-//
-// Revision 1.32 2002/09/20 17:12:58 mohor
-// CsMiss added. When address between 0x800 and 0xfff is accessed within
-// Ethernet Core, error acknowledge is generated.
-//
-// Revision 1.31 2002/09/12 14:50:17 mohor
-// CarrierSenseLost bug fixed when operating in full duplex mode.
-//
-// Revision 1.30 2002/09/10 10:35:23 mohor
-// Ethernet debug registers removed.
-//
-// Revision 1.29 2002/09/09 13:03:13 mohor
-// Error acknowledge is generated when accessing BDs and RST bit in the
-// MODER register (r_Rst) is set.
-//
-// Revision 1.28 2002/09/04 18:44:10 mohor
-// Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
-// connected.
-//
-// Revision 1.27 2002/07/25 18:15:37 mohor
-// RxAbort changed. Packets received with MRxErr (from PHY) are also
-// aborted.
-//
-// Revision 1.26 2002/07/17 18:51:50 mohor
-// EXTERNAL_DMA removed. External DMA not supported.
-//
-// Revision 1.25 2002/05/03 10:15:50 mohor
-// Outputs registered. Reset changed for eth_wishbone module.
-//
-// Revision 1.24 2002/04/22 14:15:42 mohor
-// Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
-// selected in eth_defines.v
-//
-// Revision 1.23 2002/03/25 13:33:53 mohor
-// md_padoen_o changed to md_padoe_o. Signal was always active high, just
-// name was incorrect.
-//
-// Revision 1.22 2002/02/26 16:59:54 mohor
-// Small fixes for external/internal DMA missmatches.
-//
-// Revision 1.21 2002/02/26 16:21:00 mohor
-// Interrupts changed in the top file
-//
-// Revision 1.20 2002/02/18 10:40:17 mohor
-// Small fixes.
-//
-// Revision 1.19 2002/02/16 14:03:44 mohor
-// Registered trimmed. Unused registers removed.
-//
-// Revision 1.18 2002/02/16 13:06:33 mohor
-// EXTERNAL_DMA used instead of WISHBONE_DMA.
-//
-// Revision 1.17 2002/02/16 07:15:27 mohor
-// Testbench fixed, code simplified, unused signals removed.
-//
-// Revision 1.16 2002/02/15 13:49:39 mohor
-// RxAbort is connected differently.
-//
-// Revision 1.15 2002/02/15 11:38:26 mohor
-// Changes that were lost when updating from 1.11 to 1.14 fixed.
-//
-// Revision 1.14 2002/02/14 20:19:11 billditt
-// Modified for Address Checking,
-// addition of eth_addrcheck.v
-//
-// Revision 1.13 2002/02/12 17:03:03 mohor
-// HASH0 and HASH1 registers added. Registers address width was
-// changed to 8 bits.
-//
-// Revision 1.12 2002/02/11 09:18:22 mohor
-// Tx status is written back to the BD.
-//
-// Revision 1.11 2002/02/08 16:21:54 mohor
-// Rx status is written back to the BD.
-//
-// Revision 1.10 2002/02/06 14:10:21 mohor
-// non-DMA host interface added. Select the right configutation in eth_defines.
-//
-// Revision 1.9 2002/01/23 10:28:16 mohor
-// Link in the header changed.
-//
-// Revision 1.8 2001/12/05 15:00:16 mohor
-// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
-// instead of the number of RX descriptors).
-//
-// Revision 1.7 2001/12/05 10:45:59 mohor
-// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
-//
-// Revision 1.6 2001/10/19 11:24:29 mohor
-// Number of addresses (wb_adr_i) minimized.
-//
-// Revision 1.5 2001/10/19 08:43:51 mohor
-// eth_timescale.v changed to timescale.v This is done because of the
-// simulation of the few cores in a one joined project.
-//
-// Revision 1.4 2001/10/18 12:07:11 mohor
-// Status signals changed, Adress decoding changed, interrupt controller
-// added.
-//
-// Revision 1.3 2001/09/24 15:02:56 mohor
-// Defines changed (All precede with ETH_). Small changes because some
-// tools generate warnings when two operands are together. Synchronization
-// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
-// demands).
-//
-// Revision 1.2 2001/08/15 14:03:59 mohor
-// Signal names changed on the top level for easier pad insertion (ASIC).
-//
-// Revision 1.1 2001/08/06 14:44:29 mohor
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
-// Include files fixed to contain no path.
-// File names and module names changed ta have a eth_ prologue in the name.
-// File eth_timescale.v is used to define timescale
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
-// and Mdo_OE. The bidirectional signal must be created on the top level. This
-// is done due to the ASIC tools.
-//
-// Revision 1.2 2001/08/02 09:25:31 mohor
-// Unconnected signals are now connected.
-//
-// Revision 1.1 2001/07/30 21:23:42 mohor
-// Directory structure changed. Files checked and joind together.
-//
-//
-//
-//
-
-
-`include "eth_defines.v"
-`include "timescale.v"
-
-
-module eth_top
-(
- // WISHBONE common
- wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
-
- // WISHBONE slave
- wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
-
- // WISHBONE master
- m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
- m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
- m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
-
-`ifdef ETH_WISHBONE_B3
- m_wb_cti_o, m_wb_bte_o,
-`endif
-
- //TX
- mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
-
- //RX
- mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i,
-
- // MIIM
- mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o,
-
- int_o
-
- // Bist
-`ifdef ETH_BIST
- ,
- // debug chain signals
- mbist_si_i, // bist scan serial in
- mbist_so_o, // bist scan serial out
- mbist_ctrl_i // bist chain shift control
-`endif
-
-);
-
-
-parameter Tp = 1;
-
-
-// WISHBONE common
-input wb_clk_i; // WISHBONE clock
-input wb_rst_i; // WISHBONE reset
-input [31:0] wb_dat_i; // WISHBONE data input
-output [31:0] wb_dat_o; // WISHBONE data output
-output wb_err_o; // WISHBONE error output
-
-// WISHBONE slave
-input [11:2] wb_adr_i; // WISHBONE address input
-input [3:0] wb_sel_i; // WISHBONE byte select input
-input wb_we_i; // WISHBONE write enable input
-input wb_cyc_i; // WISHBONE cycle input
-input wb_stb_i; // WISHBONE strobe input
-output wb_ack_o; // WISHBONE acknowledge output
-
-// WISHBONE master
-output [31:0] m_wb_adr_o;
-output [3:0] m_wb_sel_o;
-output m_wb_we_o;
-input [31:0] m_wb_dat_i;
-output [31:0] m_wb_dat_o;
-output m_wb_cyc_o;
-output m_wb_stb_o;
-input m_wb_ack_i;
-input m_wb_err_i;
-
-wire [29:0] m_wb_adr_tmp;
-
-`ifdef ETH_WISHBONE_B3
-output [2:0] m_wb_cti_o; // Cycle Type Identifier
-output [1:0] m_wb_bte_o; // Burst Type Extension
-`endif
-
-// Tx
-input mtx_clk_pad_i; // Transmit clock (from PHY)
-output [3:0] mtxd_pad_o; // Transmit nibble (to PHY)
-output mtxen_pad_o; // Transmit enable (to PHY)
-output mtxerr_pad_o; // Transmit error (to PHY)
-
-// Rx
-input mrx_clk_pad_i; // Receive clock (from PHY)
-input [3:0] mrxd_pad_i; // Receive nibble (from PHY)
-input mrxdv_pad_i; // Receive data valid (from PHY)
-input mrxerr_pad_i; // Receive data error (from PHY)
-
-// Common Tx and Rx
-input mcoll_pad_i; // Collision (from PHY)
-input mcrs_pad_i; // Carrier sense (from PHY)
-
-// MII Management interface
-input md_pad_i; // MII data input (from I/O cell)
-output mdc_pad_o; // MII Management data clock (to PHY)
-output md_pad_o; // MII data output (to I/O cell)
-output md_padoe_o; // MII data output enable (to I/O cell)
-
-output int_o; // Interrupt output
-
-// Bist
-`ifdef ETH_BIST
-input mbist_si_i; // bist scan serial in
-output mbist_so_o; // bist scan serial out
-input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
-`endif
-
-wire [7:0] r_ClkDiv;
-wire r_MiiNoPre;
-wire [15:0] r_CtrlData;
-wire [4:0] r_FIAD;
-wire [4:0] r_RGAD;
-wire r_WCtrlData;
-wire r_RStat;
-wire r_ScanStat;
-wire NValid_stat;
-wire Busy_stat;
-wire LinkFail;
-wire [15:0] Prsd; // Read Status Data (data read from the PHY)
-wire WCtrlDataStart;
-wire RStatStart;
-wire UpdateMIIRX_DATAReg;
-
-wire TxStartFrm;
-wire TxEndFrm;
-wire TxUsedData;
-wire [7:0] TxData;
-wire TxRetry;
-wire TxAbort;
-wire TxUnderRun;
-wire TxDone;
-
-
-reg WillSendControlFrame_sync1;
-reg WillSendControlFrame_sync2;
-reg WillSendControlFrame_sync3;
-reg RstTxPauseRq;
-
-reg TxPauseRq_sync1;
-reg TxPauseRq_sync2;
-reg TxPauseRq_sync3;
-reg TPauseRq;
-
-
-// Connecting Miim module
-eth_miim miim1
-(
- .Clk(wb_clk_i), .Reset(wb_rst_i), .Divider(r_ClkDiv),
- .NoPre(r_MiiNoPre), .CtrlData(r_CtrlData), .Rgad(r_RGAD),
- .Fiad(r_FIAD), .WCtrlData(r_WCtrlData), .RStat(r_RStat),
- .ScanStat(r_ScanStat), .Mdi(md_pad_i), .Mdo(md_pad_o),
- .MdoEn(md_padoe_o), .Mdc(mdc_pad_o), .Busy(Busy_stat),
- .Prsd(Prsd), .LinkFail(LinkFail), .Nvalid(NValid_stat),
- .WCtrlDataStart(WCtrlDataStart), .RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg)
-);
-
-
-
-
-wire [3:0] RegCs; // Connected to registers
-wire [31:0] RegDataOut; // Multiplexed to wb_dat_o
-wire r_RecSmall; // Receive small frames
-wire r_LoopBck; // Loopback
-wire r_TxEn; // Tx Enable
-wire r_RxEn; // Rx Enable
-
-wire MRxDV_Lb; // Muxed MII receive data valid
-wire MRxErr_Lb; // Muxed MII Receive Error
-wire [3:0] MRxD_Lb; // Muxed MII Receive Data
-wire Transmitting; // Indication that TxEthMAC is transmitting
-wire r_HugEn; // Huge packet enable
-wire r_DlyCrcEn; // Delayed CRC enabled
-wire [15:0] r_MaxFL; // Maximum frame length
-
-wire [15:0] r_MinFL; // Minimum frame length
-wire ShortFrame;
-wire DribbleNibble; // Extra nibble received
-wire ReceivedPacketTooBig; // Received packet is too big
-wire [47:0] r_MAC; // MAC address
-wire LoadRxStatus; // Rx status was loaded
-wire [31:0] r_HASH0; // HASH table, lower 4 bytes
-wire [31:0] r_HASH1; // HASH table, upper 4 bytes
-wire [7:0] r_TxBDNum; // Receive buffer descriptor number
-wire [6:0] r_IPGT; //
-wire [6:0] r_IPGR1; //
-wire [6:0] r_IPGR2; //
-wire [5:0] r_CollValid; //
-wire [15:0] r_TxPauseTV; // Transmit PAUSE value
-wire r_TxPauseRq; // Transmit PAUSE request
-
-wire [3:0] r_MaxRet; //
-wire r_NoBckof; //
-wire r_ExDfrEn; //
-wire r_TxFlow; // Tx flow control enable
-wire r_IFG; // Minimum interframe gap for incoming packets
-
-wire TxB_IRQ; // Interrupt Tx Buffer
-wire TxE_IRQ; // Interrupt Tx Error
-wire RxB_IRQ; // Interrupt Rx Buffer
-wire RxE_IRQ; // Interrupt Rx Error
-wire Busy_IRQ; // Interrupt Busy (lack of buffers)
-
-//wire DWord;
-wire ByteSelected;
-wire BDAck;
-wire [31:0] BD_WB_DAT_O; // wb_dat_o that comes from the Wishbone module (for buffer descriptors read/write)
-wire [3:0] BDCs; // Buffer descriptor CS
-wire CsMiss; // When access to the address between 0x800 and 0xfff occurs, acknowledge is set
- // but data is not valid.
-wire r_Pad;
-wire r_CrcEn;
-wire r_FullD;
-wire r_Pro;
-wire r_Bro;
-wire r_NoPre;
-wire r_RxFlow;
-wire r_PassAll;
-wire TxCtrlEndFrm;
-wire StartTxDone;
-wire SetPauseTimer;
-wire TxUsedDataIn;
-wire TxDoneIn;
-wire TxAbortIn;
-wire PerPacketPad;
-wire PadOut;
-wire PerPacketCrcEn;
-wire CrcEnOut;
-wire TxStartFrmOut;
-wire TxEndFrmOut;
-wire ReceivedPauseFrm;
-wire ControlFrmAddressOK;
-wire RxStatusWriteLatched_sync2;
-wire LateCollision;
-wire DeferIndication;
-wire LateCollLatched;
-wire DeferLatched;
-wire RstDeferLatched;
-wire CarrierSenseLost;
-
-wire temp_wb_ack_o;
-wire [31:0] temp_wb_dat_o;
-wire temp_wb_err_o;
-
-`ifdef ETH_REGISTERED_OUTPUTS
- reg temp_wb_ack_o_reg;
- reg [31:0] temp_wb_dat_o_reg;
- reg temp_wb_err_o_reg;
-`endif
-
-//assign DWord = &wb_sel_i;
-assign ByteSelected = |wb_sel_i;
-assign RegCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[3]; // 0x0 - 0x3FF
-assign RegCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[2]; // 0x0 - 0x3FF
-assign RegCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[1]; // 0x0 - 0x3FF
-assign RegCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[0]; // 0x0 - 0x3FF
-assign BDCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[3]; // 0x400 - 0x7FF
-assign BDCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[2]; // 0x400 - 0x7FF
-assign BDCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[1]; // 0x400 - 0x7FF
-assign BDCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[0]; // 0x400 - 0x7FF
-assign CsMiss = wb_stb_i & wb_cyc_i & ByteSelected & wb_adr_i[11]; // 0x800 - 0xfFF
-assign temp_wb_dat_o = ((|RegCs) & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
-assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~ByteSelected | CsMiss);
-
-`ifdef ETH_REGISTERED_OUTPUTS
- assign wb_ack_o = temp_wb_ack_o_reg;
- assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
- assign wb_err_o = temp_wb_err_o_reg;
-`else
- assign wb_ack_o = temp_wb_ack_o;
- assign wb_dat_o[31:0] = temp_wb_dat_o;
- assign wb_err_o = temp_wb_err_o;
-`endif
-
-`ifdef ETH_AVALON_BUS
- // As Avalon has no corresponding "error" signal, I (erroneously) will
- // send an ack to Avalon, even when accessing undefined memory. This
- // is a grey area in Avalon vs. Wishbone specs: My understanding
- // is that Avalon expects all memory addressable by the addr bus feeding
- // a slave to be, at the very minimum, readable.
- assign temp_wb_ack_o = (|RegCs) | BDAck | CsMiss;
-`else // WISHBONE
- assign temp_wb_ack_o = (|RegCs) | BDAck;
-`endif
-
-`ifdef ETH_REGISTERED_OUTPUTS
- always @ (posedge wb_clk_i or posedge wb_rst_i)
- begin
- if(wb_rst_i)
- begin
- temp_wb_ack_o_reg <=#Tp 1'b0;
- temp_wb_dat_o_reg <=#Tp 32'h0;
- temp_wb_err_o_reg <=#Tp 1'b0;
- end
- else
- begin
- temp_wb_ack_o_reg <=#Tp temp_wb_ack_o & ~temp_wb_ack_o_reg;
- temp_wb_dat_o_reg <=#Tp temp_wb_dat_o;
- temp_wb_err_o_reg <=#Tp temp_wb_err_o & ~temp_wb_err_o_reg;
- end
- end
-`endif
-
-
-// Connecting Ethernet registers
-eth_registers ethreg1
-(
- .DataIn(wb_dat_i), .Address(wb_adr_i[9:2]), .Rw(wb_we_i),
- .Cs(RegCs), .Clk(wb_clk_i), .Reset(wb_rst_i),
- .DataOut(RegDataOut), .r_RecSmall(r_RecSmall),
- .r_Pad(r_Pad), .r_HugEn(r_HugEn), .r_CrcEn(r_CrcEn),
- .r_DlyCrcEn(r_DlyCrcEn), .r_FullD(r_FullD),
- .r_ExDfrEn(r_ExDfrEn), .r_NoBckof(r_NoBckof), .r_LoopBck(r_LoopBck),
- .r_IFG(r_IFG), .r_Pro(r_Pro), .r_Iam(),
- .r_Bro(r_Bro), .r_NoPre(r_NoPre), .r_TxEn(r_TxEn),
- .r_RxEn(r_RxEn), .Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ),
- .RxB_IRQ(RxB_IRQ), .TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
- .r_IPGT(r_IPGT),
- .r_IPGR1(r_IPGR1), .r_IPGR2(r_IPGR2), .r_MinFL(r_MinFL),
- .r_MaxFL(r_MaxFL), .r_MaxRet(r_MaxRet), .r_CollValid(r_CollValid),
- .r_TxFlow(r_TxFlow), .r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll),
- .r_MiiNoPre(r_MiiNoPre), .r_ClkDiv(r_ClkDiv),
- .r_WCtrlData(r_WCtrlData), .r_RStat(r_RStat), .r_ScanStat(r_ScanStat),
- .r_RGAD(r_RGAD), .r_FIAD(r_FIAD), .r_CtrlData(r_CtrlData),
- .NValid_stat(NValid_stat), .Busy_stat(Busy_stat),
- .LinkFail(LinkFail), .r_MAC(r_MAC), .WCtrlDataStart(WCtrlDataStart),
- .RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg), .Prsd(Prsd),
- .r_TxBDNum(r_TxBDNum), .int_o(int_o),
- .r_HASH0(r_HASH0), .r_HASH1(r_HASH1), .r_TxPauseRq(r_TxPauseRq),
- .r_TxPauseTV(r_TxPauseTV), .RstTxPauseRq(RstTxPauseRq), .TxCtrlEndFrm(TxCtrlEndFrm),
- .StartTxDone(StartTxDone), .TxClk(mtx_clk_pad_i), .RxClk(mrx_clk_pad_i),
- .SetPauseTimer(SetPauseTimer)
-
-);
-
-
-
-wire [7:0] RxData;
-wire RxValid;
-wire RxStartFrm;
-wire RxEndFrm;
-wire RxAbort;
-
-wire WillTransmit; // Will transmit (to RxEthMAC)
-wire ResetCollision; // Reset Collision (for synchronizing collision)
-wire [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC)
-wire WillSendControlFrame;
-wire ReceiveEnd;
-wire ReceivedPacketGood;
-wire ReceivedLengthOK;
-wire InvalidSymbol;
-wire LatchedCrcError;
-wire RxLateCollision;
-wire [3:0] RetryCntLatched;
-wire [3:0] RetryCnt;
-wire StartTxAbort;
-wire MaxCollisionOccured;
-wire RetryLimit;
-wire StatePreamble;
-wire [1:0] StateData;
-
-// Connecting MACControl
-eth_maccontrol maccontrol1
-(
- .MTxClk(mtx_clk_pad_i), .TPauseRq(TPauseRq),
- .TxPauseTV(r_TxPauseTV), .TxDataIn(TxData),
- .TxStartFrmIn(TxStartFrm), .TxEndFrmIn(TxEndFrm),
- .TxUsedDataIn(TxUsedDataIn), .TxDoneIn(TxDoneIn),
- .TxAbortIn(TxAbortIn), .MRxClk(mrx_clk_pad_i),
- .RxData(RxData), .RxValid(RxValid),
- .RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
- .ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood),
- .TxFlow(r_TxFlow),
- .RxFlow(r_RxFlow), .DlyCrcEn(r_DlyCrcEn),
- .MAC(r_MAC), .PadIn(r_Pad | PerPacketPad),
- .PadOut(PadOut), .CrcEnIn(r_CrcEn | PerPacketCrcEn),
- .CrcEnOut(CrcEnOut), .TxReset(wb_rst_i),
- .RxReset(wb_rst_i), .ReceivedLengthOK(ReceivedLengthOK),
- .TxDataOut(TxDataOut), .TxStartFrmOut(TxStartFrmOut),
- .TxEndFrmOut(TxEndFrmOut), .TxUsedDataOut(TxUsedData),
- .TxDoneOut(TxDone), .TxAbortOut(TxAbort),
- .WillSendControlFrame(WillSendControlFrame), .TxCtrlEndFrm(TxCtrlEndFrm),
- .ReceivedPauseFrm(ReceivedPauseFrm), .ControlFrmAddressOK(ControlFrmAddressOK),
- .SetPauseTimer(SetPauseTimer),
- .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2), .r_PassAll(r_PassAll)
-);
-
-
-
-wire TxCarrierSense; // Synchronized CarrierSense (to Tx clock)
-wire Collision; // Synchronized Collision
-
-reg CarrierSense_Tx1;
-reg CarrierSense_Tx2;
-reg Collision_Tx1;
-reg Collision_Tx2;
-
-reg RxEnSync; // Synchronized Receive Enable
-reg WillTransmit_q;
-reg WillTransmit_q2;
-
-
-
-// Muxed MII receive data valid
-assign MRxDV_Lb = r_LoopBck? mtxen_pad_o : mrxdv_pad_i & RxEnSync;
-
-// Muxed MII Receive Error
-assign MRxErr_Lb = r_LoopBck? mtxerr_pad_o : mrxerr_pad_i & RxEnSync;
-
-// Muxed MII Receive Data
-assign MRxD_Lb[3:0] = r_LoopBck? mtxd_pad_o[3:0] : mrxd_pad_i[3:0];
-
-
-
-// Connecting TxEthMAC
-eth_txethmac txethmac1
-(
- .MTxClk(mtx_clk_pad_i), .Reset(wb_rst_i), .CarrierSense(TxCarrierSense),
- .Collision(Collision), .TxData(TxDataOut), .TxStartFrm(TxStartFrmOut),
- .TxUnderRun(TxUnderRun), .TxEndFrm(TxEndFrmOut), .Pad(PadOut),
- .MinFL(r_MinFL), .CrcEn(CrcEnOut), .FullD(r_FullD),
- .HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn), .IPGT(r_IPGT),
- .IPGR1(r_IPGR1), .IPGR2(r_IPGR2), .CollValid(r_CollValid),
- .MaxRet(r_MaxRet), .NoBckof(r_NoBckof), .ExDfrEn(r_ExDfrEn),
- .MaxFL(r_MaxFL), .MTxEn(mtxen_pad_o), .MTxD(mtxd_pad_o),
- .MTxErr(mtxerr_pad_o), .TxUsedData(TxUsedDataIn), .TxDone(TxDoneIn),
- .TxRetry(TxRetry), .TxAbort(TxAbortIn), .WillTransmit(WillTransmit),
- .ResetCollision(ResetCollision), .RetryCnt(RetryCnt), .StartTxDone(StartTxDone),
- .StartTxAbort(StartTxAbort), .MaxCollisionOccured(MaxCollisionOccured), .LateCollision(LateCollision),
- .DeferIndication(DeferIndication), .StatePreamble(StatePreamble), .StateData(StateData)
-);
-
-
-
-
-wire [15:0] RxByteCnt;
-wire RxByteCntEq0;
-wire RxByteCntGreat2;
-wire RxByteCntMaxFrame;
-wire RxCrcError;
-wire RxStateIdle;
-wire RxStatePreamble;
-wire RxStateSFD;
-wire [1:0] RxStateData;
-wire AddressMiss;
-
-
-
-// Connecting RxEthMAC
-eth_rxethmac rxethmac1
-(
- .MRxClk(mrx_clk_pad_i), .MRxDV(MRxDV_Lb), .MRxD(MRxD_Lb),
- .Transmitting(Transmitting), .HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn),
- .MaxFL(r_MaxFL), .r_IFG(r_IFG), .Reset(wb_rst_i),
- .RxData(RxData), .RxValid(RxValid), .RxStartFrm(RxStartFrm),
- .RxEndFrm(RxEndFrm), .ByteCnt(RxByteCnt),
- .ByteCntEq0(RxByteCntEq0), .ByteCntGreat2(RxByteCntGreat2), .ByteCntMaxFrame(RxByteCntMaxFrame),
- .CrcError(RxCrcError), .StateIdle(RxStateIdle), .StatePreamble(RxStatePreamble),
- .StateSFD(RxStateSFD), .StateData(RxStateData),
- .MAC(r_MAC), .r_Pro(r_Pro), .r_Bro(r_Bro),
- .r_HASH0(r_HASH0), .r_HASH1(r_HASH1), .RxAbort(RxAbort),
- .AddressMiss(AddressMiss), .PassAll(r_PassAll), .ControlFrmAddressOK(ControlFrmAddressOK)
-);
-
-
-// MII Carrier Sense Synchronization
-always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
-begin
- if(wb_rst_i)
- begin
- CarrierSense_Tx1 <= #Tp 1'b0;
- CarrierSense_Tx2 <= #Tp 1'b0;
- end
- else
- begin
- CarrierSense_Tx1 <= #Tp mcrs_pad_i;
- CarrierSense_Tx2 <= #Tp CarrierSense_Tx1;
- end
-end
-
-assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2;
-
-
-// MII Collision Synchronization
-always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
-begin
- if(wb_rst_i)
- begin
- Collision_Tx1 <= #Tp 1'b0;
- Collision_Tx2 <= #Tp 1'b0;
- end
- else
- begin
- Collision_Tx1 <= #Tp mcoll_pad_i;
- if(ResetCollision)
- Collision_Tx2 <= #Tp 1'b0;
- else
- if(Collision_Tx1)
- Collision_Tx2 <= #Tp 1'b1;
- end
-end
-
-
-// Synchronized Collision
-assign Collision = ~r_FullD & Collision_Tx2;
-
-
-
-// Delayed WillTransmit
-always @ (posedge mrx_clk_pad_i)
-begin
- WillTransmit_q <= #Tp WillTransmit;
- WillTransmit_q2 <= #Tp WillTransmit_q;
-end
-
-
-assign Transmitting = ~r_FullD & WillTransmit_q2;
-
-
-
-// Synchronized Receive Enable
-always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
-begin
- if(wb_rst_i)
- RxEnSync <= #Tp 1'b0;
- else
- if(~mrxdv_pad_i)
- RxEnSync <= #Tp r_RxEn;
-end
-
-
-
-// Synchronizing WillSendControlFrame to WB_CLK;
-always @ (posedge wb_clk_i or posedge wb_rst_i)
-begin
- if(wb_rst_i)
- WillSendControlFrame_sync1 <= 1'b0;
- else
- WillSendControlFrame_sync1 <=#Tp WillSendControlFrame;
-end
-
-always @ (posedge wb_clk_i or posedge wb_rst_i)
-begin
- if(wb_rst_i)
- WillSendControlFrame_sync2 <= 1'b0;
- else
- WillSendControlFrame_sync2 <=#Tp WillSendControlFrame_sync1;
-end
-
-always @ (posedge wb_clk_i or posedge wb_rst_i)
-begin
- if(wb_rst_i)
- WillSendControlFrame_sync3 <= 1'b0;
- else
- WillSendControlFrame_sync3 <=#Tp WillSendControlFrame_sync2;
-end
-
-always @ (posedge wb_clk_i or posedge wb_rst_i)
-begin
- if(wb_rst_i)
- RstTxPauseRq <= 1'b0;
- else
- RstTxPauseRq <=#Tp WillSendControlFrame_sync2 & ~WillSendControlFrame_sync3;
-end
-
-
-
-
-// TX Pause request Synchronization
-always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
-begin
- if(wb_rst_i)
- begin
- TxPauseRq_sync1 <= #Tp 1'b0;
- TxPauseRq_sync2 <= #Tp 1'b0;
- TxPauseRq_sync3 <= #Tp 1'b0;
- end
- else
- begin
- TxPauseRq_sync1 <= #Tp (r_TxPauseRq & r_TxFlow);
- TxPauseRq_sync2 <= #Tp TxPauseRq_sync1;
- TxPauseRq_sync3 <= #Tp TxPauseRq_sync2;
- end
-end
-
-
-always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
-begin
- if(wb_rst_i)
- TPauseRq <= #Tp 1'b0;
- else
- TPauseRq <= #Tp TxPauseRq_sync2 & (~TxPauseRq_sync3);
-end
-
-
-wire LatchedMRxErr;
-reg RxAbort_latch;
-reg RxAbort_sync1;
-reg RxAbort_wb;
-reg RxAbortRst_sync1;
-reg RxAbortRst;
-
-// Synchronizing RxAbort to the WISHBONE clock
-always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
-begin
- if(wb_rst_i)
- RxAbort_latch <= #Tp 1'b0;
- else if(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr & ~InvalidSymbol | (ReceivedPauseFrm & (~r_PassAll)))
- RxAbort_latch <= #Tp 1'b1;
- else if(RxAbortRst)
- RxAbort_latch <= #Tp 1'b0;
-end
-
-always @ (posedge wb_clk_i or posedge wb_rst_i)
-begin
- if(wb_rst_i)
- begin
- RxAbort_sync1 <= #Tp 1'b0;
- RxAbort_wb <= #Tp 1'b0;
- RxAbort_wb <= #Tp 1'b0;
- end
- else
- begin
- RxAbort_sync1 <= #Tp RxAbort_latch;
- RxAbort_wb <= #Tp RxAbort_sync1;
- end
-end
-
-always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
-begin
- if(wb_rst_i)
- begin
- RxAbortRst_sync1 <= #Tp 1'b0;
- RxAbortRst <= #Tp 1'b0;
- end
- else
- begin
- RxAbortRst_sync1 <= #Tp RxAbort_wb;
- RxAbortRst <= #Tp RxAbortRst_sync1;
- end
-end
-
-
-
-// Connecting Wishbone module
-eth_wishbone wishbone
-(
- .WB_CLK_I(wb_clk_i), .WB_DAT_I(wb_dat_i),
- .WB_DAT_O(BD_WB_DAT_O),
-
- // WISHBONE slave
- .WB_ADR_I(wb_adr_i[9:2]), .WB_WE_I(wb_we_i),
- .BDCs(BDCs), .WB_ACK_O(BDAck),
-
- .Reset(wb_rst_i),
-
- // WISHBONE master
- .m_wb_adr_o(m_wb_adr_tmp), .m_wb_sel_o(m_wb_sel_o), .m_wb_we_o(m_wb_we_o),
- .m_wb_dat_i(m_wb_dat_i), .m_wb_dat_o(m_wb_dat_o), .m_wb_cyc_o(m_wb_cyc_o),
- .m_wb_stb_o(m_wb_stb_o), .m_wb_ack_i(m_wb_ack_i), .m_wb_err_i(m_wb_err_i),
-
-`ifdef ETH_WISHBONE_B3
- .m_wb_cti_o(m_wb_cti_o), .m_wb_bte_o(m_wb_bte_o),
-`endif
-
-
- //TX
- .MTxClk(mtx_clk_pad_i), .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm),
- .TxUsedData(TxUsedData), .TxData(TxData),
- .TxRetry(TxRetry), .TxAbort(TxAbort), .TxUnderRun(TxUnderRun),
- .TxDone(TxDone),
- .PerPacketCrcEn(PerPacketCrcEn), .PerPacketPad(PerPacketPad),
-
- // Register
- .r_TxEn(r_TxEn), .r_RxEn(r_RxEn), .r_TxBDNum(r_TxBDNum),
- .r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll),
-
- //RX
- .MRxClk(mrx_clk_pad_i), .RxData(RxData), .RxValid(RxValid),
- .RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
- .Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ), .RxB_IRQ(RxB_IRQ),
- .TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
-
- .RxAbort(RxAbort_wb), .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2),
-
- .InvalidSymbol(InvalidSymbol), .LatchedCrcError(LatchedCrcError), .RxLength(RxByteCnt),
- .RxLateCollision(RxLateCollision), .ShortFrame(ShortFrame), .DribbleNibble(DribbleNibble),
- .ReceivedPacketTooBig(ReceivedPacketTooBig), .LoadRxStatus(LoadRxStatus), .RetryCntLatched(RetryCntLatched),
- .RetryLimit(RetryLimit), .LateCollLatched(LateCollLatched), .DeferLatched(DeferLatched),
- .RstDeferLatched(RstDeferLatched),
- .CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood), .AddressMiss(AddressMiss),
- .ReceivedPauseFrm(ReceivedPauseFrm)
-
-`ifdef ETH_BIST
- ,
- .mbist_si_i (mbist_si_i),
- .mbist_so_o (mbist_so_o),
- .mbist_ctrl_i (mbist_ctrl_i)
-`endif
-);
-
-assign m_wb_adr_o = {m_wb_adr_tmp, 2'h0};
-
-// Connecting MacStatus module
-eth_macstatus macstatus1
-(
- .MRxClk(mrx_clk_pad_i), .Reset(wb_rst_i),
- .ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood), .ReceivedLengthOK(ReceivedLengthOK),
- .RxCrcError(RxCrcError), .MRxErr(MRxErr_Lb), .MRxDV(MRxDV_Lb),
- .RxStateSFD(RxStateSFD), .RxStateData(RxStateData), .RxStatePreamble(RxStatePreamble),
- .RxStateIdle(RxStateIdle), .Transmitting(Transmitting), .RxByteCnt(RxByteCnt),
- .RxByteCntEq0(RxByteCntEq0), .RxByteCntGreat2(RxByteCntGreat2), .RxByteCntMaxFrame(RxByteCntMaxFrame),
- .InvalidSymbol(InvalidSymbol),
- .MRxD(MRxD_Lb), .LatchedCrcError(LatchedCrcError), .Collision(mcoll_pad_i),
- .CollValid(r_CollValid), .RxLateCollision(RxLateCollision), .r_RecSmall(r_RecSmall),
- .r_MinFL(r_MinFL), .r_MaxFL(r_MaxFL), .ShortFrame(ShortFrame),
- .DribbleNibble(DribbleNibble), .ReceivedPacketTooBig(ReceivedPacketTooBig), .r_HugEn(r_HugEn),
- .LoadRxStatus(LoadRxStatus), .RetryCnt(RetryCnt), .StartTxDone(StartTxDone),
- .StartTxAbort(StartTxAbort), .RetryCntLatched(RetryCntLatched), .MTxClk(mtx_clk_pad_i),
- .MaxCollisionOccured(MaxCollisionOccured), .RetryLimit(RetryLimit), .LateCollision(LateCollision),
- .LateCollLatched(LateCollLatched), .DeferIndication(DeferIndication), .DeferLatched(DeferLatched),
- .RstDeferLatched(RstDeferLatched),
- .TxStartFrm(TxStartFrmOut), .StatePreamble(StatePreamble), .StateData(StateData),
- .CarrierSense(CarrierSense_Tx2), .CarrierSenseLost(CarrierSenseLost), .TxUsedData(TxUsedDataIn),
- .LatchedMRxErr(LatchedMRxErr), .Loopback(r_LoopBck), .r_FullD(r_FullD)
-);
-
-
-endmodule
rtl/verilog/eth/eth_top.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: rtl/verilog/eth/eth_transmitcontrol.v
===================================================================
--- rtl/verilog/eth/eth_transmitcontrol.v (revision 408)
+++ rtl/verilog/eth/eth_transmitcontrol.v (nonexistent)
@@ -1,326 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_transmitcontrol.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.5 2002/11/19 17:37:32 mohor
-// When control frame (PAUSE) was sent, status was written in the
-// eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
-// Only TXC interrupt is set.
-//
-// Revision 1.4 2002/01/23 10:28:16 mohor
-// Link in the header changed.
-//
-// Revision 1.3 2001/10/19 08:43:51 mohor
-// eth_timescale.v changed to timescale.v This is done because of the
-// simulation of the few cores in a one joined project.
-//
-// Revision 1.2 2001/09/11 14:17:00 mohor
-// Few little NCSIM warnings fixed.
-//
-// Revision 1.1 2001/08/06 14:44:29 mohor
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
-// Include files fixed to contain no path.
-// File names and module names changed ta have a eth_ prologue in the name.
-// File eth_timescale.v is used to define timescale
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
-// and Mdo_OE. The bidirectional signal must be created on the top level. This
-// is done due to the ASIC tools.
-//
-// Revision 1.1 2001/07/30 21:23:42 mohor
-// Directory structure changed. Files checked and joind together.
-//
-// Revision 1.1 2001/07/03 12:51:54 mohor
-// Initial release of the MAC Control module.
-//
-//
-//
-//
-//
-//
-
-
-`include "timescale.v"
-
-
-module eth_transmitcontrol (MTxClk, TxReset, TxUsedDataIn, TxUsedDataOut, TxDoneIn, TxAbortIn,
- TxStartFrmIn, TPauseRq, TxUsedDataOutDetected, TxFlow, DlyCrcEn,
- TxPauseTV, MAC, TxCtrlStartFrm, TxCtrlEndFrm, SendingCtrlFrm, CtrlMux,
- ControlData, WillSendControlFrame, BlockTxDone
- );
-
-parameter Tp = 1;
-
-
-input MTxClk;
-input TxReset;
-input TxUsedDataIn;
-input TxUsedDataOut;
-input TxDoneIn;
-input TxAbortIn;
-input TxStartFrmIn;
-input TPauseRq;
-input TxUsedDataOutDetected;
-input TxFlow;
-input DlyCrcEn;
-input [15:0] TxPauseTV;
-input [47:0] MAC;
-
-output TxCtrlStartFrm;
-output TxCtrlEndFrm;
-output SendingCtrlFrm;
-output CtrlMux;
-output [7:0] ControlData;
-output WillSendControlFrame;
-output BlockTxDone;
-
-reg SendingCtrlFrm;
-reg CtrlMux;
-reg WillSendControlFrame;
-reg [3:0] DlyCrcCnt;
-reg [5:0] ByteCnt;
-reg ControlEnd_q;
-reg [7:0] MuxedCtrlData;
-reg TxCtrlStartFrm;
-reg TxCtrlStartFrm_q;
-reg TxCtrlEndFrm;
-reg [7:0] ControlData;
-reg TxUsedDataIn_q;
-reg BlockTxDone;
-
-wire IncrementDlyCrcCnt;
-wire ResetByteCnt;
-wire IncrementByteCnt;
-wire ControlEnd;
-wire IncrementByteCntBy2;
-wire EnableCnt;
-
-
-// A command for Sending the control frame is active (latched)
-always @ (posedge MTxClk or posedge TxReset)
-begin
- if(TxReset)
- WillSendControlFrame <= 1'b0;
- else
- if(TxCtrlEndFrm & CtrlMux)
- WillSendControlFrame <= 1'b0;
- else
- if(TPauseRq & TxFlow)
- WillSendControlFrame <= 1'b1;
-end
-
-
-// Generation of the transmit control packet start frame
-always @ (posedge MTxClk or posedge TxReset)
-begin
- if(TxReset)
- TxCtrlStartFrm <= 1'b0;
- else
- if(TxUsedDataIn_q & CtrlMux)
- TxCtrlStartFrm <= 1'b0;
- else
- if(WillSendControlFrame & ~TxUsedDataOut & (TxDoneIn | TxAbortIn | TxStartFrmIn | (~TxUsedDataOutDetected)))
- TxCtrlStartFrm <= 1'b1;
-end
-
-
-
-// Generation of the transmit control packet end frame
-always @ (posedge MTxClk or posedge TxReset)
-begin
- if(TxReset)
- TxCtrlEndFrm <= 1'b0;
- else
- if(ControlEnd | ControlEnd_q)
- TxCtrlEndFrm <= 1'b1;
- else
- TxCtrlEndFrm <= 1'b0;
-end
-
-
-// Generation of the multiplexer signal (controls muxes for switching between
-// normal and control packets)
-always @ (posedge MTxClk or posedge TxReset)
-begin
- if(TxReset)
- CtrlMux <= 1'b0;
- else
- if(WillSendControlFrame & ~TxUsedDataOut)
- CtrlMux <= 1'b1;
- else
- if(TxDoneIn)
- CtrlMux <= 1'b0;
-end
-
-
-
-// Generation of the Sending Control Frame signal (enables padding and CRC)
-always @ (posedge MTxClk or posedge TxReset)
-begin
- if(TxReset)
- SendingCtrlFrm <= 1'b0;
- else
- if(WillSendControlFrame & TxCtrlStartFrm)
- SendingCtrlFrm <= 1'b1;
- else
- if(TxDoneIn)
- SendingCtrlFrm <= 1'b0;
-end
-
-
-always @ (posedge MTxClk or posedge TxReset)
-begin
- if(TxReset)
- TxUsedDataIn_q <= 1'b0;
- else
- TxUsedDataIn_q <= TxUsedDataIn;
-end
-
-
-
-// Generation of the signal that will block sending the Done signal to the eth_wishbone module
-// While sending the control frame
-always @ (posedge MTxClk or posedge TxReset)
-begin
- if(TxReset)
- BlockTxDone <= 1'b0;
- else
- if(TxCtrlStartFrm)
- BlockTxDone <= 1'b1;
- else
- if(TxStartFrmIn)
- BlockTxDone <= 1'b0;
-end
-
-
-always @ (posedge MTxClk)
-begin
- ControlEnd_q <= ControlEnd;
- TxCtrlStartFrm_q <= TxCtrlStartFrm;
-end
-
-
-assign IncrementDlyCrcCnt = CtrlMux & TxUsedDataIn & ~DlyCrcCnt[2];
-
-
-// Delayed CRC counter
-always @ (posedge MTxClk or posedge TxReset)
-begin
- if(TxReset)
- DlyCrcCnt <= 4'h0;
- else
- if(ResetByteCnt)
- DlyCrcCnt <= 4'h0;
- else
- if(IncrementDlyCrcCnt)
- DlyCrcCnt <= DlyCrcCnt + 1'b1;
-end
-
-
-assign ResetByteCnt = TxReset | (~TxCtrlStartFrm & (TxDoneIn | TxAbortIn));
-assign IncrementByteCnt = CtrlMux & (TxCtrlStartFrm & ~TxCtrlStartFrm_q & ~TxUsedDataIn | TxUsedDataIn & ~ControlEnd);
-assign IncrementByteCntBy2 = CtrlMux & TxCtrlStartFrm & (~TxCtrlStartFrm_q) & TxUsedDataIn; // When TxUsedDataIn and CtrlMux are set at the same time
-
-assign EnableCnt = (~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0]));
-// Byte counter
-always @ (posedge MTxClk or posedge TxReset)
-begin
- if(TxReset)
- ByteCnt <= 6'h0;
- else
- if(ResetByteCnt)
- ByteCnt <= 6'h0;
- else
- if(IncrementByteCntBy2 & EnableCnt)
- ByteCnt <= (ByteCnt[5:0] ) + 2'h2;
- else
- if(IncrementByteCnt & EnableCnt)
- ByteCnt <= (ByteCnt[5:0] ) + 1'b1;
-end
-
-
-assign ControlEnd = ByteCnt[5:0] == 6'h22;
-
-
-// Control data generation (goes to the TxEthMAC module)
-always @ (ByteCnt or DlyCrcEn or MAC or TxPauseTV or DlyCrcCnt)
-begin
- case(ByteCnt)
- 6'h0: if(~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0]))
- MuxedCtrlData[7:0] = 8'h01; // Reserved Multicast Address
- else
- MuxedCtrlData[7:0] = 8'h0;
- 6'h2: MuxedCtrlData[7:0] = 8'h80;
- 6'h4: MuxedCtrlData[7:0] = 8'hC2;
- 6'h6: MuxedCtrlData[7:0] = 8'h00;
- 6'h8: MuxedCtrlData[7:0] = 8'h00;
- 6'hA: MuxedCtrlData[7:0] = 8'h01;
- 6'hC: MuxedCtrlData[7:0] = MAC[47:40];
- 6'hE: MuxedCtrlData[7:0] = MAC[39:32];
- 6'h10: MuxedCtrlData[7:0] = MAC[31:24];
- 6'h12: MuxedCtrlData[7:0] = MAC[23:16];
- 6'h14: MuxedCtrlData[7:0] = MAC[15:8];
- 6'h16: MuxedCtrlData[7:0] = MAC[7:0];
- 6'h18: MuxedCtrlData[7:0] = 8'h88; // Type/Length
- 6'h1A: MuxedCtrlData[7:0] = 8'h08;
- 6'h1C: MuxedCtrlData[7:0] = 8'h00; // Opcode
- 6'h1E: MuxedCtrlData[7:0] = 8'h01;
- 6'h20: MuxedCtrlData[7:0] = TxPauseTV[15:8]; // Pause timer value
- 6'h22: MuxedCtrlData[7:0] = TxPauseTV[7:0];
- default: MuxedCtrlData[7:0] = 8'h0;
- endcase
-end
-
-
-// Latched Control data
-always @ (posedge MTxClk or posedge TxReset)
-begin
- if(TxReset)
- ControlData[7:0] <= 8'h0;
- else
- if(~ByteCnt[0])
- ControlData[7:0] <= MuxedCtrlData[7:0];
-end
-
-
-
-endmodule
rtl/verilog/eth/eth_transmitcontrol.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: rtl/verilog/eth/eth_macstatus.v
===================================================================
--- rtl/verilog/eth/eth_macstatus.v (revision 408)
+++ rtl/verilog/eth/eth_macstatus.v (nonexistent)
@@ -1,425 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_macstatus.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// ////
-//// All additional information is available in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001, 2002 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.16 2005/02/21 10:42:11 igorm
-// Defer indication fixed.
-//
-// Revision 1.15 2003/01/30 13:28:19 tadejm
-// Defer indication changed.
-//
-// Revision 1.14 2002/11/22 01:57:06 mohor
-// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
-// synchronized.
-//
-// Revision 1.13 2002/11/13 22:30:58 tadejm
-// Late collision is reported only when not in the full duplex.
-// Sample is taken (for status) as soon as MRxDV is not valid (regardless
-// of the received byte cnt).
-//
-// Revision 1.12 2002/09/12 14:50:16 mohor
-// CarrierSenseLost bug fixed when operating in full duplex mode.
-//
-// Revision 1.11 2002/09/04 18:38:03 mohor
-// CarrierSenseLost status is not set when working in loopback mode.
-//
-// Revision 1.10 2002/07/25 18:17:46 mohor
-// InvalidSymbol generation changed.
-//
-// Revision 1.9 2002/04/22 13:51:44 mohor
-// Short frame and ReceivedLengthOK were not detected correctly.
-//
-// Revision 1.8 2002/02/18 10:40:17 mohor
-// Small fixes.
-//
-// Revision 1.7 2002/02/15 17:07:39 mohor
-// Status was not written correctly when frames were discarted because of
-// address mismatch.
-//
-// Revision 1.6 2002/02/11 09:18:21 mohor
-// Tx status is written back to the BD.
-//
-// Revision 1.5 2002/02/08 16:21:54 mohor
-// Rx status is written back to the BD.
-//
-// Revision 1.4 2002/01/23 10:28:16 mohor
-// Link in the header changed.
-//
-// Revision 1.3 2001/10/19 08:43:51 mohor
-// eth_timescale.v changed to timescale.v This is done because of the
-// simulation of the few cores in a one joined project.
-//
-// Revision 1.2 2001/09/11 14:17:00 mohor
-// Few little NCSIM warnings fixed.
-//
-// Revision 1.1 2001/08/06 14:44:29 mohor
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
-// Include files fixed to contain no path.
-// File names and module names changed ta have a eth_ prologue in the name.
-// File eth_timescale.v is used to define timescale
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
-// and Mdo_OE. The bidirectional signal must be created on the top level. This
-// is done due to the ASIC tools.
-//
-// Revision 1.1 2001/07/30 21:23:42 mohor
-// Directory structure changed. Files checked and joind together.
-//
-//
-//
-//
-//
-
-`include "timescale.v"
-
-
-module eth_macstatus(
- MRxClk, Reset, ReceivedLengthOK, ReceiveEnd, ReceivedPacketGood, RxCrcError,
- MRxErr, MRxDV, RxStateSFD, RxStateData, RxStatePreamble, RxStateIdle, Transmitting,
- RxByteCnt, RxByteCntEq0, RxByteCntGreat2, RxByteCntMaxFrame,
- InvalidSymbol, MRxD, LatchedCrcError, Collision, CollValid, RxLateCollision,
- r_RecSmall, r_MinFL, r_MaxFL, ShortFrame, DribbleNibble, ReceivedPacketTooBig, r_HugEn,
- LoadRxStatus, StartTxDone, StartTxAbort, RetryCnt, RetryCntLatched, MTxClk, MaxCollisionOccured,
- RetryLimit, LateCollision, LateCollLatched, DeferIndication, DeferLatched, RstDeferLatched, TxStartFrm,
- StatePreamble, StateData, CarrierSense, CarrierSenseLost, TxUsedData, LatchedMRxErr, Loopback,
- r_FullD
- );
-
-
-
-parameter Tp = 1;
-
-
-input MRxClk;
-input Reset;
-input RxCrcError;
-input MRxErr;
-input MRxDV;
-
-input RxStateSFD;
-input [1:0] RxStateData;
-input RxStatePreamble;
-input RxStateIdle;
-input Transmitting;
-input [15:0] RxByteCnt;
-input RxByteCntEq0;
-input RxByteCntGreat2;
-input RxByteCntMaxFrame;
-input [3:0] MRxD;
-input Collision;
-input [5:0] CollValid;
-input r_RecSmall;
-input [15:0] r_MinFL;
-input [15:0] r_MaxFL;
-input r_HugEn;
-input StartTxDone;
-input StartTxAbort;
-input [3:0] RetryCnt;
-input MTxClk;
-input MaxCollisionOccured;
-input LateCollision;
-input DeferIndication;
-input TxStartFrm;
-input StatePreamble;
-input [1:0] StateData;
-input CarrierSense;
-input TxUsedData;
-input Loopback;
-input r_FullD;
-
-
-output ReceivedLengthOK;
-output ReceiveEnd;
-output ReceivedPacketGood;
-output InvalidSymbol;
-output LatchedCrcError;
-output RxLateCollision;
-output ShortFrame;
-output DribbleNibble;
-output ReceivedPacketTooBig;
-output LoadRxStatus;
-output [3:0] RetryCntLatched;
-output RetryLimit;
-output LateCollLatched;
-output DeferLatched;
-input RstDeferLatched;
-output CarrierSenseLost;
-output LatchedMRxErr;
-
-
-reg ReceiveEnd;
-
-reg LatchedCrcError;
-reg LatchedMRxErr;
-reg LoadRxStatus;
-reg InvalidSymbol;
-reg [3:0] RetryCntLatched;
-reg RetryLimit;
-reg LateCollLatched;
-reg DeferLatched;
-reg CarrierSenseLost;
-
-wire TakeSample;
-wire SetInvalidSymbol; // Invalid symbol was received during reception in 100Mbps
-
-// Crc error
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- LatchedCrcError <= 1'b0;
- else
- if(RxStateSFD)
- LatchedCrcError <= 1'b0;
- else
- if(RxStateData[0])
- LatchedCrcError <= RxCrcError & ~RxByteCntEq0;
-end
-
-
-// LatchedMRxErr
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- LatchedMRxErr <= 1'b0;
- else
- if(MRxErr & MRxDV & (RxStatePreamble | RxStateSFD | (|RxStateData) | RxStateIdle & ~Transmitting))
- LatchedMRxErr <= 1'b1;
- else
- LatchedMRxErr <= 1'b0;
-end
-
-
-// ReceivedPacketGood
-assign ReceivedPacketGood = ~LatchedCrcError;
-
-
-// ReceivedLengthOK
-assign ReceivedLengthOK = RxByteCnt[15:0] >= r_MinFL[15:0] & RxByteCnt[15:0] <= r_MaxFL[15:0];
-
-
-
-
-
-// Time to take a sample
-//assign TakeSample = |RxStateData & ~MRxDV & RxByteCntGreat2 |
-assign TakeSample = (|RxStateData) & (~MRxDV) |
- RxStateData[0] & MRxDV & RxByteCntMaxFrame;
-
-
-// LoadRxStatus
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- LoadRxStatus <= 1'b0;
- else
- LoadRxStatus <= TakeSample;
-end
-
-
-
-// ReceiveEnd
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- ReceiveEnd <= 1'b0;
- else
- ReceiveEnd <= LoadRxStatus;
-end
-
-
-// Invalid Symbol received during 100Mbps mode
-assign SetInvalidSymbol = MRxDV & MRxErr & MRxD[3:0] == 4'he;
-
-
-// InvalidSymbol
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- InvalidSymbol <= 1'b0;
- else
- if(LoadRxStatus & ~SetInvalidSymbol)
- InvalidSymbol <= 1'b0;
- else
- if(SetInvalidSymbol)
- InvalidSymbol <= 1'b1;
-end
-
-
-// Late Collision
-
-reg RxLateCollision;
-reg RxColWindow;
-// Collision Window
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- RxLateCollision <= 1'b0;
- else
- if(LoadRxStatus)
- RxLateCollision <= 1'b0;
- else
- if(Collision & (~r_FullD) & (~RxColWindow | r_RecSmall))
- RxLateCollision <= 1'b1;
-end
-
-// Collision Window
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- RxColWindow <= 1'b1;
- else
- if(~Collision & RxByteCnt[5:0] == CollValid[5:0] & RxStateData[1])
- RxColWindow <= 1'b0;
- else
- if(RxStateIdle)
- RxColWindow <= 1'b1;
-end
-
-
-// ShortFrame
-reg ShortFrame;
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- ShortFrame <= 1'b0;
- else
- if(LoadRxStatus)
- ShortFrame <= 1'b0;
- else
- if(TakeSample)
- ShortFrame <= RxByteCnt[15:0] < r_MinFL[15:0];
-end
-
-
-// DribbleNibble
-reg DribbleNibble;
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- DribbleNibble <= 1'b0;
- else
- if(RxStateSFD)
- DribbleNibble <= 1'b0;
- else
- if(~MRxDV & RxStateData[1])
- DribbleNibble <= 1'b1;
-end
-
-
-reg ReceivedPacketTooBig;
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- ReceivedPacketTooBig <= 1'b0;
- else
- if(LoadRxStatus)
- ReceivedPacketTooBig <= 1'b0;
- else
- if(TakeSample)
- ReceivedPacketTooBig <= ~r_HugEn & RxByteCnt[15:0] > r_MaxFL[15:0];
-end
-
-
-
-// Latched Retry counter for tx status
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- RetryCntLatched <= 4'h0;
- else
- if(StartTxDone | StartTxAbort)
- RetryCntLatched <= RetryCnt;
-end
-
-
-// Latched Retransmission limit
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- RetryLimit <= 1'h0;
- else
- if(StartTxDone | StartTxAbort)
- RetryLimit <= MaxCollisionOccured;
-end
-
-
-// Latched Late Collision
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- LateCollLatched <= 1'b0;
- else
- if(StartTxDone | StartTxAbort)
- LateCollLatched <= LateCollision;
-end
-
-
-
-// Latched Defer state
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- DeferLatched <= 1'b0;
- else
- if(DeferIndication)
- DeferLatched <= 1'b1;
- else
- if(RstDeferLatched)
- DeferLatched <= 1'b0;
-end
-
-
-// CarrierSenseLost
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- CarrierSenseLost <= 1'b0;
- else
- if((StatePreamble | (|StateData)) & ~CarrierSense & ~Loopback & ~Collision & ~r_FullD)
- CarrierSenseLost <= 1'b1;
- else
- if(TxStartFrm)
- CarrierSenseLost <= 1'b0;
-end
-
-
-endmodule
rtl/verilog/eth/eth_macstatus.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: rtl/verilog/eth/eth_crc.v
===================================================================
--- rtl/verilog/eth/eth_crc.v (revision 408)
+++ rtl/verilog/eth/eth_crc.v (nonexistent)
@@ -1,145 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_crc.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// - Novan Hartadi (novan@vlsi.itb.ac.id) ////
-//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.2 2001/10/19 08:43:51 mohor
-// eth_timescale.v changed to timescale.v This is done because of the
-// simulation of the few cores in a one joined project.
-//
-// Revision 1.1 2001/08/06 14:44:29 mohor
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
-// Include files fixed to contain no path.
-// File names and module names changed ta have a eth_ prologue in the name.
-// File eth_timescale.v is used to define timescale
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
-// and Mdo_OE. The bidirectional signal must be created on the top level. This
-// is done due to the ASIC tools.
-//
-// Revision 1.1 2001/07/30 21:23:42 mohor
-// Directory structure changed. Files checked and joind together.
-//
-// Revision 1.3 2001/06/19 18:16:40 mohor
-// TxClk changed to MTxClk (as discribed in the documentation).
-// Crc changed so only one file can be used instead of two.
-//
-// Revision 1.2 2001/06/19 10:38:07 mohor
-// Minor changes in header.
-//
-// Revision 1.1 2001/06/19 10:27:57 mohor
-// TxEthMAC initial release.
-//
-//
-//
-
-
-`include "timescale.v"
-
-module eth_crc (Clk, Reset, Data, Enable, Initialize, Crc, CrcError);
-
-
-parameter Tp = 1;
-
-input Clk;
-input Reset;
-input [3:0] Data;
-input Enable;
-input Initialize;
-
-output [31:0] Crc;
-output CrcError;
-
-reg [31:0] Crc;
-
-wire [31:0] CrcNext;
-
-
-assign CrcNext[0] = Enable & (Data[0] ^ Crc[28]);
-assign CrcNext[1] = Enable & (Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29]);
-assign CrcNext[2] = Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30]);
-assign CrcNext[3] = Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31]);
-assign CrcNext[4] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[0];
-assign CrcNext[5] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[1];
-assign CrcNext[6] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[ 2];
-assign CrcNext[7] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[3];
-assign CrcNext[8] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[4];
-assign CrcNext[9] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[5];
-assign CrcNext[10] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[6];
-assign CrcNext[11] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[7];
-assign CrcNext[12] = (Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30])) ^ Crc[8];
-assign CrcNext[13] = (Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31])) ^ Crc[9];
-assign CrcNext[14] = (Enable & (Data[3] ^ Data[2] ^ Crc[30] ^ Crc[31])) ^ Crc[10];
-assign CrcNext[15] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[11];
-assign CrcNext[16] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[12];
-assign CrcNext[17] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[13];
-assign CrcNext[18] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[14];
-assign CrcNext[19] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[15];
-assign CrcNext[20] = Crc[16];
-assign CrcNext[21] = Crc[17];
-assign CrcNext[22] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[18];
-assign CrcNext[23] = (Enable & (Data[1] ^ Data[0] ^ Crc[29] ^ Crc[28])) ^ Crc[19];
-assign CrcNext[24] = (Enable & (Data[2] ^ Data[1] ^ Crc[30] ^ Crc[29])) ^ Crc[20];
-assign CrcNext[25] = (Enable & (Data[3] ^ Data[2] ^ Crc[31] ^ Crc[30])) ^ Crc[21];
-assign CrcNext[26] = (Enable & (Data[3] ^ Data[0] ^ Crc[31] ^ Crc[28])) ^ Crc[22];
-assign CrcNext[27] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[23];
-assign CrcNext[28] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[24];
-assign CrcNext[29] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[25];
-assign CrcNext[30] = Crc[26];
-assign CrcNext[31] = Crc[27];
-
-
-always @ (posedge Clk or posedge Reset)
-begin
- if (Reset)
- Crc <= 32'hffffffff;
- else
- if(Initialize)
- Crc <= 32'hffffffff;
- else
- Crc <= CrcNext;
-end
-
-assign CrcError = Crc[31:0] != 32'hc704dd7b; // CRC not equal to magic number
-
-endmodule
rtl/verilog/eth/eth_crc.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: rtl/verilog/eth/eth_registers.v
===================================================================
--- rtl/verilog/eth/eth_registers.v (revision 408)
+++ rtl/verilog/eth/eth_registers.v (nonexistent)
@@ -1,1188 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_registers.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001, 2002 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.28 2004/04/26 15:26:23 igorm
-// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
-// previous update of the core.
-// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
-// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
-// register. (thanks to Mathias and Torbjorn)
-// - Multicast reception was fixed. Thanks to Ulrich Gries
-//
-// Revision 1.27 2004/04/26 11:42:17 igorm
-// TX_BD_NUM_Wr error fixed. Error was entered with the last check-in.
-//
-// Revision 1.26 2003/11/12 18:24:59 tadejm
-// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
-//
-// Revision 1.25 2003/04/18 16:26:25 mohor
-// RxBDAddress was updated also when value to r_TxBDNum was written with
-// greater value than allowed.
-//
-// Revision 1.24 2002/11/22 01:57:06 mohor
-// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
-// synchronized.
-//
-// Revision 1.23 2002/11/19 18:13:49 mohor
-// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
-//
-// Revision 1.22 2002/11/14 18:37:20 mohor
-// r_Rst signal does not reset any module any more and is removed from the design.
-//
-// Revision 1.21 2002/09/10 10:35:23 mohor
-// Ethernet debug registers removed.
-//
-// Revision 1.20 2002/09/04 18:40:25 mohor
-// ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
-// the control frames connected.
-//
-// Revision 1.19 2002/08/19 16:01:40 mohor
-// Only values smaller or equal to 0x80 can be written to TX_BD_NUM register.
-// r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.
-//
-// Revision 1.18 2002/08/16 22:28:23 mohor
-// Syntax error fixed.
-//
-// Revision 1.17 2002/08/16 22:23:03 mohor
-// Syntax error fixed.
-//
-// Revision 1.16 2002/08/16 22:14:22 mohor
-// Synchronous reset added to all registers. Defines used for width. r_MiiMRst
-// changed from bit position 10 to 9.
-//
-// Revision 1.15 2002/08/14 18:26:37 mohor
-// LinkFailRegister is reflecting the status of the PHY's link fail status bit.
-//
-// Revision 1.14 2002/04/22 14:03:44 mohor
-// Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
-// or not.
-//
-// Revision 1.13 2002/02/26 16:18:09 mohor
-// Reset values are passed to registers through parameters
-//
-// Revision 1.12 2002/02/17 13:23:42 mohor
-// Define missmatch fixed.
-//
-// Revision 1.11 2002/02/16 14:03:44 mohor
-// Registered trimmed. Unused registers removed.
-//
-// Revision 1.10 2002/02/15 11:08:25 mohor
-// File format fixed a bit.
-//
-// Revision 1.9 2002/02/14 20:19:41 billditt
-// Modified for Address Checking,
-// addition of eth_addrcheck.v
-//
-// Revision 1.8 2002/02/12 17:01:19 mohor
-// HASH0 and HASH1 registers added.
-
-// Revision 1.7 2002/01/23 10:28:16 mohor
-// Link in the header changed.
-//
-// Revision 1.6 2001/12/05 15:00:16 mohor
-// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
-// instead of the number of RX descriptors).
-//
-// Revision 1.5 2001/12/05 10:22:19 mohor
-// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
-//
-// Revision 1.4 2001/10/19 08:43:51 mohor
-// eth_timescale.v changed to timescale.v This is done because of the
-// simulation of the few cores in a one joined project.
-//
-// Revision 1.3 2001/10/18 12:07:11 mohor
-// Status signals changed, Adress decoding changed, interrupt controller
-// added.
-//
-// Revision 1.2 2001/09/24 15:02:56 mohor
-// Defines changed (All precede with ETH_). Small changes because some
-// tools generate warnings when two operands are together. Synchronization
-// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
-// demands).
-//
-// Revision 1.1 2001/08/06 14:44:29 mohor
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
-// Include files fixed to contain no path.
-// File names and module names changed ta have a eth_ prologue in the name.
-// File eth_timescale.v is used to define timescale
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
-// and Mdo_OE. The bidirectional signal must be created on the top level. This
-// is done due to the ASIC tools.
-//
-// Revision 1.2 2001/08/02 09:25:31 mohor
-// Unconnected signals are now connected.
-//
-// Revision 1.1 2001/07/30 21:23:42 mohor
-// Directory structure changed. Files checked and joind together.
-//
-//
-//
-//
-//
-//
-
-`include "eth_defines.v"
-`include "timescale.v"
-
-
-module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
- r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
- r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG,
- r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn,
- TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
- r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
- r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
- r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
- r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
- LinkFail, r_MAC, WCtrlDataStart, RStatStart,
- UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, int_o,
- r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm,
- dbg_dat, // jb
- StartTxDone, TxClk, RxClk, SetPauseTimer
- );
-
-parameter Tp = 1;
-
-input [31:0] DataIn;
-input [7:0] Address;
-
-input Rw;
-input [3:0] Cs;
-input Clk;
-input Reset;
-
-input WCtrlDataStart;
-input RStatStart;
-
-input UpdateMIIRX_DATAReg;
-input [15:0] Prsd;
-
-output [31:0] DataOut;
-reg [31:0] DataOut;
-
-output r_RecSmall;
-output r_Pad;
-output r_HugEn;
-output r_CrcEn;
-output r_DlyCrcEn;
-output r_FullD;
-output r_ExDfrEn;
-output r_NoBckof;
-output r_LoopBck;
-output r_IFG;
-output r_Pro;
-output r_Iam;
-output r_Bro;
-output r_NoPre;
-output r_TxEn;
-output r_RxEn;
-output [31:0] r_HASH0;
-output [31:0] r_HASH1;
-
-input TxB_IRQ;
-input TxE_IRQ;
-input RxB_IRQ;
-input RxE_IRQ;
-input Busy_IRQ;
-
-output [6:0] r_IPGT;
-
-output [6:0] r_IPGR1;
-
-output [6:0] r_IPGR2;
-
-output [15:0] r_MinFL;
-output [15:0] r_MaxFL;
-
-output [3:0] r_MaxRet;
-output [5:0] r_CollValid;
-
-output r_TxFlow;
-output r_RxFlow;
-output r_PassAll;
-
-output r_MiiNoPre;
-output [7:0] r_ClkDiv;
-
-output r_WCtrlData;
-output r_RStat;
-output r_ScanStat;
-
-output [4:0] r_RGAD;
-output [4:0] r_FIAD;
-
-output [15:0]r_CtrlData;
-
-
-input NValid_stat;
-input Busy_stat;
-input LinkFail;
-
-output [47:0]r_MAC;
-output [7:0] r_TxBDNum;
-output int_o;
-output [15:0]r_TxPauseTV;
-output r_TxPauseRq;
-input RstTxPauseRq;
-input TxCtrlEndFrm;
-input StartTxDone;
-input TxClk;
-input RxClk;
-input SetPauseTimer;
-
-input [31:0] dbg_dat; // debug data input - JB
-
-
-reg irq_txb;
-reg irq_txe;
-reg irq_rxb;
-reg irq_rxe;
-reg irq_busy;
-reg irq_txc;
-reg irq_rxc;
-
-reg SetTxCIrq_txclk;
-reg SetTxCIrq_sync1, SetTxCIrq_sync2, SetTxCIrq_sync3;
-reg SetTxCIrq;
-reg ResetTxCIrq_sync1, ResetTxCIrq_sync2;
-
-reg SetRxCIrq_rxclk;
-reg SetRxCIrq_sync1, SetRxCIrq_sync2, SetRxCIrq_sync3;
-reg SetRxCIrq;
-reg ResetRxCIrq_sync1;
-reg ResetRxCIrq_sync2;
-reg ResetRxCIrq_sync3;
-
-wire [3:0] Write = Cs & {4{Rw}};
-wire Read = (|Cs) & ~Rw;
-
-wire MODER_Sel = (Address == `ETH_MODER_ADR );
-wire INT_SOURCE_Sel = (Address == `ETH_INT_SOURCE_ADR );
-wire INT_MASK_Sel = (Address == `ETH_INT_MASK_ADR );
-wire IPGT_Sel = (Address == `ETH_IPGT_ADR );
-wire IPGR1_Sel = (Address == `ETH_IPGR1_ADR );
-wire IPGR2_Sel = (Address == `ETH_IPGR2_ADR );
-wire PACKETLEN_Sel = (Address == `ETH_PACKETLEN_ADR );
-wire COLLCONF_Sel = (Address == `ETH_COLLCONF_ADR );
-
-wire CTRLMODER_Sel = (Address == `ETH_CTRLMODER_ADR );
-wire MIIMODER_Sel = (Address == `ETH_MIIMODER_ADR );
-wire MIICOMMAND_Sel = (Address == `ETH_MIICOMMAND_ADR );
-wire MIIADDRESS_Sel = (Address == `ETH_MIIADDRESS_ADR );
-wire MIITX_DATA_Sel = (Address == `ETH_MIITX_DATA_ADR );
-wire MAC_ADDR0_Sel = (Address == `ETH_MAC_ADDR0_ADR );
-wire MAC_ADDR1_Sel = (Address == `ETH_MAC_ADDR1_ADR );
-wire HASH0_Sel = (Address == `ETH_HASH0_ADR );
-wire HASH1_Sel = (Address == `ETH_HASH1_ADR );
-wire TXCTRL_Sel = (Address == `ETH_TX_CTRL_ADR );
-wire RXCTRL_Sel = (Address == `ETH_RX_CTRL_ADR );
-wire DBG_REG_Sel = (Address == `ETH_DBG_ADR ); // JB
-wire TX_BD_NUM_Sel = (Address == `ETH_TX_BD_NUM_ADR );
-
-
-
-wire [2:0] MODER_Wr;
-wire [0:0] INT_SOURCE_Wr;
-wire [0:0] INT_MASK_Wr;
-wire [0:0] IPGT_Wr;
-wire [0:0] IPGR1_Wr;
-wire [0:0] IPGR2_Wr;
-wire [3:0] PACKETLEN_Wr;
-wire [2:0] COLLCONF_Wr;
-wire [0:0] CTRLMODER_Wr;
-wire [1:0] MIIMODER_Wr;
-wire [0:0] MIICOMMAND_Wr;
-wire [1:0] MIIADDRESS_Wr;
-wire [1:0] MIITX_DATA_Wr;
-wire MIIRX_DATA_Wr;
-wire [3:0] MAC_ADDR0_Wr;
-wire [1:0] MAC_ADDR1_Wr;
-wire [3:0] HASH0_Wr;
-wire [3:0] HASH1_Wr;
-wire [2:0] TXCTRL_Wr;
-wire [0:0] TX_BD_NUM_Wr;
-
-assign MODER_Wr[0] = Write[0] & MODER_Sel;
-assign MODER_Wr[1] = Write[1] & MODER_Sel;
-assign MODER_Wr[2] = Write[2] & MODER_Sel;
-assign INT_SOURCE_Wr[0] = Write[0] & INT_SOURCE_Sel;
-assign INT_MASK_Wr[0] = Write[0] & INT_MASK_Sel;
-assign IPGT_Wr[0] = Write[0] & IPGT_Sel;
-assign IPGR1_Wr[0] = Write[0] & IPGR1_Sel;
-assign IPGR2_Wr[0] = Write[0] & IPGR2_Sel;
-assign PACKETLEN_Wr[0] = Write[0] & PACKETLEN_Sel;
-assign PACKETLEN_Wr[1] = Write[1] & PACKETLEN_Sel;
-assign PACKETLEN_Wr[2] = Write[2] & PACKETLEN_Sel;
-assign PACKETLEN_Wr[3] = Write[3] & PACKETLEN_Sel;
-assign COLLCONF_Wr[0] = Write[0] & COLLCONF_Sel;
-assign COLLCONF_Wr[1] = 1'b0; // Not used
-assign COLLCONF_Wr[2] = Write[2] & COLLCONF_Sel;
-
-assign CTRLMODER_Wr[0] = Write[0] & CTRLMODER_Sel;
-assign MIIMODER_Wr[0] = Write[0] & MIIMODER_Sel;
-assign MIIMODER_Wr[1] = Write[1] & MIIMODER_Sel;
-assign MIICOMMAND_Wr[0] = Write[0] & MIICOMMAND_Sel;
-assign MIIADDRESS_Wr[0] = Write[0] & MIIADDRESS_Sel;
-assign MIIADDRESS_Wr[1] = Write[1] & MIIADDRESS_Sel;
-assign MIITX_DATA_Wr[0] = Write[0] & MIITX_DATA_Sel;
-assign MIITX_DATA_Wr[1] = Write[1] & MIITX_DATA_Sel;
-assign MIIRX_DATA_Wr = UpdateMIIRX_DATAReg;
-assign MAC_ADDR0_Wr[0] = Write[0] & MAC_ADDR0_Sel;
-assign MAC_ADDR0_Wr[1] = Write[1] & MAC_ADDR0_Sel;
-assign MAC_ADDR0_Wr[2] = Write[2] & MAC_ADDR0_Sel;
-assign MAC_ADDR0_Wr[3] = Write[3] & MAC_ADDR0_Sel;
-assign MAC_ADDR1_Wr[0] = Write[0] & MAC_ADDR1_Sel;
-assign MAC_ADDR1_Wr[1] = Write[1] & MAC_ADDR1_Sel;
-assign HASH0_Wr[0] = Write[0] & HASH0_Sel;
-assign HASH0_Wr[1] = Write[1] & HASH0_Sel;
-assign HASH0_Wr[2] = Write[2] & HASH0_Sel;
-assign HASH0_Wr[3] = Write[3] & HASH0_Sel;
-assign HASH1_Wr[0] = Write[0] & HASH1_Sel;
-assign HASH1_Wr[1] = Write[1] & HASH1_Sel;
-assign HASH1_Wr[2] = Write[2] & HASH1_Sel;
-assign HASH1_Wr[3] = Write[3] & HASH1_Sel;
-assign TXCTRL_Wr[0] = Write[0] & TXCTRL_Sel;
-assign TXCTRL_Wr[1] = Write[1] & TXCTRL_Sel;
-assign TXCTRL_Wr[2] = Write[2] & TXCTRL_Sel;
-assign TX_BD_NUM_Wr[0] = Write[0] & TX_BD_NUM_Sel & (DataIn<='h80);
-
-
-
-wire [31:0] MODEROut;
-wire [31:0] INT_SOURCEOut;
-wire [31:0] INT_MASKOut;
-wire [31:0] IPGTOut;
-wire [31:0] IPGR1Out;
-wire [31:0] IPGR2Out;
-wire [31:0] PACKETLENOut;
-wire [31:0] COLLCONFOut;
-wire [31:0] CTRLMODEROut;
-wire [31:0] MIIMODEROut;
-wire [31:0] MIICOMMANDOut;
-wire [31:0] MIIADDRESSOut;
-wire [31:0] MIITX_DATAOut;
-wire [31:0] MIIRX_DATAOut;
-wire [31:0] MIISTATUSOut;
-wire [31:0] MAC_ADDR0Out;
-wire [31:0] MAC_ADDR1Out;
-wire [31:0] TX_BD_NUMOut;
-wire [31:0] HASH0Out;
-wire [31:0] HASH1Out;
-wire [31:0] TXCTRLOut;
-wire [31:0] DBGOut; // JB
-
-// MODER Register
-eth_register #(`ETH_MODER_WIDTH_0, `ETH_MODER_DEF_0) MODER_0
- (
- .DataIn (DataIn[`ETH_MODER_WIDTH_0 - 1:0]),
- .DataOut (MODEROut[`ETH_MODER_WIDTH_0 - 1:0]),
- .Write (MODER_Wr[0]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (1'b0)
- );
-eth_register #(`ETH_MODER_WIDTH_1, `ETH_MODER_DEF_1) MODER_1
- (
- .DataIn (DataIn[`ETH_MODER_WIDTH_1 + 7:8]),
- .DataOut (MODEROut[`ETH_MODER_WIDTH_1 + 7:8]),
- .Write (MODER_Wr[1]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (1'b0)
- );
-eth_register #(`ETH_MODER_WIDTH_2, `ETH_MODER_DEF_2) MODER_2
- (
- .DataIn (DataIn[`ETH_MODER_WIDTH_2 + 15:16]),
- .DataOut (MODEROut[`ETH_MODER_WIDTH_2 + 15:16]),
- .Write (MODER_Wr[2]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (1'b0)
- );
-assign MODEROut[31:`ETH_MODER_WIDTH_2 + 16] = 0;
-
-// INT_MASK Register
-eth_register #(`ETH_INT_MASK_WIDTH_0, `ETH_INT_MASK_DEF_0) INT_MASK_0
- (
- .DataIn (DataIn[`ETH_INT_MASK_WIDTH_0 - 1:0]),
- .DataOut (INT_MASKOut[`ETH_INT_MASK_WIDTH_0 - 1:0]),
- .Write (INT_MASK_Wr[0]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (1'b0)
- );
-assign INT_MASKOut[31:`ETH_INT_MASK_WIDTH_0] = 0;
-
-// IPGT Register
-eth_register #(`ETH_IPGT_WIDTH_0, `ETH_IPGT_DEF_0) IPGT_0
- (
- .DataIn (DataIn[`ETH_IPGT_WIDTH_0 - 1:0]),
- .DataOut (IPGTOut[`ETH_IPGT_WIDTH_0 - 1:0]),
- .Write (IPGT_Wr[0]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (1'b0)
- );
-assign IPGTOut[31:`ETH_IPGT_WIDTH_0] = 0;
-
-// IPGR1 Register
-eth_register #(`ETH_IPGR1_WIDTH_0, `ETH_IPGR1_DEF_0) IPGR1_0
- (
- .DataIn (DataIn[`ETH_IPGR1_WIDTH_0 - 1:0]),
- .DataOut (IPGR1Out[`ETH_IPGR1_WIDTH_0 - 1:0]),
- .Write (IPGR1_Wr[0]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (1'b0)
- );
-assign IPGR1Out[31:`ETH_IPGR1_WIDTH_0] = 0;
-
-// IPGR2 Register
-eth_register #(`ETH_IPGR2_WIDTH_0, `ETH_IPGR2_DEF_0) IPGR2_0
- (
- .DataIn (DataIn[`ETH_IPGR2_WIDTH_0 - 1:0]),
- .DataOut (IPGR2Out[`ETH_IPGR2_WIDTH_0 - 1:0]),
- .Write (IPGR2_Wr[0]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (1'b0)
- );
-assign IPGR2Out[31:`ETH_IPGR2_WIDTH_0] = 0;
-
-// PACKETLEN Register
-eth_register #(`ETH_PACKETLEN_WIDTH_0, `ETH_PACKETLEN_DEF_0) PACKETLEN_0
- (
- .DataIn (DataIn[`ETH_PACKETLEN_WIDTH_0 - 1:0]),
- .DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_0 - 1:0]),
- .Write (PACKETLEN_Wr[0]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (1'b0)
- );
-eth_register #(`ETH_PACKETLEN_WIDTH_1, `ETH_PACKETLEN_DEF_1) PACKETLEN_1
- (
- .DataIn (DataIn[`ETH_PACKETLEN_WIDTH_1 + 7:8]),
- .DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_1 + 7:8]),
- .Write (PACKETLEN_Wr[1]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (1'b0)
- );
-eth_register #(`ETH_PACKETLEN_WIDTH_2, `ETH_PACKETLEN_DEF_2) PACKETLEN_2
- (
- .DataIn (DataIn[`ETH_PACKETLEN_WIDTH_2 + 15:16]),
- .DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_2 + 15:16]),
- .Write (PACKETLEN_Wr[2]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (1'b0)
- );
-eth_register #(`ETH_PACKETLEN_WIDTH_3, `ETH_PACKETLEN_DEF_3) PACKETLEN_3
- (
- .DataIn (DataIn[`ETH_PACKETLEN_WIDTH_3 + 23:24]),
- .DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_3 + 23:24]),
- .Write (PACKETLEN_Wr[3]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (1'b0)
- );
-
-// COLLCONF Register
-eth_register #(`ETH_COLLCONF_WIDTH_0, `ETH_COLLCONF_DEF_0) COLLCONF_0
- (
- .DataIn (DataIn[`ETH_COLLCONF_WIDTH_0 - 1:0]),
- .DataOut (COLLCONFOut[`ETH_COLLCONF_WIDTH_0 - 1:0]),
- .Write (COLLCONF_Wr[0]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (1'b0)
- );
-eth_register #(`ETH_COLLCONF_WIDTH_2, `ETH_COLLCONF_DEF_2) COLLCONF_2
- (
- .DataIn (DataIn[`ETH_COLLCONF_WIDTH_2 + 15:16]),
- .DataOut (COLLCONFOut[`ETH_COLLCONF_WIDTH_2 + 15:16]),
- .Write (COLLCONF_Wr[2]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (1'b0)
- );
-assign COLLCONFOut[15:`ETH_COLLCONF_WIDTH_0] = 0;
-assign COLLCONFOut[31:`ETH_COLLCONF_WIDTH_2 + 16] = 0;
-
-// TX_BD_NUM Register
-eth_register #(`ETH_TX_BD_NUM_WIDTH_0, `ETH_TX_BD_NUM_DEF_0) TX_BD_NUM_0
- (
- .DataIn (DataIn[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]),
- .DataOut (TX_BD_NUMOut[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]),
- .Write (TX_BD_NUM_Wr[0]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (1'b0)
- );
-assign TX_BD_NUMOut[31:`ETH_TX_BD_NUM_WIDTH_0] = 0;
-
-// CTRLMODER Register
-eth_register #(`ETH_CTRLMODER_WIDTH_0, `ETH_CTRLMODER_DEF_0) CTRLMODER_0
- (
- .DataIn (DataIn[`ETH_CTRLMODER_WIDTH_0 - 1:0]),
- .DataOut (CTRLMODEROut[`ETH_CTRLMODER_WIDTH_0 - 1:0]),
- .Write (CTRLMODER_Wr[0]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (1'b0)
- );
-assign CTRLMODEROut[31:`ETH_CTRLMODER_WIDTH_0] = 0;
-
-// MIIMODER Register
-eth_register #(`ETH_MIIMODER_WIDTH_0, `ETH_MIIMODER_DEF_0) MIIMODER_0
- (
- .DataIn (DataIn[`ETH_MIIMODER_WIDTH_0 - 1:0]),
- .DataOut (MIIMODEROut[`ETH_MIIMODER_WIDTH_0 - 1:0]),
- .Write (MIIMODER_Wr[0]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (1'b0)
- );
-eth_register #(`ETH_MIIMODER_WIDTH_1, `ETH_MIIMODER_DEF_1) MIIMODER_1
- (
- .DataIn (DataIn[`ETH_MIIMODER_WIDTH_1 + 7:8]),
- .DataOut (MIIMODEROut[`ETH_MIIMODER_WIDTH_1 + 7:8]),
- .Write (MIIMODER_Wr[1]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (1'b0)
- );
-assign MIIMODEROut[31:`ETH_MIIMODER_WIDTH_1 + 8] = 0;
-
-// MIICOMMAND Register
-eth_register #(1, 0) MIICOMMAND0
- (
- .DataIn (DataIn[0]),
- .DataOut (MIICOMMANDOut[0]),
- .Write (MIICOMMAND_Wr[0]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (1'b0)
- );
-eth_register #(1, 0) MIICOMMAND1
- (
- .DataIn (DataIn[1]),
- .DataOut (MIICOMMANDOut[1]),
- .Write (MIICOMMAND_Wr[0]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (RStatStart)
- );
-eth_register #(1, 0) MIICOMMAND2
- (
- .DataIn (DataIn[2]),
- .DataOut (MIICOMMANDOut[2]),
- .Write (MIICOMMAND_Wr[0]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (WCtrlDataStart)
- );
-assign MIICOMMANDOut[31:`ETH_MIICOMMAND_WIDTH_0] = 29'h0;
-
-// MIIADDRESSRegister
-eth_register #(`ETH_MIIADDRESS_WIDTH_0, `ETH_MIIADDRESS_DEF_0) MIIADDRESS_0
- (
- .DataIn (DataIn[`ETH_MIIADDRESS_WIDTH_0 - 1:0]),
- .DataOut (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_0 - 1:0]),
- .Write (MIIADDRESS_Wr[0]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (1'b0)
- );
-eth_register #(`ETH_MIIADDRESS_WIDTH_1, `ETH_MIIADDRESS_DEF_1) MIIADDRESS_1
- (
- .DataIn (DataIn[`ETH_MIIADDRESS_WIDTH_1 + 7:8]),
- .DataOut (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_1 + 7:8]),
- .Write (MIIADDRESS_Wr[1]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (1'b0)
- );
-assign MIIADDRESSOut[7:`ETH_MIIADDRESS_WIDTH_0] = 0;
-assign MIIADDRESSOut[31:`ETH_MIIADDRESS_WIDTH_1 + 8] = 0;
-
-// MIITX_DATA Register
-eth_register #(`ETH_MIITX_DATA_WIDTH_0, `ETH_MIITX_DATA_DEF_0) MIITX_DATA_0
- (
- .DataIn (DataIn[`ETH_MIITX_DATA_WIDTH_0 - 1:0]),
- .DataOut (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_0 - 1:0]),
- .Write (MIITX_DATA_Wr[0]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (1'b0)
- );
-eth_register #(`ETH_MIITX_DATA_WIDTH_1, `ETH_MIITX_DATA_DEF_1) MIITX_DATA_1
- (
- .DataIn (DataIn[`ETH_MIITX_DATA_WIDTH_1 + 7:8]),
- .DataOut (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_1 + 7:8]),
- .Write (MIITX_DATA_Wr[1]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (1'b0)
- );
-assign MIITX_DATAOut[31:`ETH_MIITX_DATA_WIDTH_1 + 8] = 0;
-
-// MIIRX_DATA Register
-eth_register #(`ETH_MIIRX_DATA_WIDTH, `ETH_MIIRX_DATA_DEF) MIIRX_DATA
- (
- .DataIn (Prsd[`ETH_MIIRX_DATA_WIDTH-1:0]),
- .DataOut (MIIRX_DATAOut[`ETH_MIIRX_DATA_WIDTH-1:0]),
- .Write (MIIRX_DATA_Wr), // not written from WB
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (1'b0)
- );
-assign MIIRX_DATAOut[31:`ETH_MIIRX_DATA_WIDTH] = 0;
-
-// MAC_ADDR0 Register
-eth_register #(`ETH_MAC_ADDR0_WIDTH_0, `ETH_MAC_ADDR0_DEF_0) MAC_ADDR0_0
- (
- .DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]),
- .DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]),
- .Write (MAC_ADDR0_Wr[0]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (1'b0)
- );
-eth_register #(`ETH_MAC_ADDR0_WIDTH_1, `ETH_MAC_ADDR0_DEF_1) MAC_ADDR0_1
- (
- .DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]),
- .DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]),
- .Write (MAC_ADDR0_Wr[1]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (1'b0)
- );
-eth_register #(`ETH_MAC_ADDR0_WIDTH_2, `ETH_MAC_ADDR0_DEF_2) MAC_ADDR0_2
- (
- .DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]),
- .DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]),
- .Write (MAC_ADDR0_Wr[2]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (1'b0)
- );
-eth_register #(`ETH_MAC_ADDR0_WIDTH_3, `ETH_MAC_ADDR0_DEF_3) MAC_ADDR0_3
- (
- .DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]),
- .DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]),
- .Write (MAC_ADDR0_Wr[3]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (1'b0)
- );
-
-// MAC_ADDR1 Register
-eth_register #(`ETH_MAC_ADDR1_WIDTH_0, `ETH_MAC_ADDR1_DEF_0) MAC_ADDR1_0
- (
- .DataIn (DataIn[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]),
- .DataOut (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]),
- .Write (MAC_ADDR1_Wr[0]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (1'b0)
- );
-eth_register #(`ETH_MAC_ADDR1_WIDTH_1, `ETH_MAC_ADDR1_DEF_1) MAC_ADDR1_1
- (
- .DataIn (DataIn[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]),
- .DataOut (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]),
- .Write (MAC_ADDR1_Wr[1]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (1'b0)
- );
-assign MAC_ADDR1Out[31:`ETH_MAC_ADDR1_WIDTH_1 + 8] = 0;
-
-// RXHASH0 Register
-eth_register #(`ETH_HASH0_WIDTH_0, `ETH_HASH0_DEF_0) RXHASH0_0
- (
- .DataIn (DataIn[`ETH_HASH0_WIDTH_0 - 1:0]),
- .DataOut (HASH0Out[`ETH_HASH0_WIDTH_0 - 1:0]),
- .Write (HASH0_Wr[0]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (1'b0)
- );
-eth_register #(`ETH_HASH0_WIDTH_1, `ETH_HASH0_DEF_1) RXHASH0_1
- (
- .DataIn (DataIn[`ETH_HASH0_WIDTH_1 + 7:8]),
- .DataOut (HASH0Out[`ETH_HASH0_WIDTH_1 + 7:8]),
- .Write (HASH0_Wr[1]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (1'b0)
- );
-eth_register #(`ETH_HASH0_WIDTH_2, `ETH_HASH0_DEF_2) RXHASH0_2
- (
- .DataIn (DataIn[`ETH_HASH0_WIDTH_2 + 15:16]),
- .DataOut (HASH0Out[`ETH_HASH0_WIDTH_2 + 15:16]),
- .Write (HASH0_Wr[2]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (1'b0)
- );
-eth_register #(`ETH_HASH0_WIDTH_3, `ETH_HASH0_DEF_3) RXHASH0_3
- (
- .DataIn (DataIn[`ETH_HASH0_WIDTH_3 + 23:24]),
- .DataOut (HASH0Out[`ETH_HASH0_WIDTH_3 + 23:24]),
- .Write (HASH0_Wr[3]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (1'b0)
- );
-
-// RXHASH1 Register
-eth_register #(`ETH_HASH1_WIDTH_0, `ETH_HASH1_DEF_0) RXHASH1_0
- (
- .DataIn (DataIn[`ETH_HASH1_WIDTH_0 - 1:0]),
- .DataOut (HASH1Out[`ETH_HASH1_WIDTH_0 - 1:0]),
- .Write (HASH1_Wr[0]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (1'b0)
- );
-eth_register #(`ETH_HASH1_WIDTH_1, `ETH_HASH1_DEF_1) RXHASH1_1
- (
- .DataIn (DataIn[`ETH_HASH1_WIDTH_1 + 7:8]),
- .DataOut (HASH1Out[`ETH_HASH1_WIDTH_1 + 7:8]),
- .Write (HASH1_Wr[1]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (1'b0)
- );
-eth_register #(`ETH_HASH1_WIDTH_2, `ETH_HASH1_DEF_2) RXHASH1_2
- (
- .DataIn (DataIn[`ETH_HASH1_WIDTH_2 + 15:16]),
- .DataOut (HASH1Out[`ETH_HASH1_WIDTH_2 + 15:16]),
- .Write (HASH1_Wr[2]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (1'b0)
- );
-eth_register #(`ETH_HASH1_WIDTH_3, `ETH_HASH1_DEF_3) RXHASH1_3
- (
- .DataIn (DataIn[`ETH_HASH1_WIDTH_3 + 23:24]),
- .DataOut (HASH1Out[`ETH_HASH1_WIDTH_3 + 23:24]),
- .Write (HASH1_Wr[3]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (1'b0)
- );
-
-// TXCTRL Register
-eth_register #(`ETH_TX_CTRL_WIDTH_0, `ETH_TX_CTRL_DEF_0) TXCTRL_0
- (
- .DataIn (DataIn[`ETH_TX_CTRL_WIDTH_0 - 1:0]),
- .DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_0 - 1:0]),
- .Write (TXCTRL_Wr[0]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (1'b0)
- );
-eth_register #(`ETH_TX_CTRL_WIDTH_1, `ETH_TX_CTRL_DEF_1) TXCTRL_1
- (
- .DataIn (DataIn[`ETH_TX_CTRL_WIDTH_1 + 7:8]),
- .DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_1 + 7:8]),
- .Write (TXCTRL_Wr[1]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (1'b0)
- );
-eth_register #(`ETH_TX_CTRL_WIDTH_2, `ETH_TX_CTRL_DEF_2) TXCTRL_2 // Request bit is synchronously reset
- (
- .DataIn (DataIn[`ETH_TX_CTRL_WIDTH_2 + 15:16]),
- .DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_2 + 15:16]),
- .Write (TXCTRL_Wr[2]),
- .Clk (Clk),
- .Reset (Reset),
- .SyncReset (RstTxPauseRq)
- );
-assign TXCTRLOut[31:`ETH_TX_CTRL_WIDTH_2 + 16] = 0;
-
-
-
-// Reading data from registers
-always @ (Address or Read or MODEROut or INT_SOURCEOut or
- INT_MASKOut or IPGTOut or IPGR1Out or IPGR2Out or
- PACKETLENOut or COLLCONFOut or CTRLMODEROut or MIIMODEROut or
- MIICOMMANDOut or MIIADDRESSOut or MIITX_DATAOut or MIIRX_DATAOut or
- MIISTATUSOut or MAC_ADDR0Out or MAC_ADDR1Out or TX_BD_NUMOut or
- HASH0Out or HASH1Out or TXCTRLOut
- )
-begin
- if(Read) // read
- begin
- case(Address)
- `ETH_MODER_ADR : DataOut<=MODEROut;
- `ETH_INT_SOURCE_ADR : DataOut<=INT_SOURCEOut;
- `ETH_INT_MASK_ADR : DataOut<=INT_MASKOut;
- `ETH_IPGT_ADR : DataOut<=IPGTOut;
- `ETH_IPGR1_ADR : DataOut<=IPGR1Out;
- `ETH_IPGR2_ADR : DataOut<=IPGR2Out;
- `ETH_PACKETLEN_ADR : DataOut<=PACKETLENOut;
- `ETH_COLLCONF_ADR : DataOut<=COLLCONFOut;
- `ETH_CTRLMODER_ADR : DataOut<=CTRLMODEROut;
- `ETH_MIIMODER_ADR : DataOut<=MIIMODEROut;
- `ETH_MIICOMMAND_ADR : DataOut<=MIICOMMANDOut;
- `ETH_MIIADDRESS_ADR : DataOut<=MIIADDRESSOut;
- `ETH_MIITX_DATA_ADR : DataOut<=MIITX_DATAOut;
- `ETH_MIIRX_DATA_ADR : DataOut<=MIIRX_DATAOut;
- `ETH_MIISTATUS_ADR : DataOut<=MIISTATUSOut;
- `ETH_MAC_ADDR0_ADR : DataOut<=MAC_ADDR0Out;
- `ETH_MAC_ADDR1_ADR : DataOut<=MAC_ADDR1Out;
- `ETH_TX_BD_NUM_ADR : DataOut<=TX_BD_NUMOut;
- `ETH_HASH0_ADR : DataOut<=HASH0Out;
- `ETH_HASH1_ADR : DataOut<=HASH1Out;
- `ETH_TX_CTRL_ADR : DataOut<=TXCTRLOut;
- `ETH_DBG_ADR : DataOut<=dbg_dat; // debug data out -- JB
- default: DataOut<=32'h0;
- endcase
- end
- else
- DataOut<=32'h0;
-end
-
-
-assign r_RecSmall = MODEROut[16];
-assign r_Pad = MODEROut[15];
-assign r_HugEn = MODEROut[14];
-assign r_CrcEn = MODEROut[13];
-assign r_DlyCrcEn = MODEROut[12];
-// assign r_Rst = MODEROut[11]; This signal is not used any more
-assign r_FullD = MODEROut[10];
-assign r_ExDfrEn = MODEROut[9];
-assign r_NoBckof = MODEROut[8];
-assign r_LoopBck = MODEROut[7];
-assign r_IFG = MODEROut[6];
-assign r_Pro = MODEROut[5];
-assign r_Iam = MODEROut[4];
-assign r_Bro = MODEROut[3];
-assign r_NoPre = MODEROut[2];
-assign r_TxEn = MODEROut[1] & (TX_BD_NUMOut>0); // Transmission is enabled when there is at least one TxBD.
-assign r_RxEn = MODEROut[0] & (TX_BD_NUMOut<'h80); // Reception is enabled when there is at least one RxBD.
-
-assign r_IPGT[6:0] = IPGTOut[6:0];
-
-assign r_IPGR1[6:0] = IPGR1Out[6:0];
-
-assign r_IPGR2[6:0] = IPGR2Out[6:0];
-
-assign r_MinFL[15:0] = PACKETLENOut[31:16];
-assign r_MaxFL[15:0] = PACKETLENOut[15:0];
-
-assign r_MaxRet[3:0] = COLLCONFOut[19:16];
-assign r_CollValid[5:0] = COLLCONFOut[5:0];
-
-assign r_TxFlow = CTRLMODEROut[2];
-assign r_RxFlow = CTRLMODEROut[1];
-assign r_PassAll = CTRLMODEROut[0];
-
-assign r_MiiNoPre = MIIMODEROut[8];
-assign r_ClkDiv[7:0] = MIIMODEROut[7:0];
-
-assign r_WCtrlData = MIICOMMANDOut[2];
-assign r_RStat = MIICOMMANDOut[1];
-assign r_ScanStat = MIICOMMANDOut[0];
-
-assign r_RGAD[4:0] = MIIADDRESSOut[12:8];
-assign r_FIAD[4:0] = MIIADDRESSOut[4:0];
-
-assign r_CtrlData[15:0] = MIITX_DATAOut[15:0];
-
-assign MIISTATUSOut[31:`ETH_MIISTATUS_WIDTH] = 0;
-assign MIISTATUSOut[2] = NValid_stat ;
-assign MIISTATUSOut[1] = Busy_stat ;
-assign MIISTATUSOut[0] = LinkFail ;
-
-assign r_MAC[31:0] = MAC_ADDR0Out[31:0];
-assign r_MAC[47:32] = MAC_ADDR1Out[15:0];
-assign r_HASH1[31:0] = HASH1Out;
-assign r_HASH0[31:0] = HASH0Out;
-
-assign r_TxBDNum[7:0] = TX_BD_NUMOut[7:0];
-
-assign r_TxPauseTV[15:0] = TXCTRLOut[15:0];
-assign r_TxPauseRq = TXCTRLOut[16];
-
-
-// Synchronizing TxC Interrupt
-always @ (posedge TxClk or posedge Reset)
-begin
- if(Reset)
- SetTxCIrq_txclk <= 1'b0;
- else
- if(TxCtrlEndFrm & StartTxDone & r_TxFlow)
- SetTxCIrq_txclk <= 1'b1;
- else
- if(ResetTxCIrq_sync2)
- SetTxCIrq_txclk <= 1'b0;
-end
-
-
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- SetTxCIrq_sync1 <= 1'b0;
- else
- SetTxCIrq_sync1 <= SetTxCIrq_txclk;
-end
-
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- SetTxCIrq_sync2 <= 1'b0;
- else
- SetTxCIrq_sync2 <= SetTxCIrq_sync1;
-end
-
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- SetTxCIrq_sync3 <= 1'b0;
- else
- SetTxCIrq_sync3 <= SetTxCIrq_sync2;
-end
-
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- SetTxCIrq <= 1'b0;
- else
- SetTxCIrq <= SetTxCIrq_sync2 & ~SetTxCIrq_sync3;
-end
-
-always @ (posedge TxClk or posedge Reset)
-begin
- if(Reset)
- ResetTxCIrq_sync1 <= 1'b0;
- else
- ResetTxCIrq_sync1 <= SetTxCIrq_sync2;
-end
-
-always @ (posedge TxClk or posedge Reset)
-begin
- if(Reset)
- ResetTxCIrq_sync2 <= 1'b0;
- else
- ResetTxCIrq_sync2 <= SetTxCIrq_sync1;
-end
-
-
-// Synchronizing RxC Interrupt
-always @ (posedge RxClk or posedge Reset)
-begin
- if(Reset)
- SetRxCIrq_rxclk <= 1'b0;
- else
- if(SetPauseTimer & r_RxFlow)
- SetRxCIrq_rxclk <= 1'b1;
- else
- if(ResetRxCIrq_sync2 & (~ResetRxCIrq_sync3))
- SetRxCIrq_rxclk <= 1'b0;
-end
-
-
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- SetRxCIrq_sync1 <= 1'b0;
- else
- SetRxCIrq_sync1 <= SetRxCIrq_rxclk;
-end
-
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- SetRxCIrq_sync2 <= 1'b0;
- else
- SetRxCIrq_sync2 <= SetRxCIrq_sync1;
-end
-
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- SetRxCIrq_sync3 <= 1'b0;
- else
- SetRxCIrq_sync3 <= SetRxCIrq_sync2;
-end
-
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- SetRxCIrq <= 1'b0;
- else
- SetRxCIrq <= SetRxCIrq_sync2 & ~SetRxCIrq_sync3;
-end
-
-always @ (posedge RxClk or posedge Reset)
-begin
- if(Reset)
- ResetRxCIrq_sync1 <= 1'b0;
- else
- ResetRxCIrq_sync1 <= SetRxCIrq_sync2;
-end
-
-always @ (posedge RxClk or posedge Reset)
-begin
- if(Reset)
- ResetRxCIrq_sync2 <= 1'b0;
- else
- ResetRxCIrq_sync2 <= ResetRxCIrq_sync1;
-end
-
-always @ (posedge RxClk or posedge Reset)
-begin
- if(Reset)
- ResetRxCIrq_sync3 <= 1'b0;
- else
- ResetRxCIrq_sync3 <= ResetRxCIrq_sync2;
-end
-
-
-
-// Interrupt generation
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- irq_txb <= 1'b0;
- else
- if(TxB_IRQ)
- irq_txb <= 1'b1;
- else
- if(INT_SOURCE_Wr[0] & DataIn[0])
- irq_txb <= 1'b0;
-end
-
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- irq_txe <= 1'b0;
- else
- if(TxE_IRQ)
- irq_txe <= 1'b1;
- else
- if(INT_SOURCE_Wr[0] & DataIn[1])
- irq_txe <= 1'b0;
-end
-
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- irq_rxb <= 1'b0;
- else
- if(RxB_IRQ)
- irq_rxb <= 1'b1;
- else
- if(INT_SOURCE_Wr[0] & DataIn[2])
- irq_rxb <= 1'b0;
-end
-
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- irq_rxe <= 1'b0;
- else
- if(RxE_IRQ)
- irq_rxe <= 1'b1;
- else
- if(INT_SOURCE_Wr[0] & DataIn[3])
- irq_rxe <= 1'b0;
-end
-
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- irq_busy <= 1'b0;
- else
- if(Busy_IRQ)
- irq_busy <= 1'b1;
- else
- if(INT_SOURCE_Wr[0] & DataIn[4])
- irq_busy <= 1'b0;
-end
-
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- irq_txc <= 1'b0;
- else
- if(SetTxCIrq)
- irq_txc <= 1'b1;
- else
- if(INT_SOURCE_Wr[0] & DataIn[5])
- irq_txc <= 1'b0;
-end
-
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- irq_rxc <= 1'b0;
- else
- if(SetRxCIrq)
- irq_rxc <= 1'b1;
- else
- if(INT_SOURCE_Wr[0] & DataIn[6])
- irq_rxc <= 1'b0;
-end
-
-// Generating interrupt signal
-assign int_o = irq_txb & INT_MASKOut[0] |
- irq_txe & INT_MASKOut[1] |
- irq_rxb & INT_MASKOut[2] |
- irq_rxe & INT_MASKOut[3] |
- irq_busy & INT_MASKOut[4] |
- irq_txc & INT_MASKOut[5] |
- irq_rxc & INT_MASKOut[6] ;
-
-// For reading interrupt status
-assign INT_SOURCEOut = {{(32-`ETH_INT_SOURCE_WIDTH_0){1'b0}}, irq_rxc, irq_txc, irq_busy, irq_rxe, irq_rxb, irq_txe, irq_txb};
-
-
-
-endmodule
rtl/verilog/eth/eth_registers.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: rtl/verilog/eth/eth_rxstatem.v
===================================================================
--- rtl/verilog/eth/eth_rxstatem.v (revision 408)
+++ rtl/verilog/eth/eth_rxstatem.v (nonexistent)
@@ -1,196 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_rxstatem.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// - Novan Hartadi (novan@vlsi.itb.ac.id) ////
-//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.5 2002/01/23 10:28:16 mohor
-// Link in the header changed.
-//
-// Revision 1.4 2001/10/19 08:43:51 mohor
-// eth_timescale.v changed to timescale.v This is done because of the
-// simulation of the few cores in a one joined project.
-//
-// Revision 1.3 2001/10/18 12:07:11 mohor
-// Status signals changed, Adress decoding changed, interrupt controller
-// added.
-//
-// Revision 1.2 2001/09/11 14:17:00 mohor
-// Few little NCSIM warnings fixed.
-//
-// Revision 1.1 2001/08/06 14:44:29 mohor
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
-// Include files fixed to contain no path.
-// File names and module names changed ta have a eth_ prologue in the name.
-// File eth_timescale.v is used to define timescale
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
-// and Mdo_OE. The bidirectional signal must be created on the top level. This
-// is done due to the ASIC tools.
-//
-// Revision 1.1 2001/07/30 21:23:42 mohor
-// Directory structure changed. Files checked and joind together.
-//
-// Revision 1.2 2001/07/03 12:55:41 mohor
-// Minor changes because of the synthesys warnings.
-//
-//
-// Revision 1.1 2001/06/27 21:26:19 mohor
-// Initial release of the RxEthMAC module.
-//
-//
-//
-//
-
-
-`include "timescale.v"
-
-
-module eth_rxstatem (MRxClk, Reset, MRxDV, ByteCntEq0, ByteCntGreat2, Transmitting, MRxDEq5, MRxDEqD,
- IFGCounterEq24, ByteCntMaxFrame, StateData, StateIdle, StatePreamble, StateSFD,
- StateDrop
- );
-
-parameter Tp = 1;
-
-input MRxClk;
-input Reset;
-input MRxDV;
-input ByteCntEq0;
-input ByteCntGreat2;
-input MRxDEq5;
-input Transmitting;
-input MRxDEqD;
-input IFGCounterEq24;
-input ByteCntMaxFrame;
-
-output [1:0] StateData;
-output StateIdle;
-output StateDrop;
-output StatePreamble;
-output StateSFD;
-
-reg StateData0;
-reg StateData1;
-reg StateIdle;
-reg StateDrop;
-reg StatePreamble;
-reg StateSFD;
-
-wire StartIdle;
-wire StartDrop;
-wire StartData0;
-wire StartData1;
-wire StartPreamble;
-wire StartSFD;
-
-
-// Defining the next state
-assign StartIdle = ~MRxDV & (StateDrop | StatePreamble | StateSFD | (|StateData));
-
-assign StartPreamble = MRxDV & ~MRxDEq5 & (StateIdle & ~Transmitting);
-
-assign StartSFD = MRxDV & MRxDEq5 & (StateIdle & ~Transmitting | StatePreamble);
-
-assign StartData0 = MRxDV & (StateSFD & MRxDEqD & IFGCounterEq24 | StateData1);
-
-assign StartData1 = MRxDV & StateData0 & (~ByteCntMaxFrame);
-
-assign StartDrop = MRxDV & (StateIdle & Transmitting | StateSFD & ~IFGCounterEq24 & MRxDEqD
- | StateData0 & ByteCntMaxFrame
- );
-
-// Rx State Machine
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- begin
- StateIdle <= 1'b0;
- StateDrop <= 1'b1;
- StatePreamble <= 1'b0;
- StateSFD <= 1'b0;
- StateData0 <= 1'b0;
- StateData1 <= 1'b0;
- end
- else
- begin
- if(StartPreamble | StartSFD | StartDrop)
- StateIdle <= 1'b0;
- else
- if(StartIdle)
- StateIdle <= 1'b1;
-
- if(StartIdle)
- StateDrop <= 1'b0;
- else
- if(StartDrop)
- StateDrop <= 1'b1;
-
- if(StartSFD | StartIdle | StartDrop)
- StatePreamble <= 1'b0;
- else
- if(StartPreamble)
- StatePreamble <= 1'b1;
-
- if(StartPreamble | StartIdle | StartData0 | StartDrop)
- StateSFD <= 1'b0;
- else
- if(StartSFD)
- StateSFD <= 1'b1;
-
- if(StartIdle | StartData1 | StartDrop)
- StateData0 <= 1'b0;
- else
- if(StartData0)
- StateData0 <= 1'b1;
-
- if(StartIdle | StartData0 | StartDrop)
- StateData1 <= 1'b0;
- else
- if(StartData1)
- StateData1 <= 1'b1;
- end
-end
-
-assign StateData[1:0] = {StateData1, StateData0};
-
-endmodule
rtl/verilog/eth/eth_rxstatem.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: rtl/verilog/eth/eth_txstatem.v
===================================================================
--- rtl/verilog/eth/eth_txstatem.v (revision 408)
+++ rtl/verilog/eth/eth_txstatem.v (nonexistent)
@@ -1,284 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_txstatem.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// - Novan Hartadi (novan@vlsi.itb.ac.id) ////
-//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.5 2002/10/30 12:54:50 mohor
-// State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.
-//
-// Revision 1.4 2002/01/23 10:28:16 mohor
-// Link in the header changed.
-//
-// Revision 1.3 2001/10/19 08:43:51 mohor
-// eth_timescale.v changed to timescale.v This is done because of the
-// simulation of the few cores in a one joined project.
-//
-// Revision 1.2 2001/09/11 14:17:00 mohor
-// Few little NCSIM warnings fixed.
-//
-// Revision 1.1 2001/08/06 14:44:29 mohor
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
-// Include files fixed to contain no path.
-// File names and module names changed ta have a eth_ prologue in the name.
-// File eth_timescale.v is used to define timescale
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
-// and Mdo_OE. The bidirectional signal must be created on the top level. This
-// is done due to the ASIC tools.
-//
-// Revision 1.1 2001/07/30 21:23:42 mohor
-// Directory structure changed. Files checked and joind together.
-//
-// Revision 1.3 2001/06/19 18:16:40 mohor
-// TxClk changed to MTxClk (as discribed in the documentation).
-// Crc changed so only one file can be used instead of two.
-//
-// Revision 1.2 2001/06/19 10:38:07 mohor
-// Minor changes in header.
-//
-// Revision 1.1 2001/06/19 10:27:57 mohor
-// TxEthMAC initial release.
-//
-//
-//
-//
-
-
-`include "timescale.v"
-
-
-module eth_txstatem (MTxClk, Reset, ExcessiveDefer, CarrierSense, NibCnt, IPGT, IPGR1,
- IPGR2, FullD, TxStartFrm, TxEndFrm, TxUnderRun, Collision, UnderRun,
- StartTxDone, TooBig, NibCntEq7, NibCntEq15, MaxFrame, Pad, CrcEn,
- NibbleMinFl, RandomEq0, ColWindow, RetryMax, NoBckof, RandomEqByteCnt,
- StateIdle, StateIPG, StatePreamble, StateData, StatePAD, StateFCS,
- StateJam, StateJam_q, StateBackOff, StateDefer, StartFCS, StartJam,
- StartBackoff, StartDefer, DeferIndication, StartPreamble, StartData, StartIPG
- );
-
-parameter Tp = 1;
-
-input MTxClk;
-input Reset;
-input ExcessiveDefer;
-input CarrierSense;
-input [6:0] NibCnt;
-input [6:0] IPGT;
-input [6:0] IPGR1;
-input [6:0] IPGR2;
-input FullD;
-input TxStartFrm;
-input TxEndFrm;
-input TxUnderRun;
-input Collision;
-input UnderRun;
-input StartTxDone;
-input TooBig;
-input NibCntEq7;
-input NibCntEq15;
-input MaxFrame;
-input Pad;
-input CrcEn;
-input NibbleMinFl;
-input RandomEq0;
-input ColWindow;
-input RetryMax;
-input NoBckof;
-input RandomEqByteCnt;
-
-
-output StateIdle; // Idle state
-output StateIPG; // IPG state
-output StatePreamble; // Preamble state
-output [1:0] StateData; // Data state
-output StatePAD; // PAD state
-output StateFCS; // FCS state
-output StateJam; // Jam state
-output StateJam_q; // Delayed Jam state
-output StateBackOff; // Backoff state
-output StateDefer; // Defer state
-
-output StartFCS; // FCS state will be activated in next clock
-output StartJam; // Jam state will be activated in next clock
-output StartBackoff; // Backoff state will be activated in next clock
-output StartDefer; // Defer state will be activated in next clock
-output DeferIndication;
-output StartPreamble; // Preamble state will be activated in next clock
-output [1:0] StartData; // Data state will be activated in next clock
-output StartIPG; // IPG state will be activated in next clock
-
-wire StartIdle; // Idle state will be activated in next clock
-wire StartPAD; // PAD state will be activated in next clock
-
-
-reg StateIdle;
-reg StateIPG;
-reg StatePreamble;
-reg [1:0] StateData;
-reg StatePAD;
-reg StateFCS;
-reg StateJam;
-reg StateJam_q;
-reg StateBackOff;
-reg StateDefer;
-reg Rule1;
-
-
-// Defining the next state
-assign StartIPG = StateDefer & ~ExcessiveDefer & ~CarrierSense;
-
-assign StartIdle = StateIPG & (Rule1 & NibCnt[6:0] >= IPGT | ~Rule1 & NibCnt[6:0] >= IPGR2);
-
-assign StartPreamble = StateIdle & TxStartFrm & ~CarrierSense;
-
-assign StartData[0] = ~Collision & (StatePreamble & NibCntEq15 | StateData[1] & ~TxEndFrm);
-
-assign StartData[1] = ~Collision & StateData[0] & ~TxUnderRun & ~MaxFrame;
-
-assign StartPAD = ~Collision & StateData[1] & TxEndFrm & Pad & ~NibbleMinFl;
-
-assign StartFCS = ~Collision & StateData[1] & TxEndFrm & (~Pad | Pad & NibbleMinFl) & CrcEn
- | ~Collision & StatePAD & NibbleMinFl & CrcEn;
-
-assign StartJam = (Collision | UnderRun) & ((StatePreamble & NibCntEq15) | (|StateData[1:0]) | StatePAD | StateFCS);
-
-assign StartBackoff = StateJam & ~RandomEq0 & ColWindow & ~RetryMax & NibCntEq7 & ~NoBckof;
-
-assign StartDefer = StateIPG & ~Rule1 & CarrierSense & NibCnt[6:0] <= IPGR1 & NibCnt[6:0] != IPGR2
- | StateIdle & CarrierSense
- | StateJam & NibCntEq7 & (NoBckof | RandomEq0 | ~ColWindow | RetryMax)
- | StateBackOff & (TxUnderRun | RandomEqByteCnt)
- | StartTxDone | TooBig;
-
-assign DeferIndication = StateIdle & CarrierSense;
-
-// Tx State Machine
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- begin
- StateIPG <= 1'b0;
- StateIdle <= 1'b0;
- StatePreamble <= 1'b0;
- StateData[1:0] <= 2'b0;
- StatePAD <= 1'b0;
- StateFCS <= 1'b0;
- StateJam <= 1'b0;
- StateJam_q <= 1'b0;
- StateBackOff <= 1'b0;
- StateDefer <= 1'b1;
- end
- else
- begin
- StateData[1:0] <= StartData[1:0];
- StateJam_q <= StateJam;
-
- if(StartDefer | StartIdle)
- StateIPG <= 1'b0;
- else
- if(StartIPG)
- StateIPG <= 1'b1;
-
- if(StartDefer | StartPreamble)
- StateIdle <= 1'b0;
- else
- if(StartIdle)
- StateIdle <= 1'b1;
-
- if(StartData[0] | StartJam)
- StatePreamble <= 1'b0;
- else
- if(StartPreamble)
- StatePreamble <= 1'b1;
-
- if(StartFCS | StartJam)
- StatePAD <= 1'b0;
- else
- if(StartPAD)
- StatePAD <= 1'b1;
-
- if(StartJam | StartDefer)
- StateFCS <= 1'b0;
- else
- if(StartFCS)
- StateFCS <= 1'b1;
-
- if(StartBackoff | StartDefer)
- StateJam <= 1'b0;
- else
- if(StartJam)
- StateJam <= 1'b1;
-
- if(StartDefer)
- StateBackOff <= 1'b0;
- else
- if(StartBackoff)
- StateBackOff <= 1'b1;
-
- if(StartIPG)
- StateDefer <= 1'b0;
- else
- if(StartDefer)
- StateDefer <= 1'b1;
- end
-end
-
-
-// This sections defines which interpack gap rule to use
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- Rule1 <= 1'b0;
- else
- begin
- if(StateIdle | StateBackOff)
- Rule1 <= 1'b0;
- else
- if(StatePreamble | FullD)
- Rule1 <= 1'b1;
- end
-end
-
-
-
-endmodule
rtl/verilog/eth/eth_txstatem.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: rtl/verilog/eth/eth_rxethmac.v
===================================================================
--- rtl/verilog/eth/eth_rxethmac.v (revision 408)
+++ rtl/verilog/eth/eth_rxethmac.v (nonexistent)
@@ -1,377 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_rxethmac.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// - Novan Hartadi (novan@vlsi.itb.ac.id) ////
-//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.12 2004/04/26 15:26:23 igorm
-// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
-// previous update of the core.
-// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
-// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
-// register. (thanks to Mathias and Torbjorn)
-// - Multicast reception was fixed. Thanks to Ulrich Gries
-//
-// Revision 1.11 2004/03/17 09:32:15 igorm
-// Multicast detection fixed. Only the LSB of the first byte is checked.
-//
-// Revision 1.10 2002/11/22 01:57:06 mohor
-// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
-// synchronized.
-//
-// Revision 1.9 2002/11/19 17:35:35 mohor
-// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
-// that a frame was received because of the promiscous mode.
-//
-// Revision 1.8 2002/02/16 07:15:27 mohor
-// Testbench fixed, code simplified, unused signals removed.
-//
-// Revision 1.7 2002/02/15 13:44:28 mohor
-// RxAbort is an output. No need to have is declared as wire.
-//
-// Revision 1.6 2002/02/15 11:17:48 mohor
-// File format changed.
-//
-// Revision 1.5 2002/02/14 20:48:43 billditt
-// Addition of new module eth_addrcheck.v
-//
-// Revision 1.4 2002/01/23 10:28:16 mohor
-// Link in the header changed.
-//
-// Revision 1.3 2001/10/19 08:43:51 mohor
-// eth_timescale.v changed to timescale.v This is done because of the
-// simulation of the few cores in a one joined project.
-//
-// Revision 1.2 2001/09/11 14:17:00 mohor
-// Few little NCSIM warnings fixed.
-//
-// Revision 1.1 2001/08/06 14:44:29 mohor
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
-// Include files fixed to contain no path.
-// File names and module names changed ta have a eth_ prologue in the name.
-// File eth_timescale.v is used to define timescale
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
-// and Mdo_OE. The bidirectional signal must be created on the top level. This
-// is done due to the ASIC tools.
-//
-// Revision 1.1 2001/07/30 21:23:42 mohor
-// Directory structure changed. Files checked and joind together.
-//
-// Revision 1.1 2001/06/27 21:26:19 mohor
-// Initial release of the RxEthMAC module.
-//
-//
-//
-//
-//
-
-`include "timescale.v"
-
-
-module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG, HugEn, DlyCrcEn,
- RxData, RxValid, RxStartFrm, RxEndFrm, ByteCnt, ByteCntEq0, ByteCntGreat2,
- ByteCntMaxFrame, CrcError, StateIdle, StatePreamble, StateSFD, StateData,
- MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort, AddressMiss, PassAll, ControlFrmAddressOK
- );
-
-parameter Tp = 1;
-
-
-
-input MRxClk;
-input MRxDV;
-input [3:0] MRxD;
-input Transmitting;
-input HugEn;
-input DlyCrcEn;
-input [15:0] MaxFL;
-input r_IFG;
-input Reset;
-input [47:0] MAC; // Station Address
-input r_Bro; // broadcast disable
-input r_Pro; // promiscuous enable
-input [31:0] r_HASH0; // lower 4 bytes Hash Table
-input [31:0] r_HASH1; // upper 4 bytes Hash Table
-input PassAll;
-input ControlFrmAddressOK;
-
-output [7:0] RxData;
-output RxValid;
-output RxStartFrm;
-output RxEndFrm;
-output [15:0] ByteCnt;
-output ByteCntEq0;
-output ByteCntGreat2;
-output ByteCntMaxFrame;
-output CrcError;
-output StateIdle;
-output StatePreamble;
-output StateSFD;
-output [1:0] StateData;
-output RxAbort;
-output AddressMiss;
-
-reg [7:0] RxData;
-reg RxValid;
-reg RxStartFrm;
-reg RxEndFrm;
-reg Broadcast;
-reg Multicast;
-reg [5:0] CrcHash;
-reg CrcHashGood;
-reg DelayData;
-reg [7:0] LatchedByte;
-reg [7:0] RxData_d;
-reg RxValid_d;
-reg RxStartFrm_d;
-reg RxEndFrm_d;
-
-wire MRxDEqD;
-wire MRxDEq5;
-wire StateDrop;
-wire ByteCntEq1;
-wire ByteCntEq2;
-wire ByteCntEq3;
-wire ByteCntEq4;
-wire ByteCntEq5;
-wire ByteCntEq6;
-wire ByteCntEq7;
-wire ByteCntSmall7;
-wire [31:0] Crc;
-wire Enable_Crc;
-wire Initialize_Crc;
-wire [3:0] Data_Crc;
-wire GenerateRxValid;
-wire GenerateRxStartFrm;
-wire GenerateRxEndFrm;
-wire DribbleRxEndFrm;
-wire [3:0] DlyCrcCnt;
-wire IFGCounterEq24;
-
-assign MRxDEqD = MRxD == 4'hd;
-assign MRxDEq5 = MRxD == 4'h5;
-
-
-// Rx State Machine module
-eth_rxstatem rxstatem1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .ByteCntEq0(ByteCntEq0),
- .ByteCntGreat2(ByteCntGreat2), .Transmitting(Transmitting), .MRxDEq5(MRxDEq5),
- .MRxDEqD(MRxDEqD), .IFGCounterEq24(IFGCounterEq24), .ByteCntMaxFrame(ByteCntMaxFrame),
- .StateData(StateData), .StateIdle(StateIdle), .StatePreamble(StatePreamble),
- .StateSFD(StateSFD), .StateDrop(StateDrop)
- );
-
-
-// Rx Counters module
-eth_rxcounters rxcounters1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .StateIdle(StateIdle),
- .StateSFD(StateSFD), .StateData(StateData), .StateDrop(StateDrop),
- .StatePreamble(StatePreamble), .MRxDEqD(MRxDEqD), .DlyCrcEn(DlyCrcEn),
- .DlyCrcCnt(DlyCrcCnt), .Transmitting(Transmitting), .MaxFL(MaxFL), .r_IFG(r_IFG),
- .HugEn(HugEn), .IFGCounterEq24(IFGCounterEq24), .ByteCntEq0(ByteCntEq0),
- .ByteCntEq1(ByteCntEq1), .ByteCntEq2(ByteCntEq2), .ByteCntEq3(ByteCntEq3),
- .ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5), .ByteCntEq6(ByteCntEq6),
- .ByteCntEq7(ByteCntEq7), .ByteCntGreat2(ByteCntGreat2),
- .ByteCntSmall7(ByteCntSmall7), .ByteCntMaxFrame(ByteCntMaxFrame),
- .ByteCntOut(ByteCnt)
- );
-
-// Rx Address Check
-
-eth_rxaddrcheck rxaddrcheck1
- (.MRxClk(MRxClk), .Reset( Reset), .RxData(RxData),
- .Broadcast (Broadcast), .r_Bro (r_Bro), .r_Pro(r_Pro),
- .ByteCntEq6(ByteCntEq6), .ByteCntEq7(ByteCntEq7), .ByteCntEq2(ByteCntEq2),
- .ByteCntEq3(ByteCntEq3), .ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5),
- .HASH0(r_HASH0), .HASH1(r_HASH1),
- .CrcHash(CrcHash), .CrcHashGood(CrcHashGood), .StateData(StateData),
- .Multicast(Multicast), .MAC(MAC), .RxAbort(RxAbort),
- .RxEndFrm(RxEndFrm), .AddressMiss(AddressMiss), .PassAll(PassAll),
- .ControlFrmAddressOK(ControlFrmAddressOK)
- );
-
-
-assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame);
-assign Initialize_Crc = StateSFD | DlyCrcEn & (|DlyCrcCnt[3:0]) & DlyCrcCnt[3:0] < 4'h9;
-
-assign Data_Crc[0] = MRxD[3];
-assign Data_Crc[1] = MRxD[2];
-assign Data_Crc[2] = MRxD[1];
-assign Data_Crc[3] = MRxD[0];
-
-
-// Connecting module Crc
-eth_crc crcrx (.Clk(MRxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
- .Crc(Crc), .CrcError(CrcError)
- );
-
-
-
-// Latching CRC for use in the hash table
-
-always @ (posedge MRxClk)
-begin
- CrcHashGood <= StateData[0] & ByteCntEq6;
-end
-
-always @ (posedge MRxClk)
-begin
- if(Reset | StateIdle)
- CrcHash[5:0] <= 6'h0;
- else
- if(StateData[0] & ByteCntEq6)
- CrcHash[5:0] <= Crc[31:26];
-end
-
-
-// Output byte stream
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- begin
- RxData_d[7:0] <= 8'h0;
- DelayData <= 1'b0;
- LatchedByte[7:0] <= 8'h0;
- RxData[7:0] <= 8'h0;
- end
- else
- begin
- LatchedByte[7:0] <= {MRxD[3:0], LatchedByte[7:4]}; // Latched byte
- DelayData <= StateData[0];
-
- if(GenerateRxValid)
- RxData_d[7:0] <= LatchedByte[7:0] & {8{|StateData}}; // Data goes through only in data state
- else
- if(~DelayData)
- RxData_d[7:0] <= 8'h0; // Delaying data to be valid for two cycles. Zero when not active.
-
- RxData[7:0] <= RxData_d[7:0]; // Output data byte
- end
-end
-
-
-
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- Broadcast <= 1'b0;
- else
- begin
- if(StateData[0] & ~(&LatchedByte[7:0]) & ByteCntSmall7)
- Broadcast <= 1'b0;
- else
- if(StateData[0] & (&LatchedByte[7:0]) & ByteCntEq1)
- Broadcast <= 1'b1;
- else
- if(RxAbort | RxEndFrm)
- Broadcast <= 1'b0;
- end
-end
-
-
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- Multicast <= 1'b0;
- else
- begin
- if(StateData[0] & ByteCntEq1 & LatchedByte[0])
- Multicast <= 1'b1;
- else if(RxAbort | RxEndFrm)
- Multicast <= 1'b0;
- end
-end
-
-
-assign GenerateRxValid = StateData[0] & (~ByteCntEq0 | DlyCrcCnt >= 4'h3);
-
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- begin
- RxValid_d <= 1'b0;
- RxValid <= 1'b0;
- end
- else
- begin
- RxValid_d <= GenerateRxValid;
- RxValid <= RxValid_d;
- end
-end
-
-
-assign GenerateRxStartFrm = StateData[0] & (ByteCntEq1 & ~DlyCrcEn | DlyCrcCnt == 4'h3 & DlyCrcEn);
-
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- begin
- RxStartFrm_d <= 1'b0;
- RxStartFrm <= 1'b0;
- end
- else
- begin
- RxStartFrm_d <= GenerateRxStartFrm;
- RxStartFrm <= RxStartFrm_d;
- end
-end
-
-
-assign GenerateRxEndFrm = StateData[0] & (~MRxDV & ByteCntGreat2 | ByteCntMaxFrame);
-assign DribbleRxEndFrm = StateData[1] & ~MRxDV & ByteCntGreat2;
-
-
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- begin
- RxEndFrm_d <= 1'b0;
- RxEndFrm <= 1'b0;
- end
- else
- begin
- RxEndFrm_d <= GenerateRxEndFrm;
- RxEndFrm <= RxEndFrm_d | DribbleRxEndFrm;
- end
-end
-
-
-endmodule
rtl/verilog/eth/eth_rxethmac.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: rtl/verilog/eth/eth_shiftreg.v
===================================================================
--- rtl/verilog/eth/eth_shiftreg.v (revision 408)
+++ rtl/verilog/eth/eth_shiftreg.v (nonexistent)
@@ -1,151 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_shiftreg.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.5 2002/08/14 18:16:59 mohor
-// LinkFail signal was not latching appropriate bit.
-//
-// Revision 1.4 2002/03/02 21:06:01 mohor
-// LinkFail signal was not latching appropriate bit.
-//
-// Revision 1.3 2002/01/23 10:28:16 mohor
-// Link in the header changed.
-//
-// Revision 1.2 2001/10/19 08:43:51 mohor
-// eth_timescale.v changed to timescale.v This is done because of the
-// simulation of the few cores in a one joined project.
-//
-// Revision 1.1 2001/08/06 14:44:29 mohor
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
-// Include files fixed to contain no path.
-// File names and module names changed ta have a eth_ prologue in the name.
-// File eth_timescale.v is used to define timescale
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
-// and Mdo_OE. The bidirectional signal must be created on the top level. This
-// is done due to the ASIC tools.
-//
-// Revision 1.1 2001/07/30 21:23:42 mohor
-// Directory structure changed. Files checked and joind together.
-//
-// Revision 1.3 2001/06/01 22:28:56 mohor
-// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
-//
-//
-
-`include "timescale.v"
-
-
-module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
- LatchByte, ShiftedBit, Prsd, LinkFail);
-
-
-parameter Tp=1;
-
-input Clk; // Input clock (Host clock)
-input Reset; // Reset signal
-input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
-input Mdi; // MII input data
-input [4:0] Fiad; // PHY address
-input [4:0] Rgad; // Register address (within the selected PHY)
-input [15:0]CtrlData; // Control data (data to be written to the PHY)
-input WriteOp; // The current operation is a PHY register write operation
-input [3:0] ByteSelect; // Byte select
-input [1:0] LatchByte; // Byte select for latching (read operation)
-
-output ShiftedBit; // Bit shifted out of the shift register
-output[15:0]Prsd; // Read Status Data (data read from the PHY)
-output LinkFail; // Link Integrity Signal
-
-reg [7:0] ShiftReg; // Shift register for shifting the data in and out
-reg [15:0]Prsd;
-reg LinkFail;
-
-
-
-
-// ShiftReg[7:0] :: Shift Register Data
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- begin
- ShiftReg[7:0] <= 8'h0;
- Prsd[15:0] <= 16'h0;
- LinkFail <= 1'b0;
- end
- else
- begin
- if(MdcEn_n)
- begin
- if(|ByteSelect)
- begin
- case (ByteSelect[3:0]) // synopsys parallel_case full_case
- 4'h1 : ShiftReg[7:0] <= {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};
- 4'h2 : ShiftReg[7:0] <= {Fiad[0], Rgad[4:0], 2'b10};
- 4'h4 : ShiftReg[7:0] <= CtrlData[15:8];
- 4'h8 : ShiftReg[7:0] <= CtrlData[7:0];
- endcase
- end
- else
- begin
- ShiftReg[7:0] <= {ShiftReg[6:0], Mdi};
- if(LatchByte[0])
- begin
- Prsd[7:0] <= {ShiftReg[6:0], Mdi};
- if(Rgad == 5'h01)
- LinkFail <= ~ShiftReg[1]; // this is bit [2], because it is not shifted yet
- end
- else
- begin
- if(LatchByte[1])
- Prsd[15:8] <= {ShiftReg[6:0], Mdi};
- end
- end
- end
- end
-end
-
-
-assign ShiftedBit = ShiftReg[7];
-
-
-endmodule
rtl/verilog/eth/eth_shiftreg.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: rtl/verilog/eth/eth_spram_256x32.v
===================================================================
--- rtl/verilog/eth/eth_spram_256x32.v (revision 408)
+++ rtl/verilog/eth/eth_spram_256x32.v (nonexistent)
@@ -1,334 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_spram_256x32.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// ////
-//// All additional information is available in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001, 2002 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.9 2003/12/05 12:43:06 tadejm
-// Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16.
-//
-// Revision 1.8 2003/12/04 14:59:13 simons
-// Lapsus fixed (!we -> ~we).
-//
-// Revision 1.7 2003/11/12 18:24:59 tadejm
-// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
-//
-// Revision 1.6 2003/10/17 07:46:15 markom
-// mbist signals updated according to newest convention
-//
-// Revision 1.5 2003/08/14 16:42:58 simons
-// Artisan ram instance added.
-//
-// Revision 1.4 2002/10/18 17:04:20 tadejm
-// Changed BIST scan signals.
-//
-// Revision 1.3 2002/10/10 16:29:30 mohor
-// BIST added.
-//
-// Revision 1.2 2002/09/23 18:24:31 mohor
-// ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).
-//
-// Revision 1.1 2002/07/23 16:36:09 mohor
-// ethernet spram added. So far a generic ram and xilinx RAMB4 are used.
-//
-//
-//
-
-`include "eth_defines.v"
-`include "timescale.v"
-
-module eth_spram_256x32(
- // Generic synchronous single-port RAM interface
- clk, rst, ce, we, oe, addr, di, do
-
-`ifdef ETH_BIST
- ,
- // debug chain signals
- mbist_si_i, // bist scan serial in
- mbist_so_o, // bist scan serial out
- mbist_ctrl_i // bist chain shift control
-`endif
-
-
-
- );
- parameter we_width = 4;
-
- //
- // Generic synchronous single-port RAM interface
- //
- input clk; // Clock, rising edge
- input rst; // Reset, active high
- input ce; // Chip enable input, active high
- input [we_width-1:0] we; // Write enable input, active high
- input oe; // Output enable input, active high
- input [7:0] addr; // address bus inputs
- input [31:0] di; // input data bus
- output [31:0] do; // output data bus
-
-
-`ifdef ETH_BIST
- input mbist_si_i; // bist scan serial in
- output mbist_so_o; // bist scan serial out
- input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
-`endif
-
-`ifdef ETH_XILINX_RAMB4
-
- /*RAMB4_S16 ram0
- (
- .DO (do[15:0]),
- .ADDR (addr),
- .DI (di[15:0]),
- .EN (ce),
- .CLK (clk),
- .WE (we),
- .RST (rst)
- );
-
- RAMB4_S16 ram1
- (
- .DO (do[31:16]),
- .ADDR (addr),
- .DI (di[31:16]),
- .EN (ce),
- .CLK (clk),
- .WE (we),
- .RST (rst)
- );*/
-
- RAMB4_S8 ram0
- (
- .DO (do[7:0]),
- .ADDR ({1'b0, addr}),
- .DI (di[7:0]),
- .EN (ce),
- .CLK (clk),
- .WE (we[0]),
- .RST (rst)
- );
-
- RAMB4_S8 ram1
- (
- .DO (do[15:8]),
- .ADDR ({1'b0, addr}),
- .DI (di[15:8]),
- .EN (ce),
- .CLK (clk),
- .WE (we[1]),
- .RST (rst)
- );
-
- RAMB4_S8 ram2
- (
- .DO (do[23:16]),
- .ADDR ({1'b0, addr}),
- .DI (di[23:16]),
- .EN (ce),
- .CLK (clk),
- .WE (we[2]),
- .RST (rst)
- );
-
- RAMB4_S8 ram3
- (
- .DO (do[31:24]),
- .ADDR ({1'b0, addr}),
- .DI (di[31:24]),
- .EN (ce),
- .CLK (clk),
- .WE (we[3]),
- .RST (rst)
- );
-
-`else // !ETH_XILINX_RAMB4
- `ifdef ETH_VIRTUAL_SILICON_RAM
- `ifdef ETH_BIST
- //vs_hdsp_256x32_bist ram0_bist
- vs_hdsp_256x32_bw_bist ram0_bist
- `else
- //vs_hdsp_256x32 ram0
- vs_hdsp_256x32_bw ram0
- `endif
- (
- .CK (clk),
- .CEN (!ce),
- .WEN (~we),
- .OEN (!oe),
- .ADR (addr),
- .DI (di),
- .DOUT (do)
-
- `ifdef ETH_BIST
- ,
- // debug chain signals
- .mbist_si_i (mbist_si_i),
- .mbist_so_o (mbist_so_o),
- .mbist_ctrl_i (mbist_ctrl_i)
- `endif
- );
-
- `else // !ETH_VIRTUAL_SILICON_RAM
-
- `ifdef ETH_ARTISAN_RAM
- `ifdef ETH_BIST
- //art_hssp_256x32_bist ram0_bist
- art_hssp_256x32_bw_bist ram0_bist
- `else
- //art_hssp_256x32 ram0
- art_hssp_256x32_bw ram0
- `endif
- (
- .CLK (clk),
- .CEN (!ce),
- .WEN (~we),
- .OEN (!oe),
- .A (addr),
- .D (di),
- .Q (do)
-
- `ifdef ETH_BIST
- ,
- // debug chain signals
- .mbist_si_i (mbist_si_i),
- .mbist_so_o (mbist_so_o),
- .mbist_ctrl_i (mbist_ctrl_i)
- `endif
- );
-
- `else // !ETH_ARTISAN_RAM
- `ifdef ETH_ALTERA_ALTSYNCRAM
-
- altera_spram_256x32 altera_spram_256x32_inst
- (
- .address (addr),
- .wren (ce & we),
- .clock (clk),
- .data (di),
- .q (do)
- ); //exemplar attribute altera_spram_256x32_inst NOOPT TRUE
-
- `else // !ETH_ALTERA_ALTSYNCRAM
-
-
- //
- // Generic single-port synchronous RAM model
- //
-
- //
- // Generic RAM's registers and wires
- //
- reg [ 7: 0] mem0 [255:0]; // RAM content
- reg [15: 8] mem1 [255:0]; // RAM content
- reg [23:16] mem2 [255:0]; // RAM content
- reg [31:24] mem3 [255:0]; // RAM content
- wire [31:0] q; // RAM output
- reg [7:0] raddr; // RAM read address
-
- reg [31:0] mem[255:0];
-
- //
- // Data output drivers
- //
- //assign do = (oe & ce) ? q : {32{1'bz}};
- assign do = (oe & ce) ? q : {32{1'bx}};
-
- //
- // RAM read and write
- //
-
- // read operation
- always@(posedge clk)
- if (ce)
- raddr <= addr; // read address needs to be registered to read clock
-
- generate
- if (we_width > 1)
- begin
-
- assign q = rst ? {32{1'b0}} : {mem3[raddr], mem2[raddr], mem1[raddr],
- mem0[raddr]};
-
- // write operation
- always@(posedge clk)
- begin
- if (ce && we[3])
- mem3[addr] <= di[31:24];
- if (ce && we[2])
- mem2[addr] <= di[23:16];
- if (ce && we[1])
- mem1[addr] <= di[15: 8];
- if (ce && we[0])
- mem0[addr] <= di[ 7: 0];
- end
-
- end // if (we_width > 1)
- else
- begin
- assign q = rst ? {32{1'b0}} : {mem[raddr]};
-
- // write operation
- always@(posedge clk)
- begin
- if (ce && we[0])
- mem[addr] <= di[ 31: 0];
- end
-
- end // else: !if(we_width > 1)
- endgenerate
-
- // Task prints range of memory
- // *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations.
- task print_ram;
- input [7:0] start;
- input [7:0] finish;
- integer rnum;
- begin
- for (rnum=start;rnum<=finish;rnum=rnum+1)
- $display("Addr %h = %0h %0h %0h %0h",rnum,mem3[rnum],mem2[rnum],mem1[rnum],mem0[rnum]);
- end
- endtask
-
- `endif // !ETH_ALTERA_ALTSYNCRAM
- `endif // !ETH_ARTISAN_RAM
- `endif // !ETH_VIRTUAL_SILICON_RAM
-`endif // !ETH_XILINX_RAMB4
-
-endmodule
rtl/verilog/eth/eth_spram_256x32.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: rtl/verilog/eth/eth_rxcounters.v
===================================================================
--- rtl/verilog/eth/eth_rxcounters.v (revision 408)
+++ rtl/verilog/eth/eth_rxcounters.v (nonexistent)
@@ -1,218 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_rxcounters.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// - Novan Hartadi (novan@vlsi.itb.ac.id) ////
-//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.5 2002/02/15 11:13:29 mohor
-// Format of the file changed a bit.
-//
-// Revision 1.4 2002/02/14 20:19:41 billditt
-// Modified for Address Checking,
-// addition of eth_addrcheck.v
-//
-// Revision 1.3 2002/01/23 10:28:16 mohor
-// Link in the header changed.
-//
-// Revision 1.2 2001/10/19 08:43:51 mohor
-// eth_timescale.v changed to timescale.v This is done because of the
-// simulation of the few cores in a one joined project.
-//
-// Revision 1.1 2001/08/06 14:44:29 mohor
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
-// Include files fixed to contain no path.
-// File names and module names changed ta have a eth_ prologue in the name.
-// File eth_timescale.v is used to define timescale
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
-// and Mdo_OE. The bidirectional signal must be created on the top level. This
-// is done due to the ASIC tools.
-//
-// Revision 1.1 2001/07/30 21:23:42 mohor
-// Directory structure changed. Files checked and joind together.
-//
-// Revision 1.1 2001/06/27 21:26:19 mohor
-// Initial release of the RxEthMAC module.
-//
-//
-//
-//
-//
-//
-
-
-`include "timescale.v"
-
-
-module eth_rxcounters (MRxClk, Reset, MRxDV, StateIdle, StateSFD, StateData, StateDrop, StatePreamble,
- MRxDEqD, DlyCrcEn, DlyCrcCnt, Transmitting, MaxFL, r_IFG, HugEn, IFGCounterEq24,
- ByteCntEq0, ByteCntEq1, ByteCntEq2,ByteCntEq3,ByteCntEq4,ByteCntEq5, ByteCntEq6,
- ByteCntEq7, ByteCntGreat2, ByteCntSmall7, ByteCntMaxFrame, ByteCntOut
- );
-
-parameter Tp = 1;
-
-input MRxClk;
-input Reset;
-input MRxDV;
-input StateSFD;
-input [1:0] StateData;
-input MRxDEqD;
-input StateIdle;
-input StateDrop;
-input DlyCrcEn;
-input StatePreamble;
-input Transmitting;
-input HugEn;
-input [15:0] MaxFL;
-input r_IFG;
-
-output IFGCounterEq24; // IFG counter reaches 9600 ns (960 ns)
-output [3:0] DlyCrcCnt; // Delayed CRC counter
-output ByteCntEq0; // Byte counter = 0
-output ByteCntEq1; // Byte counter = 1
-output ByteCntEq2; // Byte counter = 2
-output ByteCntEq3; // Byte counter = 3
-output ByteCntEq4; // Byte counter = 4
-output ByteCntEq5; // Byte counter = 5
-output ByteCntEq6; // Byte counter = 6
-output ByteCntEq7; // Byte counter = 7
-output ByteCntGreat2; // Byte counter > 2
-output ByteCntSmall7; // Byte counter < 7
-output ByteCntMaxFrame; // Byte counter = MaxFL
-output [15:0] ByteCntOut; // Byte counter
-
-wire ResetByteCounter;
-wire IncrementByteCounter;
-wire ResetIFGCounter;
-wire IncrementIFGCounter;
-wire ByteCntMax;
-
-reg [15:0] ByteCnt;
-reg [3:0] DlyCrcCnt;
-reg [4:0] IFGCounter;
-
-wire [15:0] ByteCntDelayed;
-
-
-
-assign ResetByteCounter = MRxDV & (StateSFD & MRxDEqD | StateData[0] & ByteCntMaxFrame);
-
-assign IncrementByteCounter = ~ResetByteCounter & MRxDV &
- (StatePreamble | StateSFD | StateIdle & ~Transmitting |
- StateData[1] & ~ByteCntMax & ~(DlyCrcEn & |DlyCrcCnt)
- );
-
-
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- ByteCnt[15:0] <= 16'h0;
- else
- begin
- if(ResetByteCounter)
- ByteCnt[15:0] <= 16'h0;
- else
- if(IncrementByteCounter)
- ByteCnt[15:0] <= ByteCnt[15:0] + 1'b1;
- end
-end
-
-assign ByteCntDelayed = ByteCnt + 3'h4;
-assign ByteCntOut = DlyCrcEn? ByteCntDelayed : ByteCnt;
-
-assign ByteCntEq0 = ByteCnt == 16'h0;
-assign ByteCntEq1 = ByteCnt == 16'h1;
-assign ByteCntEq2 = ByteCnt == 16'h2;
-assign ByteCntEq3 = ByteCnt == 16'h3;
-assign ByteCntEq4 = ByteCnt == 16'h4;
-assign ByteCntEq5 = ByteCnt == 16'h5;
-assign ByteCntEq6 = ByteCnt == 16'h6;
-assign ByteCntEq7 = ByteCnt == 16'h7;
-assign ByteCntGreat2 = ByteCnt > 16'h2;
-assign ByteCntSmall7 = ByteCnt < 16'h7;
-assign ByteCntMax = ByteCnt == 16'hffff;
-assign ByteCntMaxFrame = ByteCnt == MaxFL[15:0] & ~HugEn;
-
-
-assign ResetIFGCounter = StateSFD & MRxDV & MRxDEqD | StateDrop;
-
-assign IncrementIFGCounter = ~ResetIFGCounter & (StateDrop | StateIdle | StatePreamble | StateSFD) & ~IFGCounterEq24;
-
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- IFGCounter[4:0] <= 5'h0;
- else
- begin
- if(ResetIFGCounter)
- IFGCounter[4:0] <= 5'h0;
- else
- if(IncrementIFGCounter)
- IFGCounter[4:0] <= IFGCounter[4:0] + 1'b1;
- end
-end
-
-
-
-assign IFGCounterEq24 = (IFGCounter[4:0] == 5'h18) | r_IFG; // 24*400 = 9600 ns or r_IFG is set to 1
-
-
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- DlyCrcCnt[3:0] <= 4'h0;
- else
- begin
- if(DlyCrcCnt[3:0] == 4'h9)
- DlyCrcCnt[3:0] <= 4'h0;
- else
- if(DlyCrcEn & StateSFD)
- DlyCrcCnt[3:0] <= 4'h1;
- else
- if(DlyCrcEn & (|DlyCrcCnt[3:0]))
- DlyCrcCnt[3:0] <= DlyCrcCnt[3:0] + 1'b1;
- end
-end
-
-
-endmodule
rtl/verilog/eth/eth_rxcounters.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: rtl/verilog/eth/eth_txethmac.v
===================================================================
--- rtl/verilog/eth/eth_txethmac.v (revision 408)
+++ rtl/verilog/eth/eth_txethmac.v (nonexistent)
@@ -1,492 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_txethmac.v ////
-/// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// - Novan Hartadi (novan@vlsi.itb.ac.id) ////
-//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.8 2003/01/30 13:33:24 mohor
-// When padding was enabled and crc disabled, frame was not ended correctly.
-//
-// Revision 1.7 2002/02/26 16:24:01 mohor
-// RetryCntLatched was unused and removed from design
-//
-// Revision 1.6 2002/02/22 12:56:35 mohor
-// Retry is not activated when a Tx Underrun occured
-//
-// Revision 1.5 2002/02/11 09:18:22 mohor
-// Tx status is written back to the BD.
-//
-// Revision 1.4 2002/01/23 10:28:16 mohor
-// Link in the header changed.
-//
-// Revision 1.3 2001/10/19 08:43:51 mohor
-// eth_timescale.v changed to timescale.v This is done because of the
-// simulation of the few cores in a one joined project.
-//
-// Revision 1.2 2001/09/11 14:17:00 mohor
-// Few little NCSIM warnings fixed.
-//
-// Revision 1.1 2001/08/06 14:44:29 mohor
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
-// Include files fixed to contain no path.
-// File names and module names changed ta have a eth_ prologue in the name.
-// File eth_timescale.v is used to define timescale
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
-// and Mdo_OE. The bidirectional signal must be created on the top level. This
-// is done due to the ASIC tools.
-//
-// Revision 1.1 2001/07/30 21:23:42 mohor
-// Directory structure changed. Files checked and joind together.
-//
-// Revision 1.3 2001/06/19 18:16:40 mohor
-// TxClk changed to MTxClk (as discribed in the documentation).
-// Crc changed so only one file can be used instead of two.
-//
-// Revision 1.2 2001/06/19 10:38:08 mohor
-// Minor changes in header.
-//
-// Revision 1.1 2001/06/19 10:27:58 mohor
-// TxEthMAC initial release.
-//
-//
-//
-
-`include "timescale.v"
-
-
-module eth_txethmac (MTxClk, Reset, TxStartFrm, TxEndFrm, TxUnderRun, TxData, CarrierSense,
- Collision, Pad, CrcEn, FullD, HugEn, DlyCrcEn, MinFL, MaxFL, IPGT,
- IPGR1, IPGR2, CollValid, MaxRet, NoBckof, ExDfrEn,
- MTxD, MTxEn, MTxErr, TxDone, TxRetry, TxAbort, TxUsedData, WillTransmit,
- ResetCollision, RetryCnt, StartTxDone, StartTxAbort, MaxCollisionOccured,
- LateCollision, DeferIndication, StatePreamble, StateData
-
- );
-
-parameter Tp = 1;
-
-
-input MTxClk; // Transmit clock (from PHY)
-input Reset; // Reset
-input TxStartFrm; // Transmit packet start frame
-input TxEndFrm; // Transmit packet end frame
-input TxUnderRun; // Transmit packet under-run
-input [7:0] TxData; // Transmit packet data byte
-input CarrierSense; // Carrier sense (synchronized)
-input Collision; // Collision (synchronized)
-input Pad; // Pad enable (from register)
-input CrcEn; // Crc enable (from register)
-input FullD; // Full duplex (from register)
-input HugEn; // Huge packets enable (from register)
-input DlyCrcEn; // Delayed Crc enabled (from register)
-input [15:0] MinFL; // Minimum frame length (from register)
-input [15:0] MaxFL; // Maximum frame length (from register)
-input [6:0] IPGT; // Back to back transmit inter packet gap parameter (from register)
-input [6:0] IPGR1; // Non back to back transmit inter packet gap parameter IPGR1 (from register)
-input [6:0] IPGR2; // Non back to back transmit inter packet gap parameter IPGR2 (from register)
-input [5:0] CollValid; // Valid collision window (from register)
-input [3:0] MaxRet; // Maximum retry number (from register)
-input NoBckof; // No backoff (from register)
-input ExDfrEn; // Excessive defferal enable (from register)
-
-output [3:0] MTxD; // Transmit nibble (to PHY)
-output MTxEn; // Transmit enable (to PHY)
-output MTxErr; // Transmit error (to PHY)
-output TxDone; // Transmit packet done (to RISC)
-output TxRetry; // Transmit packet retry (to RISC)
-output TxAbort; // Transmit packet abort (to RISC)
-output TxUsedData; // Transmit packet used data (to RISC)
-output WillTransmit; // Will transmit (to RxEthMAC)
-output ResetCollision; // Reset Collision (for synchronizing collision)
-output [3:0] RetryCnt; // Latched Retry Counter for tx status purposes
-output StartTxDone;
-output StartTxAbort;
-output MaxCollisionOccured;
-output LateCollision;
-output DeferIndication;
-output StatePreamble;
-output [1:0] StateData;
-
-reg [3:0] MTxD;
-reg MTxEn;
-reg MTxErr;
-reg TxDone;
-reg TxRetry;
-reg TxAbort;
-reg TxUsedData;
-reg WillTransmit;
-reg ColWindow;
-reg StopExcessiveDeferOccured;
-reg [3:0] RetryCnt;
-reg [3:0] MTxD_d;
-reg StatusLatch;
-reg PacketFinished_q;
-reg PacketFinished;
-
-
-wire ExcessiveDeferOccured;
-wire StartIPG;
-wire StartPreamble;
-wire [1:0] StartData;
-wire StartFCS;
-wire StartJam;
-wire StartDefer;
-wire StartBackoff;
-wire StateDefer;
-wire StateIPG;
-wire StateIdle;
-wire StatePAD;
-wire StateFCS;
-wire StateJam;
-wire StateJam_q;
-wire StateBackOff;
-wire StateSFD;
-wire StartTxRetry;
-wire UnderRun;
-wire TooBig;
-wire [31:0] Crc;
-wire CrcError;
-wire [2:0] DlyCrcCnt;
-wire [15:0] NibCnt;
-wire NibCntEq7;
-wire NibCntEq15;
-wire NibbleMinFl;
-wire ExcessiveDefer;
-wire [15:0] ByteCnt;
-wire MaxFrame;
-wire RetryMax;
-wire RandomEq0;
-wire RandomEqByteCnt;
-wire PacketFinished_d;
-
-
-
-assign ResetCollision = ~(StatePreamble | (|StateData) | StatePAD | StateFCS);
-
-assign ExcessiveDeferOccured = TxStartFrm & StateDefer & ExcessiveDefer & ~StopExcessiveDeferOccured;
-
-assign StartTxDone = ~Collision & (StateFCS & NibCntEq7 | StateData[1] & TxEndFrm & (~Pad | Pad & NibbleMinFl) & ~CrcEn);
-
-assign UnderRun = StateData[0] & TxUnderRun & ~Collision;
-
-assign TooBig = ~Collision & MaxFrame & (StateData[0] & ~TxUnderRun | StateFCS);
-
-// assign StartTxRetry = StartJam & (ColWindow & ~RetryMax);
-assign StartTxRetry = StartJam & (ColWindow & ~RetryMax) & ~UnderRun;
-
-assign LateCollision = StartJam & ~ColWindow & ~UnderRun;
-
-assign MaxCollisionOccured = StartJam & ColWindow & RetryMax;
-
-assign StateSFD = StatePreamble & NibCntEq15;
-
-assign StartTxAbort = TooBig | UnderRun | ExcessiveDeferOccured | LateCollision | MaxCollisionOccured;
-
-
-// StopExcessiveDeferOccured
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- StopExcessiveDeferOccured <= 1'b0;
- else
- begin
- if(~TxStartFrm)
- StopExcessiveDeferOccured <= 1'b0;
- else
- if(ExcessiveDeferOccured)
- StopExcessiveDeferOccured <= 1'b1;
- end
-end
-
-
-// Collision Window
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- ColWindow <= 1'b1;
- else
- begin
- if(~Collision & ByteCnt[5:0] == CollValid[5:0] & (StateData[1] | StatePAD & NibCnt[0] | StateFCS & NibCnt[0]))
- ColWindow <= 1'b0;
- else
- if(StateIdle | StateIPG)
- ColWindow <= 1'b1;
- end
-end
-
-
-// Start Window
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- StatusLatch <= 1'b0;
- else
- begin
- if(~TxStartFrm)
- StatusLatch <= 1'b0;
- else
- if(ExcessiveDeferOccured | StateIdle)
- StatusLatch <= 1'b1;
- end
-end
-
-
-// Transmit packet used data
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- TxUsedData <= 1'b0;
- else
- TxUsedData <= |StartData;
-end
-
-
-// Transmit packet done
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- TxDone <= 1'b0;
- else
- begin
- if(TxStartFrm & ~StatusLatch)
- TxDone <= 1'b0;
- else
- if(StartTxDone)
- TxDone <= 1'b1;
- end
-end
-
-
-// Transmit packet retry
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- TxRetry <= 1'b0;
- else
- begin
- if(TxStartFrm & ~StatusLatch)
- TxRetry <= 1'b0;
- else
- if(StartTxRetry)
- TxRetry <= 1'b1;
- end
-end
-
-
-// Transmit packet abort
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- TxAbort <= 1'b0;
- else
- begin
- if(TxStartFrm & ~StatusLatch & ~ExcessiveDeferOccured)
- TxAbort <= 1'b0;
- else
- if(StartTxAbort)
- TxAbort <= 1'b1;
- end
-end
-
-
-// Retry counter
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- RetryCnt[3:0] <= 4'h0;
- else
- begin
- if(ExcessiveDeferOccured | UnderRun | TooBig | StartTxDone | TxUnderRun
- | StateJam & NibCntEq7 & (~ColWindow | RetryMax))
- RetryCnt[3:0] <= 4'h0;
- else
- if(StateJam & NibCntEq7 & ColWindow & (RandomEq0 | NoBckof) | StateBackOff & RandomEqByteCnt)
- RetryCnt[3:0] <= RetryCnt[3:0] + 1'b1;
- end
-end
-
-
-assign RetryMax = RetryCnt[3:0] == MaxRet[3:0];
-
-
-// Transmit nibble
-always @ (StatePreamble or StateData or StateData or StateFCS or StateJam or StateSFD or TxData or
- Crc or NibCntEq15)
-begin
- if(StateData[0])
- MTxD_d[3:0] = TxData[3:0]; // Lower nibble
- else
- if(StateData[1])
- MTxD_d[3:0] = TxData[7:4]; // Higher nibble
- else
- if(StateFCS)
- MTxD_d[3:0] = {~Crc[28], ~Crc[29], ~Crc[30], ~Crc[31]}; // Crc
- else
- if(StateJam)
- MTxD_d[3:0] = 4'h9; // Jam pattern
- else
- if(StatePreamble)
- if(NibCntEq15)
- MTxD_d[3:0] = 4'hd; // SFD
- else
- MTxD_d[3:0] = 4'h5; // Preamble
- else
- MTxD_d[3:0] = 4'h0;
-end
-
-
-// Transmit Enable
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- MTxEn <= 1'b0;
- else
- MTxEn <= StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
-end
-
-
-// Transmit nibble
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- MTxD[3:0] <= 4'h0;
- else
- MTxD[3:0] <= MTxD_d[3:0];
-end
-
-
-// Transmit error
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- MTxErr <= 1'b0;
- else
- MTxErr <= TooBig | UnderRun;
-end
-
-
-// WillTransmit
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- WillTransmit <= 1'b0;
- else
- WillTransmit <= StartPreamble | StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
-end
-
-
-assign PacketFinished_d = StartTxDone | TooBig | UnderRun | LateCollision | MaxCollisionOccured | ExcessiveDeferOccured;
-
-
-// Packet finished
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- begin
- PacketFinished <= 1'b0;
- PacketFinished_q <= 1'b0;
- end
- else
- begin
- PacketFinished <= PacketFinished_d;
- PacketFinished_q <= PacketFinished;
- end
-end
-
-
-// Connecting module Counters
-eth_txcounters txcounters1 (.StatePreamble(StatePreamble), .StateIPG(StateIPG), .StateData(StateData),
- .StatePAD(StatePAD), .StateFCS(StateFCS), .StateJam(StateJam), .StateBackOff(StateBackOff),
- .StateDefer(StateDefer), .StateIdle(StateIdle), .StartDefer(StartDefer), .StartIPG(StartIPG),
- .StartFCS(StartFCS), .StartJam(StartJam), .TxStartFrm(TxStartFrm), .MTxClk(MTxClk),
- .Reset(Reset), .MinFL(MinFL), .MaxFL(MaxFL), .HugEn(HugEn), .ExDfrEn(ExDfrEn),
- .PacketFinished_q(PacketFinished_q), .DlyCrcEn(DlyCrcEn), .StartBackoff(StartBackoff),
- .StateSFD(StateSFD), .ByteCnt(ByteCnt), .NibCnt(NibCnt), .ExcessiveDefer(ExcessiveDefer),
- .NibCntEq7(NibCntEq7), .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .NibbleMinFl(NibbleMinFl),
- .DlyCrcCnt(DlyCrcCnt)
- );
-
-
-// Connecting module StateM
-eth_txstatem txstatem1 (.MTxClk(MTxClk), .Reset(Reset), .ExcessiveDefer(ExcessiveDefer), .CarrierSense(CarrierSense),
- .NibCnt(NibCnt[6:0]), .IPGT(IPGT), .IPGR1(IPGR1), .IPGR2(IPGR2), .FullD(FullD),
- .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm), .TxUnderRun(TxUnderRun), .Collision(Collision),
- .UnderRun(UnderRun), .StartTxDone(StartTxDone), .TooBig(TooBig), .NibCntEq7(NibCntEq7),
- .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .Pad(Pad), .CrcEn(CrcEn),
- .NibbleMinFl(NibbleMinFl), .RandomEq0(RandomEq0), .ColWindow(ColWindow), .RetryMax(RetryMax),
- .NoBckof(NoBckof), .RandomEqByteCnt(RandomEqByteCnt), .StateIdle(StateIdle),
- .StateIPG(StateIPG), .StatePreamble(StatePreamble), .StateData(StateData), .StatePAD(StatePAD),
- .StateFCS(StateFCS), .StateJam(StateJam), .StateJam_q(StateJam_q), .StateBackOff(StateBackOff),
- .StateDefer(StateDefer), .StartFCS(StartFCS), .StartJam(StartJam), .StartBackoff(StartBackoff),
- .StartDefer(StartDefer), .DeferIndication(DeferIndication), .StartPreamble(StartPreamble), .StartData(StartData), .StartIPG(StartIPG)
- );
-
-
-wire Enable_Crc;
-wire [3:0] Data_Crc;
-wire Initialize_Crc;
-
-assign Enable_Crc = ~StateFCS;
-
-assign Data_Crc[0] = StateData[0]? TxData[3] : StateData[1]? TxData[7] : 1'b0;
-assign Data_Crc[1] = StateData[0]? TxData[2] : StateData[1]? TxData[6] : 1'b0;
-assign Data_Crc[2] = StateData[0]? TxData[1] : StateData[1]? TxData[5] : 1'b0;
-assign Data_Crc[3] = StateData[0]? TxData[0] : StateData[1]? TxData[4] : 1'b0;
-
-assign Initialize_Crc = StateIdle | StatePreamble | (|DlyCrcCnt);
-
-
-// Connecting module Crc
-eth_crc txcrc (.Clk(MTxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
- .Crc(Crc), .CrcError(CrcError)
- );
-
-
-// Connecting module Random
-eth_random random1 (.MTxClk(MTxClk), .Reset(Reset), .StateJam(StateJam), .StateJam_q(StateJam_q), .RetryCnt(RetryCnt),
- .NibCnt(NibCnt), .ByteCnt(ByteCnt[9:0]), .RandomEq0(RandomEq0), .RandomEqByteCnt(RandomEqByteCnt));
-
-
-
-
-endmodule
rtl/verilog/eth/eth_txethmac.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: rtl/verilog/eth/eth_txcounters.v
===================================================================
--- rtl/verilog/eth/eth_txcounters.v (revision 408)
+++ rtl/verilog/eth/eth_txcounters.v (nonexistent)
@@ -1,221 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_txcounters.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// - Novan Hartadi (novan@vlsi.itb.ac.id) ////
-//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.5 2002/04/22 14:54:14 mohor
-// FCS should not be included in NibbleMinFl.
-//
-// Revision 1.4 2002/01/23 10:28:16 mohor
-// Link in the header changed.
-//
-// Revision 1.3 2001/10/19 08:43:51 mohor
-// eth_timescale.v changed to timescale.v This is done because of the
-// simulation of the few cores in a one joined project.
-//
-// Revision 1.2 2001/09/11 14:17:00 mohor
-// Few little NCSIM warnings fixed.
-//
-// Revision 1.1 2001/08/06 14:44:29 mohor
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
-// Include files fixed to contain no path.
-// File names and module names changed ta have a eth_ prologue in the name.
-// File eth_timescale.v is used to define timescale
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
-// and Mdo_OE. The bidirectional signal must be created on the top level. This
-// is done due to the ASIC tools.
-//
-// Revision 1.1 2001/07/30 21:23:42 mohor
-// Directory structure changed. Files checked and joind together.
-//
-// Revision 1.4 2001/06/27 21:27:45 mohor
-// Few typos fixed.
-//
-// Revision 1.2 2001/06/19 10:38:07 mohor
-// Minor changes in header.
-//
-// Revision 1.1 2001/06/19 10:27:57 mohor
-// TxEthMAC initial release.
-//
-//
-//
-
-
-`include "timescale.v"
-
-
-module eth_txcounters (StatePreamble, StateIPG, StateData, StatePAD, StateFCS, StateJam,
- StateBackOff, StateDefer, StateIdle, StartDefer, StartIPG, StartFCS,
- StartJam, StartBackoff, TxStartFrm, MTxClk, Reset, MinFL, MaxFL, HugEn,
- ExDfrEn, PacketFinished_q, DlyCrcEn, StateSFD, ByteCnt, NibCnt,
- ExcessiveDefer, NibCntEq7, NibCntEq15, MaxFrame, NibbleMinFl, DlyCrcCnt
- );
-
-parameter Tp = 1;
-
-input MTxClk; // Tx clock
-input Reset; // Reset
-input StatePreamble; // Preamble state
-input StateIPG; // IPG state
-input [1:0] StateData; // Data state
-input StatePAD; // PAD state
-input StateFCS; // FCS state
-input StateJam; // Jam state
-input StateBackOff; // Backoff state
-input StateDefer; // Defer state
-input StateIdle; // Idle state
-input StateSFD; // SFD state
-input StartDefer; // Defer state will be activated in next clock
-input StartIPG; // IPG state will be activated in next clock
-input StartFCS; // FCS state will be activated in next clock
-input StartJam; // Jam state will be activated in next clock
-input StartBackoff; // Backoff state will be activated in next clock
-input TxStartFrm; // Tx start frame
-input [15:0] MinFL; // Minimum frame length (in bytes)
-input [15:0] MaxFL; // Miximum frame length (in bytes)
-input HugEn; // Pakets bigger then MaxFL enabled
-input ExDfrEn; // Excessive deferral enabled
-input PacketFinished_q;
-input DlyCrcEn; // Delayed CRC enabled
-
-output [15:0] ByteCnt; // Byte counter
-output [15:0] NibCnt; // Nibble counter
-output ExcessiveDefer; // Excessive Deferral occuring
-output NibCntEq7; // Nibble counter is equal to 7
-output NibCntEq15; // Nibble counter is equal to 15
-output MaxFrame; // Maximum frame occured
-output NibbleMinFl; // Nibble counter is greater than the minimum frame length
-output [2:0] DlyCrcCnt; // Delayed CRC Count
-
-wire ExcessiveDeferCnt;
-wire ResetNibCnt;
-wire IncrementNibCnt;
-wire ResetByteCnt;
-wire IncrementByteCnt;
-wire ByteCntMax;
-
-reg [15:0] NibCnt;
-reg [15:0] ByteCnt;
-reg [2:0] DlyCrcCnt;
-
-
-
-assign IncrementNibCnt = StateIPG | StatePreamble | (|StateData) | StatePAD
- | StateFCS | StateJam | StateBackOff | StateDefer & ~ExcessiveDefer & TxStartFrm;
-
-
-assign ResetNibCnt = StateDefer & ExcessiveDefer & ~TxStartFrm | StatePreamble & NibCntEq15
- | StateJam & NibCntEq7 | StateIdle | StartDefer | StartIPG | StartFCS | StartJam;
-
-// Nibble Counter
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- NibCnt <= 16'h0;
- else
- begin
- if(ResetNibCnt)
- NibCnt <= 16'h0;
- else
- if(IncrementNibCnt)
- NibCnt <= NibCnt + 1'b1;
- end
-end
-
-
-assign NibCntEq7 = &NibCnt[2:0];
-assign NibCntEq15 = &NibCnt[3:0];
-
-assign NibbleMinFl = NibCnt >= (((MinFL-3'h4)<<1) -1); // FCS should not be included in NibbleMinFl
-
-assign ExcessiveDeferCnt = NibCnt[13:0] == 16'h17b7;
-
-assign ExcessiveDefer = NibCnt[13:0] == 16'h17b7 & ~ExDfrEn; // 6071 nibbles
-
-assign IncrementByteCnt = StateData[1] & ~ByteCntMax
- | StateBackOff & (&NibCnt[6:0])
- | (StatePAD | StateFCS) & NibCnt[0] & ~ByteCntMax;
-
-assign ResetByteCnt = StartBackoff | StateIdle & TxStartFrm | PacketFinished_q;
-
-
-// Transmit Byte Counter
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- ByteCnt[15:0] <= 16'h0;
- else
- begin
- if(ResetByteCnt)
- ByteCnt[15:0] <= 16'h0;
- else
- if(IncrementByteCnt)
- ByteCnt[15:0] <= ByteCnt[15:0] + 1'b1;
- end
-end
-
-
-assign MaxFrame = ByteCnt[15:0] == MaxFL[15:0] & ~HugEn;
-
-assign ByteCntMax = &ByteCnt[15:0];
-
-
-// Delayed CRC counter
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- DlyCrcCnt <= 3'h0;
- else
- begin
- if(StateData[1] & DlyCrcCnt == 3'h4 | StartJam | PacketFinished_q)
- DlyCrcCnt <= 3'h0;
- else
- if(DlyCrcEn & (StateSFD | StateData[1] & (|DlyCrcCnt[2:0])))
- DlyCrcCnt <= DlyCrcCnt + 1'b1;
- end
-end
-
-
-
-endmodule
rtl/verilog/eth/eth_txcounters.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: rtl/verilog/eth/eth_wishbone.v
===================================================================
--- rtl/verilog/eth/eth_wishbone.v (revision 408)
+++ rtl/verilog/eth/eth_wishbone.v (nonexistent)
@@ -1,2844 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_wishbone.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// ////
-//// All additional information is available in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001, 2002 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-
-`include "eth_defines.v"
-`include "timescale.v"
-
-
-module eth_wishbone
- (
-
- // WISHBONE common
- WB_CLK_I, WB_DAT_I, WB_DAT_O,
-
- // WISHBONE slave
- WB_ADR_I, WB_WE_I, WB_ACK_O,
- BDCs,
-
- Reset,
-
- // WISHBONE master
- m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
- m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
- m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
-
-`ifdef ETH_WISHBONE_B3
- m_wb_cti_o, m_wb_bte_o,
-`endif
-
- //TX
- MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
- TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
- PerPacketPad,
-
- //RX
- MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort, RxStatusWriteLatched_sync2,
-
- // Register
- r_TxEn, r_RxEn, r_TxBDNum, r_RxFlow, r_PassAll,
-
- // Interrupts
- TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
-
- // Rx Status
- InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
- ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood, AddressMiss,
- ReceivedPauseFrm,
-
- // Tx Status
- RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, RstDeferLatched, CarrierSenseLost
-
- // Bist
-`ifdef ETH_BIST
- ,
- // debug chain signals
- mbist_si_i, // bist scan serial in
- mbist_so_o, // bist scan serial out
- mbist_ctrl_i // bist chain shift control
-`endif
-
-`ifdef WISHBONE_DEBUG
- ,
- dbg_dat0
-`endif
-
-
- );
-
-
- //parameter Tp = 1;
- parameter Tp = 0;
-
-
- // WISHBONE common
- input WB_CLK_I; // WISHBONE clock
- input [31:0] WB_DAT_I; // WISHBONE data input
- output [31:0] WB_DAT_O; // WISHBONE data output
-
- // WISHBONE slave
- input [9:2] WB_ADR_I; // WISHBONE address input
- input WB_WE_I; // WISHBONE write enable input
- input [3:0] BDCs; // Buffer descriptors are selected
- output WB_ACK_O; // WISHBONE acknowledge output
-
- // WISHBONE master
- output [29:0] m_wb_adr_o; //
- output [3:0] m_wb_sel_o; //
- output m_wb_we_o; //
- output [31:0] m_wb_dat_o; //
- output m_wb_cyc_o; //
- output m_wb_stb_o; //
- input [31:0] m_wb_dat_i; //
- input m_wb_ack_i; //
- input m_wb_err_i; //
-
-`ifdef ETH_WISHBONE_B3
- output [2:0] m_wb_cti_o; // Cycle Type Identifier
- `ifdef BURST_4BEAT
- output reg [1:0] m_wb_bte_o; // Burst Type Extension
- `else
- output [1:0] m_wb_bte_o; // Burst Type Extension
- `endif
- reg [2:0] m_wb_cti_o; // Cycle Type Identifier
-`endif
-
- input Reset; // Reset signal
-
- // Rx Status signals
- input InvalidSymbol; // Invalid symbol was received during
- // reception in 100 Mbps mode
- input LatchedCrcError; // CRC error
- input RxLateCollision; // Late collision occured while receiving
- // frame
- input ShortFrame; // Frame shorter then the minimum size
- // (r_MinFL) was received while small
- // packets are enabled (r_RecSmall)
- input DribbleNibble; // Extra nibble received
- input ReceivedPacketTooBig;// Received packet is bigger than
- // r_MaxFL
- input [15:0] RxLength; // Length of the incoming frame
- input LoadRxStatus; // Rx status was loaded
- input ReceivedPacketGood;// Received packet's length and CRC are
- // good
- input AddressMiss; // When a packet is received AddressMiss
- // status is written to the Rx BD
- input r_RxFlow;
- input r_PassAll;
- input ReceivedPauseFrm;
-
- // Tx Status signals
- input [3:0] RetryCntLatched; // Latched Retry Counter
- input RetryLimit; // Retry limit reached (Retry Max value +
- // 1 attempts were made)
- input LateCollLatched; // Late collision occured
- input DeferLatched; // Defer indication (Frame was defered
- // before sucessfully sent)
- output RstDeferLatched;
- input CarrierSenseLost; // Carrier Sense was lost during the
- // frame transmission
-
- // Tx
- input MTxClk; // Transmit clock (from PHY)
- input TxUsedData; // Transmit packet used data
- input TxRetry; // Transmit packet retry
- input TxAbort; // Transmit packet abort
- input TxDone; // Transmission ended
- output TxStartFrm; // Transmit packet start frame
- output TxEndFrm; // Transmit packet end frame
- output [7:0] TxData; // Transmit packet data byte
- output TxUnderRun; // Transmit packet under-run
- output PerPacketCrcEn; // Per packet crc enable
- output PerPacketPad; // Per packet pading
-
- // Rx
- input MRxClk; // Receive clock (from PHY)
- input [7:0] RxData; // Received data byte (from PHY)
- input RxValid; //
- input RxStartFrm; //
- input RxEndFrm; //
- input RxAbort; // This signal is set when address doesn't
- // match.
- output RxStatusWriteLatched_sync2;
-
- //Register
- input r_TxEn; // Transmit enable
- input r_RxEn; // Receive enable
- input [7:0] r_TxBDNum; // Receive buffer descriptor number
-
- // Interrupts
- output TxB_IRQ;
- output TxE_IRQ;
- output RxB_IRQ;
- output RxE_IRQ;
- output Busy_IRQ;
-
-
- // Bist
-`ifdef ETH_BIST
- input mbist_si_i; // bist scan serial in
- output mbist_so_o; // bist scan serial out
- input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
-`endif
-
-`ifdef WISHBONE_DEBUG
- output [31:0] dbg_dat0;
-`endif
-
-
-
- reg TxB_IRQ;
- reg TxE_IRQ;
- reg RxB_IRQ;
- reg RxE_IRQ;
-
- reg TxStartFrm;
- reg TxEndFrm;
- reg [7:0] TxData;
-
- reg TxUnderRun;
- reg TxUnderRun_wb;
-
- reg TxBDRead;
- wire TxStatusWrite;
-
- reg [1:0] TxValidBytesLatched;
-
- reg [15:0] TxLength;
- reg [15:0] LatchedTxLength;
- reg [14:11] TxStatus;
-
- reg [14:13] RxStatus;
-
- reg TxStartFrm_wb;
- reg TxRetry_wb;
- reg TxAbort_wb;
- reg TxDone_wb;
-
- reg TxDone_wb_q;
- reg TxAbort_wb_q;
- reg TxRetry_wb_q;
- reg TxRetryPacket;
- reg TxRetryPacket_NotCleared;
- reg TxDonePacket;
- reg TxDonePacket_NotCleared;
- reg TxAbortPacket;
- reg TxAbortPacket_NotCleared;
- reg RxBDReady;
- reg RxBDOK;
- reg TxBDReady;
-
- reg RxBDRead;
-
- reg [31:0] TxDataLatched;
- reg [1:0] TxByteCnt;
- reg LastWord;
- reg ReadTxDataFromFifo_tck;
-
- reg BlockingTxStatusWrite;
- reg BlockingTxBDRead;
-
- reg Flop;
-
- reg [7:1] TxBDAddress;
- reg [7:1] RxBDAddress;
-
- reg TxRetrySync1;
- reg TxAbortSync1;
- reg TxDoneSync1;
-
- reg TxAbort_q;
- reg TxRetry_q;
- reg TxUsedData_q;
-
- reg [31:0] RxDataLatched2;
-
- reg [31:8] RxDataLatched1; // Big Endian Byte Ordering
-
- reg [1:0] RxValidBytes;
- reg [1:0] RxByteCnt;
- reg LastByteIn;
- reg ShiftWillEnd;
-
- reg WriteRxDataToFifo;
- reg [15:0] LatchedRxLength;
- reg RxAbortLatched;
-
- reg ShiftEnded;
- reg RxOverrun;
-
- reg [3:0] BDWrite; // BD Write Enable for access from WISHBONE side
- reg BDRead; // BD Read access from WISHBONE side
- wire [31:0] RxBDDataIn; // Rx BD data in
- wire [31:0] TxBDDataIn; // Tx BD data in
-
- reg TxEndFrm_wb;
-
- wire TxRetryPulse;
- wire TxDonePulse;
- wire TxAbortPulse;
-
- wire StartRxBDRead;
-
- wire StartTxBDRead;
-
- wire TxIRQEn;
- wire WrapTxStatusBit;
-
- wire RxIRQEn;
- wire WrapRxStatusBit;
-
- wire [1:0] TxValidBytes;
-
- wire [7:1] TempTxBDAddress;
- wire [7:1] TempRxBDAddress;
-
- wire RxStatusWrite;
- wire RxBufferFull;
- wire RxBufferAlmostEmpty;
- wire RxBufferEmpty;
-
- reg WB_ACK_O;
-
- wire [8:0] RxStatusIn;
- reg [8:0] RxStatusInLatched;
-
- reg WbEn, WbEn_q;
- reg RxEn, RxEn_q;
- reg TxEn, TxEn_q;
- reg r_TxEn_q;
- reg r_RxEn_q;
-
- wire ram_ce;
- wire [3:0] ram_we;
- wire ram_oe;
- reg [7:0] ram_addr;
- reg [31:0] ram_di;
- wire [31:0] ram_do;
-
- wire StartTxPointerRead;
- reg TxPointerRead;
- reg TxEn_needed;
- reg RxEn_needed;
-
- wire StartRxPointerRead;
- reg RxPointerRead;
-
- // RX shift ending signals
- reg ShiftEnded_rck;
- reg ShiftEndedSync1;
- reg ShiftEndedSync2;
- reg ShiftEndedSync3;
- reg ShiftEndedSync_c1;
- reg ShiftEndedSync_c2;
-
- wire StartShiftWillEnd;
-
- // Pulse for wishbone side having finished writing back
- reg rx_wb_writeback_finished;
- // Indicator of last set of writes from the Wishbone master coming up
- reg rx_wb_last_writes;
-
-
-`ifdef TXBD_POLL
- reg [31:0] TxBDReadySamples; // -- jb
- wire TxBDNotReady; // -- jb
-`endif
-
-`ifdef ETH_WISHBONE_B3
- `ifndef BURST_4BEAT
- assign m_wb_bte_o = 2'b00; // Linear burst
- `endif
-`endif
-
- assign m_wb_stb_o = m_wb_cyc_o;
-
- always @ (posedge WB_CLK_I)
- begin
- WB_ACK_O <= (|BDWrite) & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
- end
-
- assign WB_DAT_O = ram_do;
-
- // Generic synchronous single-port RAM interface
- eth_spram_256x32
- #(1) // Write enable width
- bd_ram
- (
- .clk (WB_CLK_I),
- .rst (Reset),
- .ce (ram_ce),
- .we (ram_we[0]),
- .oe (ram_oe),
- .addr (ram_addr),
- .di (ram_di),
- .do (ram_do)
-`ifdef ETH_BIST
- ,
- .mbist_si_i (mbist_si_i),
- .mbist_so_o (mbist_so_o),
- .mbist_ctrl_i (mbist_ctrl_i)
-`endif
- );
-
- assign ram_ce = 1'b1;
- assign ram_we = (BDWrite & {4{(WbEn & WbEn_q)}}) |
- {4{(TxStatusWrite | RxStatusWrite)}};
- assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q &
- (TxBDRead | TxPointerRead) | RxEn & RxEn_q &
- (RxBDRead | RxPointerRead);
-
-
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- TxEn_needed <= 1'b0;
- else
- if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q)
- TxEn_needed <= 1'b1;
- else
- if(TxPointerRead & TxEn & TxEn_q)
- TxEn_needed <= 1'b0;
- end
-
- // Enabling access to the RAM for three devices.
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- begin
- WbEn <= 1'b1;
- RxEn <= 1'b0;
- TxEn <= 1'b0;
- ram_addr <= 8'h0;
- ram_di <= 32'h0;
- BDRead <= 1'b0;
- BDWrite <= 1'b0;
- end
- else
- begin
- // Switching between three stages depends on enable signals
- case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed}) // synopsys parallel_case
- 5'b100_10, 5'b100_11 :
- begin
- WbEn <= 1'b0;
- RxEn <= 1'b1; // wb access stage and r_RxEn is enabled
- TxEn <= 1'b0;
- ram_addr <= {RxBDAddress, RxPointerRead};
- ram_di <= RxBDDataIn;
- end
- 5'b100_01 :
- begin
- WbEn <= 1'b0;
- RxEn <= 1'b0;
- TxEn <= 1'b1; // wb access stage, r_RxEn is disabled but
- // r_TxEn is enabled
- ram_addr <= {TxBDAddress, TxPointerRead};
- ram_di <= TxBDDataIn;
- end
- 5'b010_00, 5'b010_10 :
- begin
- WbEn <= 1'b1; // RxEn access stage and r_TxEn is disabled
- RxEn <= 1'b0;
- TxEn <= 1'b0;
- ram_addr <= WB_ADR_I[9:2];
- ram_di <= WB_DAT_I;
- BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
- BDRead <= (|BDCs) & ~WB_WE_I;
- end
- 5'b010_01, 5'b010_11 :
- begin
- WbEn <= 1'b0;
- RxEn <= 1'b0;
- TxEn <= 1'b1; // RxEn access stage and r_TxEn is enabled
- ram_addr <= {TxBDAddress, TxPointerRead};
- ram_di <= TxBDDataIn;
- end
- 5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
- begin
- WbEn <= 1'b1; // TxEn access stage (we always go to wb
- // access stage)
- RxEn <= 1'b0;
- TxEn <= 1'b0;
- ram_addr <= WB_ADR_I[9:2];
- ram_di <= WB_DAT_I;
- BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
- BDRead <= (|BDCs) & ~WB_WE_I;
- end
- 5'b100_00 :
- begin
- WbEn <= 1'b0; // WbEn access stage and there is no need
- // for other stages. WbEn needs to be
- // switched off for a bit
- end
- 5'b000_00 :
- begin
- WbEn <= 1'b1; // Idle state. We go to WbEn access stage.
- RxEn <= 1'b0;
- TxEn <= 1'b0;
- ram_addr <= WB_ADR_I[9:2];
- ram_di <= WB_DAT_I;
- BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
- BDRead <= (|BDCs) & ~WB_WE_I;
- end
- endcase
- end
- end
-
-
- // Delayed stage signals
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- begin
- WbEn_q <= 1'b0;
- RxEn_q <= 1'b0;
- TxEn_q <= 1'b0;
- r_TxEn_q <= 1'b0;
- r_RxEn_q <= 1'b0;
- end
- else
- begin
- WbEn_q <= WbEn;
- RxEn_q <= RxEn;
- TxEn_q <= TxEn;
- r_TxEn_q <= r_TxEn;
- r_RxEn_q <= r_RxEn;
- end
- end
-
- // Changes for tx occur every second clock. Flop is used for this manner.
- always @ (posedge MTxClk or posedge Reset)
- begin
- if(Reset)
- Flop <= 1'b0;
- else
- if(TxDone | TxAbort | TxRetry_q)
- Flop <= 1'b0;
- else
- if(TxUsedData)
- Flop <= ~Flop;
- end
-
- wire ResetTxBDReady;
- assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
-
- // Latching READY status of the Tx buffer descriptor
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- TxBDReady <= 1'b0;
- else
- if(TxEn & TxEn_q & TxBDRead)
- // TxBDReady is sampled only once at the beginning.
- TxBDReady <= ram_do[15] & (ram_do[31:16] > 4);
- else
- // Only packets larger then 4 bytes are transmitted.
- if(ResetTxBDReady)
- TxBDReady <= 1'b0;
- end
-
-`ifdef TXBD_POLL
- // Register TxBDReady 4 times, when all are low we know this one is not
- // good to transmit
- always @(posedge WB_CLK_I or posedge Reset) // -- jb
- begin
- if (Reset) TxBDReadySamples <= 32'hffffffff;
- else begin
- if (r_TxEn)
- begin
- if (TxBDNotReady)
- TxBDReadySamples <= 32'hffffffff;
- else
- TxBDReadySamples[31:0] <= {TxBDReadySamples[30:0],TxBDReady};
- end
- else
- TxBDReadySamples <= 32'hffffffff;
- end // else: !if(Reset)
- end // always @ (posedge WB_CLK_I or posedge Reset)
- // When all low, this goes high -- jb
- assign TxBDNotReady = ~(|TxBDReadySamples);
-
-
-`endif
-
- // Reading the Tx buffer descriptor
- assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) &
- ~BlockingTxBDRead & ~TxBDReady;
-
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- TxBDRead <= 1'b1;
- else
- if(StartTxBDRead)
- TxBDRead <= 1'b1;
- else
- if(TxBDReady)
- TxBDRead <= 1'b0;
- end
-
-
- // Reading Tx BD pointer
- assign StartTxPointerRead = TxBDRead & TxBDReady;
-
- // Reading Tx BD Pointer
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- TxPointerRead <= 1'b0;
- else
- if(StartTxPointerRead)
- TxPointerRead <= 1'b1;
- else
- if(TxEn_q)
- TxPointerRead <= 1'b0;
- end
-
-
- // Writing status back to the Tx buffer descriptor
- assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared)&
- TxEn & TxEn_q & ~BlockingTxStatusWrite;
-
-
-
- // Status writing must occur only once. Meanwhile it is blocked.
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- BlockingTxStatusWrite <= 1'b0;
- else
- if(~TxDone_wb & ~TxAbort_wb)
- BlockingTxStatusWrite <= 1'b0;
- else
- if(TxStatusWrite)
- BlockingTxStatusWrite <= 1'b1;
- end
-
-
- reg BlockingTxStatusWrite_sync1;
- reg BlockingTxStatusWrite_sync2;
- reg BlockingTxStatusWrite_sync3;
-
- // Synchronizing BlockingTxStatusWrite to MTxClk
- always @ (posedge MTxClk or posedge Reset)
- begin
- if(Reset)
- BlockingTxStatusWrite_sync1 <= 1'b0;
- else
- BlockingTxStatusWrite_sync1 <= BlockingTxStatusWrite;
- end
-
- // Synchronizing BlockingTxStatusWrite to MTxClk
- always @ (posedge MTxClk or posedge Reset)
- begin
- if(Reset)
- BlockingTxStatusWrite_sync2 <= 1'b0;
- else
- BlockingTxStatusWrite_sync2 <= BlockingTxStatusWrite_sync1;
- end
-
- // Synchronizing BlockingTxStatusWrite to MTxClk
- always @ (posedge MTxClk or posedge Reset)
- begin
- if(Reset)
- BlockingTxStatusWrite_sync3 <= 1'b0;
- else
- BlockingTxStatusWrite_sync3 <= BlockingTxStatusWrite_sync2;
- end
-
- assign RstDeferLatched = BlockingTxStatusWrite_sync2 &
- ~BlockingTxStatusWrite_sync3;
-
- // TxBDRead state is activated only once.
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- BlockingTxBDRead <= 1'b0;
- else
- if(StartTxBDRead)
- BlockingTxBDRead <= 1'b1;
- else
- if(~StartTxBDRead & ~TxBDReady)
- BlockingTxBDRead <= 1'b0;
- end
-
-
- // Latching status from the tx buffer descriptor
- // Data is avaliable one cycle after the access is started (at that time
- // signal TxEn is not active)
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- TxStatus <= 4'h0;
- else
- if(TxEn & TxEn_q & TxBDRead)
- TxStatus <= ram_do[14:11];
- end
-
- reg ReadTxDataFromMemory;
- wire WriteRxDataToMemory;
- reg WriteRxDataToMemory_r;
-
- // Register WriteRxDataToMemory in Wishbone clock domain
- // so it doesn't get out of sync with burst capability indication signals
- always @(posedge WB_CLK_I or posedge Reset)
- if (Reset)
- WriteRxDataToMemory_r <= 0;
- else
- WriteRxDataToMemory_r <= WriteRxDataToMemory;
-
- reg MasterWbTX;
- reg MasterWbRX;
-
- reg [29:0] m_wb_adr_o;
- reg m_wb_cyc_o;
- reg [3:0] m_wb_sel_o;
- reg m_wb_we_o;
-
- wire TxLengthEq0;
- wire TxLengthLt4;
-
- reg BlockingIncrementTxPointer;
- reg [31:2] TxPointerMSB;
- reg [1:0] TxPointerLSB;
- reg [1:0] TxPointerLSB_rst;
- reg [31:2] RxPointerMSB;
- reg [1:0] RxPointerLSB_rst;
-
- wire RxBurstAcc;
- wire RxWordAcc;
- wire RxHalfAcc;
- wire RxByteAcc;
-
- //Latching length from the buffer descriptor;
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- TxLength <= 16'h0;
- else
- if(TxEn & TxEn_q & TxBDRead)
- TxLength <= ram_do[31:16];
- else
- if(MasterWbTX & m_wb_ack_i)
- begin
- if(TxLengthLt4)
- TxLength <= 16'h0;
- else
- if(TxPointerLSB_rst==2'h0)
- TxLength <= TxLength - 3'h4; // Length is subtracted at
- // the data request
- else
- if(TxPointerLSB_rst==2'h1)
- TxLength <= TxLength - 3'h3; // Length is subtracted
- // at the data request
- else
- if(TxPointerLSB_rst==2'h2)
- TxLength <= TxLength - 3'h2; // Length is subtracted
- // at the data request
- else
- if(TxPointerLSB_rst==2'h3)
- TxLength <= TxLength - 3'h1; // Length is subtracted
- // at the data request
- end
- end
-
-
-
- //Latching length from the buffer descriptor;
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- LatchedTxLength <= 16'h0;
- else
- if(TxEn & TxEn_q & TxBDRead)
- LatchedTxLength <= ram_do[31:16];
- end
-
- assign TxLengthEq0 = TxLength == 0;
- assign TxLengthLt4 = TxLength < 4;
-
- reg cyc_cleared;
- reg IncrTxPointer;
-
-
- // Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are
- // latched because TxPointerMSB is only used for word-aligned accesses.
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- TxPointerMSB <= 30'h0;
- else
- if(TxEn & TxEn_q & TxPointerRead)
- TxPointerMSB <= ram_do[31:2];
- else
- if(IncrTxPointer & ~BlockingIncrementTxPointer)
- // TxPointer is word-aligned
- TxPointerMSB <= TxPointerMSB + 1'b1;
- end
-
-
- // Latching 2 MSB bits of the buffer descriptor. Since word accesses are
- // performed, valid data does not necesserly start at byte 0 (could be byte
- // 0, 1, 2 or 3). This signals are used for proper selection of the start
- // byte (TxData and TxByteCnt) are set by this two bits.
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- TxPointerLSB[1:0] <= 0;
- else
- if(TxEn & TxEn_q & TxPointerRead)
- TxPointerLSB[1:0] <= ram_do[1:0];
- end
-
-
- // Latching 2 MSB bits of the buffer descriptor.
- // After the read access, TxLength needs to be decremented for the number of
- // the valid bytes (1 to 4 bytes are valid in the first word). After the
- // first read all bytes are valid so this two bits are reset to zero.
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- TxPointerLSB_rst[1:0] <= 0;
- else
- if(TxEn & TxEn_q & TxPointerRead)
- TxPointerLSB_rst[1:0] <= ram_do[1:0];
- else
- // After first access pointer is word alligned
- if(MasterWbTX & m_wb_ack_i)
- TxPointerLSB_rst[1:0] <= 0;
- end
-
-
- reg [3:0] RxByteSel;
- wire MasterAccessFinished;
-
-
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- BlockingIncrementTxPointer <= 0;
- else
- if(MasterAccessFinished)
- BlockingIncrementTxPointer <= 0;
- else
- if(IncrTxPointer)
- BlockingIncrementTxPointer <= 1'b1;
- end
-
-
- wire TxBufferAlmostFull;
- wire TxBufferFull;
- wire TxBufferEmpty;
- wire TxBufferAlmostEmpty;
- wire SetReadTxDataFromMemory;
-
- reg BlockReadTxDataFromMemory;
-
- assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
-
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- ReadTxDataFromMemory <= 1'b0;
- else
- if(TxLengthEq0 | TxAbortPulse | TxRetryPulse)
- ReadTxDataFromMemory <= 1'b0;
- else
- if(SetReadTxDataFromMemory)
- ReadTxDataFromMemory <= 1'b1;
- end
-
- reg tx_burst_en;
- reg rx_burst_en;
- reg [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt;
-
- wire ReadTxDataFromMemory_2;
- wire tx_burst;
-
-
- wire [31:0] TxData_wb;
- wire ReadTxDataFromFifo_wb;
-
- assign ReadTxDataFromMemory_2 = ReadTxDataFromMemory &
- ~BlockReadTxDataFromMemory | (|tx_burst_cnt);
-
- assign tx_burst = ReadTxDataFromMemory_2 & tx_burst_en;
-
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- BlockReadTxDataFromMemory <= 1'b0;
- else
- if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX &
- (~cyc_cleared) & (!(TxAbortPacket_NotCleared |
- TxRetryPacket_NotCleared)))
- BlockReadTxDataFromMemory <= 1'b1;
- else
- if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket |
- TxRetryPacket)
- BlockReadTxDataFromMemory <= 1'b0;
- end
-
-`define TX_BURST_EN_CONDITION (txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4)))
-
- assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
- wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
- wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
-
- reg [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt;
-
- wire rx_burst;
- wire enough_data_in_rxfifo_for_burst;
- wire enough_data_in_rxfifo_for_burst_plus1;
-
- // Enabling master wishbone access to the memory for two devices TX and RX.
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- begin
- MasterWbTX <= 1'b0;
- MasterWbRX <= 1'b0;
- m_wb_adr_o <= 30'h0;
- m_wb_cyc_o <= 1'b0;
- m_wb_we_o <= 1'b0;
- m_wb_sel_o <= 4'h0;
- cyc_cleared<= 1'b0;
- tx_burst_cnt<= 0;
- rx_burst_cnt<= 0;
- IncrTxPointer<= 1'b0;
- tx_burst_en<= 1'b1;
- rx_burst_en<= 1'b0;
-`ifdef ETH_WISHBONE_B3
- m_wb_cti_o <= 3'b0;
- `ifdef BURST_4BEAT
- m_wb_bte_o <= 2'b00;
- `endif
-`endif
- end
- else
- begin
- // Switching between two stages depends on enable signals
- casex ({MasterWbTX,
- MasterWbRX,
- ReadTxDataFromMemory_2,
- WriteRxDataToMemory_r,
- MasterAccessFinished,
- cyc_cleared,
- tx_burst,
- rx_burst}) // synopsys parallel_case
-
- 8'b00_10_00_10, // Idle and MRB needed
- 8'b10_1x_10_1x, // MRB continues
- 8'b10_10_01_10, // Clear (previously MR) and MRB needed
- 8'b01_1x_01_1x: // Clear (previously MW) and MRB needed
- begin
- MasterWbTX <= 1'b1; // tx burst
- MasterWbRX <= 1'b0;
- m_wb_cyc_o <= 1'b1;
- m_wb_we_o <= 1'b0;
- m_wb_sel_o <= 4'hf;
- cyc_cleared<= 1'b0;
- IncrTxPointer<= 1'b1;
- tx_burst_cnt <= tx_burst_cnt+3'h1;
- if(tx_burst_cnt==0)
- m_wb_adr_o <= TxPointerMSB;
- else
- m_wb_adr_o <= m_wb_adr_o+1'b1;
-
- if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
- begin
- tx_burst_en<= 1'b0;
-`ifdef ETH_WISHBONE_B3
- m_wb_cti_o <= 3'b111;
-`endif
- end
- else
- begin
-`ifdef ETH_WISHBONE_B3
- m_wb_cti_o <= 3'b010;
- `ifdef BURST_4BEAT
- m_wb_bte_o <= 2'b01;
- `endif
-`endif
- end
- end // case: 8'b00_10_00_10,...
-`ifdef ETH_RX_BURST_EN
- 8'b00_x1_00_x1, // Idle and MWB needed
- 8'b01_x1_10_x1, // MWB continues
- 8'b01_01_01_01, // Clear (previously MW) and MWB needed
- 8'b10_x1_01_x1 : // Clear (previously MR) and MWB needed
- begin
- MasterWbTX <= 1'b0; // rx burst
- MasterWbRX <= 1'b1;
- m_wb_cyc_o <= 1'b1;
- m_wb_we_o <= 1'b1;
- m_wb_sel_o <= RxByteSel;
- IncrTxPointer<= 1'b0;
- cyc_cleared<= 1'b0;
- rx_burst_cnt <= rx_burst_cnt+3'h1;
-
- if(rx_burst_cnt==0)
- m_wb_adr_o <= RxPointerMSB;
- else
- m_wb_adr_o <= m_wb_adr_o+1'b1;
-
- if(rx_burst_cnt==(`ETH_BURST_LENGTH-1))
- begin
- rx_burst_en<= 1'b0;
- `ifdef ETH_WISHBONE_B3
- m_wb_cti_o <= 3'b111;
- `endif
- end
- else
- begin
- `ifdef ETH_WISHBONE_B3
- `ifdef BURST_4BEAT
- m_wb_cti_o <= 3'b010;
- m_wb_bte_o <= 2'b01;
- `endif
- `endif
- end
- end // case: 8'b00_x1_00_x1,...
-`endif // `ifdef ETH_RX_BURST_EN
- 8'b00_x1_00_x0 ,//idle and MW is needed (data write to rx buffer)
- 8'b01_x1_00_x0 :// Sometimes gets caught changing states - JB
- begin
- MasterWbTX <= 1'b0;
- MasterWbRX <= !RxBufferEmpty;
- m_wb_adr_o <= RxPointerMSB;
- m_wb_cyc_o <= !RxBufferEmpty;
- m_wb_we_o <= !RxBufferEmpty;
- m_wb_sel_o <= RxByteSel;
- IncrTxPointer<= 1'b0;
-`ifdef ETH_WISHBONE_B3
- `ifdef ETH_RX_BURST_EN
- `ifdef BURST_4BEAT
- if ((RxPointerMSB[3:2]==2'b00) & !RxBufferEmpty &
- enough_data_in_rxfifo_for_burst & !m_wb_cyc_o)
- // Added "& !_m_wb_cyc_o" here to stop burst signals
- // going high during a transfer
- begin
- rx_burst_en<= 1'b1;
- m_wb_cti_o <= 3'b010;
- m_wb_bte_o <= 2'b01;
- rx_burst_cnt<= 1;
- end
- `endif
- `endif
-`endif // `ifdef ETH_WISHBONE_B3
-
- end
- 8'b00_10_00_00 : // idle and MR is needed (data read from tx
- // buffer)
- begin
- MasterWbTX <= 1'b1;
- MasterWbRX <= 1'b0;
- m_wb_adr_o <= TxPointerMSB;
- m_wb_cyc_o <= 1'b1;
- m_wb_we_o <= 1'b0;
- m_wb_sel_o <= 4'hf;
- IncrTxPointer<= 1'b1;
-`ifdef BURST_4BEAT
-
- // Attempt ethernet bugfix, start bursts later
- if ((TxPointerMSB[3:2]==2'b00) && `TX_BURST_EN_CONDITION)
- begin
- `ifdef TX_BURST_EN_VERBOSE
- $display("(%t)(%m): %b enabling tx_burst_en",$time,
- {MasterWbTX,MasterWbRX,ReadTxDataFromMemory_2,
- WriteRxDataToMemory,MasterAccessFinished,
- cyc_cleared,tx_burst,rx_burst});
- `endif
- tx_burst_en<= 1'b1;
- tx_burst_cnt <= 3'h1;
-
- `ifdef ETH_WISHBONE_B3
- m_wb_cti_o <= 3'b010;
- m_wb_bte_o <= 2'b01;
- `endif
- end
-`endif
- end
- 8'b10_10_01_00,// MR and MR is needed (data read from tx buffer)
- 8'b01_1x_01_0x :// MW and MR is needed (data read from tx
- // buffer)
- begin
- MasterWbTX <= 1'b1; // Only switch to TX here
- // when not end of RX
- MasterWbRX <= 1'b0;
- m_wb_adr_o <= TxPointerMSB;
- m_wb_cyc_o <= 1'b1;
- m_wb_we_o <= 1'b0;
- m_wb_sel_o <= 4'hf;
- cyc_cleared<= 1'b0;
- IncrTxPointer<= 1'b1;
-`ifdef BURST_4BEAT
- if ((TxPointerMSB[3:2]==2'b00) & `TX_BURST_EN_CONDITION)
- begin
- `ifdef TX_BURST_EN_VERBOSE
- $display("(%t)(%m): %b enabling tx_burst_en",$time,
- {MasterWbTX,MasterWbRX,
- ReadTxDataFromMemory_2,
- WriteRxDataToMemory,
- MasterAccessFinished,
- cyc_cleared,
- tx_burst,
- rx_burst});
- `endif
- tx_burst_en<= 1'b1;
- tx_burst_cnt <= 3'h1;
- `ifdef ETH_WISHBONE_B3
- m_wb_cti_o <= 3'b010;
- m_wb_bte_o <= 2'b01;
- `endif
- end
-`endif
-
- end
- 8'b01_01_01_00,// MW and MW needed (data write to rx buffer)
- 8'b10_x1_01_x0 ://MR and MW is needed (data write to rx buffer)
- begin
- MasterWbTX <= 1'b0;
- MasterWbRX <= !RxBufferEmpty;
- rx_burst_cnt<= 0;
- m_wb_adr_o <= RxPointerMSB;
- m_wb_cyc_o <= !RxBufferEmpty;
- m_wb_we_o <= !RxBufferEmpty;
- m_wb_sel_o <= RxByteSel;
-`ifdef ETH_WISHBONE_B3
- `ifdef ETH_RX_BURST_EN
- `ifdef BURST_4BEAT
- if ((RxPointerMSB[3:2]==2'b00) &
- enough_data_in_rxfifo_for_burst & !RxBufferEmpty)
- //enough_data_in_rxfifo_for_burst_plus1)
-
-
- begin
- rx_burst_en<= 1'b1;
- m_wb_cti_o <= 3'b010;
- m_wb_bte_o <= 2'b01;
- rx_burst_cnt<= 1;
- end
- `endif
- `endif // `ifdef ETH_RX_BURST_EN
-`endif // `ifdef ETH_WISHBONE_B3
- cyc_cleared<= 1'b0;
- IncrTxPointer<= 1'b0;
- end
- 8'b01_01_10_00,// MW and MW needed (cycle is cleared between
- // previous and next access)
- 8'b01_1x_10_x0,// MW and MW or MR or MRB needed (cycle is
- // cleared between previous and next access)
- 8'b10_10_10_00,// MR and MR needed (cycle is cleared between
- // previous and next access)
- 8'b10_x1_10_0x :// MR and MR or MW or MWB (cycle is cleared
- // between previous and next access)
- begin
- m_wb_cyc_o <= 1'b0;// whatever and master read or write is
- // needed. We need to clear m_wb_cyc_o
- // before next access is started
- cyc_cleared<= 1'b1;
- IncrTxPointer<= 1'b0;
- tx_burst_cnt<= 0;
-`ifdef BURST_4BEAT
- // Caused a bug!
- // if (TxPointerMSB[3:2]==2'b00)
- //tx_burst_en<= `TX_BURST_EN_CONDITION;
- // Set this to 0 here
- tx_burst_en<= 0;
-
-`endif
- rx_burst_cnt<= 0;
-`ifdef ETH_WISHBONE_B3
- m_wb_bte_o <= 2'b00;
- m_wb_cti_o <= 3'b0;
-`endif
- end
- 8'bxx_00_10_00,// whatever and no master read or write is needed
- // (ack or err comes finishing previous access)
- 8'bxx_00_01_00 : // Between cyc_cleared request was cleared
- begin
- MasterWbTX <= 1'b0;
- MasterWbRX <= 1'b0;
- m_wb_cyc_o <= 1'b0;
- cyc_cleared<= 1'b0;
- IncrTxPointer<= 1'b0;
- rx_burst_cnt<= 0;
- m_wb_bte_o <= 2'b00;
- m_wb_cti_o <= 3'b0;
- end
- 8'b00_00_00_00: // whatever and no master read or write is
- // needed (ack or err comes finishing previous
- // access)
- begin
- tx_burst_cnt<= 0;
-`ifdef BURST_4BEAT
-
- // This caused tx_burst to remain set between
- // transmits, and sometimes we would burst immediately
- // and maybe get the wrong data because the offset of
- // the buffer pointer wasn't 16-byte aligned.
- //if (TxPointerMSB[3:2]==2'b00)
- // tx_burst_en<= `TX_BURST_EN_CONDITION;
-
- // Fix for transmit problems... maybe - jb
- if(TxEn & TxEn_q & TxPointerRead & (ram_do[3:0]===4'h0))
- begin
- `ifdef TX_BURST_EN_VERBOSE
- $display("(%t)(%m): %b enabling tx_burst_en",$time,
- {MasterWbTX,MasterWbRX,ReadTxDataFromMemory_2,
- WriteRxDataToMemory,MasterAccessFinished,
- cyc_cleared,tx_burst,rx_burst});
- `endif
- tx_burst_en<= `TX_BURST_EN_CONDITION;
- end
- else
- tx_burst_en<= 0;
-`endif
- end
- default: // Don't touch
- begin
- MasterWbTX <= MasterWbTX;
- MasterWbRX <= MasterWbRX;
- m_wb_cyc_o <= m_wb_cyc_o;
- m_wb_sel_o <= m_wb_sel_o;
- IncrTxPointer<= IncrTxPointer;
- end
- endcase
- end
- end
-
-
- wire TxFifoClear;
-
- assign TxFifoClear = (TxAbortPacket | TxRetryPacket | StartTxPointerRead);
-
- eth_fifo
- #(
- `ETH_TX_FIFO_DATA_WIDTH,
- `ETH_TX_FIFO_DEPTH,
- `ETH_TX_FIFO_CNT_WIDTH
- )
- tx_fifo
- (
- .data_in(m_wb_dat_i),
- .data_out(TxData_wb),
- .clk(WB_CLK_I),
- .reset(Reset),
- .write(MasterWbTX & m_wb_ack_i),
- .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
- .clear(TxFifoClear),
- .full(TxBufferFull),
- .almost_full(TxBufferAlmostFull),
- .almost_empty(TxBufferAlmostEmpty),
- .empty(TxBufferEmpty),
- .cnt(txfifo_cnt)
- );
-
-
- reg StartOccured;
- reg TxStartFrm_sync1;
- reg TxStartFrm_sync2;
- reg TxStartFrm_syncb1;
- reg TxStartFrm_syncb2;
-
-
-
- // Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- TxStartFrm_wb <= 1'b0;
- else
- if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0))
- TxStartFrm_wb <= 1'b1;
- else
- if(TxStartFrm_syncb2)
- TxStartFrm_wb <= 1'b0;
- end
-
- // StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's
- // blocked.
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- StartOccured <= 1'b0;
- else
- if(TxStartFrm_wb)
- StartOccured <= 1'b1;
- else
- if(ResetTxBDReady)
- StartOccured <= 1'b0;
- end
-
- // Synchronizing TxStartFrm_wb to MTxClk
- always @ (posedge MTxClk or posedge Reset)
- begin
- if(Reset)
- TxStartFrm_sync1 <= 1'b0;
- else
- TxStartFrm_sync1 <= TxStartFrm_wb;
- end
-
- always @ (posedge MTxClk or posedge Reset)
- begin
- if(Reset)
- TxStartFrm_sync2 <= 1'b0;
- else
- TxStartFrm_sync2 <= TxStartFrm_sync1;
- end
-
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- TxStartFrm_syncb1 <= 1'b0;
- else
- TxStartFrm_syncb1 <= TxStartFrm_sync2;
- end
-
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- TxStartFrm_syncb2 <= 1'b0;
- else
- TxStartFrm_syncb2 <= TxStartFrm_syncb1;
- end
-
- always @ (posedge MTxClk or posedge Reset)
- begin
- if(Reset)
- TxStartFrm <= 1'b0;
- else
- if(TxStartFrm_sync2)
- TxStartFrm <= 1'b1;
- else
- if(TxUsedData_q | ~TxStartFrm_sync2 &
- (TxRetry & (~TxRetry_q) | TxAbort & (~TxAbort_q)))
- TxStartFrm <= 1'b0;
- end
- // End: Generation of the TxStartFrm_wb which is then synchronized to the
- // MTxClk
-
-
- // TxEndFrm_wb: indicator of the end of frame
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- TxEndFrm_wb <= 1'b0;
- else
- if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData)
- TxEndFrm_wb <= 1'b1;
- else
- if(TxRetryPulse | TxDonePulse | TxAbortPulse)
- TxEndFrm_wb <= 1'b0;
- end
-
-
- // Marks which bytes are valid within the word.
- assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
-
- reg LatchValidBytes;
- reg LatchValidBytes_q;
-
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- LatchValidBytes <= 1'b0;
- else
- if(TxLengthLt4 & TxBDReady)
- LatchValidBytes <= 1'b1;
- else
- LatchValidBytes <= 1'b0;
- end
-
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- LatchValidBytes_q <= 1'b0;
- else
- LatchValidBytes_q <= LatchValidBytes;
- end
-
-
- // Latching valid bytes
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- TxValidBytesLatched <= 2'h0;
- else
- if(LatchValidBytes & ~LatchValidBytes_q)
- TxValidBytesLatched <= TxValidBytes;
- else
- if(TxRetryPulse | TxDonePulse | TxAbortPulse)
- TxValidBytesLatched <= 2'h0;
- end
-
-
- assign TxIRQEn = TxStatus[14];
- assign WrapTxStatusBit = TxStatus[13];
- assign PerPacketPad = TxStatus[12];
- assign PerPacketCrcEn = TxStatus[11];
-
-
- assign RxIRQEn = RxStatus[14];
- assign WrapRxStatusBit = RxStatus[13];
-
-
- // Temporary Tx and Rx buffer descriptor address
-`ifdef TXBD_POLL
- assign TempTxBDAddress[7:1] = {7{ (TxStatusWrite|TxBDNotReady) & ~WrapTxStatusBit}} & (TxBDAddress + 1'b1) ; // Tx BD increment or wrap (last BD) -- jb
-`else
- assign TempTxBDAddress[7:1] = {7{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 1'b1) ; // Tx BD increment or wrap (last BD)
-`endif
- assign TempRxBDAddress[7:1] = {7{ WrapRxStatusBit}} & (r_TxBDNum[6:0]) | // Using first Rx BD
- {7{~WrapRxStatusBit}} & (RxBDAddress + 1'b1) ; // Using next Rx BD (incremenrement address)
-
-
- // Latching Tx buffer descriptor address
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- TxBDAddress <= 7'h0;
- else if (r_TxEn & (~r_TxEn_q))
- TxBDAddress <= 7'h0;
-`ifdef TXBD_POLL
- else if (TxStatusWrite | TxBDNotReady) // -- jb
-`else
- else if (TxStatusWrite)
-`endif
- TxBDAddress <= TempTxBDAddress;
- end
-
-
- // Latching Rx buffer descriptor address
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- RxBDAddress <= 7'h0;
- else if(r_RxEn & (~r_RxEn_q))
- RxBDAddress <= r_TxBDNum[6:0];
- else if(RxStatusWrite)
- RxBDAddress <= TempRxBDAddress;
- end
-
- wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0],
- RetryLimit, LateCollLatched, DeferLatched,
- CarrierSenseLost};
-
- assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 4'h0,
- RxStatusInLatched};
- assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0,
- TxStatusInLatched};
-
-
- // Signals used for various purposes
- assign TxRetryPulse = TxRetry_wb & ~TxRetry_wb_q;
- assign TxDonePulse = TxDone_wb & ~TxDone_wb_q;
- assign TxAbortPulse = TxAbort_wb & ~TxAbort_wb_q;
-
-
-
- // Generating delayed signals
- always @ (posedge MTxClk or posedge Reset)
- begin
- if(Reset)
- begin
- TxAbort_q <= 1'b0;
- TxRetry_q <= 1'b0;
- TxUsedData_q <= 1'b0;
- end
- else
- begin
- TxAbort_q <= TxAbort;
- TxRetry_q <= TxRetry;
- TxUsedData_q <= TxUsedData;
- end
- end
-
- // Generating delayed signals
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- begin
- TxDone_wb_q <= 1'b0;
- TxAbort_wb_q <= 1'b0;
- TxRetry_wb_q <= 1'b0;
- end
- else
- begin
- TxDone_wb_q <= TxDone_wb;
- TxAbort_wb_q <= TxAbort_wb;
- TxRetry_wb_q <= TxRetry_wb;
- end
- end
-
-
- reg TxAbortPacketBlocked;
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- TxAbortPacket <= 1'b0;
- else
- if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished &
- (~TxAbortPacketBlocked) | TxAbort_wb & (~MasterWbTX) &
- (~TxAbortPacketBlocked))
- TxAbortPacket <= 1'b1;
- else
- TxAbortPacket <= 1'b0;
- end
-
-
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- TxAbortPacket_NotCleared <= 1'b0;
- else
- if(TxEn & TxEn_q & TxAbortPacket_NotCleared)
- TxAbortPacket_NotCleared <= 1'b0;
- else
- if(TxAbort_wb & (~tx_burst_en) & MasterWbTX &
- MasterAccessFinished & (~TxAbortPacketBlocked) | TxAbort_wb &
- (~MasterWbTX) & (~TxAbortPacketBlocked))
- TxAbortPacket_NotCleared <= 1'b1;
- end
-
-
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- TxAbortPacketBlocked <= 1'b0;
- else
- if(!TxAbort_wb & TxAbort_wb_q)
- TxAbortPacketBlocked <= 1'b0;
- else
- if(TxAbortPacket)
- TxAbortPacketBlocked <= 1'b1;
- end
-
-
- reg TxRetryPacketBlocked;
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- TxRetryPacket <= 1'b0;
- else
- if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished &
- !TxRetryPacketBlocked | TxRetry_wb & !MasterWbTX &
- !TxRetryPacketBlocked)
- TxRetryPacket <= 1'b1;
- else
- TxRetryPacket <= 1'b0;
- end
-
-
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- TxRetryPacket_NotCleared <= 1'b0;
- else
- if(StartTxBDRead)
- TxRetryPacket_NotCleared <= 1'b0;
- else
- if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished &
- !TxRetryPacketBlocked | TxRetry_wb & !MasterWbTX &
- !TxRetryPacketBlocked)
- TxRetryPacket_NotCleared <= 1'b1;
- end
-
-
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- TxRetryPacketBlocked <= 1'b0;
- else
- if(!TxRetry_wb & TxRetry_wb_q)
- TxRetryPacketBlocked <= 1'b0;
- else
- if(TxRetryPacket)
- TxRetryPacketBlocked <= 1'b1;
- end
-
-
- reg TxDonePacketBlocked;
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- TxDonePacket <= 1'b0;
- else
- if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished &
- !TxDonePacketBlocked | TxDone_wb & !MasterWbTX &
- !TxDonePacketBlocked)
- TxDonePacket <= 1'b1;
- else
- TxDonePacket <= 1'b0;
- end
-
-
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- TxDonePacket_NotCleared <= 1'b0;
- else
- if(TxEn & TxEn_q & TxDonePacket_NotCleared)
- TxDonePacket_NotCleared <= 1'b0;
- else
- if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished
- & (~TxDonePacketBlocked) | TxDone_wb & !MasterWbTX
- & (~TxDonePacketBlocked))
- TxDonePacket_NotCleared <= 1'b1;
- end
-
-
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- TxDonePacketBlocked <= 1'b0;
- else
- if(!TxDone_wb & TxDone_wb_q)
- TxDonePacketBlocked <= 1'b0;
- else
- if(TxDonePacket)
- TxDonePacketBlocked <= 1'b1;
- end
-
-
- // Indication of the last word
- always @ (posedge MTxClk or posedge Reset)
- begin
- if(Reset)
- LastWord <= 1'b0;
- else
- if((TxEndFrm | TxAbort | TxRetry) & Flop)
- LastWord <= 1'b0;
- else
- if(TxUsedData & Flop & TxByteCnt == 2'h3)
- LastWord <= TxEndFrm_wb;
- end
-
-
- // Tx end frame generation
- always @ (posedge MTxClk or posedge Reset)
- begin
- if(Reset)
- TxEndFrm <= 1'b0;
- else
- if(Flop & TxEndFrm | TxAbort | TxRetry_q)
- TxEndFrm <= 1'b0;
- else
- if(Flop & LastWord)
- begin
- case (TxValidBytesLatched) // synopsys parallel_case
- 1 : TxEndFrm <= TxByteCnt == 2'h0;
- 2 : TxEndFrm <= TxByteCnt == 2'h1;
- 3 : TxEndFrm <= TxByteCnt == 2'h2;
- 0 : TxEndFrm <= TxByteCnt == 2'h3;
- default : TxEndFrm <= 1'b0;
- endcase
- end
- end
-
-
- // Tx data selection (latching)
- always @ (posedge MTxClk or posedge Reset)
- begin
- if(Reset)
- TxData <= 0;
- else
- if(TxStartFrm_sync2 & ~TxStartFrm)
- case(TxPointerLSB) // synopsys parallel_case
- 2'h0 : TxData <= TxData_wb[31:24];// Big Endian Byte Ordering
- 2'h1 : TxData <= TxData_wb[23:16];// Big Endian Byte Ordering
- 2'h2 : TxData <= TxData_wb[15:08];// Big Endian Byte Ordering
- 2'h3 : TxData <= TxData_wb[07:00];// Big Endian Byte Ordering
- endcase
- else
- if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3)
- TxData <= TxData_wb[31:24];// Big Endian Byte Ordering
- else
- if(TxUsedData & Flop)
- begin
- case(TxByteCnt) // synopsys parallel_case
- // Big Endian Byte Ordering
- 0 : TxData <= TxDataLatched[31:24];
- 1 : TxData <= TxDataLatched[23:16];
- 2 : TxData <= TxDataLatched[15:8];
- 3 : TxData <= TxDataLatched[7:0];
- endcase
- end
- end
-
-
- // Latching tx data
- always @ (posedge MTxClk or posedge Reset)
- begin
- if(Reset)
- TxDataLatched[31:0] <= 32'h0;
- else
- if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop &
- TxByteCnt == 2'h3 | TxStartFrm & TxUsedData & Flop &
- TxByteCnt == 2'h0)
- TxDataLatched[31:0] <= TxData_wb[31:0];
- end
-
-
- // Tx under run
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- TxUnderRun_wb <= 1'b0;
- else
- if(TxAbortPulse)
- TxUnderRun_wb <= 1'b0;
- else
- if(TxBufferEmpty & ReadTxDataFromFifo_wb)
- TxUnderRun_wb <= 1'b1;
- end
-
-
- reg TxUnderRun_sync1;
-
- // Tx under run
- always @ (posedge MTxClk or posedge Reset)
- begin
- if(Reset)
- TxUnderRun_sync1 <= 1'b0;
- else
- if(TxUnderRun_wb)
- TxUnderRun_sync1 <= 1'b1;
- else
- if(BlockingTxStatusWrite_sync2)
- TxUnderRun_sync1 <= 1'b0;
- end
-
- // Tx under run
- always @ (posedge MTxClk or posedge Reset)
- begin
- if(Reset)
- TxUnderRun <= 1'b0;
- else
- if(BlockingTxStatusWrite_sync2)
- TxUnderRun <= 1'b0;
- else
- if(TxUnderRun_sync1)
- TxUnderRun <= 1'b1;
- end
-
-
- // Tx Byte counter
- always @ (posedge MTxClk or posedge Reset)
- begin
- if(Reset)
- TxByteCnt <= 2'h0;
- else
- if(TxAbort_q | TxRetry_q)
- TxByteCnt <= 2'h0;
- else
- if(TxStartFrm & ~TxUsedData)
- case(TxPointerLSB) // synopsys parallel_case
- 2'h0 : TxByteCnt <= 2'h1;
- 2'h1 : TxByteCnt <= 2'h2;
- 2'h2 : TxByteCnt <= 2'h3;
- 2'h3 : TxByteCnt <= 2'h0;
- endcase
- else
- if(TxUsedData & Flop)
- TxByteCnt <= TxByteCnt + 1'b1;
- end
-
-
- // Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
- reg ReadTxDataFromFifo_sync1;
- reg ReadTxDataFromFifo_sync2;
- reg ReadTxDataFromFifo_sync3;
- reg ReadTxDataFromFifo_syncb1;
- reg ReadTxDataFromFifo_syncb2;
- reg ReadTxDataFromFifo_syncb3;
-
-
- always @ (posedge MTxClk or posedge Reset)
- begin
- if(Reset)
- ReadTxDataFromFifo_tck <= 1'b0;
- else
- if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop &
- TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop &
- TxByteCnt == 2'h0)
- ReadTxDataFromFifo_tck <= 1'b1;
- else
- if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3)
- ReadTxDataFromFifo_tck <= 1'b0;
- end
-
- // Synchronizing TxStartFrm_wb to MTxClk
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- ReadTxDataFromFifo_sync1 <= 1'b0;
- else
- ReadTxDataFromFifo_sync1 <= ReadTxDataFromFifo_tck;
- end
-
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- ReadTxDataFromFifo_sync2 <= 1'b0;
- else
- ReadTxDataFromFifo_sync2 <= ReadTxDataFromFifo_sync1;
- end
-
- always @ (posedge MTxClk or posedge Reset)
- begin
- if(Reset)
- ReadTxDataFromFifo_syncb1 <= 1'b0;
- else
- ReadTxDataFromFifo_syncb1 <= ReadTxDataFromFifo_sync2;
- end
-
- always @ (posedge MTxClk or posedge Reset)
- begin
- if(Reset)
- ReadTxDataFromFifo_syncb2 <= 1'b0;
- else
- ReadTxDataFromFifo_syncb2 <= ReadTxDataFromFifo_syncb1;
- end
-
- always @ (posedge MTxClk or posedge Reset)
- begin
- if(Reset)
- ReadTxDataFromFifo_syncb3 <= 1'b0;
- else
- ReadTxDataFromFifo_syncb3 <= ReadTxDataFromFifo_syncb2;
- end
-
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- ReadTxDataFromFifo_sync3 <= 1'b0;
- else
- ReadTxDataFromFifo_sync3 <= ReadTxDataFromFifo_sync2;
- end
-
- assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 &
- ~ReadTxDataFromFifo_sync3;
- // End: Generation of the ReadTxDataFromFifo_tck signal and synchronization
- // to the WB_CLK_I
-
-
- // Synchronizing TxRetry signal (synchronized to WISHBONE clock)
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- TxRetrySync1 <= 1'b0;
- else
- TxRetrySync1 <= TxRetry;
- end
-
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- TxRetry_wb <= 1'b0;
- else
- TxRetry_wb <= TxRetrySync1;
- end
-
-
- // Synchronized TxDone_wb signal (synchronized to WISHBONE clock)
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- TxDoneSync1 <= 1'b0;
- else
- TxDoneSync1 <= TxDone;
- end
-
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- TxDone_wb <= 1'b0;
- else
- TxDone_wb <= TxDoneSync1;
- end
-
- // Synchronizing TxAbort signal (synchronized to WISHBONE clock)
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- TxAbortSync1 <= 1'b0;
- else
- TxAbortSync1 <= TxAbort;
- end
-
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- TxAbort_wb <= 1'b0;
- else
- TxAbort_wb <= TxAbortSync1;
- end
-
-
- reg RxAbortSync1;
- reg RxAbortSync2;
- reg RxAbortSync3;
- reg RxAbortSync4;
- reg RxAbortSyncb1;
- reg RxAbortSyncb2;
-
- assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4 |
- r_RxEn & ~r_RxEn_q;
-
- // Reading the Rx buffer descriptor
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- RxBDRead <= 1'b0;
- else
- if(StartRxBDRead)
- RxBDRead <= 1'b1;
- else
- if(RxBDReady)
- RxBDRead <= 1'b0;
- end
-
-
- // Reading of the next receive buffer descriptor starts after reception
- // status is written to the previous one.
-
- // Latching READY status of the Rx buffer descriptor
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- RxBDReady <= 1'b0;
- else
- if(RxPointerRead)
- RxBDReady <= 1'b0;
- else
- if(RxEn & RxEn_q & RxBDRead)
- // RxBDReady is sampled only once at the beginning
- RxBDReady <= ram_do[15];
- end // always @ (posedge WB_CLK_I or posedge Reset)
-
- // Indicate we just read the RX buffer descriptor and that RxBDReady is
- // valid.
- reg rx_just_read_bd;
- always @ (posedge WB_CLK_I or posedge Reset)
- if(Reset)
- rx_just_read_bd <= 0;
- else if (rx_just_read_bd)
- rx_just_read_bd <= 0;
- else
- rx_just_read_bd <= (RxEn & RxEn_q & RxBDRead);
-
- // Signal to indicate we've checked and the RxBD we want to use is not free
- reg rx_waiting_for_bd_to_become_free;
- always @ (posedge WB_CLK_I or posedge Reset)
- if(Reset)
- rx_waiting_for_bd_to_become_free <= 0;
- else if (rx_just_read_bd & !RxBDReady)
- // Assert if we read the BD and it's not cool
- rx_waiting_for_bd_to_become_free <= 1;
- else if (RxBDOK)
- rx_waiting_for_bd_to_become_free <= 0;
-
-
-
- // Latching Rx buffer descriptor status
- // Data is avaliable one cycle after the access is started (at that time
- // signal RxEn is not active)
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- RxStatus <= 2'h0;
- else
- if(RxEn & RxEn_q & RxBDRead)
- RxStatus <= ram_do[14:13];
- end
-
-
- // RxBDOK generation
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- RxBDOK <= 1'b0;
- else
- if(rx_wb_writeback_finished | RxAbortSync2 & ~RxAbortSync3 |
- ~r_RxEn & r_RxEn_q)
- RxBDOK <= 1'b0;
- else
- if(RxBDReady)
- RxBDOK <= 1'b1;
- end
-
- // Reading Rx BD pointer
- assign StartRxPointerRead = RxBDRead & RxBDReady;
-
- // Reading Tx BD Pointer
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- RxPointerRead <= 1'b0;
- else
- if(StartRxPointerRead)
- RxPointerRead <= 1'b1;
- else
- if(RxEn & RxEn_q)
- RxPointerRead <= 1'b0;
- end
-
-
- //Latching Rx buffer pointer from buffer descriptor;
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- RxPointerMSB <= 30'h0;
- else
- if(RxEn & RxEn_q & RxPointerRead)
- RxPointerMSB <= ram_do[31:2];
- else
- if(MasterWbRX & m_wb_ack_i)
- // Word access (always word access. m_wb_sel_o are used for
- // selecting bytes)
- RxPointerMSB <= RxPointerMSB + 1'b1;
- end
-
-
- //Latching last addresses from buffer descriptor (used as byte-half-word
- // indicator);
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- RxPointerLSB_rst[1:0] <= 0;
- else
- if(MasterWbRX & m_wb_ack_i)
- // After first write all RxByteSel are active
- RxPointerLSB_rst[1:0] <= 0;
- else
- if(RxEn & RxEn_q & RxPointerRead)
- RxPointerLSB_rst[1:0] <= ram_do[1:0];
- end
-
-
- always @ (RxPointerLSB_rst)
- begin
- case(RxPointerLSB_rst[1:0]) // synopsys parallel_case
- 2'h0 : RxByteSel[3:0] = 4'hf;
- 2'h1 : RxByteSel[3:0] = 4'h7;
- 2'h2 : RxByteSel[3:0] = 4'h3;
- 2'h3 : RxByteSel[3:0] = 4'h1;
- endcase
- end
-
-
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- RxEn_needed <= 1'b0;
- else
- if(/*~RxReady &*/ r_RxEn & WbEn & ~WbEn_q)
- RxEn_needed <= 1'b1;
- else
- if(RxPointerRead & RxEn & RxEn_q)
- RxEn_needed <= 1'b0;
- end
-
-
- // Reception status is written back to the buffer descriptor after the end
- // of frame is detected.
- assign RxStatusWrite = rx_wb_writeback_finished & RxEn & RxEn_q;
-
- reg RxEnableWindow;
-
- // Indicating that last byte is being reveived
- always @ (posedge MRxClk or posedge Reset)
- begin
- if(Reset)
- LastByteIn <= 1'b0;
- else
- if(ShiftWillEnd & (&RxByteCnt) | RxAbort)
- LastByteIn <= 1'b0;
- else
- if(RxValid /*& RxReady*/& RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
- LastByteIn <= 1'b1;
- end
-
- assign StartShiftWillEnd = LastByteIn | RxValid & RxEndFrm & (&RxByteCnt) &
- RxEnableWindow;
-
- // Indicating that data reception will end
- always @ (posedge MRxClk or posedge Reset)
- begin
- if(Reset)
- ShiftWillEnd <= 1'b0;
- else
- if(ShiftEnded_rck | RxAbort)
- ShiftWillEnd <= 1'b0;
- else
- if(StartShiftWillEnd)
- ShiftWillEnd <= 1'b1;
- end
-
- // Receive byte counter
- always @ (posedge MRxClk or posedge Reset)
- begin
- if(Reset)
- RxByteCnt <= 2'h0;
- else
- if(ShiftEnded_rck | RxAbort)
- RxByteCnt <= 2'h0;
- else
- if(RxValid & RxStartFrm /*& RxReady*/)
- case(RxPointerLSB_rst) // synopsys parallel_case
- 2'h0 : RxByteCnt <= 2'h1;
- 2'h1 : RxByteCnt <= 2'h2;
- 2'h2 : RxByteCnt <= 2'h3;
- 2'h3 : RxByteCnt <= 2'h0;
- endcase
- else
- if(RxValid & RxEnableWindow /*& RxReady*/ | LastByteIn)
- RxByteCnt <= RxByteCnt + 1'b1;
- end
-
-
- // Indicates how many bytes are valid within the last word
- always @ (posedge MRxClk or posedge Reset)
- begin
- if(Reset)
- RxValidBytes <= 2'h1;
- else
- if(RxValid & RxStartFrm)
- case(RxPointerLSB_rst) // synopsys parallel_case
- 2'h0 : RxValidBytes <= 2'h1;
- 2'h1 : RxValidBytes <= 2'h2;
- 2'h2 : RxValidBytes <= 2'h3;
- 2'h3 : RxValidBytes <= 2'h0;
- endcase
- else
- if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
- RxValidBytes <= RxValidBytes + 1'b1;
- end
-
-
- always @ (posedge MRxClk or posedge Reset)
- begin
- if(Reset)
- RxDataLatched1 <= 24'h0;
- else
- if(RxValid /*& RxReady*/ & ~LastByteIn)
- if(RxStartFrm)
- begin
- case(RxPointerLSB_rst) // synopsys parallel_case
- // Big Endian Byte Ordering
- 2'h0: RxDataLatched1[31:24] <= RxData;
- 2'h1: RxDataLatched1[23:16] <= RxData;
- 2'h2: RxDataLatched1[15:8] <= RxData;
- 2'h3: RxDataLatched1 <= RxDataLatched1;
- endcase
- end
- else if (RxEnableWindow)
- begin
- case(RxByteCnt) // synopsys parallel_case
- // Big Endian Byte Ordering
- 2'h0: RxDataLatched1[31:24] <= RxData;
- 2'h1: RxDataLatched1[23:16] <= RxData;
- 2'h2: RxDataLatched1[15:8] <= RxData;
- 2'h3: RxDataLatched1 <= RxDataLatched1;
- endcase
- end
- end
-
- wire SetWriteRxDataToFifo;
-
- // Assembling data that will be written to the rx_fifo
- always @ (posedge MRxClk or posedge Reset)
- begin
- if(Reset)
- RxDataLatched2 <= 32'h0;
- else
- if(SetWriteRxDataToFifo & ~ShiftWillEnd)
- // Big Endian Byte Ordering
- RxDataLatched2 <= {RxDataLatched1[31:8], RxData};
- else
- if(SetWriteRxDataToFifo & ShiftWillEnd)
- case(RxValidBytes) // synopsys parallel_case
- // Big Endian Byte Ordering
- 0 : RxDataLatched2 <= {RxDataLatched1[31:8], RxData};
- 1 : RxDataLatched2 <= {RxDataLatched1[31:24], 24'h0};
- 2 : RxDataLatched2 <= {RxDataLatched1[31:16], 16'h0};
- 3 : RxDataLatched2 <= {RxDataLatched1[31:8], 8'h0};
- endcase
- end
-
-
- reg WriteRxDataToFifoSync1;
- reg WriteRxDataToFifoSync2;
- reg WriteRxDataToFifoSync3;
-
-
- // Indicating start of the reception process
- assign SetWriteRxDataToFifo = (RxValid &/* RxReady &*/ ~RxStartFrm &
- RxEnableWindow & (&RxByteCnt)) |
- (RxValid &/* RxReady &*/ RxStartFrm &
- (&RxPointerLSB_rst)) |
- (ShiftWillEnd & LastByteIn & (&RxByteCnt));
-
- always @ (posedge MRxClk or posedge Reset)
- begin
- if(Reset)
- WriteRxDataToFifo <= 1'b0;
- else
- if(SetWriteRxDataToFifo & ~RxAbort)
- WriteRxDataToFifo <= 1'b1;
- else
- if(WriteRxDataToFifoSync2 | RxAbort)
- WriteRxDataToFifo <= 1'b0;
- end
-
-
-
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- WriteRxDataToFifoSync1 <= 1'b0;
- else
- if(WriteRxDataToFifo)
- WriteRxDataToFifoSync1 <= 1'b1;
- else
- WriteRxDataToFifoSync1 <= 1'b0;
- end
-
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- WriteRxDataToFifoSync2 <= 1'b0;
- else
- WriteRxDataToFifoSync2 <= WriteRxDataToFifoSync1;
- end
-
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- WriteRxDataToFifoSync3 <= 1'b0;
- else
- WriteRxDataToFifoSync3 <= WriteRxDataToFifoSync2;
- end
-
- wire WriteRxDataToFifo_wb;
- assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 &
- ~WriteRxDataToFifoSync3;
- // Receive fifo selection register - JB
- reg [3:0] rx_shift_ended_wb_shr;
- reg rx_ethside_fifo_sel;
- reg rx_wbside_fifo_sel;
-
- // Shift in this - our detection of end of data RX
- always @(posedge WB_CLK_I)
- rx_shift_ended_wb_shr <= {rx_shift_ended_wb_shr[2:0],
- ShiftEndedSync1 & ~ShiftEndedSync2};
-
-
- always @ (posedge WB_CLK_I or posedge Reset)
- if(Reset)
- rx_ethside_fifo_sel <= 0;
- else
- if(rx_shift_ended_wb_shr[3:2] == 2'b01)
- // Switch over whenever we've finished receiving last frame's data
- rx_ethside_fifo_sel <= ~rx_ethside_fifo_sel;
-
- // Wishbone side looks at other FIFO when we write back the status of this
- // received frame
- always @ (posedge WB_CLK_I or posedge Reset)
- if(Reset)
- rx_wbside_fifo_sel <= 0;
- else
- if(rx_wb_writeback_finished & RxEn & RxEn_q)
- // Switch over whenever we've finished receiving last frame's data
- rx_wbside_fifo_sel <= ~rx_wbside_fifo_sel;
-
- reg LatchedRxStartFrm;
- reg SyncRxStartFrm;
- reg SyncRxStartFrm_q;
- reg SyncRxStartFrm_q2;
- wire RxFifoReset;
-
- always @ (posedge MRxClk or posedge Reset)
- begin
- if(Reset)
- LatchedRxStartFrm <= 0;
- else
- if(RxStartFrm & ~SyncRxStartFrm_q)
- LatchedRxStartFrm <= 1;
- else
- if(SyncRxStartFrm_q)
- LatchedRxStartFrm <= 0;
- end
-
-
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- SyncRxStartFrm <= 0;
- else
- if(LatchedRxStartFrm)
- SyncRxStartFrm <= 1;
- else
- SyncRxStartFrm <= 0;
- end
-
-
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- SyncRxStartFrm_q <= 0;
- else
- SyncRxStartFrm_q <= SyncRxStartFrm;
- end
-
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- SyncRxStartFrm_q2 <= 0;
- else
- SyncRxStartFrm_q2 <= SyncRxStartFrm_q;
- end
- wire rx_startfrm_wb;
- assign rx_startfrm_wb = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
-
-
- assign RxFifoReset = rx_startfrm_wb;
-
-
- wire [31:0] rx_fifo0_data_out;
- wire rx_fifo0_write;
- wire rx_fifo0_read;
- wire rx_fifo0_clear;
- wire rx_fifo0_full;
- wire rx_fifo0_afull;
- wire rx_fifo0_empty;
- wire rx_fifo0_aempty;
-
-
- wire [31:0] rx_fifo1_data_out;
- wire rx_fifo1_write;
- wire rx_fifo1_read;
- wire rx_fifo1_clear;
- wire rx_fifo1_full;
- wire rx_fifo1_afull;
- wire rx_fifo1_empty;
- wire rx_fifo1_aempty;
-
- wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rx_fifo0_cnt;
- wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rx_fifo1_cnt;
-
- // RX FIFO buffer 0 controls
- assign rx_fifo0_write = (!rx_ethside_fifo_sel) & WriteRxDataToFifo_wb &
- ~rx_fifo0_full;
-
- assign rx_fifo0_read = (!rx_wbside_fifo_sel) & MasterWbRX & m_wb_ack_i &
- ~rx_fifo0_empty;
-
- assign rx_fifo0_clear = (!rx_ethside_fifo_sel) & RxFifoReset;
-
- // RX FIFO buffer 1 controls
- assign rx_fifo1_write = (rx_ethside_fifo_sel) & WriteRxDataToFifo_wb &
- ~rx_fifo1_full;
-
- assign rx_fifo1_read = (rx_wbside_fifo_sel) & MasterWbRX & m_wb_ack_i &
- ~rx_fifo1_empty;
-
- assign rx_fifo1_clear = (rx_ethside_fifo_sel) & RxFifoReset;
-
- eth_fifo #(
- `ETH_RX_FIFO_DATA_WIDTH,
- `ETH_RX_FIFO_DEPTH,
- `ETH_RX_FIFO_CNT_WIDTH
- )
- rx_fifo0 (
- .clk (WB_CLK_I ),
- .reset (Reset ),
- // Inputs
- .data_in (RxDataLatched2 ),
- .write (rx_fifo0_write ),
- .read (rx_fifo0_read ),
- .clear (rx_fifo0_clear ),
- // Outputs
- .data_out (rx_fifo0_data_out),
- .full (rx_fifo0_full ),
- .almost_full (),
- .almost_empty (rx_fifo0_aempty ),
- .empty (rx_fifo0_empty ),
- .cnt (rx_fifo0_cnt )
- );
-
- eth_fifo #(
- `ETH_RX_FIFO_DATA_WIDTH,
- `ETH_RX_FIFO_DEPTH,
- `ETH_RX_FIFO_CNT_WIDTH
- )
- rx_fifo1 (
- .clk (WB_CLK_I ),
- .reset (Reset ),
- // Inputs
- .data_in (RxDataLatched2 ),
- .write (rx_fifo1_write ),
- .read (rx_fifo1_read ),
- .clear (rx_fifo1_clear ),
- // Outputs
- .data_out (rx_fifo1_data_out),
- .full (rx_fifo1_full ),
- .almost_full (),
- .almost_empty (rx_fifo1_aempty ),
- .empty (rx_fifo1_empty ),
- .cnt (rx_fifo1_cnt )
- );
-
- assign m_wb_dat_o = rx_wbside_fifo_sel ?
- rx_fifo1_data_out : rx_fifo0_data_out;
- assign rxfifo_cnt = rx_wbside_fifo_sel ?
- rx_fifo1_cnt : rx_fifo0_cnt;
-
- assign RxBufferAlmostEmpty = rx_wbside_fifo_sel ?
- rx_fifo1_aempty : rx_fifo0_aempty;
-
- assign RxBufferEmpty = rx_wbside_fifo_sel ?
- rx_fifo1_empty : rx_fifo0_empty;
-
- assign RxBufferFull = rx_wbside_fifo_sel ?
- rx_fifo1_full : rx_fifo0_full;
-
-
-
-
-
- wire write_rx_data_to_memory_wait;
- assign write_rx_data_to_memory_wait = !RxBDOK | RxPointerRead;
- wire write_rx_data_to_memory_go;
-
-`ifdef ETH_RX_BURST_EN
- assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=(`ETH_BURST_LENGTH);
- assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>(`ETH_BURST_LENGTH - 1);
- // While receiving, don't flog the bus too hard, only write out when
- // we can burst. But when finishing keep going until we've emptied the fifo
- assign write_rx_data_to_memory_go =
- RxEnableWindow & (rx_wbside_fifo_sel == rx_ethside_fifo_sel) ?
- (rxfifo_cnt>(`ETH_BURST_LENGTH)+2) |
- (|rx_burst_cnt) : ~RxBufferEmpty;
-
-`else
- assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=`ETH_BURST_LENGTH;
- assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>`ETH_BURST_LENGTH;
- assign write_rx_data_to_memory_go = ~RxBufferEmpty;
-`endif // !`ifdef ETH_RX_BURST_EN
-
- assign WriteRxDataToMemory = write_rx_data_to_memory_go & !write_rx_data_to_memory_wait;
-
- assign rx_burst = rx_burst_en & WriteRxDataToMemory;
-
-
- // Generation of the end-of-frame signal
- always @ (posedge MRxClk or posedge Reset)
- begin
- if(Reset)
- ShiftEnded_rck <= 1'b0;
- else
- if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
- ShiftEnded_rck <= 1'b1;
- else
- if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
- ShiftEnded_rck <= 1'b0;
- end
-
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- ShiftEndedSync1 <= 1'b0;
- else
- ShiftEndedSync1 <= ShiftEnded_rck;
- end
-
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- ShiftEndedSync2 <= 1'b0;
- else
- ShiftEndedSync2 <= ShiftEndedSync1;
- end
-
- // indicate end of wishbone RX is coming up
- always @ (posedge WB_CLK_I or posedge Reset)
- if(Reset)
- rx_wb_last_writes <= 1'b0;
- else if (!rx_wb_last_writes)
- rx_wb_last_writes <= ShiftEndedSync1 & ~ShiftEndedSync2;
- else if (rx_wb_writeback_finished & RxEn & RxEn_q)
- rx_wb_last_writes <= 0;
-
- // Pulse indicating last of RX data has been written out
- always @ (posedge WB_CLK_I or posedge Reset)
- if(Reset)
- rx_wb_writeback_finished <= 0;
- else if (rx_wb_writeback_finished & RxEn & RxEn_q)
- rx_wb_writeback_finished <= 0;
- else
- rx_wb_writeback_finished <= rx_wb_last_writes & RxBufferEmpty &
- !WriteRxDataToFifo_wb;
-
-
- always @ (posedge MRxClk or posedge Reset)
- begin
- if(Reset)
- ShiftEndedSync_c1 <= 1'b0;
- else
- ShiftEndedSync_c1 <= ShiftEndedSync2;
- end
-
- always @ (posedge MRxClk or posedge Reset)
- begin
- if(Reset)
- ShiftEndedSync_c2 <= 1'b0;
- else
- ShiftEndedSync_c2 <= ShiftEndedSync_c1;
- end
-
- // Generation of the end-of-frame signal
- always @ (posedge MRxClk or posedge Reset)
- begin
- if(Reset)
- RxEnableWindow <= 1'b0;
- else
- if(RxStartFrm)
- RxEnableWindow <= 1'b1;
- else
- if(RxEndFrm | RxAbort)
- RxEnableWindow <= 1'b0;
- end
-
-
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- RxAbortSync1 <= 1'b0;
- else
- RxAbortSync1 <= RxAbortLatched;
- end
-
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- RxAbortSync2 <= 1'b0;
- else
- RxAbortSync2 <= RxAbortSync1;
- end
-
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- RxAbortSync3 <= 1'b0;
- else
- RxAbortSync3 <= RxAbortSync2;
- end
-
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- RxAbortSync4 <= 1'b0;
- else
- RxAbortSync4 <= RxAbortSync3;
- end
-
- always @ (posedge MRxClk or posedge Reset)
- begin
- if(Reset)
- RxAbortSyncb1 <= 1'b0;
- else
- RxAbortSyncb1 <= RxAbortSync2;
- end
-
- always @ (posedge MRxClk or posedge Reset)
- begin
- if(Reset)
- RxAbortSyncb2 <= 1'b0;
- else
- RxAbortSyncb2 <= RxAbortSyncb1;
- end
-
-
- always @ (posedge MRxClk or posedge Reset)
- begin
- if(Reset)
- RxAbortLatched <= 1'b0;
- else
- if(RxAbortSyncb2)
- RxAbortLatched <= 1'b0;
- else
- if(RxAbort)
- RxAbortLatched <= 1'b1;
- end
-
-
- always @ (posedge MRxClk or posedge Reset)
- begin
- if(Reset)
- LatchedRxLength[15:0] <= 16'h0;
- else
- if(LoadRxStatus)
- LatchedRxLength[15:0] <= RxLength[15:0];
- end
-
-
- assign RxStatusIn = {ReceivedPauseFrm, AddressMiss, RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
-
- always @ (posedge MRxClk or posedge Reset)
- begin
- if(Reset)
- RxStatusInLatched <= 'h0;
- else
- if(LoadRxStatus)
- RxStatusInLatched <= RxStatusIn;
- end
-
-
- // Rx overrun
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- RxOverrun <= 1'b0;
- else
- if(RxStatusWrite)
- RxOverrun <= 1'b0;
- else
- if(RxBufferFull & WriteRxDataToFifo_wb)
- RxOverrun <= 1'b1;
- end
-
-
-
- wire TxError;
- assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
-
- wire RxError;
-
- // ShortFrame (RxStatusInLatched[2]) can not set an error because short
- // frames are aborted when signal r_RecSmall is set to 0 in MODER register.
- // AddressMiss is identifying that a frame was received because of the
- // promiscous mode and is not an error
- assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
-
-
-
- reg RxStatusWriteLatched;
- reg RxStatusWriteLatched_sync1;
- reg RxStatusWriteLatched_sync2;
- reg RxStatusWriteLatched_syncb1;
- reg RxStatusWriteLatched_syncb2;
-
-
- // Latching and synchronizing RxStatusWrite signal. This signal is used for
- // clearing the ReceivedPauseFrm signal
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- RxStatusWriteLatched <= 1'b0;
- else
- if(RxStatusWriteLatched_syncb2)
- RxStatusWriteLatched <= 1'b0;
- else
- if(RxStatusWrite)
- RxStatusWriteLatched <= 1'b1;
- end
-
-
- always @ (posedge MRxClk or posedge Reset)
- begin
- if(Reset)
- begin
- RxStatusWriteLatched_sync1 <= 1'b0;
- RxStatusWriteLatched_sync2 <= 1'b0;
- end
- else
- begin
- RxStatusWriteLatched_sync1 <= RxStatusWriteLatched;
- RxStatusWriteLatched_sync2 <= RxStatusWriteLatched_sync1;
- end
- end
-
-
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- begin
- RxStatusWriteLatched_syncb1 <= 1'b0;
- RxStatusWriteLatched_syncb2 <= 1'b0;
- end
- else
- begin
- RxStatusWriteLatched_syncb1 <= RxStatusWriteLatched_sync2;
- RxStatusWriteLatched_syncb2 <= RxStatusWriteLatched_syncb1;
- end
- end
-
-
-
- // Tx Done Interrupt
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- TxB_IRQ <= 1'b0;
- else
- if(TxStatusWrite & TxIRQEn)
- TxB_IRQ <= ~TxError;
- else
- TxB_IRQ <= 1'b0;
- end
-
-
- // Tx Error Interrupt
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- TxE_IRQ <= 1'b0;
- else
- if(TxStatusWrite & TxIRQEn)
- TxE_IRQ <= TxError;
- else
- TxE_IRQ <= 1'b0;
- end
-
-
- // Rx Done Interrupt
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- RxB_IRQ <= 1'b0;
- else
- if(RxStatusWrite & RxIRQEn & ReceivedPacketGood &
- (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
- RxB_IRQ <= (~RxError);
- else
- RxB_IRQ <= 1'b0;
- end
-
-
- // Rx Error Interrupt
- always @ (posedge WB_CLK_I or posedge Reset)
- begin
- if(Reset)
- RxE_IRQ <= 1'b0;
- else
- if(RxStatusWrite & RxIRQEn & (~ReceivedPauseFrm | ReceivedPauseFrm
- & r_PassAll & (~r_RxFlow)))
- RxE_IRQ <= RxError;
- else
- RxE_IRQ <= 1'b0;
- end
-
- // Set this high when we started receiving another packet while the wishbone
- // side was still writing out the last one. This makes sure we check at the
- // right time if the next buffer descriptor is free.
- reg rxstartfrm_occurred;
- always @ (posedge WB_CLK_I)
- if (Reset)
- rxstartfrm_occurred <= 0;
- else if (rx_just_read_bd)
- rxstartfrm_occurred <= 0;
- else if (((rx_ethside_fifo_sel != rx_wbside_fifo_sel) | StartRxBDRead |
- RxBDRead) & rx_startfrm_wb)
- rxstartfrm_occurred <= 1;
-
-
-
- reg busy_wb;
- always @ (posedge WB_CLK_I or posedge Reset)
- if(Reset)
- busy_wb <= 0;
- else if (busy_wb)
- busy_wb <= 0;
- else if
- // Indicate busy if either:
- // a) RX is idle and we get a start frame and current BD indicates not
- // ready.
- // b) RX is already receiving another packet and we got a startframe,
- // indicated by rx_startfrm_occurred, and we then read the BD and
- // it says it's not ready.
- // This actually may not work since it's in the MII RX clock domain.
- ((rx_ethside_fifo_sel == rx_wbside_fifo_sel) &
- ((rxstartfrm_occurred & rx_just_read_bd & ~RxBDReady) |
- (!rxstartfrm_occurred & !StartRxBDRead & !RxBDRead & rx_startfrm_wb &
- rx_waiting_for_bd_to_become_free))
- )
- busy_wb <= 1;
-
-
- assign Busy_IRQ = busy_wb;
-
- always @(posedge Busy_IRQ)
- $display("(%t)(%m) Ethernet MAC BUSY signal asserted", $time);
-
-
- // Assign the debug output
-`ifdef WISHBONE_DEBUG
- // Top byte, burst progress counters
- assign dbg_dat0[31] = 0;
- assign dbg_dat0[30] = 0;
- assign dbg_dat0[29:28] = rx_burst_cnt;
- assign dbg_dat0[27] = 0;
- assign dbg_dat0[26] = 0;
- assign dbg_dat0[25:24] = tx_burst_cnt;
-
- // Third byte
- assign dbg_dat0[23] = 0;
- assign dbg_dat0[22] = 0;
- assign dbg_dat0[21] = rx_burst;
- assign dbg_dat0[20] = rx_burst_en;
- assign dbg_dat0[19] = 0;
- assign dbg_dat0[18] = 0;
- assign dbg_dat0[17] = tx_burst;
- assign dbg_dat0[16] = tx_burst_en;
- // Second byte - TxBDAddress - or TX BD address pointer
- assign dbg_dat0[15:8] = { 1'b0, TxBDAddress};
- // Bottom byte - FSM controlling vector
- assign dbg_dat0[7:0] = {MasterWbTX,MasterWbRX,
- ReadTxDataFromMemory_2,WriteRxDataToMemory,
- MasterAccessFinished,cyc_cleared,
- tx_burst,rx_burst};
-
-`endif
-
-
-
-endmodule
rtl/verilog/eth/eth_wishbone.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: rtl/verilog/eth/eth.v
===================================================================
--- rtl/verilog/eth/eth.v (revision 408)
+++ rtl/verilog/eth/eth.v (nonexistent)
@@ -1,979 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// ////
-//// All additional information is available in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001, 2002 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.51 2005/02/21 11:13:17 igorm
-// Defer indication fixed.
-//
-// Revision 1.50 2004/04/26 15:26:23 igorm
-// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
-// previous update of the core.
-// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
-// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
-// register. (thanks to Mathias and Torbjorn)
-// - Multicast reception was fixed. Thanks to Ulrich Gries
-//
-// Revision 1.49 2003/11/12 18:24:59 tadejm
-// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
-//
-// Revision 1.48 2003/10/17 07:46:16 markom
-// mbist signals updated according to newest convention
-//
-// Revision 1.47 2003/10/06 15:43:45 knguyen
-// Update RxEnSync only when mrxdv_pad_i is inactive (LOW).
-//
-// Revision 1.46 2003/01/30 13:30:22 tadejm
-// Defer indication changed.
-//
-// Revision 1.45 2003/01/22 13:49:26 tadejm
-// When control packets were received, they were ignored in some cases.
-//
-// Revision 1.44 2003/01/21 12:09:40 mohor
-// When receiving normal data frame and RxFlow control was switched on, RXB
-// interrupt was not set.
-//
-// Revision 1.43 2002/11/22 01:57:06 mohor
-// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
-// synchronized.
-//
-// Revision 1.42 2002/11/21 00:09:19 mohor
-// TPauseRq synchronized to tx_clk.
-//
-// Revision 1.41 2002/11/19 18:13:49 mohor
-// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
-//
-// Revision 1.40 2002/11/19 17:34:25 mohor
-// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
-// that a frame was received because of the promiscous mode.
-//
-// Revision 1.39 2002/11/18 17:31:55 mohor
-// wb_rst_i is used for MIIM reset.
-//
-// Revision 1.38 2002/11/14 18:37:20 mohor
-// r_Rst signal does not reset any module any more and is removed from the design.
-//
-// Revision 1.37 2002/11/13 22:25:36 tadejm
-// All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.
-//
-// Revision 1.36 2002/10/18 17:04:20 tadejm
-// Changed BIST scan signals.
-//
-// Revision 1.35 2002/10/11 13:36:58 mohor
-// Typo error fixed. (When using Bist)
-//
-// Revision 1.34 2002/10/10 16:49:50 mohor
-// Signals for WISHBONE B3 compliant interface added.
-//
-// Revision 1.33 2002/10/10 16:29:30 mohor
-// BIST added.
-//
-// Revision 1.32 2002/09/20 17:12:58 mohor
-// CsMiss added. When address between 0x800 and 0xfff is accessed within
-// Ethernet Core, error acknowledge is generated.
-//
-// Revision 1.31 2002/09/12 14:50:17 mohor
-// CarrierSenseLost bug fixed when operating in full duplex mode.
-//
-// Revision 1.30 2002/09/10 10:35:23 mohor
-// Ethernet debug registers removed.
-//
-// Revision 1.29 2002/09/09 13:03:13 mohor
-// Error acknowledge is generated when accessing BDs and RST bit in the
-// MODER register (r_Rst) is set.
-//
-// Revision 1.28 2002/09/04 18:44:10 mohor
-// Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
-// connected.
-//
-// Revision 1.27 2002/07/25 18:15:37 mohor
-// RxAbort changed. Packets received with MRxErr (from PHY) are also
-// aborted.
-//
-// Revision 1.26 2002/07/17 18:51:50 mohor
-// EXTERNAL_DMA removed. External DMA not supported.
-//
-// Revision 1.25 2002/05/03 10:15:50 mohor
-// Outputs registered. Reset changed for eth_wishbone module.
-//
-// Revision 1.24 2002/04/22 14:15:42 mohor
-// Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
-// selected in eth_defines.v
-//
-// Revision 1.23 2002/03/25 13:33:53 mohor
-// md_padoen_o changed to md_padoe_o. Signal was always active high, just
-// name was incorrect.
-//
-// Revision 1.22 2002/02/26 16:59:54 mohor
-// Small fixes for external/internal DMA missmatches.
-//
-// Revision 1.21 2002/02/26 16:21:00 mohor
-// Interrupts changed in the top file
-//
-// Revision 1.20 2002/02/18 10:40:17 mohor
-// Small fixes.
-//
-// Revision 1.19 2002/02/16 14:03:44 mohor
-// Registered trimmed. Unused registers removed.
-//
-// Revision 1.18 2002/02/16 13:06:33 mohor
-// EXTERNAL_DMA used instead of WISHBONE_DMA.
-//
-// Revision 1.17 2002/02/16 07:15:27 mohor
-// Testbench fixed, code simplified, unused signals removed.
-//
-// Revision 1.16 2002/02/15 13:49:39 mohor
-// RxAbort is connected differently.
-//
-// Revision 1.15 2002/02/15 11:38:26 mohor
-// Changes that were lost when updating from 1.11 to 1.14 fixed.
-//
-// Revision 1.14 2002/02/14 20:19:11 billditt
-// Modified for Address Checking,
-// addition of eth_addrcheck.v
-//
-// Revision 1.13 2002/02/12 17:03:03 mohor
-// HASH0 and HASH1 registers added. Registers address width was
-// changed to 8 bits.
-//
-// Revision 1.12 2002/02/11 09:18:22 mohor
-// Tx status is written back to the BD.
-//
-// Revision 1.11 2002/02/08 16:21:54 mohor
-// Rx status is written back to the BD.
-//
-// Revision 1.10 2002/02/06 14:10:21 mohor
-// non-DMA host interface added. Select the right configutation in eth_defines.
-//
-// Revision 1.9 2002/01/23 10:28:16 mohor
-// Link in the header changed.
-//
-// Revision 1.8 2001/12/05 15:00:16 mohor
-// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
-// instead of the number of RX descriptors).
-//
-// Revision 1.7 2001/12/05 10:45:59 mohor
-// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
-//
-// Revision 1.6 2001/10/19 11:24:29 mohor
-// Number of addresses (wb_adr_i) minimized.
-//
-// Revision 1.5 2001/10/19 08:43:51 mohor
-// eth_timescale.v changed to timescale.v This is done because of the
-// simulation of the few cores in a one joined project.
-//
-// Revision 1.4 2001/10/18 12:07:11 mohor
-// Status signals changed, Adress decoding changed, interrupt controller
-// added.
-//
-// Revision 1.3 2001/09/24 15:02:56 mohor
-// Defines changed (All precede with ETH_). Small changes because some
-// tools generate warnings when two operands are together. Synchronization
-// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
-// demands).
-//
-// Revision 1.2 2001/08/15 14:03:59 mohor
-// Signal names changed on the top level for easier pad insertion (ASIC).
-//
-// Revision 1.1 2001/08/06 14:44:29 mohor
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
-// Include files fixed to contain no path.
-// File names and module names changed ta have a eth_ prologue in the name.
-// File eth_timescale.v is used to define timescale
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
-// and Mdo_OE. The bidirectional signal must be created on the top level. This
-// is done due to the ASIC tools.
-//
-// Revision 1.2 2001/08/02 09:25:31 mohor
-// Unconnected signals are now connected.
-//
-// Revision 1.1 2001/07/30 21:23:42 mohor
-// Directory structure changed. Files checked and joind together.
-//
-//
-//
-//
-
-
-`include "eth_defines.v"
-`include "timescale.v"
-
-
-module eth // renamed jb
-(
- // WISHBONE common
- wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
-
- // WISHBONE slave
- wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
-
- // WISHBONE master
- m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
- m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
- m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
-
-`ifdef ETH_WISHBONE_B3
- m_wb_cti_o, m_wb_bte_o,
-`endif
-
- //TX
- mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
-
- //RX
- mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i,
-
- // MIIM
- mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o,
-
- int_o
-
- // Bist
-`ifdef ETH_BIST
- ,
- // debug chain signals
- mbist_si_i, // bist scan serial in
- mbist_so_o, // bist scan serial out
- mbist_ctrl_i // bist chain shift control
-`endif
-
-);
-
-
-parameter Tp = 1;
-
-
-// WISHBONE common
-input wb_clk_i; // WISHBONE clock
-input wb_rst_i; // WISHBONE reset
-input [31:0] wb_dat_i; // WISHBONE data input
-output [31:0] wb_dat_o; // WISHBONE data output
-output wb_err_o; // WISHBONE error output
-
-// WISHBONE slave
-input [11:2] wb_adr_i; // WISHBONE address input
-input [3:0] wb_sel_i; // WISHBONE byte select input
-input wb_we_i; // WISHBONE write enable input
-input wb_cyc_i; // WISHBONE cycle input
-input wb_stb_i; // WISHBONE strobe input
-output wb_ack_o; // WISHBONE acknowledge output
-
-// WISHBONE master
-output [31:0] m_wb_adr_o;
-output [3:0] m_wb_sel_o;
-output m_wb_we_o;
-input [31:0] m_wb_dat_i;
-output [31:0] m_wb_dat_o;
-output m_wb_cyc_o;
-output m_wb_stb_o;
-input m_wb_ack_i;
-input m_wb_err_i;
-
-wire [29:0] m_wb_adr_tmp;
-
-`ifdef ETH_WISHBONE_B3
-output [2:0] m_wb_cti_o; // Cycle Type Identifier
-output [1:0] m_wb_bte_o; // Burst Type Extension
-`endif
-
-// Tx
-input mtx_clk_pad_i; // Transmit clock (from PHY)
-output [3:0] mtxd_pad_o; // Transmit nibble (to PHY)
-output mtxen_pad_o; // Transmit enable (to PHY)
-output mtxerr_pad_o; // Transmit error (to PHY)
-
-// Rx
-input mrx_clk_pad_i; // Receive clock (from PHY)
-input [3:0] mrxd_pad_i; // Receive nibble (from PHY)
-input mrxdv_pad_i; // Receive data valid (from PHY)
-input mrxerr_pad_i; // Receive data error (from PHY)
-
-// Common Tx and Rx
-input mcoll_pad_i; // Collision (from PHY)
-input mcrs_pad_i; // Carrier sense (from PHY)
-
-// MII Management interface
-input md_pad_i; // MII data input (from I/O cell)
-output mdc_pad_o; // MII Management data clock (to PHY)
-output md_pad_o; // MII data output (to I/O cell)
-output md_padoe_o; // MII data output enable (to I/O cell)
-
-output int_o; // Interrupt output
-
-// Bist
-`ifdef ETH_BIST
-input mbist_si_i; // bist scan serial in
-output mbist_so_o; // bist scan serial out
-input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
-`endif
-
-`ifdef WISHBONE_DEBUG
- wire [31:0] wb_dbg_dat0;
-`endif
-
-
-wire [7:0] r_ClkDiv;
-wire r_MiiNoPre;
-wire [15:0] r_CtrlData;
-wire [4:0] r_FIAD;
-wire [4:0] r_RGAD;
-wire r_WCtrlData;
-wire r_RStat;
-wire r_ScanStat;
-wire NValid_stat;
-wire Busy_stat;
-wire LinkFail;
-wire [15:0] Prsd; // Read Status Data (data read from the PHY)
-wire WCtrlDataStart;
-wire RStatStart;
-wire UpdateMIIRX_DATAReg;
-
-wire TxStartFrm;
-wire TxEndFrm;
-wire TxUsedData;
-wire [7:0] TxData;
-wire TxRetry;
-wire TxAbort;
-wire TxUnderRun;
-wire TxDone;
-
-
-reg WillSendControlFrame_sync1;
-reg WillSendControlFrame_sync2;
-reg WillSendControlFrame_sync3;
-reg RstTxPauseRq;
-
-reg TxPauseRq_sync1;
-reg TxPauseRq_sync2;
-reg TxPauseRq_sync3;
-reg TPauseRq;
-
-
-// Connecting Miim module
-eth_miim miim1
-(
- .Clk(wb_clk_i), .Reset(wb_rst_i), .Divider(r_ClkDiv),
- .NoPre(r_MiiNoPre), .CtrlData(r_CtrlData), .Rgad(r_RGAD),
- .Fiad(r_FIAD), .WCtrlData(r_WCtrlData), .RStat(r_RStat),
- .ScanStat(r_ScanStat), .Mdi(md_pad_i), .Mdo(md_pad_o),
- .MdoEn(md_padoe_o), .Mdc(mdc_pad_o), .Busy(Busy_stat),
- .Prsd(Prsd), .LinkFail(LinkFail), .Nvalid(NValid_stat),
- .WCtrlDataStart(WCtrlDataStart), .RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg)
-);
-
-
-
-
-wire [3:0] RegCs; // Connected to registers
-wire [31:0] RegDataOut; // Multiplexed to wb_dat_o
-wire r_RecSmall; // Receive small frames
-wire r_LoopBck; // Loopback
-wire r_TxEn; // Tx Enable
-wire r_RxEn; // Rx Enable
-
-wire MRxDV_Lb; // Muxed MII receive data valid
-wire MRxErr_Lb; // Muxed MII Receive Error
-wire [3:0] MRxD_Lb; // Muxed MII Receive Data
-wire Transmitting; // Indication that TxEthMAC is transmitting
-wire r_HugEn; // Huge packet enable
-wire r_DlyCrcEn; // Delayed CRC enabled
-wire [15:0] r_MaxFL; // Maximum frame length
-
-wire [15:0] r_MinFL; // Minimum frame length
-wire ShortFrame;
-wire DribbleNibble; // Extra nibble received
-wire ReceivedPacketTooBig; // Received packet is too big
-wire [47:0] r_MAC; // MAC address
-wire LoadRxStatus; // Rx status was loaded
-wire [31:0] r_HASH0; // HASH table, lower 4 bytes
-wire [31:0] r_HASH1; // HASH table, upper 4 bytes
-wire [7:0] r_TxBDNum; // Receive buffer descriptor number
-wire [6:0] r_IPGT; //
-wire [6:0] r_IPGR1; //
-wire [6:0] r_IPGR2; //
-wire [5:0] r_CollValid; //
-wire [15:0] r_TxPauseTV; // Transmit PAUSE value
-wire r_TxPauseRq; // Transmit PAUSE request
-
-wire [3:0] r_MaxRet; //
-wire r_NoBckof; //
-wire r_ExDfrEn; //
-wire r_TxFlow; // Tx flow control enable
-wire r_IFG; // Minimum interframe gap for incoming packets
-
-wire TxB_IRQ; // Interrupt Tx Buffer
-wire TxE_IRQ; // Interrupt Tx Error
-wire RxB_IRQ; // Interrupt Rx Buffer
-wire RxE_IRQ; // Interrupt Rx Error
-wire Busy_IRQ; // Interrupt Busy (lack of buffers)
-
-//wire DWord;
-wire ByteSelected;
-wire BDAck;
-wire [31:0] BD_WB_DAT_O; // wb_dat_o that comes from the Wishbone module (for buffer descriptors read/write)
-wire [3:0] BDCs; // Buffer descriptor CS
-wire CsMiss; // When access to the address between 0x800 and 0xfff occurs, acknowledge is set
- // but data is not valid.
-wire r_Pad;
-wire r_CrcEn;
-wire r_FullD;
-wire r_Pro;
-wire r_Bro;
-wire r_NoPre;
-wire r_RxFlow;
-wire r_PassAll;
-wire TxCtrlEndFrm;
-wire StartTxDone;
-wire SetPauseTimer;
-wire TxUsedDataIn;
-wire TxDoneIn;
-wire TxAbortIn;
-wire PerPacketPad;
-wire PadOut;
-wire PerPacketCrcEn;
-wire CrcEnOut;
-wire TxStartFrmOut;
-wire TxEndFrmOut;
-wire ReceivedPauseFrm;
-wire ControlFrmAddressOK;
-wire RxStatusWriteLatched_sync2;
-wire LateCollision;
-wire DeferIndication;
-wire LateCollLatched;
-wire DeferLatched;
-wire RstDeferLatched;
-wire CarrierSenseLost;
-
-wire temp_wb_ack_o;
-wire [31:0] temp_wb_dat_o;
-wire temp_wb_err_o;
-
-`ifdef ETH_REGISTERED_OUTPUTS
- reg temp_wb_ack_o_reg;
- reg [31:0] temp_wb_dat_o_reg;
- reg temp_wb_err_o_reg;
-`endif
-
-//assign DWord = &wb_sel_i;
-assign ByteSelected = |wb_sel_i;
-assign RegCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[3]; // 0x0 - 0x3FF
-assign RegCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[2]; // 0x0 - 0x3FF
-assign RegCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[1]; // 0x0 - 0x3FF
-assign RegCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[0]; // 0x0 - 0x3FF
-assign BDCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[3]; // 0x400 - 0x7FF
-assign BDCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[2]; // 0x400 - 0x7FF
-assign BDCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[1]; // 0x400 - 0x7FF
-assign BDCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[0]; // 0x400 - 0x7FF
-assign CsMiss = wb_stb_i & wb_cyc_i & ByteSelected & wb_adr_i[11]; // 0x800 - 0xfFF
-assign temp_wb_dat_o = ((|RegCs) & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
-assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~ByteSelected | CsMiss);
-
-`ifdef ETH_REGISTERED_OUTPUTS
- assign wb_ack_o = temp_wb_ack_o_reg;
- assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
- assign wb_err_o = temp_wb_err_o_reg;
-`else
- assign wb_ack_o = temp_wb_ack_o;
- assign wb_dat_o[31:0] = temp_wb_dat_o;
- assign wb_err_o = temp_wb_err_o;
-`endif
-
-`ifdef ETH_AVALON_BUS
- // As Avalon has no corresponding "error" signal, I (erroneously) will
- // send an ack to Avalon, even when accessing undefined memory. This
- // is a grey area in Avalon vs. Wishbone specs: My understanding
- // is that Avalon expects all memory addressable by the addr bus feeding
- // a slave to be, at the very minimum, readable.
- assign temp_wb_ack_o = (|RegCs) | BDAck | CsMiss;
-`else // WISHBONE
- assign temp_wb_ack_o = (|RegCs) | BDAck;
-`endif
-
-`ifdef ETH_REGISTERED_OUTPUTS
- always @ (posedge wb_clk_i or posedge wb_rst_i)
- begin
- if(wb_rst_i)
- begin
- temp_wb_ack_o_reg <= 1'b0;
- temp_wb_dat_o_reg <= 32'h0;
- temp_wb_err_o_reg <= 1'b0;
- end
- else
- begin
- temp_wb_ack_o_reg <= temp_wb_ack_o & ~temp_wb_ack_o_reg;
- temp_wb_dat_o_reg <= temp_wb_dat_o;
- temp_wb_err_o_reg <= temp_wb_err_o & ~temp_wb_err_o_reg;
- end
- end
-`endif
-
-
-// Connecting Ethernet registers
-eth_registers ethreg1
-(
- .DataIn(wb_dat_i), .Address(wb_adr_i[9:2]), .Rw(wb_we_i),
- .Cs(RegCs), .Clk(wb_clk_i), .Reset(wb_rst_i),
- .DataOut(RegDataOut), .r_RecSmall(r_RecSmall),
- .r_Pad(r_Pad), .r_HugEn(r_HugEn), .r_CrcEn(r_CrcEn),
- .r_DlyCrcEn(r_DlyCrcEn), .r_FullD(r_FullD),
- .r_ExDfrEn(r_ExDfrEn), .r_NoBckof(r_NoBckof), .r_LoopBck(r_LoopBck),
- .r_IFG(r_IFG), .r_Pro(r_Pro), .r_Iam(),
- .r_Bro(r_Bro), .r_NoPre(r_NoPre), .r_TxEn(r_TxEn),
- .r_RxEn(r_RxEn), .Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ),
- .RxB_IRQ(RxB_IRQ), .TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
- .r_IPGT(r_IPGT),
- .r_IPGR1(r_IPGR1), .r_IPGR2(r_IPGR2), .r_MinFL(r_MinFL),
- .r_MaxFL(r_MaxFL), .r_MaxRet(r_MaxRet), .r_CollValid(r_CollValid),
- .r_TxFlow(r_TxFlow), .r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll),
- .r_MiiNoPre(r_MiiNoPre), .r_ClkDiv(r_ClkDiv),
- .r_WCtrlData(r_WCtrlData), .r_RStat(r_RStat), .r_ScanStat(r_ScanStat),
- .r_RGAD(r_RGAD), .r_FIAD(r_FIAD), .r_CtrlData(r_CtrlData),
- .NValid_stat(NValid_stat), .Busy_stat(Busy_stat),
- .LinkFail(LinkFail), .r_MAC(r_MAC), .WCtrlDataStart(WCtrlDataStart),
- .RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg), .Prsd(Prsd),
- .r_TxBDNum(r_TxBDNum), .int_o(int_o),
- .r_HASH0(r_HASH0), .r_HASH1(r_HASH1), .r_TxPauseRq(r_TxPauseRq),
- .r_TxPauseTV(r_TxPauseTV), .RstTxPauseRq(RstTxPauseRq), .TxCtrlEndFrm(TxCtrlEndFrm),
- .StartTxDone(StartTxDone), .TxClk(mtx_clk_pad_i), .RxClk(mrx_clk_pad_i),
- .dbg_dat(wb_dbg_dat0),
- .SetPauseTimer(SetPauseTimer)
-
-);
-
-
-
-wire [7:0] RxData;
-wire RxValid;
-wire RxStartFrm;
-wire RxEndFrm;
-wire RxAbort;
-
-wire WillTransmit; // Will transmit (to RxEthMAC)
-wire ResetCollision; // Reset Collision (for synchronizing collision)
-wire [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC)
-wire WillSendControlFrame;
-wire ReceiveEnd;
-wire ReceivedPacketGood;
-wire ReceivedLengthOK;
-wire InvalidSymbol;
-wire LatchedCrcError;
-wire RxLateCollision;
-wire [3:0] RetryCntLatched;
-wire [3:0] RetryCnt;
-wire StartTxAbort;
-wire MaxCollisionOccured;
-wire RetryLimit;
-wire StatePreamble;
-wire [1:0] StateData;
-
-// Connecting MACControl
-eth_maccontrol maccontrol1
-(
- .MTxClk(mtx_clk_pad_i), .TPauseRq(TPauseRq),
- .TxPauseTV(r_TxPauseTV), .TxDataIn(TxData),
- .TxStartFrmIn(TxStartFrm), .TxEndFrmIn(TxEndFrm),
- .TxUsedDataIn(TxUsedDataIn), .TxDoneIn(TxDoneIn),
- .TxAbortIn(TxAbortIn), .MRxClk(mrx_clk_pad_i),
- .RxData(RxData), .RxValid(RxValid),
- .RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
- .ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood),
- .TxFlow(r_TxFlow),
- .RxFlow(r_RxFlow), .DlyCrcEn(r_DlyCrcEn),
- .MAC(r_MAC), .PadIn(r_Pad | PerPacketPad),
- .PadOut(PadOut), .CrcEnIn(r_CrcEn | PerPacketCrcEn),
- .CrcEnOut(CrcEnOut), .TxReset(wb_rst_i),
- .RxReset(wb_rst_i), .ReceivedLengthOK(ReceivedLengthOK),
- .TxDataOut(TxDataOut), .TxStartFrmOut(TxStartFrmOut),
- .TxEndFrmOut(TxEndFrmOut), .TxUsedDataOut(TxUsedData),
- .TxDoneOut(TxDone), .TxAbortOut(TxAbort),
- .WillSendControlFrame(WillSendControlFrame), .TxCtrlEndFrm(TxCtrlEndFrm),
- .ReceivedPauseFrm(ReceivedPauseFrm), .ControlFrmAddressOK(ControlFrmAddressOK),
- .SetPauseTimer(SetPauseTimer),
- .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2), .r_PassAll(r_PassAll)
-);
-
-
-
-wire TxCarrierSense; // Synchronized CarrierSense (to Tx clock)
-wire Collision; // Synchronized Collision
-
-reg CarrierSense_Tx1;
-reg CarrierSense_Tx2;
-reg Collision_Tx1;
-reg Collision_Tx2;
-
-reg RxEnSync; // Synchronized Receive Enable
-reg WillTransmit_q;
-reg WillTransmit_q2;
-
-
-
-// Muxed MII receive data valid
-assign MRxDV_Lb = r_LoopBck? mtxen_pad_o : mrxdv_pad_i & RxEnSync;
-
-// Muxed MII Receive Error
-assign MRxErr_Lb = r_LoopBck? mtxerr_pad_o : mrxerr_pad_i & RxEnSync;
-
-// Muxed MII Receive Data
-assign MRxD_Lb[3:0] = r_LoopBck? mtxd_pad_o[3:0] : mrxd_pad_i[3:0];
-
-
-
-// Connecting TxEthMAC
-eth_txethmac txethmac1
-(
- .MTxClk(mtx_clk_pad_i), .Reset(wb_rst_i), .CarrierSense(TxCarrierSense),
- .Collision(Collision), .TxData(TxDataOut), .TxStartFrm(TxStartFrmOut),
- .TxUnderRun(TxUnderRun), .TxEndFrm(TxEndFrmOut), .Pad(PadOut),
- .MinFL(r_MinFL), .CrcEn(CrcEnOut), .FullD(r_FullD),
- .HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn), .IPGT(r_IPGT),
- .IPGR1(r_IPGR1), .IPGR2(r_IPGR2), .CollValid(r_CollValid),
- .MaxRet(r_MaxRet), .NoBckof(r_NoBckof), .ExDfrEn(r_ExDfrEn),
- .MaxFL(r_MaxFL), .MTxEn(mtxen_pad_o), .MTxD(mtxd_pad_o),
- .MTxErr(mtxerr_pad_o), .TxUsedData(TxUsedDataIn), .TxDone(TxDoneIn),
- .TxRetry(TxRetry), .TxAbort(TxAbortIn), .WillTransmit(WillTransmit),
- .ResetCollision(ResetCollision), .RetryCnt(RetryCnt), .StartTxDone(StartTxDone),
- .StartTxAbort(StartTxAbort), .MaxCollisionOccured(MaxCollisionOccured), .LateCollision(LateCollision),
- .DeferIndication(DeferIndication), .StatePreamble(StatePreamble), .StateData(StateData)
-);
-
-
-
-
-wire [15:0] RxByteCnt;
-wire RxByteCntEq0;
-wire RxByteCntGreat2;
-wire RxByteCntMaxFrame;
-wire RxCrcError;
-wire RxStateIdle;
-wire RxStatePreamble;
-wire RxStateSFD;
-wire [1:0] RxStateData;
-wire AddressMiss;
-
-
-
-// Connecting RxEthMAC
-eth_rxethmac rxethmac1
-(
- .MRxClk(mrx_clk_pad_i), .MRxDV(MRxDV_Lb), .MRxD(MRxD_Lb),
- .Transmitting(Transmitting), .HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn),
- .MaxFL(r_MaxFL), .r_IFG(r_IFG), .Reset(wb_rst_i),
- .RxData(RxData), .RxValid(RxValid), .RxStartFrm(RxStartFrm),
- .RxEndFrm(RxEndFrm), .ByteCnt(RxByteCnt),
- .ByteCntEq0(RxByteCntEq0), .ByteCntGreat2(RxByteCntGreat2), .ByteCntMaxFrame(RxByteCntMaxFrame),
- .CrcError(RxCrcError), .StateIdle(RxStateIdle), .StatePreamble(RxStatePreamble),
- .StateSFD(RxStateSFD), .StateData(RxStateData),
- .MAC(r_MAC), .r_Pro(r_Pro), .r_Bro(r_Bro),
- .r_HASH0(r_HASH0), .r_HASH1(r_HASH1), .RxAbort(RxAbort),
- .AddressMiss(AddressMiss), .PassAll(r_PassAll), .ControlFrmAddressOK(ControlFrmAddressOK)
-);
-
-
-// MII Carrier Sense Synchronization
-always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
-begin
- if(wb_rst_i)
- begin
- CarrierSense_Tx1 <= 1'b0;
- CarrierSense_Tx2 <= 1'b0;
- end
- else
- begin
- CarrierSense_Tx1 <= mcrs_pad_i;
- CarrierSense_Tx2 <= CarrierSense_Tx1;
- end
-end
-
-assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2;
-
-
-// MII Collision Synchronization
-always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
-begin
- if(wb_rst_i)
- begin
- Collision_Tx1 <= 1'b0;
- Collision_Tx2 <= 1'b0;
- end
- else
- begin
- Collision_Tx1 <= mcoll_pad_i;
- if(ResetCollision)
- Collision_Tx2 <= 1'b0;
- else
- if(Collision_Tx1)
- Collision_Tx2 <= 1'b1;
- end
-end
-
-
-// Synchronized Collision
-assign Collision = ~r_FullD & Collision_Tx2;
-
-
-
-// Delayed WillTransmit
-always @ (posedge mrx_clk_pad_i)
-begin
- WillTransmit_q <= WillTransmit;
- WillTransmit_q2 <= WillTransmit_q;
-end
-
-
-assign Transmitting = ~r_FullD & WillTransmit_q2;
-
-
-
-// Synchronized Receive Enable
-always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
-begin
- if(wb_rst_i)
- RxEnSync <= 1'b0;
- else
- if(~mrxdv_pad_i)
- RxEnSync <= r_RxEn;
-end
-
-
-
-// Synchronizing WillSendControlFrame to WB_CLK;
-always @ (posedge wb_clk_i or posedge wb_rst_i)
-begin
- if(wb_rst_i)
- WillSendControlFrame_sync1 <= 1'b0;
- else
- WillSendControlFrame_sync1 <= WillSendControlFrame;
-end
-
-always @ (posedge wb_clk_i or posedge wb_rst_i)
-begin
- if(wb_rst_i)
- WillSendControlFrame_sync2 <= 1'b0;
- else
- WillSendControlFrame_sync2 <= WillSendControlFrame_sync1;
-end
-
-always @ (posedge wb_clk_i or posedge wb_rst_i)
-begin
- if(wb_rst_i)
- WillSendControlFrame_sync3 <= 1'b0;
- else
- WillSendControlFrame_sync3 <= WillSendControlFrame_sync2;
-end
-
-always @ (posedge wb_clk_i or posedge wb_rst_i)
-begin
- if(wb_rst_i)
- RstTxPauseRq <= 1'b0;
- else
- RstTxPauseRq <= WillSendControlFrame_sync2 & ~WillSendControlFrame_sync3;
-end
-
-
-
-
-// TX Pause request Synchronization
-always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
-begin
- if(wb_rst_i)
- begin
- TxPauseRq_sync1 <= 1'b0;
- TxPauseRq_sync2 <= 1'b0;
- TxPauseRq_sync3 <= 1'b0;
- end
- else
- begin
- TxPauseRq_sync1 <= (r_TxPauseRq & r_TxFlow);
- TxPauseRq_sync2 <= TxPauseRq_sync1;
- TxPauseRq_sync3 <= TxPauseRq_sync2;
- end
-end
-
-
-always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
-begin
- if(wb_rst_i)
- TPauseRq <= 1'b0;
- else
- TPauseRq <= TxPauseRq_sync2 & (~TxPauseRq_sync3);
-end
-
-
-wire LatchedMRxErr;
-reg RxAbort_latch;
-reg RxAbort_sync1;
-reg RxAbort_wb;
-reg RxAbortRst_sync1;
-reg RxAbortRst;
-
-// Synchronizing RxAbort to the WISHBONE clock
-always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
-begin
- if(wb_rst_i)
- RxAbort_latch <= 1'b0;
- else if(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr & ~InvalidSymbol | (ReceivedPauseFrm & (~r_PassAll)))
- RxAbort_latch <= 1'b1;
- else if(RxAbortRst)
- RxAbort_latch <= 1'b0;
-end
-
-always @ (posedge wb_clk_i or posedge wb_rst_i)
-begin
- if(wb_rst_i)
- begin
- RxAbort_sync1 <= 1'b0;
- RxAbort_wb <= 1'b0;
- RxAbort_wb <= 1'b0;
- end
- else
- begin
- RxAbort_sync1 <= RxAbort_latch;
- RxAbort_wb <= RxAbort_sync1;
- end
-end
-
-always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
-begin
- if(wb_rst_i)
- begin
- RxAbortRst_sync1 <= 1'b0;
- RxAbortRst <= 1'b0;
- end
- else
- begin
- RxAbortRst_sync1 <= RxAbort_wb;
- RxAbortRst <= RxAbortRst_sync1;
- end
-end
-
-
-
-// Connecting Wishbone module
-eth_wishbone wishbone
-(
- .WB_CLK_I(wb_clk_i), .WB_DAT_I(wb_dat_i),
- .WB_DAT_O(BD_WB_DAT_O),
-
- // WISHBONE slave
- .WB_ADR_I(wb_adr_i[9:2]), .WB_WE_I(wb_we_i),
- .BDCs(BDCs), .WB_ACK_O(BDAck),
-
- .Reset(wb_rst_i),
-
- // WISHBONE master
- .m_wb_adr_o(m_wb_adr_tmp), .m_wb_sel_o(m_wb_sel_o), .m_wb_we_o(m_wb_we_o),
- .m_wb_dat_i(m_wb_dat_i), .m_wb_dat_o(m_wb_dat_o), .m_wb_cyc_o(m_wb_cyc_o),
- .m_wb_stb_o(m_wb_stb_o), .m_wb_ack_i(m_wb_ack_i), .m_wb_err_i(m_wb_err_i),
-
-`ifdef ETH_WISHBONE_B3
- .m_wb_cti_o(m_wb_cti_o), .m_wb_bte_o(m_wb_bte_o),
-`endif
-
-
- //TX
- .MTxClk(mtx_clk_pad_i), .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm),
- .TxUsedData(TxUsedData), .TxData(TxData),
- .TxRetry(TxRetry), .TxAbort(TxAbort), .TxUnderRun(TxUnderRun),
- .TxDone(TxDone),
- .PerPacketCrcEn(PerPacketCrcEn), .PerPacketPad(PerPacketPad),
-
- // Register
- .r_TxEn(r_TxEn), .r_RxEn(r_RxEn), .r_TxBDNum(r_TxBDNum),
- .r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll),
-
- //RX
- .MRxClk(mrx_clk_pad_i), .RxData(RxData), .RxValid(RxValid),
- .RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
- .Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ), .RxB_IRQ(RxB_IRQ),
- .TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
-
- .RxAbort(RxAbort_wb), .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2),
-
- .InvalidSymbol(InvalidSymbol), .LatchedCrcError(LatchedCrcError), .RxLength(RxByteCnt),
- .RxLateCollision(RxLateCollision), .ShortFrame(ShortFrame), .DribbleNibble(DribbleNibble),
- .ReceivedPacketTooBig(ReceivedPacketTooBig), .LoadRxStatus(LoadRxStatus), .RetryCntLatched(RetryCntLatched),
- .RetryLimit(RetryLimit), .LateCollLatched(LateCollLatched), .DeferLatched(DeferLatched),
- .RstDeferLatched(RstDeferLatched),
- .CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood), .AddressMiss(AddressMiss),
- .ReceivedPauseFrm(ReceivedPauseFrm)
-
-`ifdef ETH_BIST
- ,
- .mbist_si_i (mbist_si_i),
- .mbist_so_o (mbist_so_o),
- .mbist_ctrl_i (mbist_ctrl_i)
-`endif
- `ifdef WISHBONE_DEBUG
- ,
- .dbg_dat0(wb_dbg_dat0)
-`endif
-
-);
-
-assign m_wb_adr_o = {m_wb_adr_tmp, 2'h0};
-
-// Connecting MacStatus module
-eth_macstatus macstatus1
-(
- .MRxClk(mrx_clk_pad_i), .Reset(wb_rst_i),
- .ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood), .ReceivedLengthOK(ReceivedLengthOK),
- .RxCrcError(RxCrcError), .MRxErr(MRxErr_Lb), .MRxDV(MRxDV_Lb),
- .RxStateSFD(RxStateSFD), .RxStateData(RxStateData), .RxStatePreamble(RxStatePreamble),
- .RxStateIdle(RxStateIdle), .Transmitting(Transmitting), .RxByteCnt(RxByteCnt),
- .RxByteCntEq0(RxByteCntEq0), .RxByteCntGreat2(RxByteCntGreat2), .RxByteCntMaxFrame(RxByteCntMaxFrame),
- .InvalidSymbol(InvalidSymbol),
- .MRxD(MRxD_Lb), .LatchedCrcError(LatchedCrcError), .Collision(mcoll_pad_i),
- .CollValid(r_CollValid), .RxLateCollision(RxLateCollision), .r_RecSmall(r_RecSmall),
- .r_MinFL(r_MinFL), .r_MaxFL(r_MaxFL), .ShortFrame(ShortFrame),
- .DribbleNibble(DribbleNibble), .ReceivedPacketTooBig(ReceivedPacketTooBig), .r_HugEn(r_HugEn),
- .LoadRxStatus(LoadRxStatus), .RetryCnt(RetryCnt), .StartTxDone(StartTxDone),
- .StartTxAbort(StartTxAbort), .RetryCntLatched(RetryCntLatched), .MTxClk(mtx_clk_pad_i),
- .MaxCollisionOccured(MaxCollisionOccured), .RetryLimit(RetryLimit), .LateCollision(LateCollision),
- .LateCollLatched(LateCollLatched), .DeferIndication(DeferIndication), .DeferLatched(DeferLatched),
- .RstDeferLatched(RstDeferLatched),
- .TxStartFrm(TxStartFrmOut), .StatePreamble(StatePreamble), .StateData(StateData),
- .CarrierSense(CarrierSense_Tx2), .CarrierSenseLost(CarrierSenseLost), .TxUsedData(TxUsedDataIn),
- .LatchedMRxErr(LatchedMRxErr), .Loopback(r_LoopBck), .r_FullD(r_FullD)
-);
-
-
-endmodule
Index: rtl/verilog/eth/eth_random.v
===================================================================
--- rtl/verilog/eth/eth_random.v (revision 408)
+++ rtl/verilog/eth/eth_random.v (nonexistent)
@@ -1,141 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_random.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// - Novan Hartadi (novan@vlsi.itb.ac.id) ////
-//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.3 2002/01/23 10:28:16 mohor
-// Link in the header changed.
-//
-// Revision 1.2 2001/10/19 08:43:51 mohor
-// eth_timescale.v changed to timescale.v This is done because of the
-// simulation of the few cores in a one joined project.
-//
-// Revision 1.1 2001/08/06 14:44:29 mohor
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
-// Include files fixed to contain no path.
-// File names and module names changed ta have a eth_ prologue in the name.
-// File eth_timescale.v is used to define timescale
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
-// and Mdo_OE. The bidirectional signal must be created on the top level. This
-// is done due to the ASIC tools.
-//
-// Revision 1.1 2001/07/30 21:23:42 mohor
-// Directory structure changed. Files checked and joind together.
-//
-// Revision 1.3 2001/06/19 18:16:40 mohor
-// TxClk changed to MTxClk (as discribed in the documentation).
-// Crc changed so only one file can be used instead of two.
-//
-// Revision 1.2 2001/06/19 10:38:07 mohor
-// Minor changes in header.
-//
-// Revision 1.1 2001/06/19 10:27:57 mohor
-// TxEthMAC initial release.
-//
-//
-//
-//
-
-`include "timescale.v"
-
-module eth_random (MTxClk, Reset, StateJam, StateJam_q, RetryCnt, NibCnt, ByteCnt,
- RandomEq0, RandomEqByteCnt);
-
-parameter Tp = 1;
-
-input MTxClk;
-input Reset;
-input StateJam;
-input StateJam_q;
-input [3:0] RetryCnt;
-input [15:0] NibCnt;
-input [9:0] ByteCnt;
-output RandomEq0;
-output RandomEqByteCnt;
-
-wire Feedback;
-reg [9:0] x;
-wire [9:0] Random;
-reg [9:0] RandomLatched;
-
-
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- x[9:0] <= 0;
- else
- x[9:0] <= {x[8:0], Feedback};
-end
-
-assign Feedback = ~(x[2] ^ x[9]);
-
-assign Random [0] = x[0];
-assign Random [1] = (RetryCnt > 1) ? x[1] : 1'b0;
-assign Random [2] = (RetryCnt > 2) ? x[2] : 1'b0;
-assign Random [3] = (RetryCnt > 3) ? x[3] : 1'b0;
-assign Random [4] = (RetryCnt > 4) ? x[4] : 1'b0;
-assign Random [5] = (RetryCnt > 5) ? x[5] : 1'b0;
-assign Random [6] = (RetryCnt > 6) ? x[6] : 1'b0;
-assign Random [7] = (RetryCnt > 7) ? x[7] : 1'b0;
-assign Random [8] = (RetryCnt > 8) ? x[8] : 1'b0;
-assign Random [9] = (RetryCnt > 9) ? x[9] : 1'b0;
-
-
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- RandomLatched <= 10'h000;
- else
- begin
- if(StateJam & StateJam_q)
- RandomLatched <= Random;
- end
-end
-
-// Random Number == 0 IEEE 802.3 page 68. If 0 we go to defer and not to backoff.
-assign RandomEq0 = RandomLatched == 10'h0;
-
-assign RandomEqByteCnt = ByteCnt[9:0] == RandomLatched & (&NibCnt[6:0]);
-
-endmodule
rtl/verilog/eth/eth_random.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: rtl/verilog/eth/eth_rxaddrcheck.v
===================================================================
--- rtl/verilog/eth/eth_rxaddrcheck.v (revision 408)
+++ rtl/verilog/eth/eth_rxaddrcheck.v (nonexistent)
@@ -1,207 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_rxaddrcheck.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/cores/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Bill Dittenhofer (billditt@aol.com) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.8 2002/11/19 17:34:52 mohor
-// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
-// that a frame was received because of the promiscous mode.
-//
-// Revision 1.7 2002/09/04 18:41:06 mohor
-// Bug when last byte of destination address was not checked fixed.
-//
-// Revision 1.6 2002/03/20 15:14:11 mohor
-// When in promiscous mode some frames were not received correctly. Fixed.
-//
-// Revision 1.5 2002/03/02 21:06:32 mohor
-// Log info was missing.
-//
-//
-// Revision 1.1 2002/02/08 12:51:54 ditt
-// Initial release of the ethernet addresscheck module.
-//
-//
-//
-//
-//
-
-
-`include "timescale.v"
-
-
-module eth_rxaddrcheck(MRxClk, Reset, RxData, Broadcast ,r_Bro ,r_Pro,
- ByteCntEq2, ByteCntEq3, ByteCntEq4, ByteCntEq5,
- ByteCntEq6, ByteCntEq7, HASH0, HASH1,
- CrcHash, CrcHashGood, StateData, RxEndFrm,
- Multicast, MAC, RxAbort, AddressMiss, PassAll,
- ControlFrmAddressOK
- );
-
-parameter Tp = 1;
-
- input MRxClk;
- input Reset;
- input [7:0] RxData;
- input Broadcast;
- input r_Bro;
- input r_Pro;
- input ByteCntEq2;
- input ByteCntEq3;
- input ByteCntEq4;
- input ByteCntEq5;
- input ByteCntEq6;
- input ByteCntEq7;
- input [31:0] HASH0;
- input [31:0] HASH1;
- input [5:0] CrcHash;
- input CrcHashGood;
- input Multicast;
- input [47:0] MAC;
- input [1:0] StateData;
- input RxEndFrm;
- input PassAll;
- input ControlFrmAddressOK;
-
- output RxAbort;
- output AddressMiss;
-
- wire BroadcastOK;
- wire ByteCntEq2;
- wire ByteCntEq3;
- wire ByteCntEq4;
- wire ByteCntEq5;
- wire RxAddressInvalid;
- wire RxCheckEn;
- wire HashBit;
- wire [31:0] IntHash;
- reg [7:0] ByteHash;
- reg MulticastOK;
- reg UnicastOK;
- reg RxAbort;
- reg AddressMiss;
-
-assign RxAddressInvalid = ~(UnicastOK | BroadcastOK | MulticastOK | r_Pro);
-
-assign BroadcastOK = Broadcast & ~r_Bro;
-
-assign RxCheckEn = | StateData;
-
- // Address Error Reported at end of address cycle
- // RxAbort clears after one cycle
-
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- RxAbort <= 1'b0;
- else if(RxAddressInvalid & ByteCntEq7 & RxCheckEn)
- RxAbort <= 1'b1;
- else
- RxAbort <= 1'b0;
-end
-
-
-// This ff holds the "Address Miss" information that is written to the RX BD status.
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- AddressMiss <= 1'b0;
- else if(ByteCntEq7 & RxCheckEn)
- AddressMiss <= (~(UnicastOK | BroadcastOK | MulticastOK | (PassAll & ControlFrmAddressOK)));
-end
-
-
-// Hash Address Check, Multicast
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- MulticastOK <= 1'b0;
- else if(RxEndFrm | RxAbort)
- MulticastOK <= 1'b0;
- else if(CrcHashGood & Multicast)
- MulticastOK <= HashBit;
-end
-
-
-// Address Detection (unicast)
-// start with ByteCntEq2 due to delay of addres from RxData
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- UnicastOK <= 1'b0;
- else
- if(RxCheckEn & ByteCntEq2)
- UnicastOK <= RxData[7:0] == MAC[47:40];
- else
- if(RxCheckEn & ByteCntEq3)
- UnicastOK <= ( RxData[7:0] == MAC[39:32]) & UnicastOK;
- else
- if(RxCheckEn & ByteCntEq4)
- UnicastOK <= ( RxData[7:0] == MAC[31:24]) & UnicastOK;
- else
- if(RxCheckEn & ByteCntEq5)
- UnicastOK <= ( RxData[7:0] == MAC[23:16]) & UnicastOK;
- else
- if(RxCheckEn & ByteCntEq6)
- UnicastOK <= ( RxData[7:0] == MAC[15:8]) & UnicastOK;
- else
- if(RxCheckEn & ByteCntEq7)
- UnicastOK <= ( RxData[7:0] == MAC[7:0]) & UnicastOK;
- else
- if(RxEndFrm | RxAbort)
- UnicastOK <= 1'b0;
-end
-
-assign IntHash = (CrcHash[5])? HASH1 : HASH0;
-
-always@(CrcHash or IntHash)
-begin
- case(CrcHash[4:3])
- 2'b00: ByteHash = IntHash[7:0];
- 2'b01: ByteHash = IntHash[15:8];
- 2'b10: ByteHash = IntHash[23:16];
- 2'b11: ByteHash = IntHash[31:24];
- endcase
-end
-
-assign HashBit = ByteHash[CrcHash[2:0]];
-
-
-endmodule
rtl/verilog/eth/eth_rxaddrcheck.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: rtl/verilog/eth/eth_fifo.v
===================================================================
--- rtl/verilog/eth/eth_fifo.v (revision 408)
+++ rtl/verilog/eth/eth_fifo.v (nonexistent)
@@ -1,227 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_fifo.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.3 2002/04/22 13:45:52 mohor
-// Generic ram or Xilinx ram can be used in fifo (selectable by setting
-// ETH_FIFO_XILINX in eth_defines.v).
-//
-// Revision 1.2 2002/03/25 13:33:04 mohor
-// When clear and read/write are active at the same time, cnt and pointers are
-// set to 1.
-//
-// Revision 1.1 2002/02/05 16:44:39 mohor
-// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
-// MHz. Statuses, overrun, control frame transmission and reception still need
-// to be fixed.
-//
-//
-
-`include "eth_defines.v"
-`include "timescale.v"
-
-module eth_fifo (data_in, data_out, clk, reset, write, read, clear, almost_full, full, almost_empty, empty, cnt);
-
-parameter DATA_WIDTH = 32;
-parameter DEPTH = 8;
-parameter CNT_WIDTH = 4;
-
-input clk;
-input reset;
-input write;
-input read;
-input clear;
-input [DATA_WIDTH-1:0] data_in;
-
-output [DATA_WIDTH-1:0] data_out;
-output almost_full;
-output full;
-output almost_empty;
-output empty;
-output [CNT_WIDTH-1:0] cnt;
-
-
-
-reg [CNT_WIDTH-1:0] cnt;
- reg final_read;
-
-always @ (posedge clk or posedge reset)
-begin
- if(reset)
- cnt <= 0;
- else
- if(clear)
- cnt <= { {(CNT_WIDTH-1){1'b0}}, read^write};
- else
- if(read ^ write)
- if(read)
- cnt <= cnt - 1'b1;
- else
- cnt <= cnt + 1'b1;
-end
-
-
-`ifdef ETH_FIFO_GENERIC
-
- reg [DATA_WIDTH-1:0] fifo [0:DEPTH-1] /*synthesis syn_ramstyle = "no_rw_check"*/ ;
-
-
- // This should make the synthesis tool infer RAMs
- reg [CNT_WIDTH-2:0] waddr, raddr, raddr_reg;
- reg clear_reg; // Register the clear pulse
-
- always @(posedge clk)
- if (reset)
- waddr <= 0;
- else if (write)
- waddr <= waddr + 1;
-
- wire raddr_reg_adv;
- reg read_reg;
- always @(posedge clk)
- read_reg <= read;
-
- // Advance the address after a read = first/next word fallthrough
- assign raddr_reg_adv = (cnt > 2) & read_reg;
-
- always @(posedge clk)
- if (reset)
- raddr <= 0;
- else if (clear)
- raddr <= waddr;
- else if (read | clear_reg )
- raddr <= raddr + 1;
-
- always @ (posedge clk)
- if (write & ~full)
- fifo[waddr] <= data_in;
-
-
- always @(posedge clk)
- clear_reg <= clear;
-
- always @ (posedge clk)
- if (read | clear_reg)
- raddr_reg <= raddr;
-
- assign data_out = fifo[raddr_reg];
-
-
- always @(posedge clk)
- if (reset)
- final_read <= 0;
- else if (final_read & read & !write)
- final_read <= ~final_read;
- else if ((cnt == 1) & read & !write)
- final_read <= 1; // Indicate last read data has been output
-
-
- assign empty = ~(|cnt);
- assign almost_empty = cnt==1;
- assign full = cnt == DEPTH;
- assign almost_full = &cnt[CNT_WIDTH-2:0];
-
-`else // !`ifdef ETH_FIFO_GENERIC
-
-reg [CNT_WIDTH-2:0] read_pointer;
-reg [CNT_WIDTH-2:0] write_pointer;
-
-
-always @ (posedge clk or posedge reset)
-begin
- if(reset)
- read_pointer <= 0;
- else
- if(clear)
- //read_pointer <= { {(CNT_WIDTH-2){1'b0}}, read};
- read_pointer <= { {(CNT_WIDTH-2){1'b0}}, 1'b1};
- else
- if(read & ~empty)
- read_pointer <= read_pointer + 1'b1;
-end
-
-always @ (posedge clk or posedge reset)
-begin
- if(reset)
- write_pointer <= 0;
- else
- if(clear)
- write_pointer <= { {(CNT_WIDTH-2){1'b0}}, write};
- else
- if(write & ~full)
- write_pointer <= write_pointer + 1'b1;
-end
-
-`ifdef ETH_FIFO_XILINX
- xilinx_dist_ram_16x32 fifo
- ( .data_out(data_out),
- .we(write & ~full),
- .data_in(data_in),
- .read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer),
- .write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer),
- .wclk(clk)
- );
-`else // !ETH_FIFO_XILINX
-`ifdef ETH_ALTERA_ALTSYNCRAM
- altera_dpram_16x32 altera_dpram_16x32_inst
- (
- .data (data_in),
- .wren (write & ~full),
- .wraddress (clear ? {CNT_WIDTH-1{1'b0}} : write_pointer),
- .rdaddress (clear ? {CNT_WIDTH-1{1'b0}} : read_pointer ),
- .clock (clk),
- .q (data_out)
- ); //exemplar attribute altera_dpram_16x32_inst NOOPT TRUE
-`endif // `ifdef ETH_ALTERA_ALTSYNCRAM
-`endif // !`ifdef ETH_FIFO_XILINX
-
-
-assign empty = ~(|cnt);
-assign almost_empty = cnt == 1;
-assign full = cnt == DEPTH;
-assign almost_full = &cnt[CNT_WIDTH-2:0];
-
-`endif // !`ifdef ETH_FIFO_GENERIC
-
-
-
-endmodule
rtl/verilog/eth/eth_fifo.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: rtl/verilog/eth/eth_receivecontrol.v
===================================================================
--- rtl/verilog/eth/eth_receivecontrol.v (revision 408)
+++ rtl/verilog/eth/eth_receivecontrol.v (nonexistent)
@@ -1,438 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_receivecontrol.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.4 2002/11/22 01:57:06 mohor
-// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
-// synchronized.
-//
-// Revision 1.3 2002/01/23 10:28:16 mohor
-// Link in the header changed.
-//
-// Revision 1.2 2001/10/19 08:43:51 mohor
-// eth_timescale.v changed to timescale.v This is done because of the
-// simulation of the few cores in a one joined project.
-//
-// Revision 1.1 2001/08/06 14:44:29 mohor
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
-// Include files fixed to contain no path.
-// File names and module names changed ta have a eth_ prologue in the name.
-// File eth_timescale.v is used to define timescale
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
-// and Mdo_OE. The bidirectional signal must be created on the top level. This
-// is done due to the ASIC tools.
-//
-// Revision 1.1 2001/07/30 21:23:42 mohor
-// Directory structure changed. Files checked and joind together.
-//
-// Revision 1.1 2001/07/03 12:51:54 mohor
-// Initial release of the MAC Control module.
-//
-//
-//
-//
-//
-
-
-`include "timescale.v"
-
-
-module eth_receivecontrol (MTxClk, MRxClk, TxReset, RxReset, RxData, RxValid, RxStartFrm,
- RxEndFrm, RxFlow, ReceiveEnd, MAC, DlyCrcEn, TxDoneIn,
- TxAbortIn, TxStartFrmOut, ReceivedLengthOK, ReceivedPacketGood,
- TxUsedDataOutDetected, Pause, ReceivedPauseFrm, AddressOK,
- RxStatusWriteLatched_sync2, r_PassAll, SetPauseTimer
- );
-
-parameter Tp = 1;
-
-
-input MTxClk;
-input MRxClk;
-input TxReset;
-input RxReset;
-input [7:0] RxData;
-input RxValid;
-input RxStartFrm;
-input RxEndFrm;
-input RxFlow;
-input ReceiveEnd;
-input [47:0]MAC;
-input DlyCrcEn;
-input TxDoneIn;
-input TxAbortIn;
-input TxStartFrmOut;
-input ReceivedLengthOK;
-input ReceivedPacketGood;
-input TxUsedDataOutDetected;
-input RxStatusWriteLatched_sync2;
-input r_PassAll;
-
-output Pause;
-output ReceivedPauseFrm;
-output AddressOK;
-output SetPauseTimer;
-
-
-reg Pause;
-reg AddressOK; // Multicast or unicast address detected
-reg TypeLengthOK; // Type/Length field contains 0x8808
-reg DetectionWindow; // Detection of the PAUSE frame is possible within this window
-reg OpCodeOK; // PAUSE opcode detected (0x0001)
-reg [2:0] DlyCrcCnt;
-reg [4:0] ByteCnt;
-reg [15:0] AssembledTimerValue;
-reg [15:0] LatchedTimerValue;
-reg ReceivedPauseFrm;
-reg ReceivedPauseFrmWAddr;
-reg PauseTimerEq0_sync1;
-reg PauseTimerEq0_sync2;
-reg [15:0] PauseTimer;
-reg Divider2;
-reg [5:0] SlotTimer;
-
-wire [47:0] ReservedMulticast; // 0x0180C2000001
-wire [15:0] TypeLength; // 0x8808
-wire ResetByteCnt; //
-wire IncrementByteCnt; //
-wire ByteCntEq0; // ByteCnt = 0
-wire ByteCntEq1; // ByteCnt = 1
-wire ByteCntEq2; // ByteCnt = 2
-wire ByteCntEq3; // ByteCnt = 3
-wire ByteCntEq4; // ByteCnt = 4
-wire ByteCntEq5; // ByteCnt = 5
-wire ByteCntEq12; // ByteCnt = 12
-wire ByteCntEq13; // ByteCnt = 13
-wire ByteCntEq14; // ByteCnt = 14
-wire ByteCntEq15; // ByteCnt = 15
-wire ByteCntEq16; // ByteCnt = 16
-wire ByteCntEq17; // ByteCnt = 17
-wire ByteCntEq18; // ByteCnt = 18
-wire DecrementPauseTimer; //
-wire PauseTimerEq0; //
-wire ResetSlotTimer; //
-wire IncrementSlotTimer; //
-wire SlotFinished; //
-
-
-
-// Reserved multicast address and Type/Length for PAUSE control
-assign ReservedMulticast = 48'h0180C2000001;
-assign TypeLength = 16'h8808;
-
-
-// Address Detection (Multicast or unicast)
-always @ (posedge MRxClk or posedge RxReset)
-begin
- if(RxReset)
- AddressOK <= 1'b0;
- else
- if(DetectionWindow & ByteCntEq0)
- AddressOK <= RxData[7:0] == ReservedMulticast[47:40] | RxData[7:0] == MAC[47:40];
- else
- if(DetectionWindow & ByteCntEq1)
- AddressOK <= (RxData[7:0] == ReservedMulticast[39:32] | RxData[7:0] == MAC[39:32]) & AddressOK;
- else
- if(DetectionWindow & ByteCntEq2)
- AddressOK <= (RxData[7:0] == ReservedMulticast[31:24] | RxData[7:0] == MAC[31:24]) & AddressOK;
- else
- if(DetectionWindow & ByteCntEq3)
- AddressOK <= (RxData[7:0] == ReservedMulticast[23:16] | RxData[7:0] == MAC[23:16]) & AddressOK;
- else
- if(DetectionWindow & ByteCntEq4)
- AddressOK <= (RxData[7:0] == ReservedMulticast[15:8] | RxData[7:0] == MAC[15:8]) & AddressOK;
- else
- if(DetectionWindow & ByteCntEq5)
- AddressOK <= (RxData[7:0] == ReservedMulticast[7:0] | RxData[7:0] == MAC[7:0]) & AddressOK;
- else
- if(ReceiveEnd)
- AddressOK <= 1'b0;
-end
-
-
-
-// TypeLengthOK (Type/Length Control frame detected)
-always @ (posedge MRxClk or posedge RxReset )
-begin
- if(RxReset)
- TypeLengthOK <= 1'b0;
- else
- if(DetectionWindow & ByteCntEq12)
- TypeLengthOK <= ByteCntEq12 & (RxData[7:0] == TypeLength[15:8]);
- else
- if(DetectionWindow & ByteCntEq13)
- TypeLengthOK <= ByteCntEq13 & (RxData[7:0] == TypeLength[7:0]) & TypeLengthOK;
- else
- if(ReceiveEnd)
- TypeLengthOK <= 1'b0;
-end
-
-
-
-// Latch Control Frame Opcode
-always @ (posedge MRxClk or posedge RxReset )
-begin
- if(RxReset)
- OpCodeOK <= 1'b0;
- else
- if(ByteCntEq16)
- OpCodeOK <= 1'b0;
- else
- begin
- if(DetectionWindow & ByteCntEq14)
- OpCodeOK <= ByteCntEq14 & RxData[7:0] == 8'h00;
-
- if(DetectionWindow & ByteCntEq15)
- OpCodeOK <= ByteCntEq15 & RxData[7:0] == 8'h01 & OpCodeOK;
- end
-end
-
-
-// ReceivedPauseFrmWAddr (+Address Check)
-always @ (posedge MRxClk or posedge RxReset )
-begin
- if(RxReset)
- ReceivedPauseFrmWAddr <= 1'b0;
- else
- if(ReceiveEnd)
- ReceivedPauseFrmWAddr <= 1'b0;
- else
- if(ByteCntEq16 & TypeLengthOK & OpCodeOK & AddressOK)
- ReceivedPauseFrmWAddr <= 1'b1;
-end
-
-
-
-// Assembling 16-bit timer value from two 8-bit data
-always @ (posedge MRxClk or posedge RxReset )
-begin
- if(RxReset)
- AssembledTimerValue[15:0] <= 16'h0;
- else
- if(RxStartFrm)
- AssembledTimerValue[15:0] <= 16'h0;
- else
- begin
- if(DetectionWindow & ByteCntEq16)
- AssembledTimerValue[15:8] <= RxData[7:0];
- if(DetectionWindow & ByteCntEq17)
- AssembledTimerValue[7:0] <= RxData[7:0];
- end
-end
-
-
-// Detection window (while PAUSE detection is possible)
-always @ (posedge MRxClk or posedge RxReset )
-begin
- if(RxReset)
- DetectionWindow <= 1'b1;
- else
- if(ByteCntEq18)
- DetectionWindow <= 1'b0;
- else
- if(ReceiveEnd)
- DetectionWindow <= 1'b1;
-end
-
-
-
-// Latching Timer Value
-always @ (posedge MRxClk or posedge RxReset )
-begin
- if(RxReset)
- LatchedTimerValue[15:0] <= 16'h0;
- else
- if(DetectionWindow & ReceivedPauseFrmWAddr & ByteCntEq18)
- LatchedTimerValue[15:0] <= AssembledTimerValue[15:0];
- else
- if(ReceiveEnd)
- LatchedTimerValue[15:0] <= 16'h0;
-end
-
-
-
-// Delayed CEC counter
-always @ (posedge MRxClk or posedge RxReset)
-begin
- if(RxReset)
- DlyCrcCnt <= 3'h0;
- else
- if(RxValid & RxEndFrm)
- DlyCrcCnt <= 3'h0;
- else
- if(RxValid & ~RxEndFrm & ~DlyCrcCnt[2])
- DlyCrcCnt <= DlyCrcCnt + 1'b1;
-end
-
-
-assign ResetByteCnt = RxEndFrm;
-assign IncrementByteCnt = RxValid & DetectionWindow & ~ByteCntEq18 & (~DlyCrcEn | DlyCrcEn & DlyCrcCnt[2]);
-
-
-// Byte counter
-always @ (posedge MRxClk or posedge RxReset)
-begin
- if(RxReset)
- ByteCnt[4:0] <= 5'h0;
- else
- if(ResetByteCnt)
- ByteCnt[4:0] <= 5'h0;
- else
- if(IncrementByteCnt)
- ByteCnt[4:0] <= ByteCnt[4:0] + 1'b1;
-end
-
-
-assign ByteCntEq0 = RxValid & ByteCnt[4:0] == 5'h0;
-assign ByteCntEq1 = RxValid & ByteCnt[4:0] == 5'h1;
-assign ByteCntEq2 = RxValid & ByteCnt[4:0] == 5'h2;
-assign ByteCntEq3 = RxValid & ByteCnt[4:0] == 5'h3;
-assign ByteCntEq4 = RxValid & ByteCnt[4:0] == 5'h4;
-assign ByteCntEq5 = RxValid & ByteCnt[4:0] == 5'h5;
-assign ByteCntEq12 = RxValid & ByteCnt[4:0] == 5'h0C;
-assign ByteCntEq13 = RxValid & ByteCnt[4:0] == 5'h0D;
-assign ByteCntEq14 = RxValid & ByteCnt[4:0] == 5'h0E;
-assign ByteCntEq15 = RxValid & ByteCnt[4:0] == 5'h0F;
-assign ByteCntEq16 = RxValid & ByteCnt[4:0] == 5'h10;
-assign ByteCntEq17 = RxValid & ByteCnt[4:0] == 5'h11;
-assign ByteCntEq18 = RxValid & ByteCnt[4:0] == 5'h12 & DetectionWindow;
-
-
-assign SetPauseTimer = ReceiveEnd & ReceivedPauseFrmWAddr & ReceivedPacketGood & ReceivedLengthOK & RxFlow;
-assign DecrementPauseTimer = SlotFinished & |PauseTimer;
-
-
-// PauseTimer[15:0]
-always @ (posedge MRxClk or posedge RxReset)
-begin
- if(RxReset)
- PauseTimer[15:0] <= 16'h0;
- else
- if(SetPauseTimer)
- PauseTimer[15:0] <= LatchedTimerValue[15:0];
- else
- if(DecrementPauseTimer)
- PauseTimer[15:0] <= PauseTimer[15:0] - 1'b1;
-end
-
-assign PauseTimerEq0 = ~(|PauseTimer[15:0]);
-
-
-
-// Synchronization of the pause timer
-always @ (posedge MTxClk or posedge TxReset)
-begin
- if(TxReset)
- begin
- PauseTimerEq0_sync1 <= 1'b1;
- PauseTimerEq0_sync2 <= 1'b1;
- end
- else
- begin
- PauseTimerEq0_sync1 <= PauseTimerEq0;
- PauseTimerEq0_sync2 <= PauseTimerEq0_sync1;
- end
-end
-
-
-// Pause signal generation
-always @ (posedge MTxClk or posedge TxReset)
-begin
- if(TxReset)
- Pause <= 1'b0;
- else
- if((TxDoneIn | TxAbortIn | ~TxUsedDataOutDetected) & ~TxStartFrmOut)
- Pause <= RxFlow & ~PauseTimerEq0_sync2;
-end
-
-
-// Divider2 is used for incrementing the Slot timer every other clock
-always @ (posedge MRxClk or posedge RxReset)
-begin
- if(RxReset)
- Divider2 <= 1'b0;
- else
- if(|PauseTimer[15:0] & RxFlow)
- Divider2 <= ~Divider2;
- else
- Divider2 <= 1'b0;
-end
-
-
-assign ResetSlotTimer = RxReset;
-assign IncrementSlotTimer = Pause & RxFlow & Divider2;
-
-
-// SlotTimer
-always @ (posedge MRxClk or posedge RxReset)
-begin
- if(RxReset)
- SlotTimer[5:0] <= 6'h0;
- else
- if(ResetSlotTimer)
- SlotTimer[5:0] <= 6'h0;
- else
- if(IncrementSlotTimer)
- SlotTimer[5:0] <= SlotTimer[5:0] + 1'b1;
-end
-
-
-assign SlotFinished = &SlotTimer[5:0] & IncrementSlotTimer; // Slot is 512 bits (64 bytes)
-
-
-
-// Pause Frame received
-always @ (posedge MRxClk or posedge RxReset)
-begin
- if(RxReset)
- ReceivedPauseFrm <= 1'b0;
- else
- if(RxStatusWriteLatched_sync2 & r_PassAll | ReceivedPauseFrm & (~r_PassAll))
- ReceivedPauseFrm <= 1'b0;
- else
- if(ByteCntEq16 & TypeLengthOK & OpCodeOK)
- ReceivedPauseFrm <= 1'b1;
-end
-
-
-endmodule
rtl/verilog/eth/eth_receivecontrol.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: rtl/verilog/eth/eth_register.v
===================================================================
--- rtl/verilog/eth/eth_register.v (revision 408)
+++ rtl/verilog/eth/eth_register.v (nonexistent)
@@ -1,108 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_register.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001, 2002 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.5 2002/08/16 12:33:27 mohor
-// Parameter ResetValue changed to capital letters.
-//
-// Revision 1.4 2002/02/26 16:18:08 mohor
-// Reset values are passed to registers through parameters
-//
-// Revision 1.3 2002/01/23 10:28:16 mohor
-// Link in the header changed.
-//
-// Revision 1.2 2001/10/19 08:43:51 mohor
-// eth_timescale.v changed to timescale.v This is done because of the
-// simulation of the few cores in a one joined project.
-//
-// Revision 1.1 2001/08/06 14:44:29 mohor
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
-// Include files fixed to contain no path.
-// File names and module names changed ta have a eth_ prologue in the name.
-// File eth_timescale.v is used to define timescale
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
-// and Mdo_OE. The bidirectional signal must be created on the top level. This
-// is done due to the ASIC tools.
-//
-//
-//
-//
-//
-//
-//
-
-`include "timescale.v"
-
-
-module eth_register(DataIn, DataOut, Write, Clk, Reset, SyncReset);
-
-parameter WIDTH = 8; // default parameter of the register width
-parameter RESET_VALUE = 0;
-
-input [WIDTH-1:0] DataIn;
-
-input Write;
-input Clk;
-input Reset;
-input SyncReset;
-
-output [WIDTH-1:0] DataOut;
-reg [WIDTH-1:0] DataOut;
-
-
-
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- DataOut<= RESET_VALUE;
- else
- if(SyncReset)
- DataOut<= RESET_VALUE;
- else
- if(Write) // write
- DataOut<= DataIn;
-end
-
-
-
-endmodule // Register
rtl/verilog/eth/eth_register.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: rtl/verilog/eth/eth_clockgen.v
===================================================================
--- rtl/verilog/eth/eth_clockgen.v (revision 408)
+++ rtl/verilog/eth/eth_clockgen.v (nonexistent)
@@ -1,131 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_clockgen.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.3 2002/01/23 10:28:16 mohor
-// Link in the header changed.
-//
-// Revision 1.2 2001/10/19 08:43:51 mohor
-// eth_timescale.v changed to timescale.v This is done because of the
-// simulation of the few cores in a one joined project.
-//
-// Revision 1.1 2001/08/06 14:44:29 mohor
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
-// Include files fixed to contain no path.
-// File names and module names changed ta have a eth_ prologue in the name.
-// File eth_timescale.v is used to define timescale
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
-// and Mdo_OE. The bidirectional signal must be created on the top level. This
-// is done due to the ASIC tools.
-//
-// Revision 1.1 2001/07/30 21:23:42 mohor
-// Directory structure changed. Files checked and joind together.
-//
-// Revision 1.3 2001/06/01 22:28:55 mohor
-// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
-//
-//
-
-`include "timescale.v"
-
-module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);
-
-parameter Tp=1;
-
-input Clk; // Input clock (Host clock)
-input Reset; // Reset signal
-input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0])
-
-output Mdc; // Output clock
-output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises.
-output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
-
-reg Mdc;
-reg [7:0] Counter;
-
-wire CountEq0;
-wire [7:0] CounterPreset;
-wire [7:0] TempDivider;
-
-
-assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
-assign CounterPreset[7:0] = (TempDivider[7:0]>>1) - 1'b1; // We are counting half of period
-
-
-// Counter counts half period
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- Counter[7:0] <= 8'h1;
- else
- begin
- if(CountEq0)
- begin
- Counter[7:0] <= CounterPreset[7:0];
- end
- else
- Counter[7:0] <= Counter - 8'h1;
- end
-end
-
-
-// Mdc is asserted every other half period
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- Mdc <= 1'b0;
- else
- begin
- if(CountEq0)
- Mdc <= ~Mdc;
- end
-end
-
-
-assign CountEq0 = Counter == 8'h0;
-assign MdcEn = CountEq0 & ~Mdc;
-assign MdcEn_n = CountEq0 & Mdc;
-
-endmodule
-
-
rtl/verilog/eth/eth_clockgen.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: rtl/verilog/eth/README
===================================================================
--- rtl/verilog/eth/README (revision 408)
+++ rtl/verilog/eth/README (nonexistent)
@@ -1,5 +0,0 @@
-10/100MBps ethernet MAC core
-
-This is based on the core from OpenCores, but heavily modified and improved to provide better bus usage, and buffer configurability.
-
-See the include file, include/eth_defines.v for options.
\ No newline at end of file
Index: rtl/verilog/eth/eth_miim.v
===================================================================
--- rtl/verilog/eth/eth_miim.v (revision 408)
+++ rtl/verilog/eth/eth_miim.v (nonexistent)
@@ -1,448 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_miim.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: not supported by cvs2svn $
-// Revision 1.6 2005/02/21 12:48:07 igorm
-// Warning fixes.
-//
-// Revision 1.5 2003/05/16 10:08:27 mohor
-// Busy was set 2 cycles too late. Reported by Dennis Scott.
-//
-// Revision 1.4 2002/08/14 18:32:10 mohor
-// - Busy signal was not set on time when scan status operation was performed
-// and clock was divided with more than 2.
-// - Nvalid remains valid two more clocks (was previously cleared too soon).
-//
-// Revision 1.3 2002/01/23 10:28:16 mohor
-// Link in the header changed.
-//
-// Revision 1.2 2001/10/19 08:43:51 mohor
-// eth_timescale.v changed to timescale.v This is done because of the
-// simulation of the few cores in a one joined project.
-//
-// Revision 1.1 2001/08/06 14:44:29 mohor
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
-// Include files fixed to contain no path.
-// File names and module names changed ta have a eth_ prologue in the name.
-// File eth_timescale.v is used to define timescale
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
-// and Mdo_OE. The bidirectional signal must be created on the top level. This
-// is done due to the ASIC tools.
-//
-// Revision 1.2 2001/08/02 09:25:31 mohor
-// Unconnected signals are now connected.
-//
-// Revision 1.1 2001/07/30 21:23:42 mohor
-// Directory structure changed. Files checked and joind together.
-//
-// Revision 1.3 2001/06/01 22:28:56 mohor
-// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
-//
-//
-
-`include "timescale.v"
-
-
-module eth_miim
-(
- Clk,
- Reset,
- Divider,
- NoPre,
- CtrlData,
- Rgad,
- Fiad,
- WCtrlData,
- RStat,
- ScanStat,
- Mdi,
- Mdo,
- MdoEn,
- Mdc,
- Busy,
- Prsd,
- LinkFail,
- Nvalid,
- WCtrlDataStart,
- RStatStart,
- UpdateMIIRX_DATAReg
-);
-
-
-
-input Clk; // Host Clock
-input Reset; // General Reset
-input [7:0] Divider; // Divider for the host clock
-input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
-input [4:0] Rgad; // Register Address (within the PHY)
-input [4:0] Fiad; // PHY Address
-input NoPre; // No Preamble (no 32-bit preamble)
-input WCtrlData; // Write Control Data operation
-input RStat; // Read Status operation
-input ScanStat; // Scan Status operation
-input Mdi; // MII Management Data In
-
-output Mdc; // MII Management Data Clock
-output Mdo; // MII Management Data Output
-output MdoEn; // MII Management Data Output Enable
-output Busy; // Busy Signal
-output LinkFail; // Link Integrity Signal
-output Nvalid; // Invalid Status (qualifier for the valid scan result)
-
-output [15:0] Prsd; // Read Status Data (data read from the PHY)
-
-output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
-output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
-output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
-
-parameter Tp = 1;
-
-
-reg Nvalid;
-reg EndBusy_d; // Pre-end Busy signal
-reg EndBusy; // End Busy signal (stops the operation in progress)
-
-reg WCtrlData_q1; // Write Control Data operation delayed 1 Clk cycle
-reg WCtrlData_q2; // Write Control Data operation delayed 2 Clk cycles
-reg WCtrlData_q3; // Write Control Data operation delayed 3 Clk cycles
-reg WCtrlDataStart; // Start Write Control Data Command (positive edge detected)
-reg WCtrlDataStart_q;
-reg WCtrlDataStart_q1; // Start Write Control Data Command delayed 1 Mdc cycle
-reg WCtrlDataStart_q2; // Start Write Control Data Command delayed 2 Mdc cycles
-
-reg RStat_q1; // Read Status operation delayed 1 Clk cycle
-reg RStat_q2; // Read Status operation delayed 2 Clk cycles
-reg RStat_q3; // Read Status operation delayed 3 Clk cycles
-reg RStatStart; // Start Read Status Command (positive edge detected)
-reg RStatStart_q1; // Start Read Status Command delayed 1 Mdc cycle
-reg RStatStart_q2; // Start Read Status Command delayed 2 Mdc cycles
-
-reg ScanStat_q1; // Scan Status operation delayed 1 cycle
-reg ScanStat_q2; // Scan Status operation delayed 2 cycles
-reg SyncStatMdcEn; // Scan Status operation delayed at least cycles and synchronized to MdcEn
-
-wire WriteDataOp; // Write Data Operation (positive edge detected)
-wire ReadStatusOp; // Read Status Operation (positive edge detected)
-wire ScanStatusOp; // Scan Status Operation (positive edge detected)
-wire StartOp; // Start Operation (start of any of the preceding operations)
-wire EndOp; // End of Operation
-
-reg InProgress; // Operation in progress
-reg InProgress_q1; // Operation in progress delayed 1 Mdc cycle
-reg InProgress_q2; // Operation in progress delayed 2 Mdc cycles
-reg InProgress_q3; // Operation in progress delayed 3 Mdc cycles
-
-reg WriteOp; // Write Operation Latch (When asserted, write operation is in progress)
-reg [6:0] BitCounter; // Bit Counter
-
-
-wire [3:0] ByteSelect; // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
-wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
-wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
-wire MdcEn_n;
-
-wire LatchByte1_d2;
-wire LatchByte0_d2;
-reg LatchByte1_d;
-reg LatchByte0_d;
-reg [1:0] LatchByte; // Latch Byte selects which part of Read Status Data is updated from the shift register
-
-reg UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
-
-
-
-
-
-// Generation of the EndBusy signal. It is used for ending the MII Management operation.
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- begin
- EndBusy_d <= 1'b0;
- EndBusy <= 1'b0;
- end
- else
- begin
- EndBusy_d <= ~InProgress_q2 & InProgress_q3;
- EndBusy <= EndBusy_d;
- end
-end
-
-
-// Update MII RX_DATA register
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- UpdateMIIRX_DATAReg <= 0;
- else
- if(EndBusy & ~WCtrlDataStart_q)
- UpdateMIIRX_DATAReg <= 1;
- else
- UpdateMIIRX_DATAReg <= 0;
-end
-
-
-
-// Generation of the delayed signals used for positive edge triggering.
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- begin
- WCtrlData_q1 <= 1'b0;
- WCtrlData_q2 <= 1'b0;
- WCtrlData_q3 <= 1'b0;
-
- RStat_q1 <= 1'b0;
- RStat_q2 <= 1'b0;
- RStat_q3 <= 1'b0;
-
- ScanStat_q1 <= 1'b0;
- ScanStat_q2 <= 1'b0;
- SyncStatMdcEn <= 1'b0;
- end
- else
- begin
- WCtrlData_q1 <= WCtrlData;
- WCtrlData_q2 <= WCtrlData_q1;
- WCtrlData_q3 <= WCtrlData_q2;
-
- RStat_q1 <= RStat;
- RStat_q2 <= RStat_q1;
- RStat_q3 <= RStat_q2;
-
- ScanStat_q1 <= ScanStat;
- ScanStat_q2 <= ScanStat_q1;
- if(MdcEn)
- SyncStatMdcEn <= ScanStat_q2;
- end
-end
-
-
-// Generation of the Start Commands (Write Control Data or Read Status)
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- begin
- WCtrlDataStart <= 1'b0;
- WCtrlDataStart_q <= 1'b0;
- RStatStart <= 1'b0;
- end
- else
- begin
- if(EndBusy)
- begin
- WCtrlDataStart <= 1'b0;
- RStatStart <= 1'b0;
- end
- else
- begin
- if(WCtrlData_q2 & ~WCtrlData_q3)
- WCtrlDataStart <= 1'b1;
- if(RStat_q2 & ~RStat_q3)
- RStatStart <= 1'b1;
- WCtrlDataStart_q <= WCtrlDataStart;
- end
- end
-end
-
-
-// Generation of the Nvalid signal (indicates when the status is invalid)
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- Nvalid <= 1'b0;
- else
- begin
- if(~InProgress_q2 & InProgress_q3)
- begin
- Nvalid <= 1'b0;
- end
- else
- begin
- if(ScanStat_q2 & ~SyncStatMdcEn)
- Nvalid <= 1'b1;
- end
- end
-end
-
-// Signals used for the generation of the Operation signals (positive edge)
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- begin
- WCtrlDataStart_q1 <= 1'b0;
- WCtrlDataStart_q2 <= 1'b0;
-
- RStatStart_q1 <= 1'b0;
- RStatStart_q2 <= 1'b0;
-
- InProgress_q1 <= 1'b0;
- InProgress_q2 <= 1'b0;
- InProgress_q3 <= 1'b0;
-
- LatchByte0_d <= 1'b0;
- LatchByte1_d <= 1'b0;
-
- LatchByte <= 2'b00;
- end
- else
- begin
- if(MdcEn)
- begin
- WCtrlDataStart_q1 <= WCtrlDataStart;
- WCtrlDataStart_q2 <= WCtrlDataStart_q1;
-
- RStatStart_q1 <= RStatStart;
- RStatStart_q2 <= RStatStart_q1;
-
- LatchByte[0] <= LatchByte0_d;
- LatchByte[1] <= LatchByte1_d;
-
- LatchByte0_d <= LatchByte0_d2;
- LatchByte1_d <= LatchByte1_d2;
-
- InProgress_q1 <= InProgress;
- InProgress_q2 <= InProgress_q1;
- InProgress_q3 <= InProgress_q2;
- end
- end
-end
-
-
-// Generation of the Operation signals
-assign WriteDataOp = WCtrlDataStart_q1 & ~WCtrlDataStart_q2;
-assign ReadStatusOp = RStatStart_q1 & ~RStatStart_q2;
-assign ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q1 & ~InProgress_q2;
-assign StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp;
-
-// Busy
-assign Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
-
-
-// Generation of the InProgress signal (indicates when an operation is in progress)
-// Generation of the WriteOp signal (indicates when a write is in progress)
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- begin
- InProgress <= 1'b0;
- WriteOp <= 1'b0;
- end
- else
- begin
- if(MdcEn)
- begin
- if(StartOp)
- begin
- if(~InProgress)
- WriteOp <= WriteDataOp;
- InProgress <= 1'b1;
- end
- else
- begin
- if(EndOp)
- begin
- InProgress <= 1'b0;
- WriteOp <= 1'b0;
- end
- end
- end
- end
-end
-
-
-
-// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- BitCounter[6:0] <= 7'h0;
- else
- begin
- if(MdcEn)
- begin
- if(InProgress)
- begin
- if(NoPre & ( BitCounter == 7'h0 ))
- BitCounter[6:0] <= 7'h21;
- else
- BitCounter[6:0] <= BitCounter[6:0] + 1'b1;
- end
- else
- BitCounter[6:0] <= 7'h0;
- end
- end
-end
-
-
-// Operation ends when the Bit Counter reaches 63
-assign EndOp = BitCounter==63;
-
-assign ByteSelect[0] = InProgress & ((NoPre & (BitCounter == 7'h0)) | (~NoPre & (BitCounter == 7'h20)));
-assign ByteSelect[1] = InProgress & (BitCounter == 7'h28);
-assign ByteSelect[2] = InProgress & WriteOp & (BitCounter == 7'h30);
-assign ByteSelect[3] = InProgress & WriteOp & (BitCounter == 7'h38);
-
-
-// Latch Byte selects which part of Read Status Data is updated from the shift register
-assign LatchByte1_d2 = InProgress & ~WriteOp & BitCounter == 7'h37;
-assign LatchByte0_d2 = InProgress & ~WriteOp & BitCounter == 7'h3F;
-
-
-// Connecting the Clock Generator Module
-eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc)
- );
-
-// Connecting the Shift Register Module
-eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
- .CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
- .ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
- );
-
-// Connecting the Output Control Module
-eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
- .ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
- .Mdo(Mdo), .MdoEn(MdoEn)
- );
-
-endmodule
rtl/verilog/eth/eth_miim.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: rtl/verilog/include/eth_defines.v
===================================================================
--- rtl/verilog/include/eth_defines.v (revision 408)
+++ rtl/verilog/include/eth_defines.v (nonexistent)
@@ -1,255 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_defines.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://opencores.org/project,ethmac ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// ////
-//// Modified by: ////
-//// - Julius Baxter (julius@opencores.org) ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001, 2002 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-
-
-
-//`define ETH_BIST // Bist for usage with Virtual Silicon RAMS
-
-`define ETH_MBIST_CTRL_WIDTH 3 // width of MBIST control bus
-
-// Generic FIFO implementation - hopefully synthesizable with Synplify
-`define ETH_FIFO_GENERIC
-// Ethernet implemented in Xilinx Chips (uncomment following lines)
-// `define ETH_FIFO_XILINX // Use Xilinx distributed ram for tx and rx fifo
-// `define ETH_XILINX_RAMB4 // Selection of the used memory for Buffer descriptors
- // Core is going to be implemented in Virtex FPGA and contains Virtex
- // specific elements.
-
-// Ethernet implemented in Altera Chips (uncomment following lines)
-//`define ETH_ALTERA_ALTSYNCRAM
-
-// Ethernet implemented in ASIC with Virtual Silicon RAMs
-// `define ETH_VIRTUAL_SILICON_RAM // Virtual Silicon RAMS used storing buffer decriptors (ASIC implementation)
-
-// Ethernet implemented in ASIC with Artisan RAMs
-// `define ETH_ARTISAN_RAM // Artisan RAMS used storing buffer decriptors (ASIC implementation)
-
-// Uncomment when Avalon bus is used
-//`define ETH_AVALON_BUS
-
-`define ETH_MODER_ADR 8'h0 // 0x0
-`define ETH_INT_SOURCE_ADR 8'h1 // 0x4
-`define ETH_INT_MASK_ADR 8'h2 // 0x8
-`define ETH_IPGT_ADR 8'h3 // 0xC
-`define ETH_IPGR1_ADR 8'h4 // 0x10
-`define ETH_IPGR2_ADR 8'h5 // 0x14
-`define ETH_PACKETLEN_ADR 8'h6 // 0x18
-`define ETH_COLLCONF_ADR 8'h7 // 0x1C
-`define ETH_TX_BD_NUM_ADR 8'h8 // 0x20
-`define ETH_CTRLMODER_ADR 8'h9 // 0x24
-`define ETH_MIIMODER_ADR 8'hA // 0x28
-`define ETH_MIICOMMAND_ADR 8'hB // 0x2C
-`define ETH_MIIADDRESS_ADR 8'hC // 0x30
-`define ETH_MIITX_DATA_ADR 8'hD // 0x34
-`define ETH_MIIRX_DATA_ADR 8'hE // 0x38
-`define ETH_MIISTATUS_ADR 8'hF // 0x3C
-`define ETH_MAC_ADDR0_ADR 8'h10 // 0x40
-`define ETH_MAC_ADDR1_ADR 8'h11 // 0x44
-`define ETH_HASH0_ADR 8'h12 // 0x48
-`define ETH_HASH1_ADR 8'h13 // 0x4C
-`define ETH_TX_CTRL_ADR 8'h14 // 0x50
-`define ETH_RX_CTRL_ADR 8'h15 // 0x54
-`define ETH_DBG_ADR 8'h16 // 0x58
-
-
-`define ETH_MODER_DEF_0 8'h00
-`define ETH_MODER_DEF_1 8'hA0
-`define ETH_MODER_DEF_2 1'h0
-`define ETH_INT_MASK_DEF_0 7'h0
-`define ETH_IPGT_DEF_0 7'h12
-`define ETH_IPGR1_DEF_0 7'h0C
-`define ETH_IPGR2_DEF_0 7'h12
-`define ETH_PACKETLEN_DEF_0 8'h00
-`define ETH_PACKETLEN_DEF_1 8'h06
-`define ETH_PACKETLEN_DEF_2 8'h40
-`define ETH_PACKETLEN_DEF_3 8'h00
-`define ETH_COLLCONF_DEF_0 6'h3f
-`define ETH_COLLCONF_DEF_2 4'hF
-`define ETH_TX_BD_NUM_DEF_0 8'h40
-`define ETH_CTRLMODER_DEF_0 3'h0
-`define ETH_MIIMODER_DEF_0 8'h64
-`define ETH_MIIMODER_DEF_1 1'h0
-`define ETH_MIIADDRESS_DEF_0 5'h00
-`define ETH_MIIADDRESS_DEF_1 5'h00
-`define ETH_MIITX_DATA_DEF_0 8'h00
-`define ETH_MIITX_DATA_DEF_1 8'h00
-`define ETH_MIIRX_DATA_DEF 16'h0000 // not written from WB
-`define ETH_MAC_ADDR0_DEF_0 8'h00
-`define ETH_MAC_ADDR0_DEF_1 8'h00
-`define ETH_MAC_ADDR0_DEF_2 8'h00
-`define ETH_MAC_ADDR0_DEF_3 8'h00
-`define ETH_MAC_ADDR1_DEF_0 8'h00
-`define ETH_MAC_ADDR1_DEF_1 8'h00
-`define ETH_HASH0_DEF_0 8'h00
-`define ETH_HASH0_DEF_1 8'h00
-`define ETH_HASH0_DEF_2 8'h00
-`define ETH_HASH0_DEF_3 8'h00
-`define ETH_HASH1_DEF_0 8'h00
-`define ETH_HASH1_DEF_1 8'h00
-`define ETH_HASH1_DEF_2 8'h00
-`define ETH_HASH1_DEF_3 8'h00
-`define ETH_TX_CTRL_DEF_0 8'h00 //
-`define ETH_TX_CTRL_DEF_1 8'h00 //
-`define ETH_TX_CTRL_DEF_2 1'h0 //
-`define ETH_RX_CTRL_DEF_0 8'h00
-`define ETH_RX_CTRL_DEF_1 8'h00
-
-
-`define ETH_MODER_WIDTH_0 8
-`define ETH_MODER_WIDTH_1 8
-`define ETH_MODER_WIDTH_2 1
-`define ETH_INT_SOURCE_WIDTH_0 7
-`define ETH_INT_MASK_WIDTH_0 7
-`define ETH_IPGT_WIDTH_0 7
-`define ETH_IPGR1_WIDTH_0 7
-`define ETH_IPGR2_WIDTH_0 7
-`define ETH_PACKETLEN_WIDTH_0 8
-`define ETH_PACKETLEN_WIDTH_1 8
-`define ETH_PACKETLEN_WIDTH_2 8
-`define ETH_PACKETLEN_WIDTH_3 8
-`define ETH_COLLCONF_WIDTH_0 6
-`define ETH_COLLCONF_WIDTH_2 4
-`define ETH_TX_BD_NUM_WIDTH_0 8
-`define ETH_CTRLMODER_WIDTH_0 3
-`define ETH_MIIMODER_WIDTH_0 8
-`define ETH_MIIMODER_WIDTH_1 1
-`define ETH_MIICOMMAND_WIDTH_0 3
-`define ETH_MIIADDRESS_WIDTH_0 5
-`define ETH_MIIADDRESS_WIDTH_1 5
-`define ETH_MIITX_DATA_WIDTH_0 8
-`define ETH_MIITX_DATA_WIDTH_1 8
-`define ETH_MIIRX_DATA_WIDTH 16 // not written from WB
-`define ETH_MIISTATUS_WIDTH 3 // not written from WB
-`define ETH_MAC_ADDR0_WIDTH_0 8
-`define ETH_MAC_ADDR0_WIDTH_1 8
-`define ETH_MAC_ADDR0_WIDTH_2 8
-`define ETH_MAC_ADDR0_WIDTH_3 8
-`define ETH_MAC_ADDR1_WIDTH_0 8
-`define ETH_MAC_ADDR1_WIDTH_1 8
-`define ETH_HASH0_WIDTH_0 8
-`define ETH_HASH0_WIDTH_1 8
-`define ETH_HASH0_WIDTH_2 8
-`define ETH_HASH0_WIDTH_3 8
-`define ETH_HASH1_WIDTH_0 8
-`define ETH_HASH1_WIDTH_1 8
-`define ETH_HASH1_WIDTH_2 8
-`define ETH_HASH1_WIDTH_3 8
-`define ETH_TX_CTRL_WIDTH_0 8
-`define ETH_TX_CTRL_WIDTH_1 8
-`define ETH_TX_CTRL_WIDTH_2 1
-`define ETH_RX_CTRL_WIDTH_0 8
-`define ETH_RX_CTRL_WIDTH_1 8
-
-
-// Outputs are registered (uncomment when needed)
-`define ETH_REGISTERED_OUTPUTS
-
-// Settings for TX FIFO
-`define ETH_TX_FIFO_DATA_WIDTH 32
-
-// Defines for ethernet TX fifo size - impacts FPGA resource usage
-//`define ETH_TX_FULL_PACKET_FIFO // Full 1500 byte TX buffer - uncomment this
-//`define ETH_TX_256BYTE_FIFO // 256 byte TX buffer - uncomment this
-//`define ETH_TX_512BYTE_FIFO // 512 byte TX buffer - uncomment this
-`define ETH_TX_1KBYTE_FIFO // 1024 byte TX buffer - uncomment this
-
-`ifdef ETH_TX_FULL_PACKET_FIFO
- `define ETH_TX_FIFO_CNT_WIDTH 11
- `define ETH_TX_FIFO_DEPTH 375
-`else
- `ifdef ETH_TX_1KBYTE_FIFO
- `define ETH_TX_FIFO_CNT_WIDTH 9
- `define ETH_TX_FIFO_DEPTH 256
- `else
- `ifdef ETH_TX_512BYTE_FIFO
- `define ETH_TX_FIFO_CNT_WIDTH 8
- `define ETH_TX_FIFO_DEPTH 128
- `else
- `ifdef ETH_TX_256BYTE_FIFO
- `define ETH_TX_FIFO_CNT_WIDTH 7
- `define ETH_TX_FIFO_DEPTH 64
- `else
-// Default is 64 bytes
- `define ETH_TX_FIFO_CNT_WIDTH 5
- `define ETH_TX_FIFO_DEPTH 16
- `endif
- `endif
- `endif // !`ifdef ETH_TX_512BYTE_FIFO
-`endif // !`ifdef ETH_TX_FULL_PACKET_FIFO
-
-
-
-// Settings for RX FIFO
-`define ETH_RX_FIFO_CNT_WIDTH 9
-`define ETH_RX_FIFO_DEPTH 256
-//`define ETH_RX_FIFO_CNT_WIDTH 8
-//`define ETH_RX_FIFO_DEPTH 128
-//`define ETH_RX_FIFO_CNT_WIDTH 7
-//`define ETH_RX_FIFO_DEPTH 64
-//`define ETH_RX_FIFO_CNT_WIDTH 6
-//`define ETH_RX_FIFO_DEPTH 32
-//`define ETH_RX_FIFO_CNT_WIDTH 5
-//`define ETH_RX_FIFO_DEPTH 16
-
-`define ETH_RX_FIFO_DATA_WIDTH 32
-
-// Burst length
-`define BURST_4BEAT
-`ifdef BURST_4BEAT
- `define ETH_BURST_LENGTH 4 // Change also ETH_BURST_CNT_WIDTH
- `define ETH_BURST_CNT_WIDTH 3 // The counter must be width enough to count to ETH_BURST_LENGTH
-`endif
-
-//`define ETH_BURST_LENGTH 32 // Change also ETH_BURST_CNT_WIDTH
-//`define ETH_BURST_CNT_WIDTH 7 // The counter must be width enough to count to ETH_BURST_LENGTH
-
-// Undefine this to enable bursting for RX (writing to memory)
-`define ETH_RX_BURST_EN
-
-
-// WISHBONE interface is Revision B3 compliant (uncomment when needed)
-`define ETH_WISHBONE_B3
-
-// Hack where the transmit logic polls each of the TX buffers instead of having to keep track of what's going on
-//`define TXBD_POLL
-
-// Define this to allow reading of the Wishbone control state machine on reg
-// address 0x58
-`define WISHBONE_DEBUG
\ No newline at end of file
rtl/verilog/include/eth_defines.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: rtl/verilog/include/ethmac_defines.v
===================================================================
--- rtl/verilog/include/ethmac_defines.v (nonexistent)
+++ rtl/verilog/include/ethmac_defines.v (revision 409)
@@ -0,0 +1,255 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// eth_defines.v ////
+//// ////
+//// This file is part of the Ethernet IP core project ////
+//// http://opencores.org/project,ethmac ////
+//// ////
+//// Author(s): ////
+//// - Igor Mohor (igorM@opencores.org) ////
+//// ////
+//// Modified by: ////
+//// - Julius Baxter (julius@opencores.org) ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001, 2002 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+
+
+//`define ETH_BIST // Bist for usage with Virtual Silicon RAMS
+
+`define ETH_MBIST_CTRL_WIDTH 3 // width of MBIST control bus
+
+// Generic FIFO implementation - hopefully synthesizable with Synplify
+`define ETH_FIFO_GENERIC
+// Ethernet implemented in Xilinx Chips (uncomment following lines)
+// `define ETH_FIFO_XILINX // Use Xilinx distributed ram for tx and rx fifo
+// `define ETH_XILINX_RAMB4 // Selection of the used memory for Buffer descriptors
+ // Core is going to be implemented in Virtex FPGA and contains Virtex
+ // specific elements.
+
+// Ethernet implemented in Altera Chips (uncomment following lines)
+//`define ETH_ALTERA_ALTSYNCRAM
+
+// Ethernet implemented in ASIC with Virtual Silicon RAMs
+// `define ETH_VIRTUAL_SILICON_RAM // Virtual Silicon RAMS used storing buffer decriptors (ASIC implementation)
+
+// Ethernet implemented in ASIC with Artisan RAMs
+// `define ETH_ARTISAN_RAM // Artisan RAMS used storing buffer decriptors (ASIC implementation)
+
+// Uncomment when Avalon bus is used
+//`define ETH_AVALON_BUS
+
+`define ETH_MODER_ADR 8'h0 // 0x0
+`define ETH_INT_SOURCE_ADR 8'h1 // 0x4
+`define ETH_INT_MASK_ADR 8'h2 // 0x8
+`define ETH_IPGT_ADR 8'h3 // 0xC
+`define ETH_IPGR1_ADR 8'h4 // 0x10
+`define ETH_IPGR2_ADR 8'h5 // 0x14
+`define ETH_PACKETLEN_ADR 8'h6 // 0x18
+`define ETH_COLLCONF_ADR 8'h7 // 0x1C
+`define ETH_TX_BD_NUM_ADR 8'h8 // 0x20
+`define ETH_CTRLMODER_ADR 8'h9 // 0x24
+`define ETH_MIIMODER_ADR 8'hA // 0x28
+`define ETH_MIICOMMAND_ADR 8'hB // 0x2C
+`define ETH_MIIADDRESS_ADR 8'hC // 0x30
+`define ETH_MIITX_DATA_ADR 8'hD // 0x34
+`define ETH_MIIRX_DATA_ADR 8'hE // 0x38
+`define ETH_MIISTATUS_ADR 8'hF // 0x3C
+`define ETH_MAC_ADDR0_ADR 8'h10 // 0x40
+`define ETH_MAC_ADDR1_ADR 8'h11 // 0x44
+`define ETH_HASH0_ADR 8'h12 // 0x48
+`define ETH_HASH1_ADR 8'h13 // 0x4C
+`define ETH_TX_CTRL_ADR 8'h14 // 0x50
+`define ETH_RX_CTRL_ADR 8'h15 // 0x54
+`define ETH_DBG_ADR 8'h16 // 0x58
+
+
+`define ETH_MODER_DEF_0 8'h00
+`define ETH_MODER_DEF_1 8'hA0
+`define ETH_MODER_DEF_2 1'h0
+`define ETH_INT_MASK_DEF_0 7'h0
+`define ETH_IPGT_DEF_0 7'h12
+`define ETH_IPGR1_DEF_0 7'h0C
+`define ETH_IPGR2_DEF_0 7'h12
+`define ETH_PACKETLEN_DEF_0 8'h00
+`define ETH_PACKETLEN_DEF_1 8'h06
+`define ETH_PACKETLEN_DEF_2 8'h40
+`define ETH_PACKETLEN_DEF_3 8'h00
+`define ETH_COLLCONF_DEF_0 6'h3f
+`define ETH_COLLCONF_DEF_2 4'hF
+`define ETH_TX_BD_NUM_DEF_0 8'h40
+`define ETH_CTRLMODER_DEF_0 3'h0
+`define ETH_MIIMODER_DEF_0 8'h64
+`define ETH_MIIMODER_DEF_1 1'h0
+`define ETH_MIIADDRESS_DEF_0 5'h00
+`define ETH_MIIADDRESS_DEF_1 5'h00
+`define ETH_MIITX_DATA_DEF_0 8'h00
+`define ETH_MIITX_DATA_DEF_1 8'h00
+`define ETH_MIIRX_DATA_DEF 16'h0000 // not written from WB
+`define ETH_MAC_ADDR0_DEF_0 8'h00
+`define ETH_MAC_ADDR0_DEF_1 8'h00
+`define ETH_MAC_ADDR0_DEF_2 8'h00
+`define ETH_MAC_ADDR0_DEF_3 8'h00
+`define ETH_MAC_ADDR1_DEF_0 8'h00
+`define ETH_MAC_ADDR1_DEF_1 8'h00
+`define ETH_HASH0_DEF_0 8'h00
+`define ETH_HASH0_DEF_1 8'h00
+`define ETH_HASH0_DEF_2 8'h00
+`define ETH_HASH0_DEF_3 8'h00
+`define ETH_HASH1_DEF_0 8'h00
+`define ETH_HASH1_DEF_1 8'h00
+`define ETH_HASH1_DEF_2 8'h00
+`define ETH_HASH1_DEF_3 8'h00
+`define ETH_TX_CTRL_DEF_0 8'h00 //
+`define ETH_TX_CTRL_DEF_1 8'h00 //
+`define ETH_TX_CTRL_DEF_2 1'h0 //
+`define ETH_RX_CTRL_DEF_0 8'h00
+`define ETH_RX_CTRL_DEF_1 8'h00
+
+
+`define ETH_MODER_WIDTH_0 8
+`define ETH_MODER_WIDTH_1 8
+`define ETH_MODER_WIDTH_2 1
+`define ETH_INT_SOURCE_WIDTH_0 7
+`define ETH_INT_MASK_WIDTH_0 7
+`define ETH_IPGT_WIDTH_0 7
+`define ETH_IPGR1_WIDTH_0 7
+`define ETH_IPGR2_WIDTH_0 7
+`define ETH_PACKETLEN_WIDTH_0 8
+`define ETH_PACKETLEN_WIDTH_1 8
+`define ETH_PACKETLEN_WIDTH_2 8
+`define ETH_PACKETLEN_WIDTH_3 8
+`define ETH_COLLCONF_WIDTH_0 6
+`define ETH_COLLCONF_WIDTH_2 4
+`define ETH_TX_BD_NUM_WIDTH_0 8
+`define ETH_CTRLMODER_WIDTH_0 3
+`define ETH_MIIMODER_WIDTH_0 8
+`define ETH_MIIMODER_WIDTH_1 1
+`define ETH_MIICOMMAND_WIDTH_0 3
+`define ETH_MIIADDRESS_WIDTH_0 5
+`define ETH_MIIADDRESS_WIDTH_1 5
+`define ETH_MIITX_DATA_WIDTH_0 8
+`define ETH_MIITX_DATA_WIDTH_1 8
+`define ETH_MIIRX_DATA_WIDTH 16 // not written from WB
+`define ETH_MIISTATUS_WIDTH 3 // not written from WB
+`define ETH_MAC_ADDR0_WIDTH_0 8
+`define ETH_MAC_ADDR0_WIDTH_1 8
+`define ETH_MAC_ADDR0_WIDTH_2 8
+`define ETH_MAC_ADDR0_WIDTH_3 8
+`define ETH_MAC_ADDR1_WIDTH_0 8
+`define ETH_MAC_ADDR1_WIDTH_1 8
+`define ETH_HASH0_WIDTH_0 8
+`define ETH_HASH0_WIDTH_1 8
+`define ETH_HASH0_WIDTH_2 8
+`define ETH_HASH0_WIDTH_3 8
+`define ETH_HASH1_WIDTH_0 8
+`define ETH_HASH1_WIDTH_1 8
+`define ETH_HASH1_WIDTH_2 8
+`define ETH_HASH1_WIDTH_3 8
+`define ETH_TX_CTRL_WIDTH_0 8
+`define ETH_TX_CTRL_WIDTH_1 8
+`define ETH_TX_CTRL_WIDTH_2 1
+`define ETH_RX_CTRL_WIDTH_0 8
+`define ETH_RX_CTRL_WIDTH_1 8
+
+
+// Outputs are registered (uncomment when needed)
+`define ETH_REGISTERED_OUTPUTS
+
+// Settings for TX FIFO
+`define ETH_TX_FIFO_DATA_WIDTH 32
+
+// Defines for ethernet TX fifo size - impacts FPGA resource usage
+//`define ETH_TX_FULL_PACKET_FIFO // Full 1500 byte TX buffer - uncomment this
+//`define ETH_TX_256BYTE_FIFO // 256 byte TX buffer - uncomment this
+//`define ETH_TX_512BYTE_FIFO // 512 byte TX buffer - uncomment this
+`define ETH_TX_1KBYTE_FIFO // 1024 byte TX buffer - uncomment this
+
+`ifdef ETH_TX_FULL_PACKET_FIFO
+ `define ETH_TX_FIFO_CNT_WIDTH 11
+ `define ETH_TX_FIFO_DEPTH 375
+`else
+ `ifdef ETH_TX_1KBYTE_FIFO
+ `define ETH_TX_FIFO_CNT_WIDTH 9
+ `define ETH_TX_FIFO_DEPTH 256
+ `else
+ `ifdef ETH_TX_512BYTE_FIFO
+ `define ETH_TX_FIFO_CNT_WIDTH 8
+ `define ETH_TX_FIFO_DEPTH 128
+ `else
+ `ifdef ETH_TX_256BYTE_FIFO
+ `define ETH_TX_FIFO_CNT_WIDTH 7
+ `define ETH_TX_FIFO_DEPTH 64
+ `else
+// Default is 64 bytes
+ `define ETH_TX_FIFO_CNT_WIDTH 5
+ `define ETH_TX_FIFO_DEPTH 16
+ `endif
+ `endif
+ `endif // !`ifdef ETH_TX_512BYTE_FIFO
+`endif // !`ifdef ETH_TX_FULL_PACKET_FIFO
+
+
+
+// Settings for RX FIFO
+`define ETH_RX_FIFO_CNT_WIDTH 9
+`define ETH_RX_FIFO_DEPTH 256
+//`define ETH_RX_FIFO_CNT_WIDTH 8
+//`define ETH_RX_FIFO_DEPTH 128
+//`define ETH_RX_FIFO_CNT_WIDTH 7
+//`define ETH_RX_FIFO_DEPTH 64
+//`define ETH_RX_FIFO_CNT_WIDTH 6
+//`define ETH_RX_FIFO_DEPTH 32
+//`define ETH_RX_FIFO_CNT_WIDTH 5
+//`define ETH_RX_FIFO_DEPTH 16
+
+`define ETH_RX_FIFO_DATA_WIDTH 32
+
+// Burst length
+`define BURST_4BEAT
+`ifdef BURST_4BEAT
+ `define ETH_BURST_LENGTH 4 // Change also ETH_BURST_CNT_WIDTH
+ `define ETH_BURST_CNT_WIDTH 3 // The counter must be width enough to count to ETH_BURST_LENGTH
+`endif
+
+//`define ETH_BURST_LENGTH 32 // Change also ETH_BURST_CNT_WIDTH
+//`define ETH_BURST_CNT_WIDTH 7 // The counter must be width enough to count to ETH_BURST_LENGTH
+
+// Undefine this to enable bursting for RX (writing to memory)
+`define ETH_RX_BURST_EN
+
+
+// WISHBONE interface is Revision B3 compliant (uncomment when needed)
+`define ETH_WISHBONE_B3
+
+// Hack where the transmit logic polls each of the TX buffers instead of having to keep track of what's going on
+//`define TXBD_POLL
+
+// Define this to allow reading of the Wishbone control state machine on reg
+// address 0x58
+`define WISHBONE_DEBUG
\ No newline at end of file
rtl/verilog/include/ethmac_defines.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rtl/verilog/ethmac/eth_spram_256x32.v
===================================================================
--- rtl/verilog/ethmac/eth_spram_256x32.v (nonexistent)
+++ rtl/verilog/ethmac/eth_spram_256x32.v (revision 409)
@@ -0,0 +1,334 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// eth_spram_256x32.v ////
+//// ////
+//// This file is part of the Ethernet IP core project ////
+//// http://www.opencores.org/project,ethmac ////
+//// ////
+//// Author(s): ////
+//// - Igor Mohor (igorM@opencores.org) ////
+//// ////
+//// All additional information is available in the Readme.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001, 2002 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.9 2003/12/05 12:43:06 tadejm
+// Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16.
+//
+// Revision 1.8 2003/12/04 14:59:13 simons
+// Lapsus fixed (!we -> ~we).
+//
+// Revision 1.7 2003/11/12 18:24:59 tadejm
+// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
+//
+// Revision 1.6 2003/10/17 07:46:15 markom
+// mbist signals updated according to newest convention
+//
+// Revision 1.5 2003/08/14 16:42:58 simons
+// Artisan ram instance added.
+//
+// Revision 1.4 2002/10/18 17:04:20 tadejm
+// Changed BIST scan signals.
+//
+// Revision 1.3 2002/10/10 16:29:30 mohor
+// BIST added.
+//
+// Revision 1.2 2002/09/23 18:24:31 mohor
+// ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).
+//
+// Revision 1.1 2002/07/23 16:36:09 mohor
+// ethernet spram added. So far a generic ram and xilinx RAMB4 are used.
+//
+//
+//
+
+`include "ethmac_defines.v"
+`include "timescale.v"
+
+module eth_spram_256x32(
+ // Generic synchronous single-port RAM interface
+ clk, rst, ce, we, oe, addr, di, do
+
+`ifdef ETH_BIST
+ ,
+ // debug chain signals
+ mbist_si_i, // bist scan serial in
+ mbist_so_o, // bist scan serial out
+ mbist_ctrl_i // bist chain shift control
+`endif
+
+
+
+ );
+ parameter we_width = 4;
+
+ //
+ // Generic synchronous single-port RAM interface
+ //
+ input clk; // Clock, rising edge
+ input rst; // Reset, active high
+ input ce; // Chip enable input, active high
+ input [we_width-1:0] we; // Write enable input, active high
+ input oe; // Output enable input, active high
+ input [7:0] addr; // address bus inputs
+ input [31:0] di; // input data bus
+ output [31:0] do; // output data bus
+
+
+`ifdef ETH_BIST
+ input mbist_si_i; // bist scan serial in
+ output mbist_so_o; // bist scan serial out
+ input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
+`endif
+
+`ifdef ETH_XILINX_RAMB4
+
+ /*RAMB4_S16 ram0
+ (
+ .DO (do[15:0]),
+ .ADDR (addr),
+ .DI (di[15:0]),
+ .EN (ce),
+ .CLK (clk),
+ .WE (we),
+ .RST (rst)
+ );
+
+ RAMB4_S16 ram1
+ (
+ .DO (do[31:16]),
+ .ADDR (addr),
+ .DI (di[31:16]),
+ .EN (ce),
+ .CLK (clk),
+ .WE (we),
+ .RST (rst)
+ );*/
+
+ RAMB4_S8 ram0
+ (
+ .DO (do[7:0]),
+ .ADDR ({1'b0, addr}),
+ .DI (di[7:0]),
+ .EN (ce),
+ .CLK (clk),
+ .WE (we[0]),
+ .RST (rst)
+ );
+
+ RAMB4_S8 ram1
+ (
+ .DO (do[15:8]),
+ .ADDR ({1'b0, addr}),
+ .DI (di[15:8]),
+ .EN (ce),
+ .CLK (clk),
+ .WE (we[1]),
+ .RST (rst)
+ );
+
+ RAMB4_S8 ram2
+ (
+ .DO (do[23:16]),
+ .ADDR ({1'b0, addr}),
+ .DI (di[23:16]),
+ .EN (ce),
+ .CLK (clk),
+ .WE (we[2]),
+ .RST (rst)
+ );
+
+ RAMB4_S8 ram3
+ (
+ .DO (do[31:24]),
+ .ADDR ({1'b0, addr}),
+ .DI (di[31:24]),
+ .EN (ce),
+ .CLK (clk),
+ .WE (we[3]),
+ .RST (rst)
+ );
+
+`else // !ETH_XILINX_RAMB4
+ `ifdef ETH_VIRTUAL_SILICON_RAM
+ `ifdef ETH_BIST
+ //vs_hdsp_256x32_bist ram0_bist
+ vs_hdsp_256x32_bw_bist ram0_bist
+ `else
+ //vs_hdsp_256x32 ram0
+ vs_hdsp_256x32_bw ram0
+ `endif
+ (
+ .CK (clk),
+ .CEN (!ce),
+ .WEN (~we),
+ .OEN (!oe),
+ .ADR (addr),
+ .DI (di),
+ .DOUT (do)
+
+ `ifdef ETH_BIST
+ ,
+ // debug chain signals
+ .mbist_si_i (mbist_si_i),
+ .mbist_so_o (mbist_so_o),
+ .mbist_ctrl_i (mbist_ctrl_i)
+ `endif
+ );
+
+ `else // !ETH_VIRTUAL_SILICON_RAM
+
+ `ifdef ETH_ARTISAN_RAM
+ `ifdef ETH_BIST
+ //art_hssp_256x32_bist ram0_bist
+ art_hssp_256x32_bw_bist ram0_bist
+ `else
+ //art_hssp_256x32 ram0
+ art_hssp_256x32_bw ram0
+ `endif
+ (
+ .CLK (clk),
+ .CEN (!ce),
+ .WEN (~we),
+ .OEN (!oe),
+ .A (addr),
+ .D (di),
+ .Q (do)
+
+ `ifdef ETH_BIST
+ ,
+ // debug chain signals
+ .mbist_si_i (mbist_si_i),
+ .mbist_so_o (mbist_so_o),
+ .mbist_ctrl_i (mbist_ctrl_i)
+ `endif
+ );
+
+ `else // !ETH_ARTISAN_RAM
+ `ifdef ETH_ALTERA_ALTSYNCRAM
+
+ altera_spram_256x32 altera_spram_256x32_inst
+ (
+ .address (addr),
+ .wren (ce & we),
+ .clock (clk),
+ .data (di),
+ .q (do)
+ ); //exemplar attribute altera_spram_256x32_inst NOOPT TRUE
+
+ `else // !ETH_ALTERA_ALTSYNCRAM
+
+
+ //
+ // Generic single-port synchronous RAM model
+ //
+
+ //
+ // Generic RAM's registers and wires
+ //
+ reg [ 7: 0] mem0 [255:0]; // RAM content
+ reg [15: 8] mem1 [255:0]; // RAM content
+ reg [23:16] mem2 [255:0]; // RAM content
+ reg [31:24] mem3 [255:0]; // RAM content
+ wire [31:0] q; // RAM output
+ reg [7:0] raddr; // RAM read address
+
+ reg [31:0] mem[255:0];
+
+ //
+ // Data output drivers
+ //
+ //assign do = (oe & ce) ? q : {32{1'bz}};
+ assign do = (oe & ce) ? q : {32{1'bx}};
+
+ //
+ // RAM read and write
+ //
+
+ // read operation
+ always@(posedge clk)
+ if (ce)
+ raddr <= addr; // read address needs to be registered to read clock
+
+ generate
+ if (we_width > 1)
+ begin
+
+ assign q = rst ? {32{1'b0}} : {mem3[raddr], mem2[raddr], mem1[raddr],
+ mem0[raddr]};
+
+ // write operation
+ always@(posedge clk)
+ begin
+ if (ce && we[3])
+ mem3[addr] <= di[31:24];
+ if (ce && we[2])
+ mem2[addr] <= di[23:16];
+ if (ce && we[1])
+ mem1[addr] <= di[15: 8];
+ if (ce && we[0])
+ mem0[addr] <= di[ 7: 0];
+ end
+
+ end // if (we_width > 1)
+ else
+ begin
+ assign q = rst ? {32{1'b0}} : {mem[raddr]};
+
+ // write operation
+ always@(posedge clk)
+ begin
+ if (ce && we[0])
+ mem[addr] <= di[ 31: 0];
+ end
+
+ end // else: !if(we_width > 1)
+ endgenerate
+
+ // Task prints range of memory
+ // *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations.
+ task print_ram;
+ input [7:0] start;
+ input [7:0] finish;
+ integer rnum;
+ begin
+ for (rnum=start;rnum<=finish;rnum=rnum+1)
+ $display("Addr %h = %0h %0h %0h %0h",rnum,mem3[rnum],mem2[rnum],mem1[rnum],mem0[rnum]);
+ end
+ endtask
+
+ `endif // !ETH_ALTERA_ALTSYNCRAM
+ `endif // !ETH_ARTISAN_RAM
+ `endif // !ETH_VIRTUAL_SILICON_RAM
+`endif // !ETH_XILINX_RAMB4
+
+endmodule
rtl/verilog/ethmac/eth_spram_256x32.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rtl/verilog/ethmac/eth_shiftreg.v
===================================================================
--- rtl/verilog/ethmac/eth_shiftreg.v (nonexistent)
+++ rtl/verilog/ethmac/eth_shiftreg.v (revision 409)
@@ -0,0 +1,151 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// eth_shiftreg.v ////
+//// ////
+//// This file is part of the Ethernet IP core project ////
+//// http://www.opencores.org/project,ethmac ////
+//// ////
+//// Author(s): ////
+//// - Igor Mohor (igorM@opencores.org) ////
+//// ////
+//// All additional information is avaliable in the Readme.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.5 2002/08/14 18:16:59 mohor
+// LinkFail signal was not latching appropriate bit.
+//
+// Revision 1.4 2002/03/02 21:06:01 mohor
+// LinkFail signal was not latching appropriate bit.
+//
+// Revision 1.3 2002/01/23 10:28:16 mohor
+// Link in the header changed.
+//
+// Revision 1.2 2001/10/19 08:43:51 mohor
+// eth_timescale.v changed to timescale.v This is done because of the
+// simulation of the few cores in a one joined project.
+//
+// Revision 1.1 2001/08/06 14:44:29 mohor
+// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
+// Include files fixed to contain no path.
+// File names and module names changed ta have a eth_ prologue in the name.
+// File eth_timescale.v is used to define timescale
+// All pin names on the top module are changed to contain _I, _O or _OE at the end.
+// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
+// and Mdo_OE. The bidirectional signal must be created on the top level. This
+// is done due to the ASIC tools.
+//
+// Revision 1.1 2001/07/30 21:23:42 mohor
+// Directory structure changed. Files checked and joind together.
+//
+// Revision 1.3 2001/06/01 22:28:56 mohor
+// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
+//
+//
+
+`include "timescale.v"
+
+
+module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
+ LatchByte, ShiftedBit, Prsd, LinkFail);
+
+
+parameter Tp=1;
+
+input Clk; // Input clock (Host clock)
+input Reset; // Reset signal
+input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
+input Mdi; // MII input data
+input [4:0] Fiad; // PHY address
+input [4:0] Rgad; // Register address (within the selected PHY)
+input [15:0]CtrlData; // Control data (data to be written to the PHY)
+input WriteOp; // The current operation is a PHY register write operation
+input [3:0] ByteSelect; // Byte select
+input [1:0] LatchByte; // Byte select for latching (read operation)
+
+output ShiftedBit; // Bit shifted out of the shift register
+output[15:0]Prsd; // Read Status Data (data read from the PHY)
+output LinkFail; // Link Integrity Signal
+
+reg [7:0] ShiftReg; // Shift register for shifting the data in and out
+reg [15:0]Prsd;
+reg LinkFail;
+
+
+
+
+// ShiftReg[7:0] :: Shift Register Data
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ begin
+ ShiftReg[7:0] <= 8'h0;
+ Prsd[15:0] <= 16'h0;
+ LinkFail <= 1'b0;
+ end
+ else
+ begin
+ if(MdcEn_n)
+ begin
+ if(|ByteSelect)
+ begin
+ case (ByteSelect[3:0]) // synopsys parallel_case full_case
+ 4'h1 : ShiftReg[7:0] <= {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};
+ 4'h2 : ShiftReg[7:0] <= {Fiad[0], Rgad[4:0], 2'b10};
+ 4'h4 : ShiftReg[7:0] <= CtrlData[15:8];
+ 4'h8 : ShiftReg[7:0] <= CtrlData[7:0];
+ endcase
+ end
+ else
+ begin
+ ShiftReg[7:0] <= {ShiftReg[6:0], Mdi};
+ if(LatchByte[0])
+ begin
+ Prsd[7:0] <= {ShiftReg[6:0], Mdi};
+ if(Rgad == 5'h01)
+ LinkFail <= ~ShiftReg[1]; // this is bit [2], because it is not shifted yet
+ end
+ else
+ begin
+ if(LatchByte[1])
+ Prsd[15:8] <= {ShiftReg[6:0], Mdi};
+ end
+ end
+ end
+ end
+end
+
+
+assign ShiftedBit = ShiftReg[7];
+
+
+endmodule
rtl/verilog/ethmac/eth_shiftreg.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rtl/verilog/ethmac/eth_rxethmac.v
===================================================================
--- rtl/verilog/ethmac/eth_rxethmac.v (nonexistent)
+++ rtl/verilog/ethmac/eth_rxethmac.v (revision 409)
@@ -0,0 +1,377 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// eth_rxethmac.v ////
+//// ////
+//// This file is part of the Ethernet IP core project ////
+//// http://www.opencores.org/project,ethmac ////
+//// ////
+//// Author(s): ////
+//// - Igor Mohor (igorM@opencores.org) ////
+//// - Novan Hartadi (novan@vlsi.itb.ac.id) ////
+//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////
+//// ////
+//// All additional information is avaliable in the Readme.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.12 2004/04/26 15:26:23 igorm
+// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
+// previous update of the core.
+// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
+// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
+// register. (thanks to Mathias and Torbjorn)
+// - Multicast reception was fixed. Thanks to Ulrich Gries
+//
+// Revision 1.11 2004/03/17 09:32:15 igorm
+// Multicast detection fixed. Only the LSB of the first byte is checked.
+//
+// Revision 1.10 2002/11/22 01:57:06 mohor
+// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
+// synchronized.
+//
+// Revision 1.9 2002/11/19 17:35:35 mohor
+// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
+// that a frame was received because of the promiscous mode.
+//
+// Revision 1.8 2002/02/16 07:15:27 mohor
+// Testbench fixed, code simplified, unused signals removed.
+//
+// Revision 1.7 2002/02/15 13:44:28 mohor
+// RxAbort is an output. No need to have is declared as wire.
+//
+// Revision 1.6 2002/02/15 11:17:48 mohor
+// File format changed.
+//
+// Revision 1.5 2002/02/14 20:48:43 billditt
+// Addition of new module eth_addrcheck.v
+//
+// Revision 1.4 2002/01/23 10:28:16 mohor
+// Link in the header changed.
+//
+// Revision 1.3 2001/10/19 08:43:51 mohor
+// eth_timescale.v changed to timescale.v This is done because of the
+// simulation of the few cores in a one joined project.
+//
+// Revision 1.2 2001/09/11 14:17:00 mohor
+// Few little NCSIM warnings fixed.
+//
+// Revision 1.1 2001/08/06 14:44:29 mohor
+// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
+// Include files fixed to contain no path.
+// File names and module names changed ta have a eth_ prologue in the name.
+// File eth_timescale.v is used to define timescale
+// All pin names on the top module are changed to contain _I, _O or _OE at the end.
+// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
+// and Mdo_OE. The bidirectional signal must be created on the top level. This
+// is done due to the ASIC tools.
+//
+// Revision 1.1 2001/07/30 21:23:42 mohor
+// Directory structure changed. Files checked and joind together.
+//
+// Revision 1.1 2001/06/27 21:26:19 mohor
+// Initial release of the RxEthMAC module.
+//
+//
+//
+//
+//
+
+`include "timescale.v"
+
+
+module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG, HugEn, DlyCrcEn,
+ RxData, RxValid, RxStartFrm, RxEndFrm, ByteCnt, ByteCntEq0, ByteCntGreat2,
+ ByteCntMaxFrame, CrcError, StateIdle, StatePreamble, StateSFD, StateData,
+ MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort, AddressMiss, PassAll, ControlFrmAddressOK
+ );
+
+parameter Tp = 1;
+
+
+
+input MRxClk;
+input MRxDV;
+input [3:0] MRxD;
+input Transmitting;
+input HugEn;
+input DlyCrcEn;
+input [15:0] MaxFL;
+input r_IFG;
+input Reset;
+input [47:0] MAC; // Station Address
+input r_Bro; // broadcast disable
+input r_Pro; // promiscuous enable
+input [31:0] r_HASH0; // lower 4 bytes Hash Table
+input [31:0] r_HASH1; // upper 4 bytes Hash Table
+input PassAll;
+input ControlFrmAddressOK;
+
+output [7:0] RxData;
+output RxValid;
+output RxStartFrm;
+output RxEndFrm;
+output [15:0] ByteCnt;
+output ByteCntEq0;
+output ByteCntGreat2;
+output ByteCntMaxFrame;
+output CrcError;
+output StateIdle;
+output StatePreamble;
+output StateSFD;
+output [1:0] StateData;
+output RxAbort;
+output AddressMiss;
+
+reg [7:0] RxData;
+reg RxValid;
+reg RxStartFrm;
+reg RxEndFrm;
+reg Broadcast;
+reg Multicast;
+reg [5:0] CrcHash;
+reg CrcHashGood;
+reg DelayData;
+reg [7:0] LatchedByte;
+reg [7:0] RxData_d;
+reg RxValid_d;
+reg RxStartFrm_d;
+reg RxEndFrm_d;
+
+wire MRxDEqD;
+wire MRxDEq5;
+wire StateDrop;
+wire ByteCntEq1;
+wire ByteCntEq2;
+wire ByteCntEq3;
+wire ByteCntEq4;
+wire ByteCntEq5;
+wire ByteCntEq6;
+wire ByteCntEq7;
+wire ByteCntSmall7;
+wire [31:0] Crc;
+wire Enable_Crc;
+wire Initialize_Crc;
+wire [3:0] Data_Crc;
+wire GenerateRxValid;
+wire GenerateRxStartFrm;
+wire GenerateRxEndFrm;
+wire DribbleRxEndFrm;
+wire [3:0] DlyCrcCnt;
+wire IFGCounterEq24;
+
+assign MRxDEqD = MRxD == 4'hd;
+assign MRxDEq5 = MRxD == 4'h5;
+
+
+// Rx State Machine module
+eth_rxstatem rxstatem1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .ByteCntEq0(ByteCntEq0),
+ .ByteCntGreat2(ByteCntGreat2), .Transmitting(Transmitting), .MRxDEq5(MRxDEq5),
+ .MRxDEqD(MRxDEqD), .IFGCounterEq24(IFGCounterEq24), .ByteCntMaxFrame(ByteCntMaxFrame),
+ .StateData(StateData), .StateIdle(StateIdle), .StatePreamble(StatePreamble),
+ .StateSFD(StateSFD), .StateDrop(StateDrop)
+ );
+
+
+// Rx Counters module
+eth_rxcounters rxcounters1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .StateIdle(StateIdle),
+ .StateSFD(StateSFD), .StateData(StateData), .StateDrop(StateDrop),
+ .StatePreamble(StatePreamble), .MRxDEqD(MRxDEqD), .DlyCrcEn(DlyCrcEn),
+ .DlyCrcCnt(DlyCrcCnt), .Transmitting(Transmitting), .MaxFL(MaxFL), .r_IFG(r_IFG),
+ .HugEn(HugEn), .IFGCounterEq24(IFGCounterEq24), .ByteCntEq0(ByteCntEq0),
+ .ByteCntEq1(ByteCntEq1), .ByteCntEq2(ByteCntEq2), .ByteCntEq3(ByteCntEq3),
+ .ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5), .ByteCntEq6(ByteCntEq6),
+ .ByteCntEq7(ByteCntEq7), .ByteCntGreat2(ByteCntGreat2),
+ .ByteCntSmall7(ByteCntSmall7), .ByteCntMaxFrame(ByteCntMaxFrame),
+ .ByteCntOut(ByteCnt)
+ );
+
+// Rx Address Check
+
+eth_rxaddrcheck rxaddrcheck1
+ (.MRxClk(MRxClk), .Reset( Reset), .RxData(RxData),
+ .Broadcast (Broadcast), .r_Bro (r_Bro), .r_Pro(r_Pro),
+ .ByteCntEq6(ByteCntEq6), .ByteCntEq7(ByteCntEq7), .ByteCntEq2(ByteCntEq2),
+ .ByteCntEq3(ByteCntEq3), .ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5),
+ .HASH0(r_HASH0), .HASH1(r_HASH1),
+ .CrcHash(CrcHash), .CrcHashGood(CrcHashGood), .StateData(StateData),
+ .Multicast(Multicast), .MAC(MAC), .RxAbort(RxAbort),
+ .RxEndFrm(RxEndFrm), .AddressMiss(AddressMiss), .PassAll(PassAll),
+ .ControlFrmAddressOK(ControlFrmAddressOK)
+ );
+
+
+assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame);
+assign Initialize_Crc = StateSFD | DlyCrcEn & (|DlyCrcCnt[3:0]) & DlyCrcCnt[3:0] < 4'h9;
+
+assign Data_Crc[0] = MRxD[3];
+assign Data_Crc[1] = MRxD[2];
+assign Data_Crc[2] = MRxD[1];
+assign Data_Crc[3] = MRxD[0];
+
+
+// Connecting module Crc
+eth_crc crcrx (.Clk(MRxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
+ .Crc(Crc), .CrcError(CrcError)
+ );
+
+
+
+// Latching CRC for use in the hash table
+
+always @ (posedge MRxClk)
+begin
+ CrcHashGood <= StateData[0] & ByteCntEq6;
+end
+
+always @ (posedge MRxClk)
+begin
+ if(Reset | StateIdle)
+ CrcHash[5:0] <= 6'h0;
+ else
+ if(StateData[0] & ByteCntEq6)
+ CrcHash[5:0] <= Crc[31:26];
+end
+
+
+// Output byte stream
+always @ (posedge MRxClk or posedge Reset)
+begin
+ if(Reset)
+ begin
+ RxData_d[7:0] <= 8'h0;
+ DelayData <= 1'b0;
+ LatchedByte[7:0] <= 8'h0;
+ RxData[7:0] <= 8'h0;
+ end
+ else
+ begin
+ LatchedByte[7:0] <= {MRxD[3:0], LatchedByte[7:4]}; // Latched byte
+ DelayData <= StateData[0];
+
+ if(GenerateRxValid)
+ RxData_d[7:0] <= LatchedByte[7:0] & {8{|StateData}}; // Data goes through only in data state
+ else
+ if(~DelayData)
+ RxData_d[7:0] <= 8'h0; // Delaying data to be valid for two cycles. Zero when not active.
+
+ RxData[7:0] <= RxData_d[7:0]; // Output data byte
+ end
+end
+
+
+
+always @ (posedge MRxClk or posedge Reset)
+begin
+ if(Reset)
+ Broadcast <= 1'b0;
+ else
+ begin
+ if(StateData[0] & ~(&LatchedByte[7:0]) & ByteCntSmall7)
+ Broadcast <= 1'b0;
+ else
+ if(StateData[0] & (&LatchedByte[7:0]) & ByteCntEq1)
+ Broadcast <= 1'b1;
+ else
+ if(RxAbort | RxEndFrm)
+ Broadcast <= 1'b0;
+ end
+end
+
+
+always @ (posedge MRxClk or posedge Reset)
+begin
+ if(Reset)
+ Multicast <= 1'b0;
+ else
+ begin
+ if(StateData[0] & ByteCntEq1 & LatchedByte[0])
+ Multicast <= 1'b1;
+ else if(RxAbort | RxEndFrm)
+ Multicast <= 1'b0;
+ end
+end
+
+
+assign GenerateRxValid = StateData[0] & (~ByteCntEq0 | DlyCrcCnt >= 4'h3);
+
+always @ (posedge MRxClk or posedge Reset)
+begin
+ if(Reset)
+ begin
+ RxValid_d <= 1'b0;
+ RxValid <= 1'b0;
+ end
+ else
+ begin
+ RxValid_d <= GenerateRxValid;
+ RxValid <= RxValid_d;
+ end
+end
+
+
+assign GenerateRxStartFrm = StateData[0] & (ByteCntEq1 & ~DlyCrcEn | DlyCrcCnt == 4'h3 & DlyCrcEn);
+
+always @ (posedge MRxClk or posedge Reset)
+begin
+ if(Reset)
+ begin
+ RxStartFrm_d <= 1'b0;
+ RxStartFrm <= 1'b0;
+ end
+ else
+ begin
+ RxStartFrm_d <= GenerateRxStartFrm;
+ RxStartFrm <= RxStartFrm_d;
+ end
+end
+
+
+assign GenerateRxEndFrm = StateData[0] & (~MRxDV & ByteCntGreat2 | ByteCntMaxFrame);
+assign DribbleRxEndFrm = StateData[1] & ~MRxDV & ByteCntGreat2;
+
+
+always @ (posedge MRxClk or posedge Reset)
+begin
+ if(Reset)
+ begin
+ RxEndFrm_d <= 1'b0;
+ RxEndFrm <= 1'b0;
+ end
+ else
+ begin
+ RxEndFrm_d <= GenerateRxEndFrm;
+ RxEndFrm <= RxEndFrm_d | DribbleRxEndFrm;
+ end
+end
+
+
+endmodule
rtl/verilog/ethmac/eth_rxethmac.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rtl/verilog/ethmac/eth_rxcounters.v
===================================================================
--- rtl/verilog/ethmac/eth_rxcounters.v (nonexistent)
+++ rtl/verilog/ethmac/eth_rxcounters.v (revision 409)
@@ -0,0 +1,218 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// eth_rxcounters.v ////
+//// ////
+//// This file is part of the Ethernet IP core project ////
+//// http://www.opencores.org/project,ethmac ////
+//// ////
+//// Author(s): ////
+//// - Igor Mohor (igorM@opencores.org) ////
+//// - Novan Hartadi (novan@vlsi.itb.ac.id) ////
+//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////
+//// ////
+//// All additional information is avaliable in the Readme.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.5 2002/02/15 11:13:29 mohor
+// Format of the file changed a bit.
+//
+// Revision 1.4 2002/02/14 20:19:41 billditt
+// Modified for Address Checking,
+// addition of eth_addrcheck.v
+//
+// Revision 1.3 2002/01/23 10:28:16 mohor
+// Link in the header changed.
+//
+// Revision 1.2 2001/10/19 08:43:51 mohor
+// eth_timescale.v changed to timescale.v This is done because of the
+// simulation of the few cores in a one joined project.
+//
+// Revision 1.1 2001/08/06 14:44:29 mohor
+// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
+// Include files fixed to contain no path.
+// File names and module names changed ta have a eth_ prologue in the name.
+// File eth_timescale.v is used to define timescale
+// All pin names on the top module are changed to contain _I, _O or _OE at the end.
+// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
+// and Mdo_OE. The bidirectional signal must be created on the top level. This
+// is done due to the ASIC tools.
+//
+// Revision 1.1 2001/07/30 21:23:42 mohor
+// Directory structure changed. Files checked and joind together.
+//
+// Revision 1.1 2001/06/27 21:26:19 mohor
+// Initial release of the RxEthMAC module.
+//
+//
+//
+//
+//
+//
+
+
+`include "timescale.v"
+
+
+module eth_rxcounters (MRxClk, Reset, MRxDV, StateIdle, StateSFD, StateData, StateDrop, StatePreamble,
+ MRxDEqD, DlyCrcEn, DlyCrcCnt, Transmitting, MaxFL, r_IFG, HugEn, IFGCounterEq24,
+ ByteCntEq0, ByteCntEq1, ByteCntEq2,ByteCntEq3,ByteCntEq4,ByteCntEq5, ByteCntEq6,
+ ByteCntEq7, ByteCntGreat2, ByteCntSmall7, ByteCntMaxFrame, ByteCntOut
+ );
+
+parameter Tp = 1;
+
+input MRxClk;
+input Reset;
+input MRxDV;
+input StateSFD;
+input [1:0] StateData;
+input MRxDEqD;
+input StateIdle;
+input StateDrop;
+input DlyCrcEn;
+input StatePreamble;
+input Transmitting;
+input HugEn;
+input [15:0] MaxFL;
+input r_IFG;
+
+output IFGCounterEq24; // IFG counter reaches 9600 ns (960 ns)
+output [3:0] DlyCrcCnt; // Delayed CRC counter
+output ByteCntEq0; // Byte counter = 0
+output ByteCntEq1; // Byte counter = 1
+output ByteCntEq2; // Byte counter = 2
+output ByteCntEq3; // Byte counter = 3
+output ByteCntEq4; // Byte counter = 4
+output ByteCntEq5; // Byte counter = 5
+output ByteCntEq6; // Byte counter = 6
+output ByteCntEq7; // Byte counter = 7
+output ByteCntGreat2; // Byte counter > 2
+output ByteCntSmall7; // Byte counter < 7
+output ByteCntMaxFrame; // Byte counter = MaxFL
+output [15:0] ByteCntOut; // Byte counter
+
+wire ResetByteCounter;
+wire IncrementByteCounter;
+wire ResetIFGCounter;
+wire IncrementIFGCounter;
+wire ByteCntMax;
+
+reg [15:0] ByteCnt;
+reg [3:0] DlyCrcCnt;
+reg [4:0] IFGCounter;
+
+wire [15:0] ByteCntDelayed;
+
+
+
+assign ResetByteCounter = MRxDV & (StateSFD & MRxDEqD | StateData[0] & ByteCntMaxFrame);
+
+assign IncrementByteCounter = ~ResetByteCounter & MRxDV &
+ (StatePreamble | StateSFD | StateIdle & ~Transmitting |
+ StateData[1] & ~ByteCntMax & ~(DlyCrcEn & |DlyCrcCnt)
+ );
+
+
+always @ (posedge MRxClk or posedge Reset)
+begin
+ if(Reset)
+ ByteCnt[15:0] <= 16'h0;
+ else
+ begin
+ if(ResetByteCounter)
+ ByteCnt[15:0] <= 16'h0;
+ else
+ if(IncrementByteCounter)
+ ByteCnt[15:0] <= ByteCnt[15:0] + 1'b1;
+ end
+end
+
+assign ByteCntDelayed = ByteCnt + 3'h4;
+assign ByteCntOut = DlyCrcEn? ByteCntDelayed : ByteCnt;
+
+assign ByteCntEq0 = ByteCnt == 16'h0;
+assign ByteCntEq1 = ByteCnt == 16'h1;
+assign ByteCntEq2 = ByteCnt == 16'h2;
+assign ByteCntEq3 = ByteCnt == 16'h3;
+assign ByteCntEq4 = ByteCnt == 16'h4;
+assign ByteCntEq5 = ByteCnt == 16'h5;
+assign ByteCntEq6 = ByteCnt == 16'h6;
+assign ByteCntEq7 = ByteCnt == 16'h7;
+assign ByteCntGreat2 = ByteCnt > 16'h2;
+assign ByteCntSmall7 = ByteCnt < 16'h7;
+assign ByteCntMax = ByteCnt == 16'hffff;
+assign ByteCntMaxFrame = ByteCnt == MaxFL[15:0] & ~HugEn;
+
+
+assign ResetIFGCounter = StateSFD & MRxDV & MRxDEqD | StateDrop;
+
+assign IncrementIFGCounter = ~ResetIFGCounter & (StateDrop | StateIdle | StatePreamble | StateSFD) & ~IFGCounterEq24;
+
+always @ (posedge MRxClk or posedge Reset)
+begin
+ if(Reset)
+ IFGCounter[4:0] <= 5'h0;
+ else
+ begin
+ if(ResetIFGCounter)
+ IFGCounter[4:0] <= 5'h0;
+ else
+ if(IncrementIFGCounter)
+ IFGCounter[4:0] <= IFGCounter[4:0] + 1'b1;
+ end
+end
+
+
+
+assign IFGCounterEq24 = (IFGCounter[4:0] == 5'h18) | r_IFG; // 24*400 = 9600 ns or r_IFG is set to 1
+
+
+always @ (posedge MRxClk or posedge Reset)
+begin
+ if(Reset)
+ DlyCrcCnt[3:0] <= 4'h0;
+ else
+ begin
+ if(DlyCrcCnt[3:0] == 4'h9)
+ DlyCrcCnt[3:0] <= 4'h0;
+ else
+ if(DlyCrcEn & StateSFD)
+ DlyCrcCnt[3:0] <= 4'h1;
+ else
+ if(DlyCrcEn & (|DlyCrcCnt[3:0]))
+ DlyCrcCnt[3:0] <= DlyCrcCnt[3:0] + 1'b1;
+ end
+end
+
+
+endmodule
rtl/verilog/ethmac/eth_rxcounters.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rtl/verilog/ethmac/eth_txethmac.v
===================================================================
--- rtl/verilog/ethmac/eth_txethmac.v (nonexistent)
+++ rtl/verilog/ethmac/eth_txethmac.v (revision 409)
@@ -0,0 +1,492 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// eth_txethmac.v ////
+/// ////
+//// This file is part of the Ethernet IP core project ////
+//// http://www.opencores.org/project,ethmac ////
+//// ////
+//// Author(s): ////
+//// - Igor Mohor (igorM@opencores.org) ////
+//// - Novan Hartadi (novan@vlsi.itb.ac.id) ////
+//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////
+//// ////
+//// All additional information is avaliable in the Readme.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.8 2003/01/30 13:33:24 mohor
+// When padding was enabled and crc disabled, frame was not ended correctly.
+//
+// Revision 1.7 2002/02/26 16:24:01 mohor
+// RetryCntLatched was unused and removed from design
+//
+// Revision 1.6 2002/02/22 12:56:35 mohor
+// Retry is not activated when a Tx Underrun occured
+//
+// Revision 1.5 2002/02/11 09:18:22 mohor
+// Tx status is written back to the BD.
+//
+// Revision 1.4 2002/01/23 10:28:16 mohor
+// Link in the header changed.
+//
+// Revision 1.3 2001/10/19 08:43:51 mohor
+// eth_timescale.v changed to timescale.v This is done because of the
+// simulation of the few cores in a one joined project.
+//
+// Revision 1.2 2001/09/11 14:17:00 mohor
+// Few little NCSIM warnings fixed.
+//
+// Revision 1.1 2001/08/06 14:44:29 mohor
+// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
+// Include files fixed to contain no path.
+// File names and module names changed ta have a eth_ prologue in the name.
+// File eth_timescale.v is used to define timescale
+// All pin names on the top module are changed to contain _I, _O or _OE at the end.
+// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
+// and Mdo_OE. The bidirectional signal must be created on the top level. This
+// is done due to the ASIC tools.
+//
+// Revision 1.1 2001/07/30 21:23:42 mohor
+// Directory structure changed. Files checked and joind together.
+//
+// Revision 1.3 2001/06/19 18:16:40 mohor
+// TxClk changed to MTxClk (as discribed in the documentation).
+// Crc changed so only one file can be used instead of two.
+//
+// Revision 1.2 2001/06/19 10:38:08 mohor
+// Minor changes in header.
+//
+// Revision 1.1 2001/06/19 10:27:58 mohor
+// TxEthMAC initial release.
+//
+//
+//
+
+`include "timescale.v"
+
+
+module eth_txethmac (MTxClk, Reset, TxStartFrm, TxEndFrm, TxUnderRun, TxData, CarrierSense,
+ Collision, Pad, CrcEn, FullD, HugEn, DlyCrcEn, MinFL, MaxFL, IPGT,
+ IPGR1, IPGR2, CollValid, MaxRet, NoBckof, ExDfrEn,
+ MTxD, MTxEn, MTxErr, TxDone, TxRetry, TxAbort, TxUsedData, WillTransmit,
+ ResetCollision, RetryCnt, StartTxDone, StartTxAbort, MaxCollisionOccured,
+ LateCollision, DeferIndication, StatePreamble, StateData
+
+ );
+
+parameter Tp = 1;
+
+
+input MTxClk; // Transmit clock (from PHY)
+input Reset; // Reset
+input TxStartFrm; // Transmit packet start frame
+input TxEndFrm; // Transmit packet end frame
+input TxUnderRun; // Transmit packet under-run
+input [7:0] TxData; // Transmit packet data byte
+input CarrierSense; // Carrier sense (synchronized)
+input Collision; // Collision (synchronized)
+input Pad; // Pad enable (from register)
+input CrcEn; // Crc enable (from register)
+input FullD; // Full duplex (from register)
+input HugEn; // Huge packets enable (from register)
+input DlyCrcEn; // Delayed Crc enabled (from register)
+input [15:0] MinFL; // Minimum frame length (from register)
+input [15:0] MaxFL; // Maximum frame length (from register)
+input [6:0] IPGT; // Back to back transmit inter packet gap parameter (from register)
+input [6:0] IPGR1; // Non back to back transmit inter packet gap parameter IPGR1 (from register)
+input [6:0] IPGR2; // Non back to back transmit inter packet gap parameter IPGR2 (from register)
+input [5:0] CollValid; // Valid collision window (from register)
+input [3:0] MaxRet; // Maximum retry number (from register)
+input NoBckof; // No backoff (from register)
+input ExDfrEn; // Excessive defferal enable (from register)
+
+output [3:0] MTxD; // Transmit nibble (to PHY)
+output MTxEn; // Transmit enable (to PHY)
+output MTxErr; // Transmit error (to PHY)
+output TxDone; // Transmit packet done (to RISC)
+output TxRetry; // Transmit packet retry (to RISC)
+output TxAbort; // Transmit packet abort (to RISC)
+output TxUsedData; // Transmit packet used data (to RISC)
+output WillTransmit; // Will transmit (to RxEthMAC)
+output ResetCollision; // Reset Collision (for synchronizing collision)
+output [3:0] RetryCnt; // Latched Retry Counter for tx status purposes
+output StartTxDone;
+output StartTxAbort;
+output MaxCollisionOccured;
+output LateCollision;
+output DeferIndication;
+output StatePreamble;
+output [1:0] StateData;
+
+reg [3:0] MTxD;
+reg MTxEn;
+reg MTxErr;
+reg TxDone;
+reg TxRetry;
+reg TxAbort;
+reg TxUsedData;
+reg WillTransmit;
+reg ColWindow;
+reg StopExcessiveDeferOccured;
+reg [3:0] RetryCnt;
+reg [3:0] MTxD_d;
+reg StatusLatch;
+reg PacketFinished_q;
+reg PacketFinished;
+
+
+wire ExcessiveDeferOccured;
+wire StartIPG;
+wire StartPreamble;
+wire [1:0] StartData;
+wire StartFCS;
+wire StartJam;
+wire StartDefer;
+wire StartBackoff;
+wire StateDefer;
+wire StateIPG;
+wire StateIdle;
+wire StatePAD;
+wire StateFCS;
+wire StateJam;
+wire StateJam_q;
+wire StateBackOff;
+wire StateSFD;
+wire StartTxRetry;
+wire UnderRun;
+wire TooBig;
+wire [31:0] Crc;
+wire CrcError;
+wire [2:0] DlyCrcCnt;
+wire [15:0] NibCnt;
+wire NibCntEq7;
+wire NibCntEq15;
+wire NibbleMinFl;
+wire ExcessiveDefer;
+wire [15:0] ByteCnt;
+wire MaxFrame;
+wire RetryMax;
+wire RandomEq0;
+wire RandomEqByteCnt;
+wire PacketFinished_d;
+
+
+
+assign ResetCollision = ~(StatePreamble | (|StateData) | StatePAD | StateFCS);
+
+assign ExcessiveDeferOccured = TxStartFrm & StateDefer & ExcessiveDefer & ~StopExcessiveDeferOccured;
+
+assign StartTxDone = ~Collision & (StateFCS & NibCntEq7 | StateData[1] & TxEndFrm & (~Pad | Pad & NibbleMinFl) & ~CrcEn);
+
+assign UnderRun = StateData[0] & TxUnderRun & ~Collision;
+
+assign TooBig = ~Collision & MaxFrame & (StateData[0] & ~TxUnderRun | StateFCS);
+
+// assign StartTxRetry = StartJam & (ColWindow & ~RetryMax);
+assign StartTxRetry = StartJam & (ColWindow & ~RetryMax) & ~UnderRun;
+
+assign LateCollision = StartJam & ~ColWindow & ~UnderRun;
+
+assign MaxCollisionOccured = StartJam & ColWindow & RetryMax;
+
+assign StateSFD = StatePreamble & NibCntEq15;
+
+assign StartTxAbort = TooBig | UnderRun | ExcessiveDeferOccured | LateCollision | MaxCollisionOccured;
+
+
+// StopExcessiveDeferOccured
+always @ (posedge MTxClk or posedge Reset)
+begin
+ if(Reset)
+ StopExcessiveDeferOccured <= 1'b0;
+ else
+ begin
+ if(~TxStartFrm)
+ StopExcessiveDeferOccured <= 1'b0;
+ else
+ if(ExcessiveDeferOccured)
+ StopExcessiveDeferOccured <= 1'b1;
+ end
+end
+
+
+// Collision Window
+always @ (posedge MTxClk or posedge Reset)
+begin
+ if(Reset)
+ ColWindow <= 1'b1;
+ else
+ begin
+ if(~Collision & ByteCnt[5:0] == CollValid[5:0] & (StateData[1] | StatePAD & NibCnt[0] | StateFCS & NibCnt[0]))
+ ColWindow <= 1'b0;
+ else
+ if(StateIdle | StateIPG)
+ ColWindow <= 1'b1;
+ end
+end
+
+
+// Start Window
+always @ (posedge MTxClk or posedge Reset)
+begin
+ if(Reset)
+ StatusLatch <= 1'b0;
+ else
+ begin
+ if(~TxStartFrm)
+ StatusLatch <= 1'b0;
+ else
+ if(ExcessiveDeferOccured | StateIdle)
+ StatusLatch <= 1'b1;
+ end
+end
+
+
+// Transmit packet used data
+always @ (posedge MTxClk or posedge Reset)
+begin
+ if(Reset)
+ TxUsedData <= 1'b0;
+ else
+ TxUsedData <= |StartData;
+end
+
+
+// Transmit packet done
+always @ (posedge MTxClk or posedge Reset)
+begin
+ if(Reset)
+ TxDone <= 1'b0;
+ else
+ begin
+ if(TxStartFrm & ~StatusLatch)
+ TxDone <= 1'b0;
+ else
+ if(StartTxDone)
+ TxDone <= 1'b1;
+ end
+end
+
+
+// Transmit packet retry
+always @ (posedge MTxClk or posedge Reset)
+begin
+ if(Reset)
+ TxRetry <= 1'b0;
+ else
+ begin
+ if(TxStartFrm & ~StatusLatch)
+ TxRetry <= 1'b0;
+ else
+ if(StartTxRetry)
+ TxRetry <= 1'b1;
+ end
+end
+
+
+// Transmit packet abort
+always @ (posedge MTxClk or posedge Reset)
+begin
+ if(Reset)
+ TxAbort <= 1'b0;
+ else
+ begin
+ if(TxStartFrm & ~StatusLatch & ~ExcessiveDeferOccured)
+ TxAbort <= 1'b0;
+ else
+ if(StartTxAbort)
+ TxAbort <= 1'b1;
+ end
+end
+
+
+// Retry counter
+always @ (posedge MTxClk or posedge Reset)
+begin
+ if(Reset)
+ RetryCnt[3:0] <= 4'h0;
+ else
+ begin
+ if(ExcessiveDeferOccured | UnderRun | TooBig | StartTxDone | TxUnderRun
+ | StateJam & NibCntEq7 & (~ColWindow | RetryMax))
+ RetryCnt[3:0] <= 4'h0;
+ else
+ if(StateJam & NibCntEq7 & ColWindow & (RandomEq0 | NoBckof) | StateBackOff & RandomEqByteCnt)
+ RetryCnt[3:0] <= RetryCnt[3:0] + 1'b1;
+ end
+end
+
+
+assign RetryMax = RetryCnt[3:0] == MaxRet[3:0];
+
+
+// Transmit nibble
+always @ (StatePreamble or StateData or StateData or StateFCS or StateJam or StateSFD or TxData or
+ Crc or NibCntEq15)
+begin
+ if(StateData[0])
+ MTxD_d[3:0] = TxData[3:0]; // Lower nibble
+ else
+ if(StateData[1])
+ MTxD_d[3:0] = TxData[7:4]; // Higher nibble
+ else
+ if(StateFCS)
+ MTxD_d[3:0] = {~Crc[28], ~Crc[29], ~Crc[30], ~Crc[31]}; // Crc
+ else
+ if(StateJam)
+ MTxD_d[3:0] = 4'h9; // Jam pattern
+ else
+ if(StatePreamble)
+ if(NibCntEq15)
+ MTxD_d[3:0] = 4'hd; // SFD
+ else
+ MTxD_d[3:0] = 4'h5; // Preamble
+ else
+ MTxD_d[3:0] = 4'h0;
+end
+
+
+// Transmit Enable
+always @ (posedge MTxClk or posedge Reset)
+begin
+ if(Reset)
+ MTxEn <= 1'b0;
+ else
+ MTxEn <= StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
+end
+
+
+// Transmit nibble
+always @ (posedge MTxClk or posedge Reset)
+begin
+ if(Reset)
+ MTxD[3:0] <= 4'h0;
+ else
+ MTxD[3:0] <= MTxD_d[3:0];
+end
+
+
+// Transmit error
+always @ (posedge MTxClk or posedge Reset)
+begin
+ if(Reset)
+ MTxErr <= 1'b0;
+ else
+ MTxErr <= TooBig | UnderRun;
+end
+
+
+// WillTransmit
+always @ (posedge MTxClk or posedge Reset)
+begin
+ if(Reset)
+ WillTransmit <= 1'b0;
+ else
+ WillTransmit <= StartPreamble | StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
+end
+
+
+assign PacketFinished_d = StartTxDone | TooBig | UnderRun | LateCollision | MaxCollisionOccured | ExcessiveDeferOccured;
+
+
+// Packet finished
+always @ (posedge MTxClk or posedge Reset)
+begin
+ if(Reset)
+ begin
+ PacketFinished <= 1'b0;
+ PacketFinished_q <= 1'b0;
+ end
+ else
+ begin
+ PacketFinished <= PacketFinished_d;
+ PacketFinished_q <= PacketFinished;
+ end
+end
+
+
+// Connecting module Counters
+eth_txcounters txcounters1 (.StatePreamble(StatePreamble), .StateIPG(StateIPG), .StateData(StateData),
+ .StatePAD(StatePAD), .StateFCS(StateFCS), .StateJam(StateJam), .StateBackOff(StateBackOff),
+ .StateDefer(StateDefer), .StateIdle(StateIdle), .StartDefer(StartDefer), .StartIPG(StartIPG),
+ .StartFCS(StartFCS), .StartJam(StartJam), .TxStartFrm(TxStartFrm), .MTxClk(MTxClk),
+ .Reset(Reset), .MinFL(MinFL), .MaxFL(MaxFL), .HugEn(HugEn), .ExDfrEn(ExDfrEn),
+ .PacketFinished_q(PacketFinished_q), .DlyCrcEn(DlyCrcEn), .StartBackoff(StartBackoff),
+ .StateSFD(StateSFD), .ByteCnt(ByteCnt), .NibCnt(NibCnt), .ExcessiveDefer(ExcessiveDefer),
+ .NibCntEq7(NibCntEq7), .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .NibbleMinFl(NibbleMinFl),
+ .DlyCrcCnt(DlyCrcCnt)
+ );
+
+
+// Connecting module StateM
+eth_txstatem txstatem1 (.MTxClk(MTxClk), .Reset(Reset), .ExcessiveDefer(ExcessiveDefer), .CarrierSense(CarrierSense),
+ .NibCnt(NibCnt[6:0]), .IPGT(IPGT), .IPGR1(IPGR1), .IPGR2(IPGR2), .FullD(FullD),
+ .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm), .TxUnderRun(TxUnderRun), .Collision(Collision),
+ .UnderRun(UnderRun), .StartTxDone(StartTxDone), .TooBig(TooBig), .NibCntEq7(NibCntEq7),
+ .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .Pad(Pad), .CrcEn(CrcEn),
+ .NibbleMinFl(NibbleMinFl), .RandomEq0(RandomEq0), .ColWindow(ColWindow), .RetryMax(RetryMax),
+ .NoBckof(NoBckof), .RandomEqByteCnt(RandomEqByteCnt), .StateIdle(StateIdle),
+ .StateIPG(StateIPG), .StatePreamble(StatePreamble), .StateData(StateData), .StatePAD(StatePAD),
+ .StateFCS(StateFCS), .StateJam(StateJam), .StateJam_q(StateJam_q), .StateBackOff(StateBackOff),
+ .StateDefer(StateDefer), .StartFCS(StartFCS), .StartJam(StartJam), .StartBackoff(StartBackoff),
+ .StartDefer(StartDefer), .DeferIndication(DeferIndication), .StartPreamble(StartPreamble), .StartData(StartData), .StartIPG(StartIPG)
+ );
+
+
+wire Enable_Crc;
+wire [3:0] Data_Crc;
+wire Initialize_Crc;
+
+assign Enable_Crc = ~StateFCS;
+
+assign Data_Crc[0] = StateData[0]? TxData[3] : StateData[1]? TxData[7] : 1'b0;
+assign Data_Crc[1] = StateData[0]? TxData[2] : StateData[1]? TxData[6] : 1'b0;
+assign Data_Crc[2] = StateData[0]? TxData[1] : StateData[1]? TxData[5] : 1'b0;
+assign Data_Crc[3] = StateData[0]? TxData[0] : StateData[1]? TxData[4] : 1'b0;
+
+assign Initialize_Crc = StateIdle | StatePreamble | (|DlyCrcCnt);
+
+
+// Connecting module Crc
+eth_crc txcrc (.Clk(MTxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
+ .Crc(Crc), .CrcError(CrcError)
+ );
+
+
+// Connecting module Random
+eth_random random1 (.MTxClk(MTxClk), .Reset(Reset), .StateJam(StateJam), .StateJam_q(StateJam_q), .RetryCnt(RetryCnt),
+ .NibCnt(NibCnt), .ByteCnt(ByteCnt[9:0]), .RandomEq0(RandomEq0), .RandomEqByteCnt(RandomEqByteCnt));
+
+
+
+
+endmodule
rtl/verilog/ethmac/eth_txethmac.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rtl/verilog/ethmac/eth_wishbone.v
===================================================================
--- rtl/verilog/ethmac/eth_wishbone.v (nonexistent)
+++ rtl/verilog/ethmac/eth_wishbone.v (revision 409)
@@ -0,0 +1,2844 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// eth_wishbone.v ////
+//// ////
+//// This file is part of the Ethernet IP core project ////
+//// http://www.opencores.org/project,ethmac ////
+//// ////
+//// Author(s): ////
+//// - Igor Mohor (igorM@opencores.org) ////
+//// ////
+//// All additional information is available in the Readme.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001, 2002 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+
+`include "ethmac_defines.v"
+`include "timescale.v"
+
+
+module eth_wishbone
+ (
+
+ // WISHBONE common
+ WB_CLK_I, WB_DAT_I, WB_DAT_O,
+
+ // WISHBONE slave
+ WB_ADR_I, WB_WE_I, WB_ACK_O,
+ BDCs,
+
+ Reset,
+
+ // WISHBONE master
+ m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
+ m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
+ m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
+
+`ifdef ETH_WISHBONE_B3
+ m_wb_cti_o, m_wb_bte_o,
+`endif
+
+ //TX
+ MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
+ TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
+ PerPacketPad,
+
+ //RX
+ MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort, RxStatusWriteLatched_sync2,
+
+ // Register
+ r_TxEn, r_RxEn, r_TxBDNum, r_RxFlow, r_PassAll,
+
+ // Interrupts
+ TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
+
+ // Rx Status
+ InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
+ ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood, AddressMiss,
+ ReceivedPauseFrm,
+
+ // Tx Status
+ RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, RstDeferLatched, CarrierSenseLost
+
+ // Bist
+`ifdef ETH_BIST
+ ,
+ // debug chain signals
+ mbist_si_i, // bist scan serial in
+ mbist_so_o, // bist scan serial out
+ mbist_ctrl_i // bist chain shift control
+`endif
+
+`ifdef WISHBONE_DEBUG
+ ,
+ dbg_dat0
+`endif
+
+
+ );
+
+
+ //parameter Tp = 1;
+ parameter Tp = 0;
+
+
+ // WISHBONE common
+ input WB_CLK_I; // WISHBONE clock
+ input [31:0] WB_DAT_I; // WISHBONE data input
+ output [31:0] WB_DAT_O; // WISHBONE data output
+
+ // WISHBONE slave
+ input [9:2] WB_ADR_I; // WISHBONE address input
+ input WB_WE_I; // WISHBONE write enable input
+ input [3:0] BDCs; // Buffer descriptors are selected
+ output WB_ACK_O; // WISHBONE acknowledge output
+
+ // WISHBONE master
+ output [29:0] m_wb_adr_o; //
+ output [3:0] m_wb_sel_o; //
+ output m_wb_we_o; //
+ output [31:0] m_wb_dat_o; //
+ output m_wb_cyc_o; //
+ output m_wb_stb_o; //
+ input [31:0] m_wb_dat_i; //
+ input m_wb_ack_i; //
+ input m_wb_err_i; //
+
+`ifdef ETH_WISHBONE_B3
+ output [2:0] m_wb_cti_o; // Cycle Type Identifier
+ `ifdef BURST_4BEAT
+ output reg [1:0] m_wb_bte_o; // Burst Type Extension
+ `else
+ output [1:0] m_wb_bte_o; // Burst Type Extension
+ `endif
+ reg [2:0] m_wb_cti_o; // Cycle Type Identifier
+`endif
+
+ input Reset; // Reset signal
+
+ // Rx Status signals
+ input InvalidSymbol; // Invalid symbol was received during
+ // reception in 100 Mbps mode
+ input LatchedCrcError; // CRC error
+ input RxLateCollision; // Late collision occured while receiving
+ // frame
+ input ShortFrame; // Frame shorter then the minimum size
+ // (r_MinFL) was received while small
+ // packets are enabled (r_RecSmall)
+ input DribbleNibble; // Extra nibble received
+ input ReceivedPacketTooBig;// Received packet is bigger than
+ // r_MaxFL
+ input [15:0] RxLength; // Length of the incoming frame
+ input LoadRxStatus; // Rx status was loaded
+ input ReceivedPacketGood;// Received packet's length and CRC are
+ // good
+ input AddressMiss; // When a packet is received AddressMiss
+ // status is written to the Rx BD
+ input r_RxFlow;
+ input r_PassAll;
+ input ReceivedPauseFrm;
+
+ // Tx Status signals
+ input [3:0] RetryCntLatched; // Latched Retry Counter
+ input RetryLimit; // Retry limit reached (Retry Max value +
+ // 1 attempts were made)
+ input LateCollLatched; // Late collision occured
+ input DeferLatched; // Defer indication (Frame was defered
+ // before sucessfully sent)
+ output RstDeferLatched;
+ input CarrierSenseLost; // Carrier Sense was lost during the
+ // frame transmission
+
+ // Tx
+ input MTxClk; // Transmit clock (from PHY)
+ input TxUsedData; // Transmit packet used data
+ input TxRetry; // Transmit packet retry
+ input TxAbort; // Transmit packet abort
+ input TxDone; // Transmission ended
+ output TxStartFrm; // Transmit packet start frame
+ output TxEndFrm; // Transmit packet end frame
+ output [7:0] TxData; // Transmit packet data byte
+ output TxUnderRun; // Transmit packet under-run
+ output PerPacketCrcEn; // Per packet crc enable
+ output PerPacketPad; // Per packet pading
+
+ // Rx
+ input MRxClk; // Receive clock (from PHY)
+ input [7:0] RxData; // Received data byte (from PHY)
+ input RxValid; //
+ input RxStartFrm; //
+ input RxEndFrm; //
+ input RxAbort; // This signal is set when address doesn't
+ // match.
+ output RxStatusWriteLatched_sync2;
+
+ //Register
+ input r_TxEn; // Transmit enable
+ input r_RxEn; // Receive enable
+ input [7:0] r_TxBDNum; // Receive buffer descriptor number
+
+ // Interrupts
+ output TxB_IRQ;
+ output TxE_IRQ;
+ output RxB_IRQ;
+ output RxE_IRQ;
+ output Busy_IRQ;
+
+
+ // Bist
+`ifdef ETH_BIST
+ input mbist_si_i; // bist scan serial in
+ output mbist_so_o; // bist scan serial out
+ input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
+`endif
+
+`ifdef WISHBONE_DEBUG
+ output [31:0] dbg_dat0;
+`endif
+
+
+
+ reg TxB_IRQ;
+ reg TxE_IRQ;
+ reg RxB_IRQ;
+ reg RxE_IRQ;
+
+ reg TxStartFrm;
+ reg TxEndFrm;
+ reg [7:0] TxData;
+
+ reg TxUnderRun;
+ reg TxUnderRun_wb;
+
+ reg TxBDRead;
+ wire TxStatusWrite;
+
+ reg [1:0] TxValidBytesLatched;
+
+ reg [15:0] TxLength;
+ reg [15:0] LatchedTxLength;
+ reg [14:11] TxStatus;
+
+ reg [14:13] RxStatus;
+
+ reg TxStartFrm_wb;
+ reg TxRetry_wb;
+ reg TxAbort_wb;
+ reg TxDone_wb;
+
+ reg TxDone_wb_q;
+ reg TxAbort_wb_q;
+ reg TxRetry_wb_q;
+ reg TxRetryPacket;
+ reg TxRetryPacket_NotCleared;
+ reg TxDonePacket;
+ reg TxDonePacket_NotCleared;
+ reg TxAbortPacket;
+ reg TxAbortPacket_NotCleared;
+ reg RxBDReady;
+ reg RxBDOK;
+ reg TxBDReady;
+
+ reg RxBDRead;
+
+ reg [31:0] TxDataLatched;
+ reg [1:0] TxByteCnt;
+ reg LastWord;
+ reg ReadTxDataFromFifo_tck;
+
+ reg BlockingTxStatusWrite;
+ reg BlockingTxBDRead;
+
+ reg Flop;
+
+ reg [7:1] TxBDAddress;
+ reg [7:1] RxBDAddress;
+
+ reg TxRetrySync1;
+ reg TxAbortSync1;
+ reg TxDoneSync1;
+
+ reg TxAbort_q;
+ reg TxRetry_q;
+ reg TxUsedData_q;
+
+ reg [31:0] RxDataLatched2;
+
+ reg [31:8] RxDataLatched1; // Big Endian Byte Ordering
+
+ reg [1:0] RxValidBytes;
+ reg [1:0] RxByteCnt;
+ reg LastByteIn;
+ reg ShiftWillEnd;
+
+ reg WriteRxDataToFifo;
+ reg [15:0] LatchedRxLength;
+ reg RxAbortLatched;
+
+ reg ShiftEnded;
+ reg RxOverrun;
+
+ reg [3:0] BDWrite; // BD Write Enable for access from WISHBONE side
+ reg BDRead; // BD Read access from WISHBONE side
+ wire [31:0] RxBDDataIn; // Rx BD data in
+ wire [31:0] TxBDDataIn; // Tx BD data in
+
+ reg TxEndFrm_wb;
+
+ wire TxRetryPulse;
+ wire TxDonePulse;
+ wire TxAbortPulse;
+
+ wire StartRxBDRead;
+
+ wire StartTxBDRead;
+
+ wire TxIRQEn;
+ wire WrapTxStatusBit;
+
+ wire RxIRQEn;
+ wire WrapRxStatusBit;
+
+ wire [1:0] TxValidBytes;
+
+ wire [7:1] TempTxBDAddress;
+ wire [7:1] TempRxBDAddress;
+
+ wire RxStatusWrite;
+ wire RxBufferFull;
+ wire RxBufferAlmostEmpty;
+ wire RxBufferEmpty;
+
+ reg WB_ACK_O;
+
+ wire [8:0] RxStatusIn;
+ reg [8:0] RxStatusInLatched;
+
+ reg WbEn, WbEn_q;
+ reg RxEn, RxEn_q;
+ reg TxEn, TxEn_q;
+ reg r_TxEn_q;
+ reg r_RxEn_q;
+
+ wire ram_ce;
+ wire [3:0] ram_we;
+ wire ram_oe;
+ reg [7:0] ram_addr;
+ reg [31:0] ram_di;
+ wire [31:0] ram_do;
+
+ wire StartTxPointerRead;
+ reg TxPointerRead;
+ reg TxEn_needed;
+ reg RxEn_needed;
+
+ wire StartRxPointerRead;
+ reg RxPointerRead;
+
+ // RX shift ending signals
+ reg ShiftEnded_rck;
+ reg ShiftEndedSync1;
+ reg ShiftEndedSync2;
+ reg ShiftEndedSync3;
+ reg ShiftEndedSync_c1;
+ reg ShiftEndedSync_c2;
+
+ wire StartShiftWillEnd;
+
+ // Pulse for wishbone side having finished writing back
+ reg rx_wb_writeback_finished;
+ // Indicator of last set of writes from the Wishbone master coming up
+ reg rx_wb_last_writes;
+
+
+`ifdef TXBD_POLL
+ reg [31:0] TxBDReadySamples; // -- jb
+ wire TxBDNotReady; // -- jb
+`endif
+
+`ifdef ETH_WISHBONE_B3
+ `ifndef BURST_4BEAT
+ assign m_wb_bte_o = 2'b00; // Linear burst
+ `endif
+`endif
+
+ assign m_wb_stb_o = m_wb_cyc_o;
+
+ always @ (posedge WB_CLK_I)
+ begin
+ WB_ACK_O <= (|BDWrite) & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
+ end
+
+ assign WB_DAT_O = ram_do;
+
+ // Generic synchronous single-port RAM interface
+ eth_spram_256x32
+ #(1) // Write enable width
+ bd_ram
+ (
+ .clk (WB_CLK_I),
+ .rst (Reset),
+ .ce (ram_ce),
+ .we (ram_we[0]),
+ .oe (ram_oe),
+ .addr (ram_addr),
+ .di (ram_di),
+ .do (ram_do)
+`ifdef ETH_BIST
+ ,
+ .mbist_si_i (mbist_si_i),
+ .mbist_so_o (mbist_so_o),
+ .mbist_ctrl_i (mbist_ctrl_i)
+`endif
+ );
+
+ assign ram_ce = 1'b1;
+ assign ram_we = (BDWrite & {4{(WbEn & WbEn_q)}}) |
+ {4{(TxStatusWrite | RxStatusWrite)}};
+ assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q &
+ (TxBDRead | TxPointerRead) | RxEn & RxEn_q &
+ (RxBDRead | RxPointerRead);
+
+
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ TxEn_needed <= 1'b0;
+ else
+ if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q)
+ TxEn_needed <= 1'b1;
+ else
+ if(TxPointerRead & TxEn & TxEn_q)
+ TxEn_needed <= 1'b0;
+ end
+
+ // Enabling access to the RAM for three devices.
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ begin
+ WbEn <= 1'b1;
+ RxEn <= 1'b0;
+ TxEn <= 1'b0;
+ ram_addr <= 8'h0;
+ ram_di <= 32'h0;
+ BDRead <= 1'b0;
+ BDWrite <= 1'b0;
+ end
+ else
+ begin
+ // Switching between three stages depends on enable signals
+ case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed}) // synopsys parallel_case
+ 5'b100_10, 5'b100_11 :
+ begin
+ WbEn <= 1'b0;
+ RxEn <= 1'b1; // wb access stage and r_RxEn is enabled
+ TxEn <= 1'b0;
+ ram_addr <= {RxBDAddress, RxPointerRead};
+ ram_di <= RxBDDataIn;
+ end
+ 5'b100_01 :
+ begin
+ WbEn <= 1'b0;
+ RxEn <= 1'b0;
+ TxEn <= 1'b1; // wb access stage, r_RxEn is disabled but
+ // r_TxEn is enabled
+ ram_addr <= {TxBDAddress, TxPointerRead};
+ ram_di <= TxBDDataIn;
+ end
+ 5'b010_00, 5'b010_10 :
+ begin
+ WbEn <= 1'b1; // RxEn access stage and r_TxEn is disabled
+ RxEn <= 1'b0;
+ TxEn <= 1'b0;
+ ram_addr <= WB_ADR_I[9:2];
+ ram_di <= WB_DAT_I;
+ BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
+ BDRead <= (|BDCs) & ~WB_WE_I;
+ end
+ 5'b010_01, 5'b010_11 :
+ begin
+ WbEn <= 1'b0;
+ RxEn <= 1'b0;
+ TxEn <= 1'b1; // RxEn access stage and r_TxEn is enabled
+ ram_addr <= {TxBDAddress, TxPointerRead};
+ ram_di <= TxBDDataIn;
+ end
+ 5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
+ begin
+ WbEn <= 1'b1; // TxEn access stage (we always go to wb
+ // access stage)
+ RxEn <= 1'b0;
+ TxEn <= 1'b0;
+ ram_addr <= WB_ADR_I[9:2];
+ ram_di <= WB_DAT_I;
+ BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
+ BDRead <= (|BDCs) & ~WB_WE_I;
+ end
+ 5'b100_00 :
+ begin
+ WbEn <= 1'b0; // WbEn access stage and there is no need
+ // for other stages. WbEn needs to be
+ // switched off for a bit
+ end
+ 5'b000_00 :
+ begin
+ WbEn <= 1'b1; // Idle state. We go to WbEn access stage.
+ RxEn <= 1'b0;
+ TxEn <= 1'b0;
+ ram_addr <= WB_ADR_I[9:2];
+ ram_di <= WB_DAT_I;
+ BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
+ BDRead <= (|BDCs) & ~WB_WE_I;
+ end
+ endcase
+ end
+ end
+
+
+ // Delayed stage signals
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ begin
+ WbEn_q <= 1'b0;
+ RxEn_q <= 1'b0;
+ TxEn_q <= 1'b0;
+ r_TxEn_q <= 1'b0;
+ r_RxEn_q <= 1'b0;
+ end
+ else
+ begin
+ WbEn_q <= WbEn;
+ RxEn_q <= RxEn;
+ TxEn_q <= TxEn;
+ r_TxEn_q <= r_TxEn;
+ r_RxEn_q <= r_RxEn;
+ end
+ end
+
+ // Changes for tx occur every second clock. Flop is used for this manner.
+ always @ (posedge MTxClk or posedge Reset)
+ begin
+ if(Reset)
+ Flop <= 1'b0;
+ else
+ if(TxDone | TxAbort | TxRetry_q)
+ Flop <= 1'b0;
+ else
+ if(TxUsedData)
+ Flop <= ~Flop;
+ end
+
+ wire ResetTxBDReady;
+ assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
+
+ // Latching READY status of the Tx buffer descriptor
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ TxBDReady <= 1'b0;
+ else
+ if(TxEn & TxEn_q & TxBDRead)
+ // TxBDReady is sampled only once at the beginning.
+ TxBDReady <= ram_do[15] & (ram_do[31:16] > 4);
+ else
+ // Only packets larger then 4 bytes are transmitted.
+ if(ResetTxBDReady)
+ TxBDReady <= 1'b0;
+ end
+
+`ifdef TXBD_POLL
+ // Register TxBDReady 4 times, when all are low we know this one is not
+ // good to transmit
+ always @(posedge WB_CLK_I or posedge Reset) // -- jb
+ begin
+ if (Reset) TxBDReadySamples <= 32'hffffffff;
+ else begin
+ if (r_TxEn)
+ begin
+ if (TxBDNotReady)
+ TxBDReadySamples <= 32'hffffffff;
+ else
+ TxBDReadySamples[31:0] <= {TxBDReadySamples[30:0],TxBDReady};
+ end
+ else
+ TxBDReadySamples <= 32'hffffffff;
+ end // else: !if(Reset)
+ end // always @ (posedge WB_CLK_I or posedge Reset)
+ // When all low, this goes high -- jb
+ assign TxBDNotReady = ~(|TxBDReadySamples);
+
+
+`endif
+
+ // Reading the Tx buffer descriptor
+ assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) &
+ ~BlockingTxBDRead & ~TxBDReady;
+
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ TxBDRead <= 1'b1;
+ else
+ if(StartTxBDRead)
+ TxBDRead <= 1'b1;
+ else
+ if(TxBDReady)
+ TxBDRead <= 1'b0;
+ end
+
+
+ // Reading Tx BD pointer
+ assign StartTxPointerRead = TxBDRead & TxBDReady;
+
+ // Reading Tx BD Pointer
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ TxPointerRead <= 1'b0;
+ else
+ if(StartTxPointerRead)
+ TxPointerRead <= 1'b1;
+ else
+ if(TxEn_q)
+ TxPointerRead <= 1'b0;
+ end
+
+
+ // Writing status back to the Tx buffer descriptor
+ assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared)&
+ TxEn & TxEn_q & ~BlockingTxStatusWrite;
+
+
+
+ // Status writing must occur only once. Meanwhile it is blocked.
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ BlockingTxStatusWrite <= 1'b0;
+ else
+ if(~TxDone_wb & ~TxAbort_wb)
+ BlockingTxStatusWrite <= 1'b0;
+ else
+ if(TxStatusWrite)
+ BlockingTxStatusWrite <= 1'b1;
+ end
+
+
+ reg BlockingTxStatusWrite_sync1;
+ reg BlockingTxStatusWrite_sync2;
+ reg BlockingTxStatusWrite_sync3;
+
+ // Synchronizing BlockingTxStatusWrite to MTxClk
+ always @ (posedge MTxClk or posedge Reset)
+ begin
+ if(Reset)
+ BlockingTxStatusWrite_sync1 <= 1'b0;
+ else
+ BlockingTxStatusWrite_sync1 <= BlockingTxStatusWrite;
+ end
+
+ // Synchronizing BlockingTxStatusWrite to MTxClk
+ always @ (posedge MTxClk or posedge Reset)
+ begin
+ if(Reset)
+ BlockingTxStatusWrite_sync2 <= 1'b0;
+ else
+ BlockingTxStatusWrite_sync2 <= BlockingTxStatusWrite_sync1;
+ end
+
+ // Synchronizing BlockingTxStatusWrite to MTxClk
+ always @ (posedge MTxClk or posedge Reset)
+ begin
+ if(Reset)
+ BlockingTxStatusWrite_sync3 <= 1'b0;
+ else
+ BlockingTxStatusWrite_sync3 <= BlockingTxStatusWrite_sync2;
+ end
+
+ assign RstDeferLatched = BlockingTxStatusWrite_sync2 &
+ ~BlockingTxStatusWrite_sync3;
+
+ // TxBDRead state is activated only once.
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ BlockingTxBDRead <= 1'b0;
+ else
+ if(StartTxBDRead)
+ BlockingTxBDRead <= 1'b1;
+ else
+ if(~StartTxBDRead & ~TxBDReady)
+ BlockingTxBDRead <= 1'b0;
+ end
+
+
+ // Latching status from the tx buffer descriptor
+ // Data is avaliable one cycle after the access is started (at that time
+ // signal TxEn is not active)
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ TxStatus <= 4'h0;
+ else
+ if(TxEn & TxEn_q & TxBDRead)
+ TxStatus <= ram_do[14:11];
+ end
+
+ reg ReadTxDataFromMemory;
+ wire WriteRxDataToMemory;
+ reg WriteRxDataToMemory_r;
+
+ // Register WriteRxDataToMemory in Wishbone clock domain
+ // so it doesn't get out of sync with burst capability indication signals
+ always @(posedge WB_CLK_I or posedge Reset)
+ if (Reset)
+ WriteRxDataToMemory_r <= 0;
+ else
+ WriteRxDataToMemory_r <= WriteRxDataToMemory;
+
+ reg MasterWbTX;
+ reg MasterWbRX;
+
+ reg [29:0] m_wb_adr_o;
+ reg m_wb_cyc_o;
+ reg [3:0] m_wb_sel_o;
+ reg m_wb_we_o;
+
+ wire TxLengthEq0;
+ wire TxLengthLt4;
+
+ reg BlockingIncrementTxPointer;
+ reg [31:2] TxPointerMSB;
+ reg [1:0] TxPointerLSB;
+ reg [1:0] TxPointerLSB_rst;
+ reg [31:2] RxPointerMSB;
+ reg [1:0] RxPointerLSB_rst;
+
+ wire RxBurstAcc;
+ wire RxWordAcc;
+ wire RxHalfAcc;
+ wire RxByteAcc;
+
+ //Latching length from the buffer descriptor;
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ TxLength <= 16'h0;
+ else
+ if(TxEn & TxEn_q & TxBDRead)
+ TxLength <= ram_do[31:16];
+ else
+ if(MasterWbTX & m_wb_ack_i)
+ begin
+ if(TxLengthLt4)
+ TxLength <= 16'h0;
+ else
+ if(TxPointerLSB_rst==2'h0)
+ TxLength <= TxLength - 3'h4; // Length is subtracted at
+ // the data request
+ else
+ if(TxPointerLSB_rst==2'h1)
+ TxLength <= TxLength - 3'h3; // Length is subtracted
+ // at the data request
+ else
+ if(TxPointerLSB_rst==2'h2)
+ TxLength <= TxLength - 3'h2; // Length is subtracted
+ // at the data request
+ else
+ if(TxPointerLSB_rst==2'h3)
+ TxLength <= TxLength - 3'h1; // Length is subtracted
+ // at the data request
+ end
+ end
+
+
+
+ //Latching length from the buffer descriptor;
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ LatchedTxLength <= 16'h0;
+ else
+ if(TxEn & TxEn_q & TxBDRead)
+ LatchedTxLength <= ram_do[31:16];
+ end
+
+ assign TxLengthEq0 = TxLength == 0;
+ assign TxLengthLt4 = TxLength < 4;
+
+ reg cyc_cleared;
+ reg IncrTxPointer;
+
+
+ // Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are
+ // latched because TxPointerMSB is only used for word-aligned accesses.
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ TxPointerMSB <= 30'h0;
+ else
+ if(TxEn & TxEn_q & TxPointerRead)
+ TxPointerMSB <= ram_do[31:2];
+ else
+ if(IncrTxPointer & ~BlockingIncrementTxPointer)
+ // TxPointer is word-aligned
+ TxPointerMSB <= TxPointerMSB + 1'b1;
+ end
+
+
+ // Latching 2 MSB bits of the buffer descriptor. Since word accesses are
+ // performed, valid data does not necesserly start at byte 0 (could be byte
+ // 0, 1, 2 or 3). This signals are used for proper selection of the start
+ // byte (TxData and TxByteCnt) are set by this two bits.
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ TxPointerLSB[1:0] <= 0;
+ else
+ if(TxEn & TxEn_q & TxPointerRead)
+ TxPointerLSB[1:0] <= ram_do[1:0];
+ end
+
+
+ // Latching 2 MSB bits of the buffer descriptor.
+ // After the read access, TxLength needs to be decremented for the number of
+ // the valid bytes (1 to 4 bytes are valid in the first word). After the
+ // first read all bytes are valid so this two bits are reset to zero.
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ TxPointerLSB_rst[1:0] <= 0;
+ else
+ if(TxEn & TxEn_q & TxPointerRead)
+ TxPointerLSB_rst[1:0] <= ram_do[1:0];
+ else
+ // After first access pointer is word alligned
+ if(MasterWbTX & m_wb_ack_i)
+ TxPointerLSB_rst[1:0] <= 0;
+ end
+
+
+ reg [3:0] RxByteSel;
+ wire MasterAccessFinished;
+
+
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ BlockingIncrementTxPointer <= 0;
+ else
+ if(MasterAccessFinished)
+ BlockingIncrementTxPointer <= 0;
+ else
+ if(IncrTxPointer)
+ BlockingIncrementTxPointer <= 1'b1;
+ end
+
+
+ wire TxBufferAlmostFull;
+ wire TxBufferFull;
+ wire TxBufferEmpty;
+ wire TxBufferAlmostEmpty;
+ wire SetReadTxDataFromMemory;
+
+ reg BlockReadTxDataFromMemory;
+
+ assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
+
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ ReadTxDataFromMemory <= 1'b0;
+ else
+ if(TxLengthEq0 | TxAbortPulse | TxRetryPulse)
+ ReadTxDataFromMemory <= 1'b0;
+ else
+ if(SetReadTxDataFromMemory)
+ ReadTxDataFromMemory <= 1'b1;
+ end
+
+ reg tx_burst_en;
+ reg rx_burst_en;
+ reg [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt;
+
+ wire ReadTxDataFromMemory_2;
+ wire tx_burst;
+
+
+ wire [31:0] TxData_wb;
+ wire ReadTxDataFromFifo_wb;
+
+ assign ReadTxDataFromMemory_2 = ReadTxDataFromMemory &
+ ~BlockReadTxDataFromMemory | (|tx_burst_cnt);
+
+ assign tx_burst = ReadTxDataFromMemory_2 & tx_burst_en;
+
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ BlockReadTxDataFromMemory <= 1'b0;
+ else
+ if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX &
+ (~cyc_cleared) & (!(TxAbortPacket_NotCleared |
+ TxRetryPacket_NotCleared)))
+ BlockReadTxDataFromMemory <= 1'b1;
+ else
+ if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket |
+ TxRetryPacket)
+ BlockReadTxDataFromMemory <= 1'b0;
+ end
+
+`define TX_BURST_EN_CONDITION (txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4)))
+
+ assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
+ wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
+ wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
+
+ reg [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt;
+
+ wire rx_burst;
+ wire enough_data_in_rxfifo_for_burst;
+ wire enough_data_in_rxfifo_for_burst_plus1;
+
+ // Enabling master wishbone access to the memory for two devices TX and RX.
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ begin
+ MasterWbTX <= 1'b0;
+ MasterWbRX <= 1'b0;
+ m_wb_adr_o <= 30'h0;
+ m_wb_cyc_o <= 1'b0;
+ m_wb_we_o <= 1'b0;
+ m_wb_sel_o <= 4'h0;
+ cyc_cleared<= 1'b0;
+ tx_burst_cnt<= 0;
+ rx_burst_cnt<= 0;
+ IncrTxPointer<= 1'b0;
+ tx_burst_en<= 1'b1;
+ rx_burst_en<= 1'b0;
+`ifdef ETH_WISHBONE_B3
+ m_wb_cti_o <= 3'b0;
+ `ifdef BURST_4BEAT
+ m_wb_bte_o <= 2'b00;
+ `endif
+`endif
+ end
+ else
+ begin
+ // Switching between two stages depends on enable signals
+ casex ({MasterWbTX,
+ MasterWbRX,
+ ReadTxDataFromMemory_2,
+ WriteRxDataToMemory_r,
+ MasterAccessFinished,
+ cyc_cleared,
+ tx_burst,
+ rx_burst}) // synopsys parallel_case
+
+ 8'b00_10_00_10, // Idle and MRB needed
+ 8'b10_1x_10_1x, // MRB continues
+ 8'b10_10_01_10, // Clear (previously MR) and MRB needed
+ 8'b01_1x_01_1x: // Clear (previously MW) and MRB needed
+ begin
+ MasterWbTX <= 1'b1; // tx burst
+ MasterWbRX <= 1'b0;
+ m_wb_cyc_o <= 1'b1;
+ m_wb_we_o <= 1'b0;
+ m_wb_sel_o <= 4'hf;
+ cyc_cleared<= 1'b0;
+ IncrTxPointer<= 1'b1;
+ tx_burst_cnt <= tx_burst_cnt+3'h1;
+ if(tx_burst_cnt==0)
+ m_wb_adr_o <= TxPointerMSB;
+ else
+ m_wb_adr_o <= m_wb_adr_o+1'b1;
+
+ if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
+ begin
+ tx_burst_en<= 1'b0;
+`ifdef ETH_WISHBONE_B3
+ m_wb_cti_o <= 3'b111;
+`endif
+ end
+ else
+ begin
+`ifdef ETH_WISHBONE_B3
+ m_wb_cti_o <= 3'b010;
+ `ifdef BURST_4BEAT
+ m_wb_bte_o <= 2'b01;
+ `endif
+`endif
+ end
+ end // case: 8'b00_10_00_10,...
+`ifdef ETH_RX_BURST_EN
+ 8'b00_x1_00_x1, // Idle and MWB needed
+ 8'b01_x1_10_x1, // MWB continues
+ 8'b01_01_01_01, // Clear (previously MW) and MWB needed
+ 8'b10_x1_01_x1 : // Clear (previously MR) and MWB needed
+ begin
+ MasterWbTX <= 1'b0; // rx burst
+ MasterWbRX <= 1'b1;
+ m_wb_cyc_o <= 1'b1;
+ m_wb_we_o <= 1'b1;
+ m_wb_sel_o <= RxByteSel;
+ IncrTxPointer<= 1'b0;
+ cyc_cleared<= 1'b0;
+ rx_burst_cnt <= rx_burst_cnt+3'h1;
+
+ if(rx_burst_cnt==0)
+ m_wb_adr_o <= RxPointerMSB;
+ else
+ m_wb_adr_o <= m_wb_adr_o+1'b1;
+
+ if(rx_burst_cnt==(`ETH_BURST_LENGTH-1))
+ begin
+ rx_burst_en<= 1'b0;
+ `ifdef ETH_WISHBONE_B3
+ m_wb_cti_o <= 3'b111;
+ `endif
+ end
+ else
+ begin
+ `ifdef ETH_WISHBONE_B3
+ `ifdef BURST_4BEAT
+ m_wb_cti_o <= 3'b010;
+ m_wb_bte_o <= 2'b01;
+ `endif
+ `endif
+ end
+ end // case: 8'b00_x1_00_x1,...
+`endif // `ifdef ETH_RX_BURST_EN
+ 8'b00_x1_00_x0 ,//idle and MW is needed (data write to rx buffer)
+ 8'b01_x1_00_x0 :// Sometimes gets caught changing states - JB
+ begin
+ MasterWbTX <= 1'b0;
+ MasterWbRX <= !RxBufferEmpty;
+ m_wb_adr_o <= RxPointerMSB;
+ m_wb_cyc_o <= !RxBufferEmpty;
+ m_wb_we_o <= !RxBufferEmpty;
+ m_wb_sel_o <= RxByteSel;
+ IncrTxPointer<= 1'b0;
+`ifdef ETH_WISHBONE_B3
+ `ifdef ETH_RX_BURST_EN
+ `ifdef BURST_4BEAT
+ if ((RxPointerMSB[3:2]==2'b00) & !RxBufferEmpty &
+ enough_data_in_rxfifo_for_burst & !m_wb_cyc_o)
+ // Added "& !_m_wb_cyc_o" here to stop burst signals
+ // going high during a transfer
+ begin
+ rx_burst_en<= 1'b1;
+ m_wb_cti_o <= 3'b010;
+ m_wb_bte_o <= 2'b01;
+ rx_burst_cnt<= 1;
+ end
+ `endif
+ `endif
+`endif // `ifdef ETH_WISHBONE_B3
+
+ end
+ 8'b00_10_00_00 : // idle and MR is needed (data read from tx
+ // buffer)
+ begin
+ MasterWbTX <= 1'b1;
+ MasterWbRX <= 1'b0;
+ m_wb_adr_o <= TxPointerMSB;
+ m_wb_cyc_o <= 1'b1;
+ m_wb_we_o <= 1'b0;
+ m_wb_sel_o <= 4'hf;
+ IncrTxPointer<= 1'b1;
+`ifdef BURST_4BEAT
+
+ // Attempt ethernet bugfix, start bursts later
+ if ((TxPointerMSB[3:2]==2'b00) && `TX_BURST_EN_CONDITION)
+ begin
+ `ifdef TX_BURST_EN_VERBOSE
+ $display("(%t)(%m): %b enabling tx_burst_en",$time,
+ {MasterWbTX,MasterWbRX,ReadTxDataFromMemory_2,
+ WriteRxDataToMemory,MasterAccessFinished,
+ cyc_cleared,tx_burst,rx_burst});
+ `endif
+ tx_burst_en<= 1'b1;
+ tx_burst_cnt <= 3'h1;
+
+ `ifdef ETH_WISHBONE_B3
+ m_wb_cti_o <= 3'b010;
+ m_wb_bte_o <= 2'b01;
+ `endif
+ end
+`endif
+ end
+ 8'b10_10_01_00,// MR and MR is needed (data read from tx buffer)
+ 8'b01_1x_01_0x :// MW and MR is needed (data read from tx
+ // buffer)
+ begin
+ MasterWbTX <= 1'b1; // Only switch to TX here
+ // when not end of RX
+ MasterWbRX <= 1'b0;
+ m_wb_adr_o <= TxPointerMSB;
+ m_wb_cyc_o <= 1'b1;
+ m_wb_we_o <= 1'b0;
+ m_wb_sel_o <= 4'hf;
+ cyc_cleared<= 1'b0;
+ IncrTxPointer<= 1'b1;
+`ifdef BURST_4BEAT
+ if ((TxPointerMSB[3:2]==2'b00) & `TX_BURST_EN_CONDITION)
+ begin
+ `ifdef TX_BURST_EN_VERBOSE
+ $display("(%t)(%m): %b enabling tx_burst_en",$time,
+ {MasterWbTX,MasterWbRX,
+ ReadTxDataFromMemory_2,
+ WriteRxDataToMemory,
+ MasterAccessFinished,
+ cyc_cleared,
+ tx_burst,
+ rx_burst});
+ `endif
+ tx_burst_en<= 1'b1;
+ tx_burst_cnt <= 3'h1;
+ `ifdef ETH_WISHBONE_B3
+ m_wb_cti_o <= 3'b010;
+ m_wb_bte_o <= 2'b01;
+ `endif
+ end
+`endif
+
+ end
+ 8'b01_01_01_00,// MW and MW needed (data write to rx buffer)
+ 8'b10_x1_01_x0 ://MR and MW is needed (data write to rx buffer)
+ begin
+ MasterWbTX <= 1'b0;
+ MasterWbRX <= !RxBufferEmpty;
+ rx_burst_cnt<= 0;
+ m_wb_adr_o <= RxPointerMSB;
+ m_wb_cyc_o <= !RxBufferEmpty;
+ m_wb_we_o <= !RxBufferEmpty;
+ m_wb_sel_o <= RxByteSel;
+`ifdef ETH_WISHBONE_B3
+ `ifdef ETH_RX_BURST_EN
+ `ifdef BURST_4BEAT
+ if ((RxPointerMSB[3:2]==2'b00) &
+ enough_data_in_rxfifo_for_burst & !RxBufferEmpty)
+ //enough_data_in_rxfifo_for_burst_plus1)
+
+
+ begin
+ rx_burst_en<= 1'b1;
+ m_wb_cti_o <= 3'b010;
+ m_wb_bte_o <= 2'b01;
+ rx_burst_cnt<= 1;
+ end
+ `endif
+ `endif // `ifdef ETH_RX_BURST_EN
+`endif // `ifdef ETH_WISHBONE_B3
+ cyc_cleared<= 1'b0;
+ IncrTxPointer<= 1'b0;
+ end
+ 8'b01_01_10_00,// MW and MW needed (cycle is cleared between
+ // previous and next access)
+ 8'b01_1x_10_x0,// MW and MW or MR or MRB needed (cycle is
+ // cleared between previous and next access)
+ 8'b10_10_10_00,// MR and MR needed (cycle is cleared between
+ // previous and next access)
+ 8'b10_x1_10_0x :// MR and MR or MW or MWB (cycle is cleared
+ // between previous and next access)
+ begin
+ m_wb_cyc_o <= 1'b0;// whatever and master read or write is
+ // needed. We need to clear m_wb_cyc_o
+ // before next access is started
+ cyc_cleared<= 1'b1;
+ IncrTxPointer<= 1'b0;
+ tx_burst_cnt<= 0;
+`ifdef BURST_4BEAT
+ // Caused a bug!
+ // if (TxPointerMSB[3:2]==2'b00)
+ //tx_burst_en<= `TX_BURST_EN_CONDITION;
+ // Set this to 0 here
+ tx_burst_en<= 0;
+
+`endif
+ rx_burst_cnt<= 0;
+`ifdef ETH_WISHBONE_B3
+ m_wb_bte_o <= 2'b00;
+ m_wb_cti_o <= 3'b0;
+`endif
+ end
+ 8'bxx_00_10_00,// whatever and no master read or write is needed
+ // (ack or err comes finishing previous access)
+ 8'bxx_00_01_00 : // Between cyc_cleared request was cleared
+ begin
+ MasterWbTX <= 1'b0;
+ MasterWbRX <= 1'b0;
+ m_wb_cyc_o <= 1'b0;
+ cyc_cleared<= 1'b0;
+ IncrTxPointer<= 1'b0;
+ rx_burst_cnt<= 0;
+ m_wb_bte_o <= 2'b00;
+ m_wb_cti_o <= 3'b0;
+ end
+ 8'b00_00_00_00: // whatever and no master read or write is
+ // needed (ack or err comes finishing previous
+ // access)
+ begin
+ tx_burst_cnt<= 0;
+`ifdef BURST_4BEAT
+
+ // This caused tx_burst to remain set between
+ // transmits, and sometimes we would burst immediately
+ // and maybe get the wrong data because the offset of
+ // the buffer pointer wasn't 16-byte aligned.
+ //if (TxPointerMSB[3:2]==2'b00)
+ // tx_burst_en<= `TX_BURST_EN_CONDITION;
+
+ // Fix for transmit problems... maybe - jb
+ if(TxEn & TxEn_q & TxPointerRead & (ram_do[3:0]===4'h0))
+ begin
+ `ifdef TX_BURST_EN_VERBOSE
+ $display("(%t)(%m): %b enabling tx_burst_en",$time,
+ {MasterWbTX,MasterWbRX,ReadTxDataFromMemory_2,
+ WriteRxDataToMemory,MasterAccessFinished,
+ cyc_cleared,tx_burst,rx_burst});
+ `endif
+ tx_burst_en<= `TX_BURST_EN_CONDITION;
+ end
+ else
+ tx_burst_en<= 0;
+`endif
+ end
+ default: // Don't touch
+ begin
+ MasterWbTX <= MasterWbTX;
+ MasterWbRX <= MasterWbRX;
+ m_wb_cyc_o <= m_wb_cyc_o;
+ m_wb_sel_o <= m_wb_sel_o;
+ IncrTxPointer<= IncrTxPointer;
+ end
+ endcase
+ end
+ end
+
+
+ wire TxFifoClear;
+
+ assign TxFifoClear = (TxAbortPacket | TxRetryPacket | StartTxPointerRead);
+
+ eth_fifo
+ #(
+ `ETH_TX_FIFO_DATA_WIDTH,
+ `ETH_TX_FIFO_DEPTH,
+ `ETH_TX_FIFO_CNT_WIDTH
+ )
+ tx_fifo
+ (
+ .data_in(m_wb_dat_i),
+ .data_out(TxData_wb),
+ .clk(WB_CLK_I),
+ .reset(Reset),
+ .write(MasterWbTX & m_wb_ack_i),
+ .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
+ .clear(TxFifoClear),
+ .full(TxBufferFull),
+ .almost_full(TxBufferAlmostFull),
+ .almost_empty(TxBufferAlmostEmpty),
+ .empty(TxBufferEmpty),
+ .cnt(txfifo_cnt)
+ );
+
+
+ reg StartOccured;
+ reg TxStartFrm_sync1;
+ reg TxStartFrm_sync2;
+ reg TxStartFrm_syncb1;
+ reg TxStartFrm_syncb2;
+
+
+
+ // Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ TxStartFrm_wb <= 1'b0;
+ else
+ if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0))
+ TxStartFrm_wb <= 1'b1;
+ else
+ if(TxStartFrm_syncb2)
+ TxStartFrm_wb <= 1'b0;
+ end
+
+ // StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's
+ // blocked.
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ StartOccured <= 1'b0;
+ else
+ if(TxStartFrm_wb)
+ StartOccured <= 1'b1;
+ else
+ if(ResetTxBDReady)
+ StartOccured <= 1'b0;
+ end
+
+ // Synchronizing TxStartFrm_wb to MTxClk
+ always @ (posedge MTxClk or posedge Reset)
+ begin
+ if(Reset)
+ TxStartFrm_sync1 <= 1'b0;
+ else
+ TxStartFrm_sync1 <= TxStartFrm_wb;
+ end
+
+ always @ (posedge MTxClk or posedge Reset)
+ begin
+ if(Reset)
+ TxStartFrm_sync2 <= 1'b0;
+ else
+ TxStartFrm_sync2 <= TxStartFrm_sync1;
+ end
+
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ TxStartFrm_syncb1 <= 1'b0;
+ else
+ TxStartFrm_syncb1 <= TxStartFrm_sync2;
+ end
+
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ TxStartFrm_syncb2 <= 1'b0;
+ else
+ TxStartFrm_syncb2 <= TxStartFrm_syncb1;
+ end
+
+ always @ (posedge MTxClk or posedge Reset)
+ begin
+ if(Reset)
+ TxStartFrm <= 1'b0;
+ else
+ if(TxStartFrm_sync2)
+ TxStartFrm <= 1'b1;
+ else
+ if(TxUsedData_q | ~TxStartFrm_sync2 &
+ (TxRetry & (~TxRetry_q) | TxAbort & (~TxAbort_q)))
+ TxStartFrm <= 1'b0;
+ end
+ // End: Generation of the TxStartFrm_wb which is then synchronized to the
+ // MTxClk
+
+
+ // TxEndFrm_wb: indicator of the end of frame
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ TxEndFrm_wb <= 1'b0;
+ else
+ if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData)
+ TxEndFrm_wb <= 1'b1;
+ else
+ if(TxRetryPulse | TxDonePulse | TxAbortPulse)
+ TxEndFrm_wb <= 1'b0;
+ end
+
+
+ // Marks which bytes are valid within the word.
+ assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
+
+ reg LatchValidBytes;
+ reg LatchValidBytes_q;
+
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ LatchValidBytes <= 1'b0;
+ else
+ if(TxLengthLt4 & TxBDReady)
+ LatchValidBytes <= 1'b1;
+ else
+ LatchValidBytes <= 1'b0;
+ end
+
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ LatchValidBytes_q <= 1'b0;
+ else
+ LatchValidBytes_q <= LatchValidBytes;
+ end
+
+
+ // Latching valid bytes
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ TxValidBytesLatched <= 2'h0;
+ else
+ if(LatchValidBytes & ~LatchValidBytes_q)
+ TxValidBytesLatched <= TxValidBytes;
+ else
+ if(TxRetryPulse | TxDonePulse | TxAbortPulse)
+ TxValidBytesLatched <= 2'h0;
+ end
+
+
+ assign TxIRQEn = TxStatus[14];
+ assign WrapTxStatusBit = TxStatus[13];
+ assign PerPacketPad = TxStatus[12];
+ assign PerPacketCrcEn = TxStatus[11];
+
+
+ assign RxIRQEn = RxStatus[14];
+ assign WrapRxStatusBit = RxStatus[13];
+
+
+ // Temporary Tx and Rx buffer descriptor address
+`ifdef TXBD_POLL
+ assign TempTxBDAddress[7:1] = {7{ (TxStatusWrite|TxBDNotReady) & ~WrapTxStatusBit}} & (TxBDAddress + 1'b1) ; // Tx BD increment or wrap (last BD) -- jb
+`else
+ assign TempTxBDAddress[7:1] = {7{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 1'b1) ; // Tx BD increment or wrap (last BD)
+`endif
+ assign TempRxBDAddress[7:1] = {7{ WrapRxStatusBit}} & (r_TxBDNum[6:0]) | // Using first Rx BD
+ {7{~WrapRxStatusBit}} & (RxBDAddress + 1'b1) ; // Using next Rx BD (incremenrement address)
+
+
+ // Latching Tx buffer descriptor address
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ TxBDAddress <= 7'h0;
+ else if (r_TxEn & (~r_TxEn_q))
+ TxBDAddress <= 7'h0;
+`ifdef TXBD_POLL
+ else if (TxStatusWrite | TxBDNotReady) // -- jb
+`else
+ else if (TxStatusWrite)
+`endif
+ TxBDAddress <= TempTxBDAddress;
+ end
+
+
+ // Latching Rx buffer descriptor address
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ RxBDAddress <= 7'h0;
+ else if(r_RxEn & (~r_RxEn_q))
+ RxBDAddress <= r_TxBDNum[6:0];
+ else if(RxStatusWrite)
+ RxBDAddress <= TempRxBDAddress;
+ end
+
+ wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0],
+ RetryLimit, LateCollLatched, DeferLatched,
+ CarrierSenseLost};
+
+ assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 4'h0,
+ RxStatusInLatched};
+ assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0,
+ TxStatusInLatched};
+
+
+ // Signals used for various purposes
+ assign TxRetryPulse = TxRetry_wb & ~TxRetry_wb_q;
+ assign TxDonePulse = TxDone_wb & ~TxDone_wb_q;
+ assign TxAbortPulse = TxAbort_wb & ~TxAbort_wb_q;
+
+
+
+ // Generating delayed signals
+ always @ (posedge MTxClk or posedge Reset)
+ begin
+ if(Reset)
+ begin
+ TxAbort_q <= 1'b0;
+ TxRetry_q <= 1'b0;
+ TxUsedData_q <= 1'b0;
+ end
+ else
+ begin
+ TxAbort_q <= TxAbort;
+ TxRetry_q <= TxRetry;
+ TxUsedData_q <= TxUsedData;
+ end
+ end
+
+ // Generating delayed signals
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ begin
+ TxDone_wb_q <= 1'b0;
+ TxAbort_wb_q <= 1'b0;
+ TxRetry_wb_q <= 1'b0;
+ end
+ else
+ begin
+ TxDone_wb_q <= TxDone_wb;
+ TxAbort_wb_q <= TxAbort_wb;
+ TxRetry_wb_q <= TxRetry_wb;
+ end
+ end
+
+
+ reg TxAbortPacketBlocked;
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ TxAbortPacket <= 1'b0;
+ else
+ if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished &
+ (~TxAbortPacketBlocked) | TxAbort_wb & (~MasterWbTX) &
+ (~TxAbortPacketBlocked))
+ TxAbortPacket <= 1'b1;
+ else
+ TxAbortPacket <= 1'b0;
+ end
+
+
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ TxAbortPacket_NotCleared <= 1'b0;
+ else
+ if(TxEn & TxEn_q & TxAbortPacket_NotCleared)
+ TxAbortPacket_NotCleared <= 1'b0;
+ else
+ if(TxAbort_wb & (~tx_burst_en) & MasterWbTX &
+ MasterAccessFinished & (~TxAbortPacketBlocked) | TxAbort_wb &
+ (~MasterWbTX) & (~TxAbortPacketBlocked))
+ TxAbortPacket_NotCleared <= 1'b1;
+ end
+
+
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ TxAbortPacketBlocked <= 1'b0;
+ else
+ if(!TxAbort_wb & TxAbort_wb_q)
+ TxAbortPacketBlocked <= 1'b0;
+ else
+ if(TxAbortPacket)
+ TxAbortPacketBlocked <= 1'b1;
+ end
+
+
+ reg TxRetryPacketBlocked;
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ TxRetryPacket <= 1'b0;
+ else
+ if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished &
+ !TxRetryPacketBlocked | TxRetry_wb & !MasterWbTX &
+ !TxRetryPacketBlocked)
+ TxRetryPacket <= 1'b1;
+ else
+ TxRetryPacket <= 1'b0;
+ end
+
+
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ TxRetryPacket_NotCleared <= 1'b0;
+ else
+ if(StartTxBDRead)
+ TxRetryPacket_NotCleared <= 1'b0;
+ else
+ if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished &
+ !TxRetryPacketBlocked | TxRetry_wb & !MasterWbTX &
+ !TxRetryPacketBlocked)
+ TxRetryPacket_NotCleared <= 1'b1;
+ end
+
+
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ TxRetryPacketBlocked <= 1'b0;
+ else
+ if(!TxRetry_wb & TxRetry_wb_q)
+ TxRetryPacketBlocked <= 1'b0;
+ else
+ if(TxRetryPacket)
+ TxRetryPacketBlocked <= 1'b1;
+ end
+
+
+ reg TxDonePacketBlocked;
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ TxDonePacket <= 1'b0;
+ else
+ if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished &
+ !TxDonePacketBlocked | TxDone_wb & !MasterWbTX &
+ !TxDonePacketBlocked)
+ TxDonePacket <= 1'b1;
+ else
+ TxDonePacket <= 1'b0;
+ end
+
+
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ TxDonePacket_NotCleared <= 1'b0;
+ else
+ if(TxEn & TxEn_q & TxDonePacket_NotCleared)
+ TxDonePacket_NotCleared <= 1'b0;
+ else
+ if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished
+ & (~TxDonePacketBlocked) | TxDone_wb & !MasterWbTX
+ & (~TxDonePacketBlocked))
+ TxDonePacket_NotCleared <= 1'b1;
+ end
+
+
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ TxDonePacketBlocked <= 1'b0;
+ else
+ if(!TxDone_wb & TxDone_wb_q)
+ TxDonePacketBlocked <= 1'b0;
+ else
+ if(TxDonePacket)
+ TxDonePacketBlocked <= 1'b1;
+ end
+
+
+ // Indication of the last word
+ always @ (posedge MTxClk or posedge Reset)
+ begin
+ if(Reset)
+ LastWord <= 1'b0;
+ else
+ if((TxEndFrm | TxAbort | TxRetry) & Flop)
+ LastWord <= 1'b0;
+ else
+ if(TxUsedData & Flop & TxByteCnt == 2'h3)
+ LastWord <= TxEndFrm_wb;
+ end
+
+
+ // Tx end frame generation
+ always @ (posedge MTxClk or posedge Reset)
+ begin
+ if(Reset)
+ TxEndFrm <= 1'b0;
+ else
+ if(Flop & TxEndFrm | TxAbort | TxRetry_q)
+ TxEndFrm <= 1'b0;
+ else
+ if(Flop & LastWord)
+ begin
+ case (TxValidBytesLatched) // synopsys parallel_case
+ 1 : TxEndFrm <= TxByteCnt == 2'h0;
+ 2 : TxEndFrm <= TxByteCnt == 2'h1;
+ 3 : TxEndFrm <= TxByteCnt == 2'h2;
+ 0 : TxEndFrm <= TxByteCnt == 2'h3;
+ default : TxEndFrm <= 1'b0;
+ endcase
+ end
+ end
+
+
+ // Tx data selection (latching)
+ always @ (posedge MTxClk or posedge Reset)
+ begin
+ if(Reset)
+ TxData <= 0;
+ else
+ if(TxStartFrm_sync2 & ~TxStartFrm)
+ case(TxPointerLSB) // synopsys parallel_case
+ 2'h0 : TxData <= TxData_wb[31:24];// Big Endian Byte Ordering
+ 2'h1 : TxData <= TxData_wb[23:16];// Big Endian Byte Ordering
+ 2'h2 : TxData <= TxData_wb[15:08];// Big Endian Byte Ordering
+ 2'h3 : TxData <= TxData_wb[07:00];// Big Endian Byte Ordering
+ endcase
+ else
+ if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3)
+ TxData <= TxData_wb[31:24];// Big Endian Byte Ordering
+ else
+ if(TxUsedData & Flop)
+ begin
+ case(TxByteCnt) // synopsys parallel_case
+ // Big Endian Byte Ordering
+ 0 : TxData <= TxDataLatched[31:24];
+ 1 : TxData <= TxDataLatched[23:16];
+ 2 : TxData <= TxDataLatched[15:8];
+ 3 : TxData <= TxDataLatched[7:0];
+ endcase
+ end
+ end
+
+
+ // Latching tx data
+ always @ (posedge MTxClk or posedge Reset)
+ begin
+ if(Reset)
+ TxDataLatched[31:0] <= 32'h0;
+ else
+ if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop &
+ TxByteCnt == 2'h3 | TxStartFrm & TxUsedData & Flop &
+ TxByteCnt == 2'h0)
+ TxDataLatched[31:0] <= TxData_wb[31:0];
+ end
+
+
+ // Tx under run
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ TxUnderRun_wb <= 1'b0;
+ else
+ if(TxAbortPulse)
+ TxUnderRun_wb <= 1'b0;
+ else
+ if(TxBufferEmpty & ReadTxDataFromFifo_wb)
+ TxUnderRun_wb <= 1'b1;
+ end
+
+
+ reg TxUnderRun_sync1;
+
+ // Tx under run
+ always @ (posedge MTxClk or posedge Reset)
+ begin
+ if(Reset)
+ TxUnderRun_sync1 <= 1'b0;
+ else
+ if(TxUnderRun_wb)
+ TxUnderRun_sync1 <= 1'b1;
+ else
+ if(BlockingTxStatusWrite_sync2)
+ TxUnderRun_sync1 <= 1'b0;
+ end
+
+ // Tx under run
+ always @ (posedge MTxClk or posedge Reset)
+ begin
+ if(Reset)
+ TxUnderRun <= 1'b0;
+ else
+ if(BlockingTxStatusWrite_sync2)
+ TxUnderRun <= 1'b0;
+ else
+ if(TxUnderRun_sync1)
+ TxUnderRun <= 1'b1;
+ end
+
+
+ // Tx Byte counter
+ always @ (posedge MTxClk or posedge Reset)
+ begin
+ if(Reset)
+ TxByteCnt <= 2'h0;
+ else
+ if(TxAbort_q | TxRetry_q)
+ TxByteCnt <= 2'h0;
+ else
+ if(TxStartFrm & ~TxUsedData)
+ case(TxPointerLSB) // synopsys parallel_case
+ 2'h0 : TxByteCnt <= 2'h1;
+ 2'h1 : TxByteCnt <= 2'h2;
+ 2'h2 : TxByteCnt <= 2'h3;
+ 2'h3 : TxByteCnt <= 2'h0;
+ endcase
+ else
+ if(TxUsedData & Flop)
+ TxByteCnt <= TxByteCnt + 1'b1;
+ end
+
+
+ // Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
+ reg ReadTxDataFromFifo_sync1;
+ reg ReadTxDataFromFifo_sync2;
+ reg ReadTxDataFromFifo_sync3;
+ reg ReadTxDataFromFifo_syncb1;
+ reg ReadTxDataFromFifo_syncb2;
+ reg ReadTxDataFromFifo_syncb3;
+
+
+ always @ (posedge MTxClk or posedge Reset)
+ begin
+ if(Reset)
+ ReadTxDataFromFifo_tck <= 1'b0;
+ else
+ if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop &
+ TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop &
+ TxByteCnt == 2'h0)
+ ReadTxDataFromFifo_tck <= 1'b1;
+ else
+ if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3)
+ ReadTxDataFromFifo_tck <= 1'b0;
+ end
+
+ // Synchronizing TxStartFrm_wb to MTxClk
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ ReadTxDataFromFifo_sync1 <= 1'b0;
+ else
+ ReadTxDataFromFifo_sync1 <= ReadTxDataFromFifo_tck;
+ end
+
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ ReadTxDataFromFifo_sync2 <= 1'b0;
+ else
+ ReadTxDataFromFifo_sync2 <= ReadTxDataFromFifo_sync1;
+ end
+
+ always @ (posedge MTxClk or posedge Reset)
+ begin
+ if(Reset)
+ ReadTxDataFromFifo_syncb1 <= 1'b0;
+ else
+ ReadTxDataFromFifo_syncb1 <= ReadTxDataFromFifo_sync2;
+ end
+
+ always @ (posedge MTxClk or posedge Reset)
+ begin
+ if(Reset)
+ ReadTxDataFromFifo_syncb2 <= 1'b0;
+ else
+ ReadTxDataFromFifo_syncb2 <= ReadTxDataFromFifo_syncb1;
+ end
+
+ always @ (posedge MTxClk or posedge Reset)
+ begin
+ if(Reset)
+ ReadTxDataFromFifo_syncb3 <= 1'b0;
+ else
+ ReadTxDataFromFifo_syncb3 <= ReadTxDataFromFifo_syncb2;
+ end
+
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ ReadTxDataFromFifo_sync3 <= 1'b0;
+ else
+ ReadTxDataFromFifo_sync3 <= ReadTxDataFromFifo_sync2;
+ end
+
+ assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 &
+ ~ReadTxDataFromFifo_sync3;
+ // End: Generation of the ReadTxDataFromFifo_tck signal and synchronization
+ // to the WB_CLK_I
+
+
+ // Synchronizing TxRetry signal (synchronized to WISHBONE clock)
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ TxRetrySync1 <= 1'b0;
+ else
+ TxRetrySync1 <= TxRetry;
+ end
+
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ TxRetry_wb <= 1'b0;
+ else
+ TxRetry_wb <= TxRetrySync1;
+ end
+
+
+ // Synchronized TxDone_wb signal (synchronized to WISHBONE clock)
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ TxDoneSync1 <= 1'b0;
+ else
+ TxDoneSync1 <= TxDone;
+ end
+
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ TxDone_wb <= 1'b0;
+ else
+ TxDone_wb <= TxDoneSync1;
+ end
+
+ // Synchronizing TxAbort signal (synchronized to WISHBONE clock)
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ TxAbortSync1 <= 1'b0;
+ else
+ TxAbortSync1 <= TxAbort;
+ end
+
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ TxAbort_wb <= 1'b0;
+ else
+ TxAbort_wb <= TxAbortSync1;
+ end
+
+
+ reg RxAbortSync1;
+ reg RxAbortSync2;
+ reg RxAbortSync3;
+ reg RxAbortSync4;
+ reg RxAbortSyncb1;
+ reg RxAbortSyncb2;
+
+ assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4 |
+ r_RxEn & ~r_RxEn_q;
+
+ // Reading the Rx buffer descriptor
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ RxBDRead <= 1'b0;
+ else
+ if(StartRxBDRead)
+ RxBDRead <= 1'b1;
+ else
+ if(RxBDReady)
+ RxBDRead <= 1'b0;
+ end
+
+
+ // Reading of the next receive buffer descriptor starts after reception
+ // status is written to the previous one.
+
+ // Latching READY status of the Rx buffer descriptor
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ RxBDReady <= 1'b0;
+ else
+ if(RxPointerRead)
+ RxBDReady <= 1'b0;
+ else
+ if(RxEn & RxEn_q & RxBDRead)
+ // RxBDReady is sampled only once at the beginning
+ RxBDReady <= ram_do[15];
+ end // always @ (posedge WB_CLK_I or posedge Reset)
+
+ // Indicate we just read the RX buffer descriptor and that RxBDReady is
+ // valid.
+ reg rx_just_read_bd;
+ always @ (posedge WB_CLK_I or posedge Reset)
+ if(Reset)
+ rx_just_read_bd <= 0;
+ else if (rx_just_read_bd)
+ rx_just_read_bd <= 0;
+ else
+ rx_just_read_bd <= (RxEn & RxEn_q & RxBDRead);
+
+ // Signal to indicate we've checked and the RxBD we want to use is not free
+ reg rx_waiting_for_bd_to_become_free;
+ always @ (posedge WB_CLK_I or posedge Reset)
+ if(Reset)
+ rx_waiting_for_bd_to_become_free <= 0;
+ else if (rx_just_read_bd & !RxBDReady)
+ // Assert if we read the BD and it's not cool
+ rx_waiting_for_bd_to_become_free <= 1;
+ else if (RxBDOK)
+ rx_waiting_for_bd_to_become_free <= 0;
+
+
+
+ // Latching Rx buffer descriptor status
+ // Data is avaliable one cycle after the access is started (at that time
+ // signal RxEn is not active)
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ RxStatus <= 2'h0;
+ else
+ if(RxEn & RxEn_q & RxBDRead)
+ RxStatus <= ram_do[14:13];
+ end
+
+
+ // RxBDOK generation
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ RxBDOK <= 1'b0;
+ else
+ if(rx_wb_writeback_finished | RxAbortSync2 & ~RxAbortSync3 |
+ ~r_RxEn & r_RxEn_q)
+ RxBDOK <= 1'b0;
+ else
+ if(RxBDReady)
+ RxBDOK <= 1'b1;
+ end
+
+ // Reading Rx BD pointer
+ assign StartRxPointerRead = RxBDRead & RxBDReady;
+
+ // Reading Tx BD Pointer
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ RxPointerRead <= 1'b0;
+ else
+ if(StartRxPointerRead)
+ RxPointerRead <= 1'b1;
+ else
+ if(RxEn & RxEn_q)
+ RxPointerRead <= 1'b0;
+ end
+
+
+ //Latching Rx buffer pointer from buffer descriptor;
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ RxPointerMSB <= 30'h0;
+ else
+ if(RxEn & RxEn_q & RxPointerRead)
+ RxPointerMSB <= ram_do[31:2];
+ else
+ if(MasterWbRX & m_wb_ack_i)
+ // Word access (always word access. m_wb_sel_o are used for
+ // selecting bytes)
+ RxPointerMSB <= RxPointerMSB + 1'b1;
+ end
+
+
+ //Latching last addresses from buffer descriptor (used as byte-half-word
+ // indicator);
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ RxPointerLSB_rst[1:0] <= 0;
+ else
+ if(MasterWbRX & m_wb_ack_i)
+ // After first write all RxByteSel are active
+ RxPointerLSB_rst[1:0] <= 0;
+ else
+ if(RxEn & RxEn_q & RxPointerRead)
+ RxPointerLSB_rst[1:0] <= ram_do[1:0];
+ end
+
+
+ always @ (RxPointerLSB_rst)
+ begin
+ case(RxPointerLSB_rst[1:0]) // synopsys parallel_case
+ 2'h0 : RxByteSel[3:0] = 4'hf;
+ 2'h1 : RxByteSel[3:0] = 4'h7;
+ 2'h2 : RxByteSel[3:0] = 4'h3;
+ 2'h3 : RxByteSel[3:0] = 4'h1;
+ endcase
+ end
+
+
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ RxEn_needed <= 1'b0;
+ else
+ if(/*~RxReady &*/ r_RxEn & WbEn & ~WbEn_q)
+ RxEn_needed <= 1'b1;
+ else
+ if(RxPointerRead & RxEn & RxEn_q)
+ RxEn_needed <= 1'b0;
+ end
+
+
+ // Reception status is written back to the buffer descriptor after the end
+ // of frame is detected.
+ assign RxStatusWrite = rx_wb_writeback_finished & RxEn & RxEn_q;
+
+ reg RxEnableWindow;
+
+ // Indicating that last byte is being reveived
+ always @ (posedge MRxClk or posedge Reset)
+ begin
+ if(Reset)
+ LastByteIn <= 1'b0;
+ else
+ if(ShiftWillEnd & (&RxByteCnt) | RxAbort)
+ LastByteIn <= 1'b0;
+ else
+ if(RxValid /*& RxReady*/& RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
+ LastByteIn <= 1'b1;
+ end
+
+ assign StartShiftWillEnd = LastByteIn | RxValid & RxEndFrm & (&RxByteCnt) &
+ RxEnableWindow;
+
+ // Indicating that data reception will end
+ always @ (posedge MRxClk or posedge Reset)
+ begin
+ if(Reset)
+ ShiftWillEnd <= 1'b0;
+ else
+ if(ShiftEnded_rck | RxAbort)
+ ShiftWillEnd <= 1'b0;
+ else
+ if(StartShiftWillEnd)
+ ShiftWillEnd <= 1'b1;
+ end
+
+ // Receive byte counter
+ always @ (posedge MRxClk or posedge Reset)
+ begin
+ if(Reset)
+ RxByteCnt <= 2'h0;
+ else
+ if(ShiftEnded_rck | RxAbort)
+ RxByteCnt <= 2'h0;
+ else
+ if(RxValid & RxStartFrm /*& RxReady*/)
+ case(RxPointerLSB_rst) // synopsys parallel_case
+ 2'h0 : RxByteCnt <= 2'h1;
+ 2'h1 : RxByteCnt <= 2'h2;
+ 2'h2 : RxByteCnt <= 2'h3;
+ 2'h3 : RxByteCnt <= 2'h0;
+ endcase
+ else
+ if(RxValid & RxEnableWindow /*& RxReady*/ | LastByteIn)
+ RxByteCnt <= RxByteCnt + 1'b1;
+ end
+
+
+ // Indicates how many bytes are valid within the last word
+ always @ (posedge MRxClk or posedge Reset)
+ begin
+ if(Reset)
+ RxValidBytes <= 2'h1;
+ else
+ if(RxValid & RxStartFrm)
+ case(RxPointerLSB_rst) // synopsys parallel_case
+ 2'h0 : RxValidBytes <= 2'h1;
+ 2'h1 : RxValidBytes <= 2'h2;
+ 2'h2 : RxValidBytes <= 2'h3;
+ 2'h3 : RxValidBytes <= 2'h0;
+ endcase
+ else
+ if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
+ RxValidBytes <= RxValidBytes + 1'b1;
+ end
+
+
+ always @ (posedge MRxClk or posedge Reset)
+ begin
+ if(Reset)
+ RxDataLatched1 <= 24'h0;
+ else
+ if(RxValid /*& RxReady*/ & ~LastByteIn)
+ if(RxStartFrm)
+ begin
+ case(RxPointerLSB_rst) // synopsys parallel_case
+ // Big Endian Byte Ordering
+ 2'h0: RxDataLatched1[31:24] <= RxData;
+ 2'h1: RxDataLatched1[23:16] <= RxData;
+ 2'h2: RxDataLatched1[15:8] <= RxData;
+ 2'h3: RxDataLatched1 <= RxDataLatched1;
+ endcase
+ end
+ else if (RxEnableWindow)
+ begin
+ case(RxByteCnt) // synopsys parallel_case
+ // Big Endian Byte Ordering
+ 2'h0: RxDataLatched1[31:24] <= RxData;
+ 2'h1: RxDataLatched1[23:16] <= RxData;
+ 2'h2: RxDataLatched1[15:8] <= RxData;
+ 2'h3: RxDataLatched1 <= RxDataLatched1;
+ endcase
+ end
+ end
+
+ wire SetWriteRxDataToFifo;
+
+ // Assembling data that will be written to the rx_fifo
+ always @ (posedge MRxClk or posedge Reset)
+ begin
+ if(Reset)
+ RxDataLatched2 <= 32'h0;
+ else
+ if(SetWriteRxDataToFifo & ~ShiftWillEnd)
+ // Big Endian Byte Ordering
+ RxDataLatched2 <= {RxDataLatched1[31:8], RxData};
+ else
+ if(SetWriteRxDataToFifo & ShiftWillEnd)
+ case(RxValidBytes) // synopsys parallel_case
+ // Big Endian Byte Ordering
+ 0 : RxDataLatched2 <= {RxDataLatched1[31:8], RxData};
+ 1 : RxDataLatched2 <= {RxDataLatched1[31:24], 24'h0};
+ 2 : RxDataLatched2 <= {RxDataLatched1[31:16], 16'h0};
+ 3 : RxDataLatched2 <= {RxDataLatched1[31:8], 8'h0};
+ endcase
+ end
+
+
+ reg WriteRxDataToFifoSync1;
+ reg WriteRxDataToFifoSync2;
+ reg WriteRxDataToFifoSync3;
+
+
+ // Indicating start of the reception process
+ assign SetWriteRxDataToFifo = (RxValid &/* RxReady &*/ ~RxStartFrm &
+ RxEnableWindow & (&RxByteCnt)) |
+ (RxValid &/* RxReady &*/ RxStartFrm &
+ (&RxPointerLSB_rst)) |
+ (ShiftWillEnd & LastByteIn & (&RxByteCnt));
+
+ always @ (posedge MRxClk or posedge Reset)
+ begin
+ if(Reset)
+ WriteRxDataToFifo <= 1'b0;
+ else
+ if(SetWriteRxDataToFifo & ~RxAbort)
+ WriteRxDataToFifo <= 1'b1;
+ else
+ if(WriteRxDataToFifoSync2 | RxAbort)
+ WriteRxDataToFifo <= 1'b0;
+ end
+
+
+
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ WriteRxDataToFifoSync1 <= 1'b0;
+ else
+ if(WriteRxDataToFifo)
+ WriteRxDataToFifoSync1 <= 1'b1;
+ else
+ WriteRxDataToFifoSync1 <= 1'b0;
+ end
+
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ WriteRxDataToFifoSync2 <= 1'b0;
+ else
+ WriteRxDataToFifoSync2 <= WriteRxDataToFifoSync1;
+ end
+
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ WriteRxDataToFifoSync3 <= 1'b0;
+ else
+ WriteRxDataToFifoSync3 <= WriteRxDataToFifoSync2;
+ end
+
+ wire WriteRxDataToFifo_wb;
+ assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 &
+ ~WriteRxDataToFifoSync3;
+ // Receive fifo selection register - JB
+ reg [3:0] rx_shift_ended_wb_shr;
+ reg rx_ethside_fifo_sel;
+ reg rx_wbside_fifo_sel;
+
+ // Shift in this - our detection of end of data RX
+ always @(posedge WB_CLK_I)
+ rx_shift_ended_wb_shr <= {rx_shift_ended_wb_shr[2:0],
+ ShiftEndedSync1 & ~ShiftEndedSync2};
+
+
+ always @ (posedge WB_CLK_I or posedge Reset)
+ if(Reset)
+ rx_ethside_fifo_sel <= 0;
+ else
+ if(rx_shift_ended_wb_shr[3:2] == 2'b01)
+ // Switch over whenever we've finished receiving last frame's data
+ rx_ethside_fifo_sel <= ~rx_ethside_fifo_sel;
+
+ // Wishbone side looks at other FIFO when we write back the status of this
+ // received frame
+ always @ (posedge WB_CLK_I or posedge Reset)
+ if(Reset)
+ rx_wbside_fifo_sel <= 0;
+ else
+ if(rx_wb_writeback_finished & RxEn & RxEn_q)
+ // Switch over whenever we've finished receiving last frame's data
+ rx_wbside_fifo_sel <= ~rx_wbside_fifo_sel;
+
+ reg LatchedRxStartFrm;
+ reg SyncRxStartFrm;
+ reg SyncRxStartFrm_q;
+ reg SyncRxStartFrm_q2;
+ wire RxFifoReset;
+
+ always @ (posedge MRxClk or posedge Reset)
+ begin
+ if(Reset)
+ LatchedRxStartFrm <= 0;
+ else
+ if(RxStartFrm & ~SyncRxStartFrm_q)
+ LatchedRxStartFrm <= 1;
+ else
+ if(SyncRxStartFrm_q)
+ LatchedRxStartFrm <= 0;
+ end
+
+
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ SyncRxStartFrm <= 0;
+ else
+ if(LatchedRxStartFrm)
+ SyncRxStartFrm <= 1;
+ else
+ SyncRxStartFrm <= 0;
+ end
+
+
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ SyncRxStartFrm_q <= 0;
+ else
+ SyncRxStartFrm_q <= SyncRxStartFrm;
+ end
+
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ SyncRxStartFrm_q2 <= 0;
+ else
+ SyncRxStartFrm_q2 <= SyncRxStartFrm_q;
+ end
+ wire rx_startfrm_wb;
+ assign rx_startfrm_wb = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
+
+
+ assign RxFifoReset = rx_startfrm_wb;
+
+
+ wire [31:0] rx_fifo0_data_out;
+ wire rx_fifo0_write;
+ wire rx_fifo0_read;
+ wire rx_fifo0_clear;
+ wire rx_fifo0_full;
+ wire rx_fifo0_afull;
+ wire rx_fifo0_empty;
+ wire rx_fifo0_aempty;
+
+
+ wire [31:0] rx_fifo1_data_out;
+ wire rx_fifo1_write;
+ wire rx_fifo1_read;
+ wire rx_fifo1_clear;
+ wire rx_fifo1_full;
+ wire rx_fifo1_afull;
+ wire rx_fifo1_empty;
+ wire rx_fifo1_aempty;
+
+ wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rx_fifo0_cnt;
+ wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rx_fifo1_cnt;
+
+ // RX FIFO buffer 0 controls
+ assign rx_fifo0_write = (!rx_ethside_fifo_sel) & WriteRxDataToFifo_wb &
+ ~rx_fifo0_full;
+
+ assign rx_fifo0_read = (!rx_wbside_fifo_sel) & MasterWbRX & m_wb_ack_i &
+ ~rx_fifo0_empty;
+
+ assign rx_fifo0_clear = (!rx_ethside_fifo_sel) & RxFifoReset;
+
+ // RX FIFO buffer 1 controls
+ assign rx_fifo1_write = (rx_ethside_fifo_sel) & WriteRxDataToFifo_wb &
+ ~rx_fifo1_full;
+
+ assign rx_fifo1_read = (rx_wbside_fifo_sel) & MasterWbRX & m_wb_ack_i &
+ ~rx_fifo1_empty;
+
+ assign rx_fifo1_clear = (rx_ethside_fifo_sel) & RxFifoReset;
+
+ eth_fifo #(
+ `ETH_RX_FIFO_DATA_WIDTH,
+ `ETH_RX_FIFO_DEPTH,
+ `ETH_RX_FIFO_CNT_WIDTH
+ )
+ rx_fifo0 (
+ .clk (WB_CLK_I ),
+ .reset (Reset ),
+ // Inputs
+ .data_in (RxDataLatched2 ),
+ .write (rx_fifo0_write ),
+ .read (rx_fifo0_read ),
+ .clear (rx_fifo0_clear ),
+ // Outputs
+ .data_out (rx_fifo0_data_out),
+ .full (rx_fifo0_full ),
+ .almost_full (),
+ .almost_empty (rx_fifo0_aempty ),
+ .empty (rx_fifo0_empty ),
+ .cnt (rx_fifo0_cnt )
+ );
+
+ eth_fifo #(
+ `ETH_RX_FIFO_DATA_WIDTH,
+ `ETH_RX_FIFO_DEPTH,
+ `ETH_RX_FIFO_CNT_WIDTH
+ )
+ rx_fifo1 (
+ .clk (WB_CLK_I ),
+ .reset (Reset ),
+ // Inputs
+ .data_in (RxDataLatched2 ),
+ .write (rx_fifo1_write ),
+ .read (rx_fifo1_read ),
+ .clear (rx_fifo1_clear ),
+ // Outputs
+ .data_out (rx_fifo1_data_out),
+ .full (rx_fifo1_full ),
+ .almost_full (),
+ .almost_empty (rx_fifo1_aempty ),
+ .empty (rx_fifo1_empty ),
+ .cnt (rx_fifo1_cnt )
+ );
+
+ assign m_wb_dat_o = rx_wbside_fifo_sel ?
+ rx_fifo1_data_out : rx_fifo0_data_out;
+ assign rxfifo_cnt = rx_wbside_fifo_sel ?
+ rx_fifo1_cnt : rx_fifo0_cnt;
+
+ assign RxBufferAlmostEmpty = rx_wbside_fifo_sel ?
+ rx_fifo1_aempty : rx_fifo0_aempty;
+
+ assign RxBufferEmpty = rx_wbside_fifo_sel ?
+ rx_fifo1_empty : rx_fifo0_empty;
+
+ assign RxBufferFull = rx_wbside_fifo_sel ?
+ rx_fifo1_full : rx_fifo0_full;
+
+
+
+
+
+ wire write_rx_data_to_memory_wait;
+ assign write_rx_data_to_memory_wait = !RxBDOK | RxPointerRead;
+ wire write_rx_data_to_memory_go;
+
+`ifdef ETH_RX_BURST_EN
+ assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=(`ETH_BURST_LENGTH);
+ assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>(`ETH_BURST_LENGTH - 1);
+ // While receiving, don't flog the bus too hard, only write out when
+ // we can burst. But when finishing keep going until we've emptied the fifo
+ assign write_rx_data_to_memory_go =
+ RxEnableWindow & (rx_wbside_fifo_sel == rx_ethside_fifo_sel) ?
+ (rxfifo_cnt>(`ETH_BURST_LENGTH)+2) |
+ (|rx_burst_cnt) : ~RxBufferEmpty;
+
+`else
+ assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=`ETH_BURST_LENGTH;
+ assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>`ETH_BURST_LENGTH;
+ assign write_rx_data_to_memory_go = ~RxBufferEmpty;
+`endif // !`ifdef ETH_RX_BURST_EN
+
+ assign WriteRxDataToMemory = write_rx_data_to_memory_go & !write_rx_data_to_memory_wait;
+
+ assign rx_burst = rx_burst_en & WriteRxDataToMemory;
+
+
+ // Generation of the end-of-frame signal
+ always @ (posedge MRxClk or posedge Reset)
+ begin
+ if(Reset)
+ ShiftEnded_rck <= 1'b0;
+ else
+ if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
+ ShiftEnded_rck <= 1'b1;
+ else
+ if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
+ ShiftEnded_rck <= 1'b0;
+ end
+
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ ShiftEndedSync1 <= 1'b0;
+ else
+ ShiftEndedSync1 <= ShiftEnded_rck;
+ end
+
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ ShiftEndedSync2 <= 1'b0;
+ else
+ ShiftEndedSync2 <= ShiftEndedSync1;
+ end
+
+ // indicate end of wishbone RX is coming up
+ always @ (posedge WB_CLK_I or posedge Reset)
+ if(Reset)
+ rx_wb_last_writes <= 1'b0;
+ else if (!rx_wb_last_writes)
+ rx_wb_last_writes <= ShiftEndedSync1 & ~ShiftEndedSync2;
+ else if (rx_wb_writeback_finished & RxEn & RxEn_q)
+ rx_wb_last_writes <= 0;
+
+ // Pulse indicating last of RX data has been written out
+ always @ (posedge WB_CLK_I or posedge Reset)
+ if(Reset)
+ rx_wb_writeback_finished <= 0;
+ else if (rx_wb_writeback_finished & RxEn & RxEn_q)
+ rx_wb_writeback_finished <= 0;
+ else
+ rx_wb_writeback_finished <= rx_wb_last_writes & RxBufferEmpty &
+ !WriteRxDataToFifo_wb;
+
+
+ always @ (posedge MRxClk or posedge Reset)
+ begin
+ if(Reset)
+ ShiftEndedSync_c1 <= 1'b0;
+ else
+ ShiftEndedSync_c1 <= ShiftEndedSync2;
+ end
+
+ always @ (posedge MRxClk or posedge Reset)
+ begin
+ if(Reset)
+ ShiftEndedSync_c2 <= 1'b0;
+ else
+ ShiftEndedSync_c2 <= ShiftEndedSync_c1;
+ end
+
+ // Generation of the end-of-frame signal
+ always @ (posedge MRxClk or posedge Reset)
+ begin
+ if(Reset)
+ RxEnableWindow <= 1'b0;
+ else
+ if(RxStartFrm)
+ RxEnableWindow <= 1'b1;
+ else
+ if(RxEndFrm | RxAbort)
+ RxEnableWindow <= 1'b0;
+ end
+
+
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ RxAbortSync1 <= 1'b0;
+ else
+ RxAbortSync1 <= RxAbortLatched;
+ end
+
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ RxAbortSync2 <= 1'b0;
+ else
+ RxAbortSync2 <= RxAbortSync1;
+ end
+
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ RxAbortSync3 <= 1'b0;
+ else
+ RxAbortSync3 <= RxAbortSync2;
+ end
+
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ RxAbortSync4 <= 1'b0;
+ else
+ RxAbortSync4 <= RxAbortSync3;
+ end
+
+ always @ (posedge MRxClk or posedge Reset)
+ begin
+ if(Reset)
+ RxAbortSyncb1 <= 1'b0;
+ else
+ RxAbortSyncb1 <= RxAbortSync2;
+ end
+
+ always @ (posedge MRxClk or posedge Reset)
+ begin
+ if(Reset)
+ RxAbortSyncb2 <= 1'b0;
+ else
+ RxAbortSyncb2 <= RxAbortSyncb1;
+ end
+
+
+ always @ (posedge MRxClk or posedge Reset)
+ begin
+ if(Reset)
+ RxAbortLatched <= 1'b0;
+ else
+ if(RxAbortSyncb2)
+ RxAbortLatched <= 1'b0;
+ else
+ if(RxAbort)
+ RxAbortLatched <= 1'b1;
+ end
+
+
+ always @ (posedge MRxClk or posedge Reset)
+ begin
+ if(Reset)
+ LatchedRxLength[15:0] <= 16'h0;
+ else
+ if(LoadRxStatus)
+ LatchedRxLength[15:0] <= RxLength[15:0];
+ end
+
+
+ assign RxStatusIn = {ReceivedPauseFrm, AddressMiss, RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
+
+ always @ (posedge MRxClk or posedge Reset)
+ begin
+ if(Reset)
+ RxStatusInLatched <= 'h0;
+ else
+ if(LoadRxStatus)
+ RxStatusInLatched <= RxStatusIn;
+ end
+
+
+ // Rx overrun
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ RxOverrun <= 1'b0;
+ else
+ if(RxStatusWrite)
+ RxOverrun <= 1'b0;
+ else
+ if(RxBufferFull & WriteRxDataToFifo_wb)
+ RxOverrun <= 1'b1;
+ end
+
+
+
+ wire TxError;
+ assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
+
+ wire RxError;
+
+ // ShortFrame (RxStatusInLatched[2]) can not set an error because short
+ // frames are aborted when signal r_RecSmall is set to 0 in MODER register.
+ // AddressMiss is identifying that a frame was received because of the
+ // promiscous mode and is not an error
+ assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
+
+
+
+ reg RxStatusWriteLatched;
+ reg RxStatusWriteLatched_sync1;
+ reg RxStatusWriteLatched_sync2;
+ reg RxStatusWriteLatched_syncb1;
+ reg RxStatusWriteLatched_syncb2;
+
+
+ // Latching and synchronizing RxStatusWrite signal. This signal is used for
+ // clearing the ReceivedPauseFrm signal
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ RxStatusWriteLatched <= 1'b0;
+ else
+ if(RxStatusWriteLatched_syncb2)
+ RxStatusWriteLatched <= 1'b0;
+ else
+ if(RxStatusWrite)
+ RxStatusWriteLatched <= 1'b1;
+ end
+
+
+ always @ (posedge MRxClk or posedge Reset)
+ begin
+ if(Reset)
+ begin
+ RxStatusWriteLatched_sync1 <= 1'b0;
+ RxStatusWriteLatched_sync2 <= 1'b0;
+ end
+ else
+ begin
+ RxStatusWriteLatched_sync1 <= RxStatusWriteLatched;
+ RxStatusWriteLatched_sync2 <= RxStatusWriteLatched_sync1;
+ end
+ end
+
+
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ begin
+ RxStatusWriteLatched_syncb1 <= 1'b0;
+ RxStatusWriteLatched_syncb2 <= 1'b0;
+ end
+ else
+ begin
+ RxStatusWriteLatched_syncb1 <= RxStatusWriteLatched_sync2;
+ RxStatusWriteLatched_syncb2 <= RxStatusWriteLatched_syncb1;
+ end
+ end
+
+
+
+ // Tx Done Interrupt
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ TxB_IRQ <= 1'b0;
+ else
+ if(TxStatusWrite & TxIRQEn)
+ TxB_IRQ <= ~TxError;
+ else
+ TxB_IRQ <= 1'b0;
+ end
+
+
+ // Tx Error Interrupt
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ TxE_IRQ <= 1'b0;
+ else
+ if(TxStatusWrite & TxIRQEn)
+ TxE_IRQ <= TxError;
+ else
+ TxE_IRQ <= 1'b0;
+ end
+
+
+ // Rx Done Interrupt
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ RxB_IRQ <= 1'b0;
+ else
+ if(RxStatusWrite & RxIRQEn & ReceivedPacketGood &
+ (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
+ RxB_IRQ <= (~RxError);
+ else
+ RxB_IRQ <= 1'b0;
+ end
+
+
+ // Rx Error Interrupt
+ always @ (posedge WB_CLK_I or posedge Reset)
+ begin
+ if(Reset)
+ RxE_IRQ <= 1'b0;
+ else
+ if(RxStatusWrite & RxIRQEn & (~ReceivedPauseFrm | ReceivedPauseFrm
+ & r_PassAll & (~r_RxFlow)))
+ RxE_IRQ <= RxError;
+ else
+ RxE_IRQ <= 1'b0;
+ end
+
+ // Set this high when we started receiving another packet while the wishbone
+ // side was still writing out the last one. This makes sure we check at the
+ // right time if the next buffer descriptor is free.
+ reg rxstartfrm_occurred;
+ always @ (posedge WB_CLK_I)
+ if (Reset)
+ rxstartfrm_occurred <= 0;
+ else if (rx_just_read_bd)
+ rxstartfrm_occurred <= 0;
+ else if (((rx_ethside_fifo_sel != rx_wbside_fifo_sel) | StartRxBDRead |
+ RxBDRead) & rx_startfrm_wb)
+ rxstartfrm_occurred <= 1;
+
+
+
+ reg busy_wb;
+ always @ (posedge WB_CLK_I or posedge Reset)
+ if(Reset)
+ busy_wb <= 0;
+ else if (busy_wb)
+ busy_wb <= 0;
+ else if
+ // Indicate busy if either:
+ // a) RX is idle and we get a start frame and current BD indicates not
+ // ready.
+ // b) RX is already receiving another packet and we got a startframe,
+ // indicated by rx_startfrm_occurred, and we then read the BD and
+ // it says it's not ready.
+ // This actually may not work since it's in the MII RX clock domain.
+ ((rx_ethside_fifo_sel == rx_wbside_fifo_sel) &
+ ((rxstartfrm_occurred & rx_just_read_bd & ~RxBDReady) |
+ (!rxstartfrm_occurred & !StartRxBDRead & !RxBDRead & rx_startfrm_wb &
+ rx_waiting_for_bd_to_become_free))
+ )
+ busy_wb <= 1;
+
+
+ assign Busy_IRQ = busy_wb;
+
+ always @(posedge Busy_IRQ)
+ $display("(%t)(%m) Ethernet MAC BUSY signal asserted", $time);
+
+
+ // Assign the debug output
+`ifdef WISHBONE_DEBUG
+ // Top byte, burst progress counters
+ assign dbg_dat0[31] = 0;
+ assign dbg_dat0[30] = 0;
+ assign dbg_dat0[29:28] = rx_burst_cnt;
+ assign dbg_dat0[27] = 0;
+ assign dbg_dat0[26] = 0;
+ assign dbg_dat0[25:24] = tx_burst_cnt;
+
+ // Third byte
+ assign dbg_dat0[23] = 0;
+ assign dbg_dat0[22] = 0;
+ assign dbg_dat0[21] = rx_burst;
+ assign dbg_dat0[20] = rx_burst_en;
+ assign dbg_dat0[19] = 0;
+ assign dbg_dat0[18] = 0;
+ assign dbg_dat0[17] = tx_burst;
+ assign dbg_dat0[16] = tx_burst_en;
+ // Second byte - TxBDAddress - or TX BD address pointer
+ assign dbg_dat0[15:8] = { 1'b0, TxBDAddress};
+ // Bottom byte - FSM controlling vector
+ assign dbg_dat0[7:0] = {MasterWbTX,MasterWbRX,
+ ReadTxDataFromMemory_2,WriteRxDataToMemory,
+ MasterAccessFinished,cyc_cleared,
+ tx_burst,rx_burst};
+
+`endif
+
+
+
+endmodule
rtl/verilog/ethmac/eth_wishbone.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rtl/verilog/ethmac/eth_txcounters.v
===================================================================
--- rtl/verilog/ethmac/eth_txcounters.v (nonexistent)
+++ rtl/verilog/ethmac/eth_txcounters.v (revision 409)
@@ -0,0 +1,221 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// eth_txcounters.v ////
+//// ////
+//// This file is part of the Ethernet IP core project ////
+//// http://www.opencores.org/project,ethmac ////
+//// ////
+//// Author(s): ////
+//// - Igor Mohor (igorM@opencores.org) ////
+//// - Novan Hartadi (novan@vlsi.itb.ac.id) ////
+//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////
+//// ////
+//// All additional information is avaliable in the Readme.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.5 2002/04/22 14:54:14 mohor
+// FCS should not be included in NibbleMinFl.
+//
+// Revision 1.4 2002/01/23 10:28:16 mohor
+// Link in the header changed.
+//
+// Revision 1.3 2001/10/19 08:43:51 mohor
+// eth_timescale.v changed to timescale.v This is done because of the
+// simulation of the few cores in a one joined project.
+//
+// Revision 1.2 2001/09/11 14:17:00 mohor
+// Few little NCSIM warnings fixed.
+//
+// Revision 1.1 2001/08/06 14:44:29 mohor
+// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
+// Include files fixed to contain no path.
+// File names and module names changed ta have a eth_ prologue in the name.
+// File eth_timescale.v is used to define timescale
+// All pin names on the top module are changed to contain _I, _O or _OE at the end.
+// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
+// and Mdo_OE. The bidirectional signal must be created on the top level. This
+// is done due to the ASIC tools.
+//
+// Revision 1.1 2001/07/30 21:23:42 mohor
+// Directory structure changed. Files checked and joind together.
+//
+// Revision 1.4 2001/06/27 21:27:45 mohor
+// Few typos fixed.
+//
+// Revision 1.2 2001/06/19 10:38:07 mohor
+// Minor changes in header.
+//
+// Revision 1.1 2001/06/19 10:27:57 mohor
+// TxEthMAC initial release.
+//
+//
+//
+
+
+`include "timescale.v"
+
+
+module eth_txcounters (StatePreamble, StateIPG, StateData, StatePAD, StateFCS, StateJam,
+ StateBackOff, StateDefer, StateIdle, StartDefer, StartIPG, StartFCS,
+ StartJam, StartBackoff, TxStartFrm, MTxClk, Reset, MinFL, MaxFL, HugEn,
+ ExDfrEn, PacketFinished_q, DlyCrcEn, StateSFD, ByteCnt, NibCnt,
+ ExcessiveDefer, NibCntEq7, NibCntEq15, MaxFrame, NibbleMinFl, DlyCrcCnt
+ );
+
+parameter Tp = 1;
+
+input MTxClk; // Tx clock
+input Reset; // Reset
+input StatePreamble; // Preamble state
+input StateIPG; // IPG state
+input [1:0] StateData; // Data state
+input StatePAD; // PAD state
+input StateFCS; // FCS state
+input StateJam; // Jam state
+input StateBackOff; // Backoff state
+input StateDefer; // Defer state
+input StateIdle; // Idle state
+input StateSFD; // SFD state
+input StartDefer; // Defer state will be activated in next clock
+input StartIPG; // IPG state will be activated in next clock
+input StartFCS; // FCS state will be activated in next clock
+input StartJam; // Jam state will be activated in next clock
+input StartBackoff; // Backoff state will be activated in next clock
+input TxStartFrm; // Tx start frame
+input [15:0] MinFL; // Minimum frame length (in bytes)
+input [15:0] MaxFL; // Miximum frame length (in bytes)
+input HugEn; // Pakets bigger then MaxFL enabled
+input ExDfrEn; // Excessive deferral enabled
+input PacketFinished_q;
+input DlyCrcEn; // Delayed CRC enabled
+
+output [15:0] ByteCnt; // Byte counter
+output [15:0] NibCnt; // Nibble counter
+output ExcessiveDefer; // Excessive Deferral occuring
+output NibCntEq7; // Nibble counter is equal to 7
+output NibCntEq15; // Nibble counter is equal to 15
+output MaxFrame; // Maximum frame occured
+output NibbleMinFl; // Nibble counter is greater than the minimum frame length
+output [2:0] DlyCrcCnt; // Delayed CRC Count
+
+wire ExcessiveDeferCnt;
+wire ResetNibCnt;
+wire IncrementNibCnt;
+wire ResetByteCnt;
+wire IncrementByteCnt;
+wire ByteCntMax;
+
+reg [15:0] NibCnt;
+reg [15:0] ByteCnt;
+reg [2:0] DlyCrcCnt;
+
+
+
+assign IncrementNibCnt = StateIPG | StatePreamble | (|StateData) | StatePAD
+ | StateFCS | StateJam | StateBackOff | StateDefer & ~ExcessiveDefer & TxStartFrm;
+
+
+assign ResetNibCnt = StateDefer & ExcessiveDefer & ~TxStartFrm | StatePreamble & NibCntEq15
+ | StateJam & NibCntEq7 | StateIdle | StartDefer | StartIPG | StartFCS | StartJam;
+
+// Nibble Counter
+always @ (posedge MTxClk or posedge Reset)
+begin
+ if(Reset)
+ NibCnt <= 16'h0;
+ else
+ begin
+ if(ResetNibCnt)
+ NibCnt <= 16'h0;
+ else
+ if(IncrementNibCnt)
+ NibCnt <= NibCnt + 1'b1;
+ end
+end
+
+
+assign NibCntEq7 = &NibCnt[2:0];
+assign NibCntEq15 = &NibCnt[3:0];
+
+assign NibbleMinFl = NibCnt >= (((MinFL-3'h4)<<1) -1); // FCS should not be included in NibbleMinFl
+
+assign ExcessiveDeferCnt = NibCnt[13:0] == 16'h17b7;
+
+assign ExcessiveDefer = NibCnt[13:0] == 16'h17b7 & ~ExDfrEn; // 6071 nibbles
+
+assign IncrementByteCnt = StateData[1] & ~ByteCntMax
+ | StateBackOff & (&NibCnt[6:0])
+ | (StatePAD | StateFCS) & NibCnt[0] & ~ByteCntMax;
+
+assign ResetByteCnt = StartBackoff | StateIdle & TxStartFrm | PacketFinished_q;
+
+
+// Transmit Byte Counter
+always @ (posedge MTxClk or posedge Reset)
+begin
+ if(Reset)
+ ByteCnt[15:0] <= 16'h0;
+ else
+ begin
+ if(ResetByteCnt)
+ ByteCnt[15:0] <= 16'h0;
+ else
+ if(IncrementByteCnt)
+ ByteCnt[15:0] <= ByteCnt[15:0] + 1'b1;
+ end
+end
+
+
+assign MaxFrame = ByteCnt[15:0] == MaxFL[15:0] & ~HugEn;
+
+assign ByteCntMax = &ByteCnt[15:0];
+
+
+// Delayed CRC counter
+always @ (posedge MTxClk or posedge Reset)
+begin
+ if(Reset)
+ DlyCrcCnt <= 3'h0;
+ else
+ begin
+ if(StateData[1] & DlyCrcCnt == 3'h4 | StartJam | PacketFinished_q)
+ DlyCrcCnt <= 3'h0;
+ else
+ if(DlyCrcEn & (StateSFD | StateData[1] & (|DlyCrcCnt[2:0])))
+ DlyCrcCnt <= DlyCrcCnt + 1'b1;
+ end
+end
+
+
+
+endmodule
rtl/verilog/ethmac/eth_txcounters.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rtl/verilog/ethmac/eth_random.v
===================================================================
--- rtl/verilog/ethmac/eth_random.v (nonexistent)
+++ rtl/verilog/ethmac/eth_random.v (revision 409)
@@ -0,0 +1,141 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// eth_random.v ////
+//// ////
+//// This file is part of the Ethernet IP core project ////
+//// http://www.opencores.org/project,ethmac ////
+//// ////
+//// Author(s): ////
+//// - Igor Mohor (igorM@opencores.org) ////
+//// - Novan Hartadi (novan@vlsi.itb.ac.id) ////
+//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////
+//// ////
+//// All additional information is avaliable in the Readme.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.3 2002/01/23 10:28:16 mohor
+// Link in the header changed.
+//
+// Revision 1.2 2001/10/19 08:43:51 mohor
+// eth_timescale.v changed to timescale.v This is done because of the
+// simulation of the few cores in a one joined project.
+//
+// Revision 1.1 2001/08/06 14:44:29 mohor
+// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
+// Include files fixed to contain no path.
+// File names and module names changed ta have a eth_ prologue in the name.
+// File eth_timescale.v is used to define timescale
+// All pin names on the top module are changed to contain _I, _O or _OE at the end.
+// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
+// and Mdo_OE. The bidirectional signal must be created on the top level. This
+// is done due to the ASIC tools.
+//
+// Revision 1.1 2001/07/30 21:23:42 mohor
+// Directory structure changed. Files checked and joind together.
+//
+// Revision 1.3 2001/06/19 18:16:40 mohor
+// TxClk changed to MTxClk (as discribed in the documentation).
+// Crc changed so only one file can be used instead of two.
+//
+// Revision 1.2 2001/06/19 10:38:07 mohor
+// Minor changes in header.
+//
+// Revision 1.1 2001/06/19 10:27:57 mohor
+// TxEthMAC initial release.
+//
+//
+//
+//
+
+`include "timescale.v"
+
+module eth_random (MTxClk, Reset, StateJam, StateJam_q, RetryCnt, NibCnt, ByteCnt,
+ RandomEq0, RandomEqByteCnt);
+
+parameter Tp = 1;
+
+input MTxClk;
+input Reset;
+input StateJam;
+input StateJam_q;
+input [3:0] RetryCnt;
+input [15:0] NibCnt;
+input [9:0] ByteCnt;
+output RandomEq0;
+output RandomEqByteCnt;
+
+wire Feedback;
+reg [9:0] x;
+wire [9:0] Random;
+reg [9:0] RandomLatched;
+
+
+always @ (posedge MTxClk or posedge Reset)
+begin
+ if(Reset)
+ x[9:0] <= 0;
+ else
+ x[9:0] <= {x[8:0], Feedback};
+end
+
+assign Feedback = ~(x[2] ^ x[9]);
+
+assign Random [0] = x[0];
+assign Random [1] = (RetryCnt > 1) ? x[1] : 1'b0;
+assign Random [2] = (RetryCnt > 2) ? x[2] : 1'b0;
+assign Random [3] = (RetryCnt > 3) ? x[3] : 1'b0;
+assign Random [4] = (RetryCnt > 4) ? x[4] : 1'b0;
+assign Random [5] = (RetryCnt > 5) ? x[5] : 1'b0;
+assign Random [6] = (RetryCnt > 6) ? x[6] : 1'b0;
+assign Random [7] = (RetryCnt > 7) ? x[7] : 1'b0;
+assign Random [8] = (RetryCnt > 8) ? x[8] : 1'b0;
+assign Random [9] = (RetryCnt > 9) ? x[9] : 1'b0;
+
+
+always @ (posedge MTxClk or posedge Reset)
+begin
+ if(Reset)
+ RandomLatched <= 10'h000;
+ else
+ begin
+ if(StateJam & StateJam_q)
+ RandomLatched <= Random;
+ end
+end
+
+// Random Number == 0 IEEE 802.3 page 68. If 0 we go to defer and not to backoff.
+assign RandomEq0 = RandomLatched == 10'h0;
+
+assign RandomEqByteCnt = ByteCnt[9:0] == RandomLatched & (&NibCnt[6:0]);
+
+endmodule
rtl/verilog/ethmac/eth_random.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rtl/verilog/ethmac/eth_fifo.v
===================================================================
--- rtl/verilog/ethmac/eth_fifo.v (nonexistent)
+++ rtl/verilog/ethmac/eth_fifo.v (revision 409)
@@ -0,0 +1,227 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// eth_fifo.v ////
+//// ////
+//// This file is part of the Ethernet IP core project ////
+//// http://www.opencores.org/project,ethmac ////
+//// ////
+//// Author(s): ////
+//// - Igor Mohor (igorM@opencores.org) ////
+//// ////
+//// All additional information is avaliable in the Readme.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.3 2002/04/22 13:45:52 mohor
+// Generic ram or Xilinx ram can be used in fifo (selectable by setting
+// ETH_FIFO_XILINX in ethmac_defines.v).
+//
+// Revision 1.2 2002/03/25 13:33:04 mohor
+// When clear and read/write are active at the same time, cnt and pointers are
+// set to 1.
+//
+// Revision 1.1 2002/02/05 16:44:39 mohor
+// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
+// MHz. Statuses, overrun, control frame transmission and reception still need
+// to be fixed.
+//
+//
+
+`include "ethmac_defines.v"
+`include "timescale.v"
+
+module eth_fifo (data_in, data_out, clk, reset, write, read, clear, almost_full, full, almost_empty, empty, cnt);
+
+parameter DATA_WIDTH = 32;
+parameter DEPTH = 8;
+parameter CNT_WIDTH = 4;
+
+input clk;
+input reset;
+input write;
+input read;
+input clear;
+input [DATA_WIDTH-1:0] data_in;
+
+output [DATA_WIDTH-1:0] data_out;
+output almost_full;
+output full;
+output almost_empty;
+output empty;
+output [CNT_WIDTH-1:0] cnt;
+
+
+
+reg [CNT_WIDTH-1:0] cnt;
+ reg final_read;
+
+always @ (posedge clk or posedge reset)
+begin
+ if(reset)
+ cnt <= 0;
+ else
+ if(clear)
+ cnt <= { {(CNT_WIDTH-1){1'b0}}, read^write};
+ else
+ if(read ^ write)
+ if(read)
+ cnt <= cnt - 1'b1;
+ else
+ cnt <= cnt + 1'b1;
+end
+
+
+`ifdef ETH_FIFO_GENERIC
+
+ reg [DATA_WIDTH-1:0] fifo [0:DEPTH-1] /*synthesis syn_ramstyle = "no_rw_check"*/ ;
+
+
+ // This should make the synthesis tool infer RAMs
+ reg [CNT_WIDTH-2:0] waddr, raddr, raddr_reg;
+ reg clear_reg; // Register the clear pulse
+
+ always @(posedge clk)
+ if (reset)
+ waddr <= 0;
+ else if (write)
+ waddr <= waddr + 1;
+
+ wire raddr_reg_adv;
+ reg read_reg;
+ always @(posedge clk)
+ read_reg <= read;
+
+ // Advance the address after a read = first/next word fallthrough
+ assign raddr_reg_adv = (cnt > 2) & read_reg;
+
+ always @(posedge clk)
+ if (reset)
+ raddr <= 0;
+ else if (clear)
+ raddr <= waddr;
+ else if (read | clear_reg )
+ raddr <= raddr + 1;
+
+ always @ (posedge clk)
+ if (write & ~full)
+ fifo[waddr] <= data_in;
+
+
+ always @(posedge clk)
+ clear_reg <= clear;
+
+ always @ (posedge clk)
+ if (read | clear_reg)
+ raddr_reg <= raddr;
+
+ assign data_out = fifo[raddr_reg];
+
+
+ always @(posedge clk)
+ if (reset)
+ final_read <= 0;
+ else if (final_read & read & !write)
+ final_read <= ~final_read;
+ else if ((cnt == 1) & read & !write)
+ final_read <= 1; // Indicate last read data has been output
+
+
+ assign empty = ~(|cnt);
+ assign almost_empty = cnt==1;
+ assign full = cnt == DEPTH;
+ assign almost_full = &cnt[CNT_WIDTH-2:0];
+
+`else // !`ifdef ETH_FIFO_GENERIC
+
+reg [CNT_WIDTH-2:0] read_pointer;
+reg [CNT_WIDTH-2:0] write_pointer;
+
+
+always @ (posedge clk or posedge reset)
+begin
+ if(reset)
+ read_pointer <= 0;
+ else
+ if(clear)
+ //read_pointer <= { {(CNT_WIDTH-2){1'b0}}, read};
+ read_pointer <= { {(CNT_WIDTH-2){1'b0}}, 1'b1};
+ else
+ if(read & ~empty)
+ read_pointer <= read_pointer + 1'b1;
+end
+
+always @ (posedge clk or posedge reset)
+begin
+ if(reset)
+ write_pointer <= 0;
+ else
+ if(clear)
+ write_pointer <= { {(CNT_WIDTH-2){1'b0}}, write};
+ else
+ if(write & ~full)
+ write_pointer <= write_pointer + 1'b1;
+end
+
+`ifdef ETH_FIFO_XILINX
+ xilinx_dist_ram_16x32 fifo
+ ( .data_out(data_out),
+ .we(write & ~full),
+ .data_in(data_in),
+ .read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer),
+ .write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer),
+ .wclk(clk)
+ );
+`else // !ETH_FIFO_XILINX
+`ifdef ETH_ALTERA_ALTSYNCRAM
+ altera_dpram_16x32 altera_dpram_16x32_inst
+ (
+ .data (data_in),
+ .wren (write & ~full),
+ .wraddress (clear ? {CNT_WIDTH-1{1'b0}} : write_pointer),
+ .rdaddress (clear ? {CNT_WIDTH-1{1'b0}} : read_pointer ),
+ .clock (clk),
+ .q (data_out)
+ ); //exemplar attribute altera_dpram_16x32_inst NOOPT TRUE
+`endif // `ifdef ETH_ALTERA_ALTSYNCRAM
+`endif // !`ifdef ETH_FIFO_XILINX
+
+
+assign empty = ~(|cnt);
+assign almost_empty = cnt == 1;
+assign full = cnt == DEPTH;
+assign almost_full = &cnt[CNT_WIDTH-2:0];
+
+`endif // !`ifdef ETH_FIFO_GENERIC
+
+
+
+endmodule
rtl/verilog/ethmac/eth_fifo.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rtl/verilog/ethmac/eth_receivecontrol.v
===================================================================
--- rtl/verilog/ethmac/eth_receivecontrol.v (nonexistent)
+++ rtl/verilog/ethmac/eth_receivecontrol.v (revision 409)
@@ -0,0 +1,438 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// eth_receivecontrol.v ////
+//// ////
+//// This file is part of the Ethernet IP core project ////
+//// http://www.opencores.org/project,ethmac ////
+//// ////
+//// Author(s): ////
+//// - Igor Mohor (igorM@opencores.org) ////
+//// ////
+//// All additional information is avaliable in the Readme.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.4 2002/11/22 01:57:06 mohor
+// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
+// synchronized.
+//
+// Revision 1.3 2002/01/23 10:28:16 mohor
+// Link in the header changed.
+//
+// Revision 1.2 2001/10/19 08:43:51 mohor
+// eth_timescale.v changed to timescale.v This is done because of the
+// simulation of the few cores in a one joined project.
+//
+// Revision 1.1 2001/08/06 14:44:29 mohor
+// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
+// Include files fixed to contain no path.
+// File names and module names changed ta have a eth_ prologue in the name.
+// File eth_timescale.v is used to define timescale
+// All pin names on the top module are changed to contain _I, _O or _OE at the end.
+// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
+// and Mdo_OE. The bidirectional signal must be created on the top level. This
+// is done due to the ASIC tools.
+//
+// Revision 1.1 2001/07/30 21:23:42 mohor
+// Directory structure changed. Files checked and joind together.
+//
+// Revision 1.1 2001/07/03 12:51:54 mohor
+// Initial release of the MAC Control module.
+//
+//
+//
+//
+//
+
+
+`include "timescale.v"
+
+
+module eth_receivecontrol (MTxClk, MRxClk, TxReset, RxReset, RxData, RxValid, RxStartFrm,
+ RxEndFrm, RxFlow, ReceiveEnd, MAC, DlyCrcEn, TxDoneIn,
+ TxAbortIn, TxStartFrmOut, ReceivedLengthOK, ReceivedPacketGood,
+ TxUsedDataOutDetected, Pause, ReceivedPauseFrm, AddressOK,
+ RxStatusWriteLatched_sync2, r_PassAll, SetPauseTimer
+ );
+
+parameter Tp = 1;
+
+
+input MTxClk;
+input MRxClk;
+input TxReset;
+input RxReset;
+input [7:0] RxData;
+input RxValid;
+input RxStartFrm;
+input RxEndFrm;
+input RxFlow;
+input ReceiveEnd;
+input [47:0]MAC;
+input DlyCrcEn;
+input TxDoneIn;
+input TxAbortIn;
+input TxStartFrmOut;
+input ReceivedLengthOK;
+input ReceivedPacketGood;
+input TxUsedDataOutDetected;
+input RxStatusWriteLatched_sync2;
+input r_PassAll;
+
+output Pause;
+output ReceivedPauseFrm;
+output AddressOK;
+output SetPauseTimer;
+
+
+reg Pause;
+reg AddressOK; // Multicast or unicast address detected
+reg TypeLengthOK; // Type/Length field contains 0x8808
+reg DetectionWindow; // Detection of the PAUSE frame is possible within this window
+reg OpCodeOK; // PAUSE opcode detected (0x0001)
+reg [2:0] DlyCrcCnt;
+reg [4:0] ByteCnt;
+reg [15:0] AssembledTimerValue;
+reg [15:0] LatchedTimerValue;
+reg ReceivedPauseFrm;
+reg ReceivedPauseFrmWAddr;
+reg PauseTimerEq0_sync1;
+reg PauseTimerEq0_sync2;
+reg [15:0] PauseTimer;
+reg Divider2;
+reg [5:0] SlotTimer;
+
+wire [47:0] ReservedMulticast; // 0x0180C2000001
+wire [15:0] TypeLength; // 0x8808
+wire ResetByteCnt; //
+wire IncrementByteCnt; //
+wire ByteCntEq0; // ByteCnt = 0
+wire ByteCntEq1; // ByteCnt = 1
+wire ByteCntEq2; // ByteCnt = 2
+wire ByteCntEq3; // ByteCnt = 3
+wire ByteCntEq4; // ByteCnt = 4
+wire ByteCntEq5; // ByteCnt = 5
+wire ByteCntEq12; // ByteCnt = 12
+wire ByteCntEq13; // ByteCnt = 13
+wire ByteCntEq14; // ByteCnt = 14
+wire ByteCntEq15; // ByteCnt = 15
+wire ByteCntEq16; // ByteCnt = 16
+wire ByteCntEq17; // ByteCnt = 17
+wire ByteCntEq18; // ByteCnt = 18
+wire DecrementPauseTimer; //
+wire PauseTimerEq0; //
+wire ResetSlotTimer; //
+wire IncrementSlotTimer; //
+wire SlotFinished; //
+
+
+
+// Reserved multicast address and Type/Length for PAUSE control
+assign ReservedMulticast = 48'h0180C2000001;
+assign TypeLength = 16'h8808;
+
+
+// Address Detection (Multicast or unicast)
+always @ (posedge MRxClk or posedge RxReset)
+begin
+ if(RxReset)
+ AddressOK <= 1'b0;
+ else
+ if(DetectionWindow & ByteCntEq0)
+ AddressOK <= RxData[7:0] == ReservedMulticast[47:40] | RxData[7:0] == MAC[47:40];
+ else
+ if(DetectionWindow & ByteCntEq1)
+ AddressOK <= (RxData[7:0] == ReservedMulticast[39:32] | RxData[7:0] == MAC[39:32]) & AddressOK;
+ else
+ if(DetectionWindow & ByteCntEq2)
+ AddressOK <= (RxData[7:0] == ReservedMulticast[31:24] | RxData[7:0] == MAC[31:24]) & AddressOK;
+ else
+ if(DetectionWindow & ByteCntEq3)
+ AddressOK <= (RxData[7:0] == ReservedMulticast[23:16] | RxData[7:0] == MAC[23:16]) & AddressOK;
+ else
+ if(DetectionWindow & ByteCntEq4)
+ AddressOK <= (RxData[7:0] == ReservedMulticast[15:8] | RxData[7:0] == MAC[15:8]) & AddressOK;
+ else
+ if(DetectionWindow & ByteCntEq5)
+ AddressOK <= (RxData[7:0] == ReservedMulticast[7:0] | RxData[7:0] == MAC[7:0]) & AddressOK;
+ else
+ if(ReceiveEnd)
+ AddressOK <= 1'b0;
+end
+
+
+
+// TypeLengthOK (Type/Length Control frame detected)
+always @ (posedge MRxClk or posedge RxReset )
+begin
+ if(RxReset)
+ TypeLengthOK <= 1'b0;
+ else
+ if(DetectionWindow & ByteCntEq12)
+ TypeLengthOK <= ByteCntEq12 & (RxData[7:0] == TypeLength[15:8]);
+ else
+ if(DetectionWindow & ByteCntEq13)
+ TypeLengthOK <= ByteCntEq13 & (RxData[7:0] == TypeLength[7:0]) & TypeLengthOK;
+ else
+ if(ReceiveEnd)
+ TypeLengthOK <= 1'b0;
+end
+
+
+
+// Latch Control Frame Opcode
+always @ (posedge MRxClk or posedge RxReset )
+begin
+ if(RxReset)
+ OpCodeOK <= 1'b0;
+ else
+ if(ByteCntEq16)
+ OpCodeOK <= 1'b0;
+ else
+ begin
+ if(DetectionWindow & ByteCntEq14)
+ OpCodeOK <= ByteCntEq14 & RxData[7:0] == 8'h00;
+
+ if(DetectionWindow & ByteCntEq15)
+ OpCodeOK <= ByteCntEq15 & RxData[7:0] == 8'h01 & OpCodeOK;
+ end
+end
+
+
+// ReceivedPauseFrmWAddr (+Address Check)
+always @ (posedge MRxClk or posedge RxReset )
+begin
+ if(RxReset)
+ ReceivedPauseFrmWAddr <= 1'b0;
+ else
+ if(ReceiveEnd)
+ ReceivedPauseFrmWAddr <= 1'b0;
+ else
+ if(ByteCntEq16 & TypeLengthOK & OpCodeOK & AddressOK)
+ ReceivedPauseFrmWAddr <= 1'b1;
+end
+
+
+
+// Assembling 16-bit timer value from two 8-bit data
+always @ (posedge MRxClk or posedge RxReset )
+begin
+ if(RxReset)
+ AssembledTimerValue[15:0] <= 16'h0;
+ else
+ if(RxStartFrm)
+ AssembledTimerValue[15:0] <= 16'h0;
+ else
+ begin
+ if(DetectionWindow & ByteCntEq16)
+ AssembledTimerValue[15:8] <= RxData[7:0];
+ if(DetectionWindow & ByteCntEq17)
+ AssembledTimerValue[7:0] <= RxData[7:0];
+ end
+end
+
+
+// Detection window (while PAUSE detection is possible)
+always @ (posedge MRxClk or posedge RxReset )
+begin
+ if(RxReset)
+ DetectionWindow <= 1'b1;
+ else
+ if(ByteCntEq18)
+ DetectionWindow <= 1'b0;
+ else
+ if(ReceiveEnd)
+ DetectionWindow <= 1'b1;
+end
+
+
+
+// Latching Timer Value
+always @ (posedge MRxClk or posedge RxReset )
+begin
+ if(RxReset)
+ LatchedTimerValue[15:0] <= 16'h0;
+ else
+ if(DetectionWindow & ReceivedPauseFrmWAddr & ByteCntEq18)
+ LatchedTimerValue[15:0] <= AssembledTimerValue[15:0];
+ else
+ if(ReceiveEnd)
+ LatchedTimerValue[15:0] <= 16'h0;
+end
+
+
+
+// Delayed CEC counter
+always @ (posedge MRxClk or posedge RxReset)
+begin
+ if(RxReset)
+ DlyCrcCnt <= 3'h0;
+ else
+ if(RxValid & RxEndFrm)
+ DlyCrcCnt <= 3'h0;
+ else
+ if(RxValid & ~RxEndFrm & ~DlyCrcCnt[2])
+ DlyCrcCnt <= DlyCrcCnt + 1'b1;
+end
+
+
+assign ResetByteCnt = RxEndFrm;
+assign IncrementByteCnt = RxValid & DetectionWindow & ~ByteCntEq18 & (~DlyCrcEn | DlyCrcEn & DlyCrcCnt[2]);
+
+
+// Byte counter
+always @ (posedge MRxClk or posedge RxReset)
+begin
+ if(RxReset)
+ ByteCnt[4:0] <= 5'h0;
+ else
+ if(ResetByteCnt)
+ ByteCnt[4:0] <= 5'h0;
+ else
+ if(IncrementByteCnt)
+ ByteCnt[4:0] <= ByteCnt[4:0] + 1'b1;
+end
+
+
+assign ByteCntEq0 = RxValid & ByteCnt[4:0] == 5'h0;
+assign ByteCntEq1 = RxValid & ByteCnt[4:0] == 5'h1;
+assign ByteCntEq2 = RxValid & ByteCnt[4:0] == 5'h2;
+assign ByteCntEq3 = RxValid & ByteCnt[4:0] == 5'h3;
+assign ByteCntEq4 = RxValid & ByteCnt[4:0] == 5'h4;
+assign ByteCntEq5 = RxValid & ByteCnt[4:0] == 5'h5;
+assign ByteCntEq12 = RxValid & ByteCnt[4:0] == 5'h0C;
+assign ByteCntEq13 = RxValid & ByteCnt[4:0] == 5'h0D;
+assign ByteCntEq14 = RxValid & ByteCnt[4:0] == 5'h0E;
+assign ByteCntEq15 = RxValid & ByteCnt[4:0] == 5'h0F;
+assign ByteCntEq16 = RxValid & ByteCnt[4:0] == 5'h10;
+assign ByteCntEq17 = RxValid & ByteCnt[4:0] == 5'h11;
+assign ByteCntEq18 = RxValid & ByteCnt[4:0] == 5'h12 & DetectionWindow;
+
+
+assign SetPauseTimer = ReceiveEnd & ReceivedPauseFrmWAddr & ReceivedPacketGood & ReceivedLengthOK & RxFlow;
+assign DecrementPauseTimer = SlotFinished & |PauseTimer;
+
+
+// PauseTimer[15:0]
+always @ (posedge MRxClk or posedge RxReset)
+begin
+ if(RxReset)
+ PauseTimer[15:0] <= 16'h0;
+ else
+ if(SetPauseTimer)
+ PauseTimer[15:0] <= LatchedTimerValue[15:0];
+ else
+ if(DecrementPauseTimer)
+ PauseTimer[15:0] <= PauseTimer[15:0] - 1'b1;
+end
+
+assign PauseTimerEq0 = ~(|PauseTimer[15:0]);
+
+
+
+// Synchronization of the pause timer
+always @ (posedge MTxClk or posedge TxReset)
+begin
+ if(TxReset)
+ begin
+ PauseTimerEq0_sync1 <= 1'b1;
+ PauseTimerEq0_sync2 <= 1'b1;
+ end
+ else
+ begin
+ PauseTimerEq0_sync1 <= PauseTimerEq0;
+ PauseTimerEq0_sync2 <= PauseTimerEq0_sync1;
+ end
+end
+
+
+// Pause signal generation
+always @ (posedge MTxClk or posedge TxReset)
+begin
+ if(TxReset)
+ Pause <= 1'b0;
+ else
+ if((TxDoneIn | TxAbortIn | ~TxUsedDataOutDetected) & ~TxStartFrmOut)
+ Pause <= RxFlow & ~PauseTimerEq0_sync2;
+end
+
+
+// Divider2 is used for incrementing the Slot timer every other clock
+always @ (posedge MRxClk or posedge RxReset)
+begin
+ if(RxReset)
+ Divider2 <= 1'b0;
+ else
+ if(|PauseTimer[15:0] & RxFlow)
+ Divider2 <= ~Divider2;
+ else
+ Divider2 <= 1'b0;
+end
+
+
+assign ResetSlotTimer = RxReset;
+assign IncrementSlotTimer = Pause & RxFlow & Divider2;
+
+
+// SlotTimer
+always @ (posedge MRxClk or posedge RxReset)
+begin
+ if(RxReset)
+ SlotTimer[5:0] <= 6'h0;
+ else
+ if(ResetSlotTimer)
+ SlotTimer[5:0] <= 6'h0;
+ else
+ if(IncrementSlotTimer)
+ SlotTimer[5:0] <= SlotTimer[5:0] + 1'b1;
+end
+
+
+assign SlotFinished = &SlotTimer[5:0] & IncrementSlotTimer; // Slot is 512 bits (64 bytes)
+
+
+
+// Pause Frame received
+always @ (posedge MRxClk or posedge RxReset)
+begin
+ if(RxReset)
+ ReceivedPauseFrm <= 1'b0;
+ else
+ if(RxStatusWriteLatched_sync2 & r_PassAll | ReceivedPauseFrm & (~r_PassAll))
+ ReceivedPauseFrm <= 1'b0;
+ else
+ if(ByteCntEq16 & TypeLengthOK & OpCodeOK)
+ ReceivedPauseFrm <= 1'b1;
+end
+
+
+endmodule
rtl/verilog/ethmac/eth_receivecontrol.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rtl/verilog/ethmac/eth_register.v
===================================================================
--- rtl/verilog/ethmac/eth_register.v (nonexistent)
+++ rtl/verilog/ethmac/eth_register.v (revision 409)
@@ -0,0 +1,108 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// eth_register.v ////
+//// ////
+//// This file is part of the Ethernet IP core project ////
+//// http://www.opencores.org/project,ethmac ////
+//// ////
+//// Author(s): ////
+//// - Igor Mohor (igorM@opencores.org) ////
+//// ////
+//// All additional information is avaliable in the Readme.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001, 2002 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.5 2002/08/16 12:33:27 mohor
+// Parameter ResetValue changed to capital letters.
+//
+// Revision 1.4 2002/02/26 16:18:08 mohor
+// Reset values are passed to registers through parameters
+//
+// Revision 1.3 2002/01/23 10:28:16 mohor
+// Link in the header changed.
+//
+// Revision 1.2 2001/10/19 08:43:51 mohor
+// eth_timescale.v changed to timescale.v This is done because of the
+// simulation of the few cores in a one joined project.
+//
+// Revision 1.1 2001/08/06 14:44:29 mohor
+// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
+// Include files fixed to contain no path.
+// File names and module names changed ta have a eth_ prologue in the name.
+// File eth_timescale.v is used to define timescale
+// All pin names on the top module are changed to contain _I, _O or _OE at the end.
+// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
+// and Mdo_OE. The bidirectional signal must be created on the top level. This
+// is done due to the ASIC tools.
+//
+//
+//
+//
+//
+//
+//
+
+`include "timescale.v"
+
+
+module eth_register(DataIn, DataOut, Write, Clk, Reset, SyncReset);
+
+parameter WIDTH = 8; // default parameter of the register width
+parameter RESET_VALUE = 0;
+
+input [WIDTH-1:0] DataIn;
+
+input Write;
+input Clk;
+input Reset;
+input SyncReset;
+
+output [WIDTH-1:0] DataOut;
+reg [WIDTH-1:0] DataOut;
+
+
+
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ DataOut<= RESET_VALUE;
+ else
+ if(SyncReset)
+ DataOut<= RESET_VALUE;
+ else
+ if(Write) // write
+ DataOut<= DataIn;
+end
+
+
+
+endmodule // Register
rtl/verilog/ethmac/eth_register.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rtl/verilog/ethmac/eth_clockgen.v
===================================================================
--- rtl/verilog/ethmac/eth_clockgen.v (nonexistent)
+++ rtl/verilog/ethmac/eth_clockgen.v (revision 409)
@@ -0,0 +1,131 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// eth_clockgen.v ////
+//// ////
+//// This file is part of the Ethernet IP core project ////
+//// http://www.opencores.org/project,ethmac ////
+//// ////
+//// Author(s): ////
+//// - Igor Mohor (igorM@opencores.org) ////
+//// ////
+//// All additional information is avaliable in the Readme.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.3 2002/01/23 10:28:16 mohor
+// Link in the header changed.
+//
+// Revision 1.2 2001/10/19 08:43:51 mohor
+// eth_timescale.v changed to timescale.v This is done because of the
+// simulation of the few cores in a one joined project.
+//
+// Revision 1.1 2001/08/06 14:44:29 mohor
+// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
+// Include files fixed to contain no path.
+// File names and module names changed ta have a eth_ prologue in the name.
+// File eth_timescale.v is used to define timescale
+// All pin names on the top module are changed to contain _I, _O or _OE at the end.
+// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
+// and Mdo_OE. The bidirectional signal must be created on the top level. This
+// is done due to the ASIC tools.
+//
+// Revision 1.1 2001/07/30 21:23:42 mohor
+// Directory structure changed. Files checked and joind together.
+//
+// Revision 1.3 2001/06/01 22:28:55 mohor
+// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
+//
+//
+
+`include "timescale.v"
+
+module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);
+
+parameter Tp=1;
+
+input Clk; // Input clock (Host clock)
+input Reset; // Reset signal
+input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0])
+
+output Mdc; // Output clock
+output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises.
+output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
+
+reg Mdc;
+reg [7:0] Counter;
+
+wire CountEq0;
+wire [7:0] CounterPreset;
+wire [7:0] TempDivider;
+
+
+assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
+assign CounterPreset[7:0] = (TempDivider[7:0]>>1) - 1'b1; // We are counting half of period
+
+
+// Counter counts half period
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ Counter[7:0] <= 8'h1;
+ else
+ begin
+ if(CountEq0)
+ begin
+ Counter[7:0] <= CounterPreset[7:0];
+ end
+ else
+ Counter[7:0] <= Counter - 8'h1;
+ end
+end
+
+
+// Mdc is asserted every other half period
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ Mdc <= 1'b0;
+ else
+ begin
+ if(CountEq0)
+ Mdc <= ~Mdc;
+ end
+end
+
+
+assign CountEq0 = Counter == 8'h0;
+assign MdcEn = CountEq0 & ~Mdc;
+assign MdcEn_n = CountEq0 & Mdc;
+
+endmodule
+
+
rtl/verilog/ethmac/eth_clockgen.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rtl/verilog/ethmac/README
===================================================================
--- rtl/verilog/ethmac/README (nonexistent)
+++ rtl/verilog/ethmac/README (revision 409)
@@ -0,0 +1,5 @@
+10/100MBps ethernet MAC core
+
+This is based on the core from OpenCores, but heavily modified and improved to provide better bus usage, and buffer configurability.
+
+See the include file, include/ethmac_defines.v for options.
Index: rtl/verilog/ethmac/eth_miim.v
===================================================================
--- rtl/verilog/ethmac/eth_miim.v (nonexistent)
+++ rtl/verilog/ethmac/eth_miim.v (revision 409)
@@ -0,0 +1,448 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// eth_miim.v ////
+//// ////
+//// This file is part of the Ethernet IP core project ////
+//// http://www.opencores.org/project,ethmac ////
+//// ////
+//// Author(s): ////
+//// - Igor Mohor (igorM@opencores.org) ////
+//// ////
+//// All additional information is avaliable in the Readme.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.6 2005/02/21 12:48:07 igorm
+// Warning fixes.
+//
+// Revision 1.5 2003/05/16 10:08:27 mohor
+// Busy was set 2 cycles too late. Reported by Dennis Scott.
+//
+// Revision 1.4 2002/08/14 18:32:10 mohor
+// - Busy signal was not set on time when scan status operation was performed
+// and clock was divided with more than 2.
+// - Nvalid remains valid two more clocks (was previously cleared too soon).
+//
+// Revision 1.3 2002/01/23 10:28:16 mohor
+// Link in the header changed.
+//
+// Revision 1.2 2001/10/19 08:43:51 mohor
+// eth_timescale.v changed to timescale.v This is done because of the
+// simulation of the few cores in a one joined project.
+//
+// Revision 1.1 2001/08/06 14:44:29 mohor
+// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
+// Include files fixed to contain no path.
+// File names and module names changed ta have a eth_ prologue in the name.
+// File eth_timescale.v is used to define timescale
+// All pin names on the top module are changed to contain _I, _O or _OE at the end.
+// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
+// and Mdo_OE. The bidirectional signal must be created on the top level. This
+// is done due to the ASIC tools.
+//
+// Revision 1.2 2001/08/02 09:25:31 mohor
+// Unconnected signals are now connected.
+//
+// Revision 1.1 2001/07/30 21:23:42 mohor
+// Directory structure changed. Files checked and joind together.
+//
+// Revision 1.3 2001/06/01 22:28:56 mohor
+// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
+//
+//
+
+`include "timescale.v"
+
+
+module eth_miim
+(
+ Clk,
+ Reset,
+ Divider,
+ NoPre,
+ CtrlData,
+ Rgad,
+ Fiad,
+ WCtrlData,
+ RStat,
+ ScanStat,
+ Mdi,
+ Mdo,
+ MdoEn,
+ Mdc,
+ Busy,
+ Prsd,
+ LinkFail,
+ Nvalid,
+ WCtrlDataStart,
+ RStatStart,
+ UpdateMIIRX_DATAReg
+);
+
+
+
+input Clk; // Host Clock
+input Reset; // General Reset
+input [7:0] Divider; // Divider for the host clock
+input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
+input [4:0] Rgad; // Register Address (within the PHY)
+input [4:0] Fiad; // PHY Address
+input NoPre; // No Preamble (no 32-bit preamble)
+input WCtrlData; // Write Control Data operation
+input RStat; // Read Status operation
+input ScanStat; // Scan Status operation
+input Mdi; // MII Management Data In
+
+output Mdc; // MII Management Data Clock
+output Mdo; // MII Management Data Output
+output MdoEn; // MII Management Data Output Enable
+output Busy; // Busy Signal
+output LinkFail; // Link Integrity Signal
+output Nvalid; // Invalid Status (qualifier for the valid scan result)
+
+output [15:0] Prsd; // Read Status Data (data read from the PHY)
+
+output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
+output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
+output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
+
+parameter Tp = 1;
+
+
+reg Nvalid;
+reg EndBusy_d; // Pre-end Busy signal
+reg EndBusy; // End Busy signal (stops the operation in progress)
+
+reg WCtrlData_q1; // Write Control Data operation delayed 1 Clk cycle
+reg WCtrlData_q2; // Write Control Data operation delayed 2 Clk cycles
+reg WCtrlData_q3; // Write Control Data operation delayed 3 Clk cycles
+reg WCtrlDataStart; // Start Write Control Data Command (positive edge detected)
+reg WCtrlDataStart_q;
+reg WCtrlDataStart_q1; // Start Write Control Data Command delayed 1 Mdc cycle
+reg WCtrlDataStart_q2; // Start Write Control Data Command delayed 2 Mdc cycles
+
+reg RStat_q1; // Read Status operation delayed 1 Clk cycle
+reg RStat_q2; // Read Status operation delayed 2 Clk cycles
+reg RStat_q3; // Read Status operation delayed 3 Clk cycles
+reg RStatStart; // Start Read Status Command (positive edge detected)
+reg RStatStart_q1; // Start Read Status Command delayed 1 Mdc cycle
+reg RStatStart_q2; // Start Read Status Command delayed 2 Mdc cycles
+
+reg ScanStat_q1; // Scan Status operation delayed 1 cycle
+reg ScanStat_q2; // Scan Status operation delayed 2 cycles
+reg SyncStatMdcEn; // Scan Status operation delayed at least cycles and synchronized to MdcEn
+
+wire WriteDataOp; // Write Data Operation (positive edge detected)
+wire ReadStatusOp; // Read Status Operation (positive edge detected)
+wire ScanStatusOp; // Scan Status Operation (positive edge detected)
+wire StartOp; // Start Operation (start of any of the preceding operations)
+wire EndOp; // End of Operation
+
+reg InProgress; // Operation in progress
+reg InProgress_q1; // Operation in progress delayed 1 Mdc cycle
+reg InProgress_q2; // Operation in progress delayed 2 Mdc cycles
+reg InProgress_q3; // Operation in progress delayed 3 Mdc cycles
+
+reg WriteOp; // Write Operation Latch (When asserted, write operation is in progress)
+reg [6:0] BitCounter; // Bit Counter
+
+
+wire [3:0] ByteSelect; // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
+wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
+wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
+wire MdcEn_n;
+
+wire LatchByte1_d2;
+wire LatchByte0_d2;
+reg LatchByte1_d;
+reg LatchByte0_d;
+reg [1:0] LatchByte; // Latch Byte selects which part of Read Status Data is updated from the shift register
+
+reg UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
+
+
+
+
+
+// Generation of the EndBusy signal. It is used for ending the MII Management operation.
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ begin
+ EndBusy_d <= 1'b0;
+ EndBusy <= 1'b0;
+ end
+ else
+ begin
+ EndBusy_d <= ~InProgress_q2 & InProgress_q3;
+ EndBusy <= EndBusy_d;
+ end
+end
+
+
+// Update MII RX_DATA register
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ UpdateMIIRX_DATAReg <= 0;
+ else
+ if(EndBusy & ~WCtrlDataStart_q)
+ UpdateMIIRX_DATAReg <= 1;
+ else
+ UpdateMIIRX_DATAReg <= 0;
+end
+
+
+
+// Generation of the delayed signals used for positive edge triggering.
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ begin
+ WCtrlData_q1 <= 1'b0;
+ WCtrlData_q2 <= 1'b0;
+ WCtrlData_q3 <= 1'b0;
+
+ RStat_q1 <= 1'b0;
+ RStat_q2 <= 1'b0;
+ RStat_q3 <= 1'b0;
+
+ ScanStat_q1 <= 1'b0;
+ ScanStat_q2 <= 1'b0;
+ SyncStatMdcEn <= 1'b0;
+ end
+ else
+ begin
+ WCtrlData_q1 <= WCtrlData;
+ WCtrlData_q2 <= WCtrlData_q1;
+ WCtrlData_q3 <= WCtrlData_q2;
+
+ RStat_q1 <= RStat;
+ RStat_q2 <= RStat_q1;
+ RStat_q3 <= RStat_q2;
+
+ ScanStat_q1 <= ScanStat;
+ ScanStat_q2 <= ScanStat_q1;
+ if(MdcEn)
+ SyncStatMdcEn <= ScanStat_q2;
+ end
+end
+
+
+// Generation of the Start Commands (Write Control Data or Read Status)
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ begin
+ WCtrlDataStart <= 1'b0;
+ WCtrlDataStart_q <= 1'b0;
+ RStatStart <= 1'b0;
+ end
+ else
+ begin
+ if(EndBusy)
+ begin
+ WCtrlDataStart <= 1'b0;
+ RStatStart <= 1'b0;
+ end
+ else
+ begin
+ if(WCtrlData_q2 & ~WCtrlData_q3)
+ WCtrlDataStart <= 1'b1;
+ if(RStat_q2 & ~RStat_q3)
+ RStatStart <= 1'b1;
+ WCtrlDataStart_q <= WCtrlDataStart;
+ end
+ end
+end
+
+
+// Generation of the Nvalid signal (indicates when the status is invalid)
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ Nvalid <= 1'b0;
+ else
+ begin
+ if(~InProgress_q2 & InProgress_q3)
+ begin
+ Nvalid <= 1'b0;
+ end
+ else
+ begin
+ if(ScanStat_q2 & ~SyncStatMdcEn)
+ Nvalid <= 1'b1;
+ end
+ end
+end
+
+// Signals used for the generation of the Operation signals (positive edge)
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ begin
+ WCtrlDataStart_q1 <= 1'b0;
+ WCtrlDataStart_q2 <= 1'b0;
+
+ RStatStart_q1 <= 1'b0;
+ RStatStart_q2 <= 1'b0;
+
+ InProgress_q1 <= 1'b0;
+ InProgress_q2 <= 1'b0;
+ InProgress_q3 <= 1'b0;
+
+ LatchByte0_d <= 1'b0;
+ LatchByte1_d <= 1'b0;
+
+ LatchByte <= 2'b00;
+ end
+ else
+ begin
+ if(MdcEn)
+ begin
+ WCtrlDataStart_q1 <= WCtrlDataStart;
+ WCtrlDataStart_q2 <= WCtrlDataStart_q1;
+
+ RStatStart_q1 <= RStatStart;
+ RStatStart_q2 <= RStatStart_q1;
+
+ LatchByte[0] <= LatchByte0_d;
+ LatchByte[1] <= LatchByte1_d;
+
+ LatchByte0_d <= LatchByte0_d2;
+ LatchByte1_d <= LatchByte1_d2;
+
+ InProgress_q1 <= InProgress;
+ InProgress_q2 <= InProgress_q1;
+ InProgress_q3 <= InProgress_q2;
+ end
+ end
+end
+
+
+// Generation of the Operation signals
+assign WriteDataOp = WCtrlDataStart_q1 & ~WCtrlDataStart_q2;
+assign ReadStatusOp = RStatStart_q1 & ~RStatStart_q2;
+assign ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q1 & ~InProgress_q2;
+assign StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp;
+
+// Busy
+assign Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
+
+
+// Generation of the InProgress signal (indicates when an operation is in progress)
+// Generation of the WriteOp signal (indicates when a write is in progress)
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ begin
+ InProgress <= 1'b0;
+ WriteOp <= 1'b0;
+ end
+ else
+ begin
+ if(MdcEn)
+ begin
+ if(StartOp)
+ begin
+ if(~InProgress)
+ WriteOp <= WriteDataOp;
+ InProgress <= 1'b1;
+ end
+ else
+ begin
+ if(EndOp)
+ begin
+ InProgress <= 1'b0;
+ WriteOp <= 1'b0;
+ end
+ end
+ end
+ end
+end
+
+
+
+// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ BitCounter[6:0] <= 7'h0;
+ else
+ begin
+ if(MdcEn)
+ begin
+ if(InProgress)
+ begin
+ if(NoPre & ( BitCounter == 7'h0 ))
+ BitCounter[6:0] <= 7'h21;
+ else
+ BitCounter[6:0] <= BitCounter[6:0] + 1'b1;
+ end
+ else
+ BitCounter[6:0] <= 7'h0;
+ end
+ end
+end
+
+
+// Operation ends when the Bit Counter reaches 63
+assign EndOp = BitCounter==63;
+
+assign ByteSelect[0] = InProgress & ((NoPre & (BitCounter == 7'h0)) | (~NoPre & (BitCounter == 7'h20)));
+assign ByteSelect[1] = InProgress & (BitCounter == 7'h28);
+assign ByteSelect[2] = InProgress & WriteOp & (BitCounter == 7'h30);
+assign ByteSelect[3] = InProgress & WriteOp & (BitCounter == 7'h38);
+
+
+// Latch Byte selects which part of Read Status Data is updated from the shift register
+assign LatchByte1_d2 = InProgress & ~WriteOp & BitCounter == 7'h37;
+assign LatchByte0_d2 = InProgress & ~WriteOp & BitCounter == 7'h3F;
+
+
+// Connecting the Clock Generator Module
+eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc)
+ );
+
+// Connecting the Shift Register Module
+eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
+ .CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
+ .ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
+ );
+
+// Connecting the Output Control Module
+eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
+ .ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
+ .Mdo(Mdo), .MdoEn(MdoEn)
+ );
+
+endmodule
rtl/verilog/ethmac/eth_miim.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rtl/verilog/ethmac/eth_outputcontrol.v
===================================================================
--- rtl/verilog/ethmac/eth_outputcontrol.v (nonexistent)
+++ rtl/verilog/ethmac/eth_outputcontrol.v (revision 409)
@@ -0,0 +1,147 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// eth_outputcontrol.v ////
+//// ////
+//// This file is part of the Ethernet IP core project ////
+//// http://www.opencores.org/project,ethmac ////
+//// ////
+//// Author(s): ////
+//// - Igor Mohor (igorM@opencores.org) ////
+//// ////
+//// All additional information is avaliable in the Readme.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.3 2002/01/23 10:28:16 mohor
+// Link in the header changed.
+//
+// Revision 1.2 2001/10/19 08:43:51 mohor
+// eth_timescale.v changed to timescale.v This is done because of the
+// simulation of the few cores in a one joined project.
+//
+// Revision 1.1 2001/08/06 14:44:29 mohor
+// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
+// Include files fixed to contain no path.
+// File names and module names changed ta have a eth_ prologue in the name.
+// File eth_timescale.v is used to define timescale
+// All pin names on the top module are changed to contain _I, _O or _OE at the end.
+// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
+// and Mdo_OE. The bidirectional signal must be created on the top level. This
+// is done due to the ASIC tools.
+//
+// Revision 1.1 2001/07/30 21:23:42 mohor
+// Directory structure changed. Files checked and joind together.
+//
+// Revision 1.3 2001/06/01 22:28:56 mohor
+// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
+//
+//
+
+`include "timescale.v"
+
+module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn);
+
+parameter Tp = 1;
+
+input Clk; // Host Clock
+input Reset; // General Reset
+input WriteOp; // Write Operation Latch (When asserted, write operation is in progress)
+input NoPre; // No Preamble (no 32-bit preamble)
+input InProgress; // Operation in progress
+input ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
+input [6:0] BitCounter; // Bit Counter
+input MdcEn_n; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc falls.
+
+output Mdo; // MII Management Data Output
+output MdoEn; // MII Management Data Output Enable
+
+wire SerialEn;
+
+reg MdoEn_2d;
+reg MdoEn_d;
+reg MdoEn;
+
+reg Mdo_2d;
+reg Mdo_d;
+reg Mdo; // MII Management Data Output
+
+
+
+// Generation of the Serial Enable signal (enables the serialization of the data)
+assign SerialEn = WriteOp & InProgress & ( BitCounter>31 | ( ( BitCounter == 0 ) & NoPre ) )
+ | ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) | ( ( BitCounter == 0 ) & NoPre ));
+
+
+// Generation of the MdoEn signal
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ begin
+ MdoEn_2d <= 1'b0;
+ MdoEn_d <= 1'b0;
+ MdoEn <= 1'b0;
+ end
+ else
+ begin
+ if(MdcEn_n)
+ begin
+ MdoEn_2d <= SerialEn | InProgress & BitCounter<32;
+ MdoEn_d <= MdoEn_2d;
+ MdoEn <= MdoEn_d;
+ end
+ end
+end
+
+
+// Generation of the Mdo signal.
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ begin
+ Mdo_2d <= 1'b0;
+ Mdo_d <= 1'b0;
+ Mdo <= 1'b0;
+ end
+ else
+ begin
+ if(MdcEn_n)
+ begin
+ Mdo_2d <= ~SerialEn & BitCounter<32;
+ Mdo_d <= ShiftedBit | Mdo_2d;
+ Mdo <= Mdo_d;
+ end
+ end
+end
+
+
+
+endmodule
rtl/verilog/ethmac/eth_outputcontrol.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rtl/verilog/ethmac/eth_maccontrol.v
===================================================================
--- rtl/verilog/ethmac/eth_maccontrol.v (nonexistent)
+++ rtl/verilog/ethmac/eth_maccontrol.v (revision 409)
@@ -0,0 +1,271 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// eth_maccontrol.v ////
+//// ////
+//// This file is part of the Ethernet IP core project ////
+//// http://www.opencores.org/project,ethmac ////
+//// ////
+//// Author(s): ////
+//// - Igor Mohor (igorM@opencores.org) ////
+//// ////
+//// All additional information is avaliable in the Readme.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.6 2002/11/22 01:57:06 mohor
+// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
+// synchronized.
+//
+// Revision 1.5 2002/11/21 00:14:39 mohor
+// TxDone and TxAbort changed so they're not propagated to the wishbone
+// module when control frame is transmitted.
+//
+// Revision 1.4 2002/11/19 17:37:32 mohor
+// When control frame (PAUSE) was sent, status was written in the
+// eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
+// Only TXC interrupt is set.
+//
+// Revision 1.3 2002/01/23 10:28:16 mohor
+// Link in the header changed.
+//
+// Revision 1.2 2001/10/19 08:43:51 mohor
+// eth_timescale.v changed to timescale.v This is done because of the
+// simulation of the few cores in a one joined project.
+//
+// Revision 1.1 2001/08/06 14:44:29 mohor
+// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
+// Include files fixed to contain no path.
+// File names and module names changed ta have a eth_ prologue in the name.
+// File eth_timescale.v is used to define timescale
+// All pin names on the top module are changed to contain _I, _O or _OE at the end.
+// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
+// and Mdo_OE. The bidirectional signal must be created on the top level. This
+// is done due to the ASIC tools.
+//
+// Revision 1.1 2001/07/30 21:23:42 mohor
+// Directory structure changed. Files checked and joind together.
+//
+// Revision 1.1 2001/07/03 12:51:54 mohor
+// Initial release of the MAC Control module.
+//
+//
+//
+//
+
+
+`include "timescale.v"
+
+
+module eth_maccontrol (MTxClk, MRxClk, TxReset, RxReset, TPauseRq, TxDataIn, TxStartFrmIn, TxUsedDataIn,
+ TxEndFrmIn, TxDoneIn, TxAbortIn, RxData, RxValid, RxStartFrm, RxEndFrm, ReceiveEnd,
+ ReceivedPacketGood, ReceivedLengthOK, TxFlow, RxFlow, DlyCrcEn, TxPauseTV,
+ MAC, PadIn, PadOut, CrcEnIn, CrcEnOut, TxDataOut, TxStartFrmOut, TxEndFrmOut,
+ TxDoneOut, TxAbortOut, TxUsedDataOut, WillSendControlFrame, TxCtrlEndFrm,
+ ReceivedPauseFrm, ControlFrmAddressOK, SetPauseTimer, r_PassAll, RxStatusWriteLatched_sync2
+ );
+
+
+parameter Tp = 1;
+
+
+input MTxClk; // Transmit clock (from PHY)
+input MRxClk; // Receive clock (from PHY)
+input TxReset; // Transmit reset
+input RxReset; // Receive reset
+input TPauseRq; // Transmit control frame (from host)
+input [7:0] TxDataIn; // Transmit packet data byte (from host)
+input TxStartFrmIn; // Transmit packet start frame input (from host)
+input TxUsedDataIn; // Transmit packet used data (from TxEthMAC)
+input TxEndFrmIn; // Transmit packet end frame input (from host)
+input TxDoneIn; // Transmit packet done (from TxEthMAC)
+input TxAbortIn; // Transmit packet abort (input from TxEthMAC)
+input PadIn; // Padding (input from registers)
+input CrcEnIn; // Crc append (input from registers)
+input [7:0] RxData; // Receive Packet Data (from RxEthMAC)
+input RxValid; // Received a valid packet
+input RxStartFrm; // Receive packet start frame (input from RxEthMAC)
+input RxEndFrm; // Receive packet end frame (input from RxEthMAC)
+input ReceiveEnd; // End of receiving of the current packet (input from RxEthMAC)
+input ReceivedPacketGood; // Received packet is good
+input ReceivedLengthOK; // Length of the received packet is OK
+input TxFlow; // Tx flow control (from registers)
+input RxFlow; // Rx flow control (from registers)
+input DlyCrcEn; // Delayed CRC enabled (from registers)
+input [15:0] TxPauseTV; // Transmit Pause Timer Value (from registers)
+input [47:0] MAC; // MAC address (from registers)
+input RxStatusWriteLatched_sync2;
+input r_PassAll;
+
+output [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC)
+output TxStartFrmOut; // Transmit packet start frame (output to TxEthMAC)
+output TxEndFrmOut; // Transmit packet end frame (output to TxEthMAC)
+output TxDoneOut; // Transmit packet done (to host)
+output TxAbortOut; // Transmit packet aborted (to host)
+output TxUsedDataOut; // Transmit packet used data (to host)
+output PadOut; // Padding (output to TxEthMAC)
+output CrcEnOut; // Crc append (output to TxEthMAC)
+output WillSendControlFrame;
+output TxCtrlEndFrm;
+output ReceivedPauseFrm;
+output ControlFrmAddressOK;
+output SetPauseTimer;
+
+reg TxUsedDataOutDetected;
+reg TxAbortInLatched;
+reg TxDoneInLatched;
+reg MuxedDone;
+reg MuxedAbort;
+
+wire Pause;
+wire TxCtrlStartFrm;
+wire [7:0] ControlData;
+wire CtrlMux;
+wire SendingCtrlFrm; // Sending Control Frame (enables padding and CRC)
+wire BlockTxDone;
+
+
+// Signal TxUsedDataOut was detected (a transfer is already in progress)
+always @ (posedge MTxClk or posedge TxReset)
+begin
+ if(TxReset)
+ TxUsedDataOutDetected <= 1'b0;
+ else
+ if(TxDoneIn | TxAbortIn)
+ TxUsedDataOutDetected <= 1'b0;
+ else
+ if(TxUsedDataOut)
+ TxUsedDataOutDetected <= 1'b1;
+end
+
+
+// Latching variables
+always @ (posedge MTxClk or posedge TxReset)
+begin
+ if(TxReset)
+ begin
+ TxAbortInLatched <= 1'b0;
+ TxDoneInLatched <= 1'b0;
+ end
+ else
+ begin
+ TxAbortInLatched <= TxAbortIn;
+ TxDoneInLatched <= TxDoneIn;
+ end
+end
+
+
+
+// Generating muxed abort signal
+always @ (posedge MTxClk or posedge TxReset)
+begin
+ if(TxReset)
+ MuxedAbort <= 1'b0;
+ else
+ if(TxStartFrmIn)
+ MuxedAbort <= 1'b0;
+ else
+ if(TxAbortIn & ~TxAbortInLatched & TxUsedDataOutDetected)
+ MuxedAbort <= 1'b1;
+end
+
+
+// Generating muxed done signal
+always @ (posedge MTxClk or posedge TxReset)
+begin
+ if(TxReset)
+ MuxedDone <= 1'b0;
+ else
+ if(TxStartFrmIn)
+ MuxedDone <= 1'b0;
+ else
+ if(TxDoneIn & (~TxDoneInLatched) & TxUsedDataOutDetected)
+ MuxedDone <= 1'b1;
+end
+
+
+// TxDoneOut
+assign TxDoneOut = CtrlMux? ((~TxStartFrmIn) & (~BlockTxDone) & MuxedDone) :
+ ((~TxStartFrmIn) & (~BlockTxDone) & TxDoneIn);
+
+// TxAbortOut
+assign TxAbortOut = CtrlMux? ((~TxStartFrmIn) & (~BlockTxDone) & MuxedAbort) :
+ ((~TxStartFrmIn) & (~BlockTxDone) & TxAbortIn);
+
+// TxUsedDataOut
+assign TxUsedDataOut = ~CtrlMux & TxUsedDataIn;
+
+// TxStartFrmOut
+assign TxStartFrmOut = CtrlMux? TxCtrlStartFrm : (TxStartFrmIn & ~Pause);
+
+
+// TxEndFrmOut
+assign TxEndFrmOut = CtrlMux? TxCtrlEndFrm : TxEndFrmIn;
+
+
+// TxDataOut[7:0]
+assign TxDataOut[7:0] = CtrlMux? ControlData[7:0] : TxDataIn[7:0];
+
+
+// PadOut
+assign PadOut = PadIn | SendingCtrlFrm;
+
+
+// CrcEnOut
+assign CrcEnOut = CrcEnIn | SendingCtrlFrm;
+
+
+
+// Connecting receivecontrol module
+eth_receivecontrol receivecontrol1
+(
+ .MTxClk(MTxClk), .MRxClk(MRxClk), .TxReset(TxReset), .RxReset(RxReset), .RxData(RxData),
+ .RxValid(RxValid), .RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm), .RxFlow(RxFlow),
+ .ReceiveEnd(ReceiveEnd), .MAC(MAC), .DlyCrcEn(DlyCrcEn), .TxDoneIn(TxDoneIn),
+ .TxAbortIn(TxAbortIn), .TxStartFrmOut(TxStartFrmOut), .ReceivedLengthOK(ReceivedLengthOK),
+ .ReceivedPacketGood(ReceivedPacketGood), .TxUsedDataOutDetected(TxUsedDataOutDetected),
+ .Pause(Pause), .ReceivedPauseFrm(ReceivedPauseFrm), .AddressOK(ControlFrmAddressOK),
+ .r_PassAll(r_PassAll), .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2), .SetPauseTimer(SetPauseTimer)
+);
+
+
+eth_transmitcontrol transmitcontrol1
+(
+ .MTxClk(MTxClk), .TxReset(TxReset), .TxUsedDataIn(TxUsedDataIn), .TxUsedDataOut(TxUsedDataOut),
+ .TxDoneIn(TxDoneIn), .TxAbortIn(TxAbortIn), .TxStartFrmIn(TxStartFrmIn), .TPauseRq(TPauseRq),
+ .TxUsedDataOutDetected(TxUsedDataOutDetected), .TxFlow(TxFlow), .DlyCrcEn(DlyCrcEn), .TxPauseTV(TxPauseTV),
+ .MAC(MAC), .TxCtrlStartFrm(TxCtrlStartFrm), .TxCtrlEndFrm(TxCtrlEndFrm), .SendingCtrlFrm(SendingCtrlFrm),
+ .CtrlMux(CtrlMux), .ControlData(ControlData), .WillSendControlFrame(WillSendControlFrame), .BlockTxDone(BlockTxDone)
+);
+
+
+
+endmodule
rtl/verilog/ethmac/eth_maccontrol.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rtl/verilog/ethmac/ethmac.v
===================================================================
--- rtl/verilog/ethmac/ethmac.v (nonexistent)
+++ rtl/verilog/ethmac/ethmac.v (revision 409)
@@ -0,0 +1,785 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// eth.v ////
+//// ////
+//// This file is part of the Ethernet IP core project ////
+//// http://www.opencores.org/project,ethmac ////
+//// ////
+//// Author(s): ////
+//// - Igor Mohor (igorM@opencores.org) ////
+//// ////
+//// All additional information is available in the Readme.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001, 2002 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+
+
+`include "ethmac_defines.v"
+`include "timescale.v"
+
+
+module ethmac // renamed jb
+(
+ // WISHBONE common
+ wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
+
+ // WISHBONE slave
+ wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
+
+ // WISHBONE master
+ m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
+ m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
+ m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
+
+`ifdef ETH_WISHBONE_B3
+ m_wb_cti_o, m_wb_bte_o,
+`endif
+
+ //TX
+ mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
+
+ //RX
+ mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i,
+
+ // MIIM
+ mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o,
+
+ int_o
+
+ // Bist
+`ifdef ETH_BIST
+ ,
+ // debug chain signals
+ mbist_si_i, // bist scan serial in
+ mbist_so_o, // bist scan serial out
+ mbist_ctrl_i // bist chain shift control
+`endif
+
+);
+
+
+parameter Tp = 1;
+
+
+// WISHBONE common
+input wb_clk_i; // WISHBONE clock
+input wb_rst_i; // WISHBONE reset
+input [31:0] wb_dat_i; // WISHBONE data input
+output [31:0] wb_dat_o; // WISHBONE data output
+output wb_err_o; // WISHBONE error output
+
+// WISHBONE slave
+input [11:2] wb_adr_i; // WISHBONE address input
+input [3:0] wb_sel_i; // WISHBONE byte select input
+input wb_we_i; // WISHBONE write enable input
+input wb_cyc_i; // WISHBONE cycle input
+input wb_stb_i; // WISHBONE strobe input
+output wb_ack_o; // WISHBONE acknowledge output
+
+// WISHBONE master
+output [31:0] m_wb_adr_o;
+output [3:0] m_wb_sel_o;
+output m_wb_we_o;
+input [31:0] m_wb_dat_i;
+output [31:0] m_wb_dat_o;
+output m_wb_cyc_o;
+output m_wb_stb_o;
+input m_wb_ack_i;
+input m_wb_err_i;
+
+wire [29:0] m_wb_adr_tmp;
+
+`ifdef ETH_WISHBONE_B3
+output [2:0] m_wb_cti_o; // Cycle Type Identifier
+output [1:0] m_wb_bte_o; // Burst Type Extension
+`endif
+
+// Tx
+input mtx_clk_pad_i; // Transmit clock (from PHY)
+output [3:0] mtxd_pad_o; // Transmit nibble (to PHY)
+output mtxen_pad_o; // Transmit enable (to PHY)
+output mtxerr_pad_o; // Transmit error (to PHY)
+
+// Rx
+input mrx_clk_pad_i; // Receive clock (from PHY)
+input [3:0] mrxd_pad_i; // Receive nibble (from PHY)
+input mrxdv_pad_i; // Receive data valid (from PHY)
+input mrxerr_pad_i; // Receive data error (from PHY)
+
+// Common Tx and Rx
+input mcoll_pad_i; // Collision (from PHY)
+input mcrs_pad_i; // Carrier sense (from PHY)
+
+// MII Management interface
+input md_pad_i; // MII data input (from I/O cell)
+output mdc_pad_o; // MII Management data clock (to PHY)
+output md_pad_o; // MII data output (to I/O cell)
+output md_padoe_o; // MII data output enable (to I/O cell)
+
+output int_o; // Interrupt output
+
+// Bist
+`ifdef ETH_BIST
+input mbist_si_i; // bist scan serial in
+output mbist_so_o; // bist scan serial out
+input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
+`endif
+
+`ifdef WISHBONE_DEBUG
+ wire [31:0] wb_dbg_dat0;
+`endif
+
+
+wire [7:0] r_ClkDiv;
+wire r_MiiNoPre;
+wire [15:0] r_CtrlData;
+wire [4:0] r_FIAD;
+wire [4:0] r_RGAD;
+wire r_WCtrlData;
+wire r_RStat;
+wire r_ScanStat;
+wire NValid_stat;
+wire Busy_stat;
+wire LinkFail;
+wire [15:0] Prsd; // Read Status Data (data read from the PHY)
+wire WCtrlDataStart;
+wire RStatStart;
+wire UpdateMIIRX_DATAReg;
+
+wire TxStartFrm;
+wire TxEndFrm;
+wire TxUsedData;
+wire [7:0] TxData;
+wire TxRetry;
+wire TxAbort;
+wire TxUnderRun;
+wire TxDone;
+
+
+reg WillSendControlFrame_sync1;
+reg WillSendControlFrame_sync2;
+reg WillSendControlFrame_sync3;
+reg RstTxPauseRq;
+
+reg TxPauseRq_sync1;
+reg TxPauseRq_sync2;
+reg TxPauseRq_sync3;
+reg TPauseRq;
+
+
+// Connecting Miim module
+eth_miim miim1
+(
+ .Clk(wb_clk_i), .Reset(wb_rst_i), .Divider(r_ClkDiv),
+ .NoPre(r_MiiNoPre), .CtrlData(r_CtrlData), .Rgad(r_RGAD),
+ .Fiad(r_FIAD), .WCtrlData(r_WCtrlData), .RStat(r_RStat),
+ .ScanStat(r_ScanStat), .Mdi(md_pad_i), .Mdo(md_pad_o),
+ .MdoEn(md_padoe_o), .Mdc(mdc_pad_o), .Busy(Busy_stat),
+ .Prsd(Prsd), .LinkFail(LinkFail), .Nvalid(NValid_stat),
+ .WCtrlDataStart(WCtrlDataStart), .RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg)
+);
+
+
+
+
+wire [3:0] RegCs; // Connected to registers
+wire [31:0] RegDataOut; // Multiplexed to wb_dat_o
+wire r_RecSmall; // Receive small frames
+wire r_LoopBck; // Loopback
+wire r_TxEn; // Tx Enable
+wire r_RxEn; // Rx Enable
+
+wire MRxDV_Lb; // Muxed MII receive data valid
+wire MRxErr_Lb; // Muxed MII Receive Error
+wire [3:0] MRxD_Lb; // Muxed MII Receive Data
+wire Transmitting; // Indication that TxEthMAC is transmitting
+wire r_HugEn; // Huge packet enable
+wire r_DlyCrcEn; // Delayed CRC enabled
+wire [15:0] r_MaxFL; // Maximum frame length
+
+wire [15:0] r_MinFL; // Minimum frame length
+wire ShortFrame;
+wire DribbleNibble; // Extra nibble received
+wire ReceivedPacketTooBig; // Received packet is too big
+wire [47:0] r_MAC; // MAC address
+wire LoadRxStatus; // Rx status was loaded
+wire [31:0] r_HASH0; // HASH table, lower 4 bytes
+wire [31:0] r_HASH1; // HASH table, upper 4 bytes
+wire [7:0] r_TxBDNum; // Receive buffer descriptor number
+wire [6:0] r_IPGT; //
+wire [6:0] r_IPGR1; //
+wire [6:0] r_IPGR2; //
+wire [5:0] r_CollValid; //
+wire [15:0] r_TxPauseTV; // Transmit PAUSE value
+wire r_TxPauseRq; // Transmit PAUSE request
+
+wire [3:0] r_MaxRet; //
+wire r_NoBckof; //
+wire r_ExDfrEn; //
+wire r_TxFlow; // Tx flow control enable
+wire r_IFG; // Minimum interframe gap for incoming packets
+
+wire TxB_IRQ; // Interrupt Tx Buffer
+wire TxE_IRQ; // Interrupt Tx Error
+wire RxB_IRQ; // Interrupt Rx Buffer
+wire RxE_IRQ; // Interrupt Rx Error
+wire Busy_IRQ; // Interrupt Busy (lack of buffers)
+
+//wire DWord;
+wire ByteSelected;
+wire BDAck;
+wire [31:0] BD_WB_DAT_O; // wb_dat_o that comes from the Wishbone module (for buffer descriptors read/write)
+wire [3:0] BDCs; // Buffer descriptor CS
+wire CsMiss; // When access to the address between 0x800 and 0xfff occurs, acknowledge is set
+ // but data is not valid.
+wire r_Pad;
+wire r_CrcEn;
+wire r_FullD;
+wire r_Pro;
+wire r_Bro;
+wire r_NoPre;
+wire r_RxFlow;
+wire r_PassAll;
+wire TxCtrlEndFrm;
+wire StartTxDone;
+wire SetPauseTimer;
+wire TxUsedDataIn;
+wire TxDoneIn;
+wire TxAbortIn;
+wire PerPacketPad;
+wire PadOut;
+wire PerPacketCrcEn;
+wire CrcEnOut;
+wire TxStartFrmOut;
+wire TxEndFrmOut;
+wire ReceivedPauseFrm;
+wire ControlFrmAddressOK;
+wire RxStatusWriteLatched_sync2;
+wire LateCollision;
+wire DeferIndication;
+wire LateCollLatched;
+wire DeferLatched;
+wire RstDeferLatched;
+wire CarrierSenseLost;
+
+wire temp_wb_ack_o;
+wire [31:0] temp_wb_dat_o;
+wire temp_wb_err_o;
+
+`ifdef ETH_REGISTERED_OUTPUTS
+ reg temp_wb_ack_o_reg;
+ reg [31:0] temp_wb_dat_o_reg;
+ reg temp_wb_err_o_reg;
+`endif
+
+//assign DWord = &wb_sel_i;
+assign ByteSelected = |wb_sel_i;
+assign RegCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[3]; // 0x0 - 0x3FF
+assign RegCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[2]; // 0x0 - 0x3FF
+assign RegCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[1]; // 0x0 - 0x3FF
+assign RegCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[0]; // 0x0 - 0x3FF
+assign BDCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[3]; // 0x400 - 0x7FF
+assign BDCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[2]; // 0x400 - 0x7FF
+assign BDCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[1]; // 0x400 - 0x7FF
+assign BDCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[0]; // 0x400 - 0x7FF
+assign CsMiss = wb_stb_i & wb_cyc_i & ByteSelected & wb_adr_i[11]; // 0x800 - 0xfFF
+assign temp_wb_dat_o = ((|RegCs) & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
+assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~ByteSelected | CsMiss);
+
+`ifdef ETH_REGISTERED_OUTPUTS
+ assign wb_ack_o = temp_wb_ack_o_reg;
+ assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
+ assign wb_err_o = temp_wb_err_o_reg;
+`else
+ assign wb_ack_o = temp_wb_ack_o;
+ assign wb_dat_o[31:0] = temp_wb_dat_o;
+ assign wb_err_o = temp_wb_err_o;
+`endif
+
+`ifdef ETH_AVALON_BUS
+ // As Avalon has no corresponding "error" signal, I (erroneously) will
+ // send an ack to Avalon, even when accessing undefined memory. This
+ // is a grey area in Avalon vs. Wishbone specs: My understanding
+ // is that Avalon expects all memory addressable by the addr bus feeding
+ // a slave to be, at the very minimum, readable.
+ assign temp_wb_ack_o = (|RegCs) | BDAck | CsMiss;
+`else // WISHBONE
+ assign temp_wb_ack_o = (|RegCs) | BDAck;
+`endif
+
+`ifdef ETH_REGISTERED_OUTPUTS
+ always @ (posedge wb_clk_i or posedge wb_rst_i)
+ begin
+ if(wb_rst_i)
+ begin
+ temp_wb_ack_o_reg <= 1'b0;
+ temp_wb_dat_o_reg <= 32'h0;
+ temp_wb_err_o_reg <= 1'b0;
+ end
+ else
+ begin
+ temp_wb_ack_o_reg <= temp_wb_ack_o & ~temp_wb_ack_o_reg;
+ temp_wb_dat_o_reg <= temp_wb_dat_o;
+ temp_wb_err_o_reg <= temp_wb_err_o & ~temp_wb_err_o_reg;
+ end
+ end
+`endif
+
+
+// Connecting Ethernet registers
+eth_registers ethreg1
+(
+ .DataIn(wb_dat_i), .Address(wb_adr_i[9:2]), .Rw(wb_we_i),
+ .Cs(RegCs), .Clk(wb_clk_i), .Reset(wb_rst_i),
+ .DataOut(RegDataOut), .r_RecSmall(r_RecSmall),
+ .r_Pad(r_Pad), .r_HugEn(r_HugEn), .r_CrcEn(r_CrcEn),
+ .r_DlyCrcEn(r_DlyCrcEn), .r_FullD(r_FullD),
+ .r_ExDfrEn(r_ExDfrEn), .r_NoBckof(r_NoBckof), .r_LoopBck(r_LoopBck),
+ .r_IFG(r_IFG), .r_Pro(r_Pro), .r_Iam(),
+ .r_Bro(r_Bro), .r_NoPre(r_NoPre), .r_TxEn(r_TxEn),
+ .r_RxEn(r_RxEn), .Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ),
+ .RxB_IRQ(RxB_IRQ), .TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
+ .r_IPGT(r_IPGT),
+ .r_IPGR1(r_IPGR1), .r_IPGR2(r_IPGR2), .r_MinFL(r_MinFL),
+ .r_MaxFL(r_MaxFL), .r_MaxRet(r_MaxRet), .r_CollValid(r_CollValid),
+ .r_TxFlow(r_TxFlow), .r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll),
+ .r_MiiNoPre(r_MiiNoPre), .r_ClkDiv(r_ClkDiv),
+ .r_WCtrlData(r_WCtrlData), .r_RStat(r_RStat), .r_ScanStat(r_ScanStat),
+ .r_RGAD(r_RGAD), .r_FIAD(r_FIAD), .r_CtrlData(r_CtrlData),
+ .NValid_stat(NValid_stat), .Busy_stat(Busy_stat),
+ .LinkFail(LinkFail), .r_MAC(r_MAC), .WCtrlDataStart(WCtrlDataStart),
+ .RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg), .Prsd(Prsd),
+ .r_TxBDNum(r_TxBDNum), .int_o(int_o),
+ .r_HASH0(r_HASH0), .r_HASH1(r_HASH1), .r_TxPauseRq(r_TxPauseRq),
+ .r_TxPauseTV(r_TxPauseTV), .RstTxPauseRq(RstTxPauseRq), .TxCtrlEndFrm(TxCtrlEndFrm),
+ .StartTxDone(StartTxDone), .TxClk(mtx_clk_pad_i), .RxClk(mrx_clk_pad_i),
+ .dbg_dat(wb_dbg_dat0),
+ .SetPauseTimer(SetPauseTimer)
+
+);
+
+
+
+wire [7:0] RxData;
+wire RxValid;
+wire RxStartFrm;
+wire RxEndFrm;
+wire RxAbort;
+
+wire WillTransmit; // Will transmit (to RxEthMAC)
+wire ResetCollision; // Reset Collision (for synchronizing collision)
+wire [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC)
+wire WillSendControlFrame;
+wire ReceiveEnd;
+wire ReceivedPacketGood;
+wire ReceivedLengthOK;
+wire InvalidSymbol;
+wire LatchedCrcError;
+wire RxLateCollision;
+wire [3:0] RetryCntLatched;
+wire [3:0] RetryCnt;
+wire StartTxAbort;
+wire MaxCollisionOccured;
+wire RetryLimit;
+wire StatePreamble;
+wire [1:0] StateData;
+
+// Connecting MACControl
+eth_maccontrol maccontrol1
+(
+ .MTxClk(mtx_clk_pad_i), .TPauseRq(TPauseRq),
+ .TxPauseTV(r_TxPauseTV), .TxDataIn(TxData),
+ .TxStartFrmIn(TxStartFrm), .TxEndFrmIn(TxEndFrm),
+ .TxUsedDataIn(TxUsedDataIn), .TxDoneIn(TxDoneIn),
+ .TxAbortIn(TxAbortIn), .MRxClk(mrx_clk_pad_i),
+ .RxData(RxData), .RxValid(RxValid),
+ .RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
+ .ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood),
+ .TxFlow(r_TxFlow),
+ .RxFlow(r_RxFlow), .DlyCrcEn(r_DlyCrcEn),
+ .MAC(r_MAC), .PadIn(r_Pad | PerPacketPad),
+ .PadOut(PadOut), .CrcEnIn(r_CrcEn | PerPacketCrcEn),
+ .CrcEnOut(CrcEnOut), .TxReset(wb_rst_i),
+ .RxReset(wb_rst_i), .ReceivedLengthOK(ReceivedLengthOK),
+ .TxDataOut(TxDataOut), .TxStartFrmOut(TxStartFrmOut),
+ .TxEndFrmOut(TxEndFrmOut), .TxUsedDataOut(TxUsedData),
+ .TxDoneOut(TxDone), .TxAbortOut(TxAbort),
+ .WillSendControlFrame(WillSendControlFrame), .TxCtrlEndFrm(TxCtrlEndFrm),
+ .ReceivedPauseFrm(ReceivedPauseFrm), .ControlFrmAddressOK(ControlFrmAddressOK),
+ .SetPauseTimer(SetPauseTimer),
+ .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2), .r_PassAll(r_PassAll)
+);
+
+
+
+wire TxCarrierSense; // Synchronized CarrierSense (to Tx clock)
+wire Collision; // Synchronized Collision
+
+reg CarrierSense_Tx1;
+reg CarrierSense_Tx2;
+reg Collision_Tx1;
+reg Collision_Tx2;
+
+reg RxEnSync; // Synchronized Receive Enable
+reg WillTransmit_q;
+reg WillTransmit_q2;
+
+
+
+// Muxed MII receive data valid
+assign MRxDV_Lb = r_LoopBck? mtxen_pad_o : mrxdv_pad_i & RxEnSync;
+
+// Muxed MII Receive Error
+assign MRxErr_Lb = r_LoopBck? mtxerr_pad_o : mrxerr_pad_i & RxEnSync;
+
+// Muxed MII Receive Data
+assign MRxD_Lb[3:0] = r_LoopBck? mtxd_pad_o[3:0] : mrxd_pad_i[3:0];
+
+
+
+// Connecting TxEthMAC
+eth_txethmac txethmac1
+(
+ .MTxClk(mtx_clk_pad_i), .Reset(wb_rst_i), .CarrierSense(TxCarrierSense),
+ .Collision(Collision), .TxData(TxDataOut), .TxStartFrm(TxStartFrmOut),
+ .TxUnderRun(TxUnderRun), .TxEndFrm(TxEndFrmOut), .Pad(PadOut),
+ .MinFL(r_MinFL), .CrcEn(CrcEnOut), .FullD(r_FullD),
+ .HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn), .IPGT(r_IPGT),
+ .IPGR1(r_IPGR1), .IPGR2(r_IPGR2), .CollValid(r_CollValid),
+ .MaxRet(r_MaxRet), .NoBckof(r_NoBckof), .ExDfrEn(r_ExDfrEn),
+ .MaxFL(r_MaxFL), .MTxEn(mtxen_pad_o), .MTxD(mtxd_pad_o),
+ .MTxErr(mtxerr_pad_o), .TxUsedData(TxUsedDataIn), .TxDone(TxDoneIn),
+ .TxRetry(TxRetry), .TxAbort(TxAbortIn), .WillTransmit(WillTransmit),
+ .ResetCollision(ResetCollision), .RetryCnt(RetryCnt), .StartTxDone(StartTxDone),
+ .StartTxAbort(StartTxAbort), .MaxCollisionOccured(MaxCollisionOccured), .LateCollision(LateCollision),
+ .DeferIndication(DeferIndication), .StatePreamble(StatePreamble), .StateData(StateData)
+);
+
+
+
+
+wire [15:0] RxByteCnt;
+wire RxByteCntEq0;
+wire RxByteCntGreat2;
+wire RxByteCntMaxFrame;
+wire RxCrcError;
+wire RxStateIdle;
+wire RxStatePreamble;
+wire RxStateSFD;
+wire [1:0] RxStateData;
+wire AddressMiss;
+
+
+
+// Connecting RxEthMAC
+eth_rxethmac rxethmac1
+(
+ .MRxClk(mrx_clk_pad_i), .MRxDV(MRxDV_Lb), .MRxD(MRxD_Lb),
+ .Transmitting(Transmitting), .HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn),
+ .MaxFL(r_MaxFL), .r_IFG(r_IFG), .Reset(wb_rst_i),
+ .RxData(RxData), .RxValid(RxValid), .RxStartFrm(RxStartFrm),
+ .RxEndFrm(RxEndFrm), .ByteCnt(RxByteCnt),
+ .ByteCntEq0(RxByteCntEq0), .ByteCntGreat2(RxByteCntGreat2), .ByteCntMaxFrame(RxByteCntMaxFrame),
+ .CrcError(RxCrcError), .StateIdle(RxStateIdle), .StatePreamble(RxStatePreamble),
+ .StateSFD(RxStateSFD), .StateData(RxStateData),
+ .MAC(r_MAC), .r_Pro(r_Pro), .r_Bro(r_Bro),
+ .r_HASH0(r_HASH0), .r_HASH1(r_HASH1), .RxAbort(RxAbort),
+ .AddressMiss(AddressMiss), .PassAll(r_PassAll), .ControlFrmAddressOK(ControlFrmAddressOK)
+);
+
+
+// MII Carrier Sense Synchronization
+always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ begin
+ CarrierSense_Tx1 <= 1'b0;
+ CarrierSense_Tx2 <= 1'b0;
+ end
+ else
+ begin
+ CarrierSense_Tx1 <= mcrs_pad_i;
+ CarrierSense_Tx2 <= CarrierSense_Tx1;
+ end
+end
+
+assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2;
+
+
+// MII Collision Synchronization
+always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ begin
+ Collision_Tx1 <= 1'b0;
+ Collision_Tx2 <= 1'b0;
+ end
+ else
+ begin
+ Collision_Tx1 <= mcoll_pad_i;
+ if(ResetCollision)
+ Collision_Tx2 <= 1'b0;
+ else
+ if(Collision_Tx1)
+ Collision_Tx2 <= 1'b1;
+ end
+end
+
+
+// Synchronized Collision
+assign Collision = ~r_FullD & Collision_Tx2;
+
+
+
+// Delayed WillTransmit
+always @ (posedge mrx_clk_pad_i)
+begin
+ WillTransmit_q <= WillTransmit;
+ WillTransmit_q2 <= WillTransmit_q;
+end
+
+
+assign Transmitting = ~r_FullD & WillTransmit_q2;
+
+
+
+// Synchronized Receive Enable
+always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ RxEnSync <= 1'b0;
+ else
+ if(~mrxdv_pad_i)
+ RxEnSync <= r_RxEn;
+end
+
+
+
+// Synchronizing WillSendControlFrame to WB_CLK;
+always @ (posedge wb_clk_i or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ WillSendControlFrame_sync1 <= 1'b0;
+ else
+ WillSendControlFrame_sync1 <= WillSendControlFrame;
+end
+
+always @ (posedge wb_clk_i or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ WillSendControlFrame_sync2 <= 1'b0;
+ else
+ WillSendControlFrame_sync2 <= WillSendControlFrame_sync1;
+end
+
+always @ (posedge wb_clk_i or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ WillSendControlFrame_sync3 <= 1'b0;
+ else
+ WillSendControlFrame_sync3 <= WillSendControlFrame_sync2;
+end
+
+always @ (posedge wb_clk_i or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ RstTxPauseRq <= 1'b0;
+ else
+ RstTxPauseRq <= WillSendControlFrame_sync2 & ~WillSendControlFrame_sync3;
+end
+
+
+
+
+// TX Pause request Synchronization
+always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ begin
+ TxPauseRq_sync1 <= 1'b0;
+ TxPauseRq_sync2 <= 1'b0;
+ TxPauseRq_sync3 <= 1'b0;
+ end
+ else
+ begin
+ TxPauseRq_sync1 <= (r_TxPauseRq & r_TxFlow);
+ TxPauseRq_sync2 <= TxPauseRq_sync1;
+ TxPauseRq_sync3 <= TxPauseRq_sync2;
+ end
+end
+
+
+always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ TPauseRq <= 1'b0;
+ else
+ TPauseRq <= TxPauseRq_sync2 & (~TxPauseRq_sync3);
+end
+
+
+wire LatchedMRxErr;
+reg RxAbort_latch;
+reg RxAbort_sync1;
+reg RxAbort_wb;
+reg RxAbortRst_sync1;
+reg RxAbortRst;
+
+// Synchronizing RxAbort to the WISHBONE clock
+always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ RxAbort_latch <= 1'b0;
+ else if(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr & ~InvalidSymbol | (ReceivedPauseFrm & (~r_PassAll)))
+ RxAbort_latch <= 1'b1;
+ else if(RxAbortRst)
+ RxAbort_latch <= 1'b0;
+end
+
+always @ (posedge wb_clk_i or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ begin
+ RxAbort_sync1 <= 1'b0;
+ RxAbort_wb <= 1'b0;
+ RxAbort_wb <= 1'b0;
+ end
+ else
+ begin
+ RxAbort_sync1 <= RxAbort_latch;
+ RxAbort_wb <= RxAbort_sync1;
+ end
+end
+
+always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ begin
+ RxAbortRst_sync1 <= 1'b0;
+ RxAbortRst <= 1'b0;
+ end
+ else
+ begin
+ RxAbortRst_sync1 <= RxAbort_wb;
+ RxAbortRst <= RxAbortRst_sync1;
+ end
+end
+
+
+
+// Connecting Wishbone module
+eth_wishbone wishbone
+(
+ .WB_CLK_I(wb_clk_i), .WB_DAT_I(wb_dat_i),
+ .WB_DAT_O(BD_WB_DAT_O),
+
+ // WISHBONE slave
+ .WB_ADR_I(wb_adr_i[9:2]), .WB_WE_I(wb_we_i),
+ .BDCs(BDCs), .WB_ACK_O(BDAck),
+
+ .Reset(wb_rst_i),
+
+ // WISHBONE master
+ .m_wb_adr_o(m_wb_adr_tmp), .m_wb_sel_o(m_wb_sel_o), .m_wb_we_o(m_wb_we_o),
+ .m_wb_dat_i(m_wb_dat_i), .m_wb_dat_o(m_wb_dat_o), .m_wb_cyc_o(m_wb_cyc_o),
+ .m_wb_stb_o(m_wb_stb_o), .m_wb_ack_i(m_wb_ack_i), .m_wb_err_i(m_wb_err_i),
+
+`ifdef ETH_WISHBONE_B3
+ .m_wb_cti_o(m_wb_cti_o), .m_wb_bte_o(m_wb_bte_o),
+`endif
+
+
+ //TX
+ .MTxClk(mtx_clk_pad_i), .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm),
+ .TxUsedData(TxUsedData), .TxData(TxData),
+ .TxRetry(TxRetry), .TxAbort(TxAbort), .TxUnderRun(TxUnderRun),
+ .TxDone(TxDone),
+ .PerPacketCrcEn(PerPacketCrcEn), .PerPacketPad(PerPacketPad),
+
+ // Register
+ .r_TxEn(r_TxEn), .r_RxEn(r_RxEn), .r_TxBDNum(r_TxBDNum),
+ .r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll),
+
+ //RX
+ .MRxClk(mrx_clk_pad_i), .RxData(RxData), .RxValid(RxValid),
+ .RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
+ .Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ), .RxB_IRQ(RxB_IRQ),
+ .TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
+
+ .RxAbort(RxAbort_wb), .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2),
+
+ .InvalidSymbol(InvalidSymbol), .LatchedCrcError(LatchedCrcError), .RxLength(RxByteCnt),
+ .RxLateCollision(RxLateCollision), .ShortFrame(ShortFrame), .DribbleNibble(DribbleNibble),
+ .ReceivedPacketTooBig(ReceivedPacketTooBig), .LoadRxStatus(LoadRxStatus), .RetryCntLatched(RetryCntLatched),
+ .RetryLimit(RetryLimit), .LateCollLatched(LateCollLatched), .DeferLatched(DeferLatched),
+ .RstDeferLatched(RstDeferLatched),
+ .CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood), .AddressMiss(AddressMiss),
+ .ReceivedPauseFrm(ReceivedPauseFrm)
+
+`ifdef ETH_BIST
+ ,
+ .mbist_si_i (mbist_si_i),
+ .mbist_so_o (mbist_so_o),
+ .mbist_ctrl_i (mbist_ctrl_i)
+`endif
+ `ifdef WISHBONE_DEBUG
+ ,
+ .dbg_dat0(wb_dbg_dat0)
+`endif
+
+);
+
+assign m_wb_adr_o = {m_wb_adr_tmp, 2'h0};
+
+// Connecting MacStatus module
+eth_macstatus macstatus1
+(
+ .MRxClk(mrx_clk_pad_i), .Reset(wb_rst_i),
+ .ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood), .ReceivedLengthOK(ReceivedLengthOK),
+ .RxCrcError(RxCrcError), .MRxErr(MRxErr_Lb), .MRxDV(MRxDV_Lb),
+ .RxStateSFD(RxStateSFD), .RxStateData(RxStateData), .RxStatePreamble(RxStatePreamble),
+ .RxStateIdle(RxStateIdle), .Transmitting(Transmitting), .RxByteCnt(RxByteCnt),
+ .RxByteCntEq0(RxByteCntEq0), .RxByteCntGreat2(RxByteCntGreat2), .RxByteCntMaxFrame(RxByteCntMaxFrame),
+ .InvalidSymbol(InvalidSymbol),
+ .MRxD(MRxD_Lb), .LatchedCrcError(LatchedCrcError), .Collision(mcoll_pad_i),
+ .CollValid(r_CollValid), .RxLateCollision(RxLateCollision), .r_RecSmall(r_RecSmall),
+ .r_MinFL(r_MinFL), .r_MaxFL(r_MaxFL), .ShortFrame(ShortFrame),
+ .DribbleNibble(DribbleNibble), .ReceivedPacketTooBig(ReceivedPacketTooBig), .r_HugEn(r_HugEn),
+ .LoadRxStatus(LoadRxStatus), .RetryCnt(RetryCnt), .StartTxDone(StartTxDone),
+ .StartTxAbort(StartTxAbort), .RetryCntLatched(RetryCntLatched), .MTxClk(mtx_clk_pad_i),
+ .MaxCollisionOccured(MaxCollisionOccured), .RetryLimit(RetryLimit), .LateCollision(LateCollision),
+ .LateCollLatched(LateCollLatched), .DeferIndication(DeferIndication), .DeferLatched(DeferLatched),
+ .RstDeferLatched(RstDeferLatched),
+ .TxStartFrm(TxStartFrmOut), .StatePreamble(StatePreamble), .StateData(StateData),
+ .CarrierSense(CarrierSense_Tx2), .CarrierSenseLost(CarrierSenseLost), .TxUsedData(TxUsedDataIn),
+ .LatchedMRxErr(LatchedMRxErr), .Loopback(r_LoopBck), .r_FullD(r_FullD)
+);
+
+
+endmodule
Index: rtl/verilog/ethmac/eth_top.v
===================================================================
--- rtl/verilog/ethmac/eth_top.v (nonexistent)
+++ rtl/verilog/ethmac/eth_top.v (revision 409)
@@ -0,0 +1,971 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// eth_top.v ////
+//// ////
+//// This file is part of the Ethernet IP core project ////
+//// http://www.opencores.org/project,ethmac ////
+//// ////
+//// Author(s): ////
+//// - Igor Mohor (igorM@opencores.org) ////
+//// ////
+//// All additional information is available in the Readme.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001, 2002 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: eth_top.v,v $
+// Revision 1.52 2005/03/21 20:07:18 igorm
+// Some small fixes + some troubles fixed.
+//
+// Revision 1.51 2005/02/21 11:13:17 igorm
+// Defer indication fixed.
+//
+// Revision 1.50 2004/04/26 15:26:23 igorm
+// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
+// previous update of the core.
+// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
+// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
+// register. (thanks to Mathias and Torbjorn)
+// - Multicast reception was fixed. Thanks to Ulrich Gries
+//
+// Revision 1.49 2003/11/12 18:24:59 tadejm
+// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
+//
+// Revision 1.48 2003/10/17 07:46:16 markom
+// mbist signals updated according to newest convention
+//
+// Revision 1.47 2003/10/06 15:43:45 knguyen
+// Update RxEnSync only when mrxdv_pad_i is inactive (LOW).
+//
+// Revision 1.46 2003/01/30 13:30:22 tadejm
+// Defer indication changed.
+//
+// Revision 1.45 2003/01/22 13:49:26 tadejm
+// When control packets were received, they were ignored in some cases.
+//
+// Revision 1.44 2003/01/21 12:09:40 mohor
+// When receiving normal data frame and RxFlow control was switched on, RXB
+// interrupt was not set.
+//
+// Revision 1.43 2002/11/22 01:57:06 mohor
+// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
+// synchronized.
+//
+// Revision 1.42 2002/11/21 00:09:19 mohor
+// TPauseRq synchronized to tx_clk.
+//
+// Revision 1.41 2002/11/19 18:13:49 mohor
+// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
+//
+// Revision 1.40 2002/11/19 17:34:25 mohor
+// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
+// that a frame was received because of the promiscous mode.
+//
+// Revision 1.39 2002/11/18 17:31:55 mohor
+// wb_rst_i is used for MIIM reset.
+//
+// Revision 1.38 2002/11/14 18:37:20 mohor
+// r_Rst signal does not reset any module any more and is removed from the design.
+//
+// Revision 1.37 2002/11/13 22:25:36 tadejm
+// All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.
+//
+// Revision 1.36 2002/10/18 17:04:20 tadejm
+// Changed BIST scan signals.
+//
+// Revision 1.35 2002/10/11 13:36:58 mohor
+// Typo error fixed. (When using Bist)
+//
+// Revision 1.34 2002/10/10 16:49:50 mohor
+// Signals for WISHBONE B3 compliant interface added.
+//
+// Revision 1.33 2002/10/10 16:29:30 mohor
+// BIST added.
+//
+// Revision 1.32 2002/09/20 17:12:58 mohor
+// CsMiss added. When address between 0x800 and 0xfff is accessed within
+// Ethernet Core, error acknowledge is generated.
+//
+// Revision 1.31 2002/09/12 14:50:17 mohor
+// CarrierSenseLost bug fixed when operating in full duplex mode.
+//
+// Revision 1.30 2002/09/10 10:35:23 mohor
+// Ethernet debug registers removed.
+//
+// Revision 1.29 2002/09/09 13:03:13 mohor
+// Error acknowledge is generated when accessing BDs and RST bit in the
+// MODER register (r_Rst) is set.
+//
+// Revision 1.28 2002/09/04 18:44:10 mohor
+// Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
+// connected.
+//
+// Revision 1.27 2002/07/25 18:15:37 mohor
+// RxAbort changed. Packets received with MRxErr (from PHY) are also
+// aborted.
+//
+// Revision 1.26 2002/07/17 18:51:50 mohor
+// EXTERNAL_DMA removed. External DMA not supported.
+//
+// Revision 1.25 2002/05/03 10:15:50 mohor
+// Outputs registered. Reset changed for eth_wishbone module.
+//
+// Revision 1.24 2002/04/22 14:15:42 mohor
+// Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
+// selected in ethmac_defines.v
+//
+// Revision 1.23 2002/03/25 13:33:53 mohor
+// md_padoen_o changed to md_padoe_o. Signal was always active high, just
+// name was incorrect.
+//
+// Revision 1.22 2002/02/26 16:59:54 mohor
+// Small fixes for external/internal DMA missmatches.
+//
+// Revision 1.21 2002/02/26 16:21:00 mohor
+// Interrupts changed in the top file
+//
+// Revision 1.20 2002/02/18 10:40:17 mohor
+// Small fixes.
+//
+// Revision 1.19 2002/02/16 14:03:44 mohor
+// Registered trimmed. Unused registers removed.
+//
+// Revision 1.18 2002/02/16 13:06:33 mohor
+// EXTERNAL_DMA used instead of WISHBONE_DMA.
+//
+// Revision 1.17 2002/02/16 07:15:27 mohor
+// Testbench fixed, code simplified, unused signals removed.
+//
+// Revision 1.16 2002/02/15 13:49:39 mohor
+// RxAbort is connected differently.
+//
+// Revision 1.15 2002/02/15 11:38:26 mohor
+// Changes that were lost when updating from 1.11 to 1.14 fixed.
+//
+// Revision 1.14 2002/02/14 20:19:11 billditt
+// Modified for Address Checking,
+// addition of eth_addrcheck.v
+//
+// Revision 1.13 2002/02/12 17:03:03 mohor
+// HASH0 and HASH1 registers added. Registers address width was
+// changed to 8 bits.
+//
+// Revision 1.12 2002/02/11 09:18:22 mohor
+// Tx status is written back to the BD.
+//
+// Revision 1.11 2002/02/08 16:21:54 mohor
+// Rx status is written back to the BD.
+//
+// Revision 1.10 2002/02/06 14:10:21 mohor
+// non-DMA host interface added. Select the right configutation in eth_defines.
+//
+// Revision 1.9 2002/01/23 10:28:16 mohor
+// Link in the header changed.
+//
+// Revision 1.8 2001/12/05 15:00:16 mohor
+// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
+// instead of the number of RX descriptors).
+//
+// Revision 1.7 2001/12/05 10:45:59 mohor
+// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
+//
+// Revision 1.6 2001/10/19 11:24:29 mohor
+// Number of addresses (wb_adr_i) minimized.
+//
+// Revision 1.5 2001/10/19 08:43:51 mohor
+// eth_timescale.v changed to timescale.v This is done because of the
+// simulation of the few cores in a one joined project.
+//
+// Revision 1.4 2001/10/18 12:07:11 mohor
+// Status signals changed, Adress decoding changed, interrupt controller
+// added.
+//
+// Revision 1.3 2001/09/24 15:02:56 mohor
+// Defines changed (All precede with ETH_). Small changes because some
+// tools generate warnings when two operands are together. Synchronization
+// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
+// demands).
+//
+// Revision 1.2 2001/08/15 14:03:59 mohor
+// Signal names changed on the top level for easier pad insertion (ASIC).
+//
+// Revision 1.1 2001/08/06 14:44:29 mohor
+// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
+// Include files fixed to contain no path.
+// File names and module names changed ta have a eth_ prologue in the name.
+// File eth_timescale.v is used to define timescale
+// All pin names on the top module are changed to contain _I, _O or _OE at the end.
+// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
+// and Mdo_OE. The bidirectional signal must be created on the top level. This
+// is done due to the ASIC tools.
+//
+// Revision 1.2 2001/08/02 09:25:31 mohor
+// Unconnected signals are now connected.
+//
+// Revision 1.1 2001/07/30 21:23:42 mohor
+// Directory structure changed. Files checked and joind together.
+//
+//
+//
+//
+
+
+`include "ethmac_defines.v"
+`include "timescale.v"
+
+
+module eth_top
+(
+ // WISHBONE common
+ wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
+
+ // WISHBONE slave
+ wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
+
+ // WISHBONE master
+ m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
+ m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
+ m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
+
+`ifdef ETH_WISHBONE_B3
+ m_wb_cti_o, m_wb_bte_o,
+`endif
+
+ //TX
+ mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
+
+ //RX
+ mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i,
+
+ // MIIM
+ mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o,
+
+ int_o
+
+ // Bist
+`ifdef ETH_BIST
+ ,
+ // debug chain signals
+ mbist_si_i, // bist scan serial in
+ mbist_so_o, // bist scan serial out
+ mbist_ctrl_i // bist chain shift control
+`endif
+
+);
+
+
+parameter Tp = 1;
+
+
+// WISHBONE common
+input wb_clk_i; // WISHBONE clock
+input wb_rst_i; // WISHBONE reset
+input [31:0] wb_dat_i; // WISHBONE data input
+output [31:0] wb_dat_o; // WISHBONE data output
+output wb_err_o; // WISHBONE error output
+
+// WISHBONE slave
+input [11:2] wb_adr_i; // WISHBONE address input
+input [3:0] wb_sel_i; // WISHBONE byte select input
+input wb_we_i; // WISHBONE write enable input
+input wb_cyc_i; // WISHBONE cycle input
+input wb_stb_i; // WISHBONE strobe input
+output wb_ack_o; // WISHBONE acknowledge output
+
+// WISHBONE master
+output [31:0] m_wb_adr_o;
+output [3:0] m_wb_sel_o;
+output m_wb_we_o;
+input [31:0] m_wb_dat_i;
+output [31:0] m_wb_dat_o;
+output m_wb_cyc_o;
+output m_wb_stb_o;
+input m_wb_ack_i;
+input m_wb_err_i;
+
+wire [29:0] m_wb_adr_tmp;
+
+`ifdef ETH_WISHBONE_B3
+output [2:0] m_wb_cti_o; // Cycle Type Identifier
+output [1:0] m_wb_bte_o; // Burst Type Extension
+`endif
+
+// Tx
+input mtx_clk_pad_i; // Transmit clock (from PHY)
+output [3:0] mtxd_pad_o; // Transmit nibble (to PHY)
+output mtxen_pad_o; // Transmit enable (to PHY)
+output mtxerr_pad_o; // Transmit error (to PHY)
+
+// Rx
+input mrx_clk_pad_i; // Receive clock (from PHY)
+input [3:0] mrxd_pad_i; // Receive nibble (from PHY)
+input mrxdv_pad_i; // Receive data valid (from PHY)
+input mrxerr_pad_i; // Receive data error (from PHY)
+
+// Common Tx and Rx
+input mcoll_pad_i; // Collision (from PHY)
+input mcrs_pad_i; // Carrier sense (from PHY)
+
+// MII Management interface
+input md_pad_i; // MII data input (from I/O cell)
+output mdc_pad_o; // MII Management data clock (to PHY)
+output md_pad_o; // MII data output (to I/O cell)
+output md_padoe_o; // MII data output enable (to I/O cell)
+
+output int_o; // Interrupt output
+
+// Bist
+`ifdef ETH_BIST
+input mbist_si_i; // bist scan serial in
+output mbist_so_o; // bist scan serial out
+input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
+`endif
+
+wire [7:0] r_ClkDiv;
+wire r_MiiNoPre;
+wire [15:0] r_CtrlData;
+wire [4:0] r_FIAD;
+wire [4:0] r_RGAD;
+wire r_WCtrlData;
+wire r_RStat;
+wire r_ScanStat;
+wire NValid_stat;
+wire Busy_stat;
+wire LinkFail;
+wire [15:0] Prsd; // Read Status Data (data read from the PHY)
+wire WCtrlDataStart;
+wire RStatStart;
+wire UpdateMIIRX_DATAReg;
+
+wire TxStartFrm;
+wire TxEndFrm;
+wire TxUsedData;
+wire [7:0] TxData;
+wire TxRetry;
+wire TxAbort;
+wire TxUnderRun;
+wire TxDone;
+
+
+reg WillSendControlFrame_sync1;
+reg WillSendControlFrame_sync2;
+reg WillSendControlFrame_sync3;
+reg RstTxPauseRq;
+
+reg TxPauseRq_sync1;
+reg TxPauseRq_sync2;
+reg TxPauseRq_sync3;
+reg TPauseRq;
+
+
+// Connecting Miim module
+eth_miim miim1
+(
+ .Clk(wb_clk_i), .Reset(wb_rst_i), .Divider(r_ClkDiv),
+ .NoPre(r_MiiNoPre), .CtrlData(r_CtrlData), .Rgad(r_RGAD),
+ .Fiad(r_FIAD), .WCtrlData(r_WCtrlData), .RStat(r_RStat),
+ .ScanStat(r_ScanStat), .Mdi(md_pad_i), .Mdo(md_pad_o),
+ .MdoEn(md_padoe_o), .Mdc(mdc_pad_o), .Busy(Busy_stat),
+ .Prsd(Prsd), .LinkFail(LinkFail), .Nvalid(NValid_stat),
+ .WCtrlDataStart(WCtrlDataStart), .RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg)
+);
+
+
+
+
+wire [3:0] RegCs; // Connected to registers
+wire [31:0] RegDataOut; // Multiplexed to wb_dat_o
+wire r_RecSmall; // Receive small frames
+wire r_LoopBck; // Loopback
+wire r_TxEn; // Tx Enable
+wire r_RxEn; // Rx Enable
+
+wire MRxDV_Lb; // Muxed MII receive data valid
+wire MRxErr_Lb; // Muxed MII Receive Error
+wire [3:0] MRxD_Lb; // Muxed MII Receive Data
+wire Transmitting; // Indication that TxEthMAC is transmitting
+wire r_HugEn; // Huge packet enable
+wire r_DlyCrcEn; // Delayed CRC enabled
+wire [15:0] r_MaxFL; // Maximum frame length
+
+wire [15:0] r_MinFL; // Minimum frame length
+wire ShortFrame;
+wire DribbleNibble; // Extra nibble received
+wire ReceivedPacketTooBig; // Received packet is too big
+wire [47:0] r_MAC; // MAC address
+wire LoadRxStatus; // Rx status was loaded
+wire [31:0] r_HASH0; // HASH table, lower 4 bytes
+wire [31:0] r_HASH1; // HASH table, upper 4 bytes
+wire [7:0] r_TxBDNum; // Receive buffer descriptor number
+wire [6:0] r_IPGT; //
+wire [6:0] r_IPGR1; //
+wire [6:0] r_IPGR2; //
+wire [5:0] r_CollValid; //
+wire [15:0] r_TxPauseTV; // Transmit PAUSE value
+wire r_TxPauseRq; // Transmit PAUSE request
+
+wire [3:0] r_MaxRet; //
+wire r_NoBckof; //
+wire r_ExDfrEn; //
+wire r_TxFlow; // Tx flow control enable
+wire r_IFG; // Minimum interframe gap for incoming packets
+
+wire TxB_IRQ; // Interrupt Tx Buffer
+wire TxE_IRQ; // Interrupt Tx Error
+wire RxB_IRQ; // Interrupt Rx Buffer
+wire RxE_IRQ; // Interrupt Rx Error
+wire Busy_IRQ; // Interrupt Busy (lack of buffers)
+
+//wire DWord;
+wire ByteSelected;
+wire BDAck;
+wire [31:0] BD_WB_DAT_O; // wb_dat_o that comes from the Wishbone module (for buffer descriptors read/write)
+wire [3:0] BDCs; // Buffer descriptor CS
+wire CsMiss; // When access to the address between 0x800 and 0xfff occurs, acknowledge is set
+ // but data is not valid.
+wire r_Pad;
+wire r_CrcEn;
+wire r_FullD;
+wire r_Pro;
+wire r_Bro;
+wire r_NoPre;
+wire r_RxFlow;
+wire r_PassAll;
+wire TxCtrlEndFrm;
+wire StartTxDone;
+wire SetPauseTimer;
+wire TxUsedDataIn;
+wire TxDoneIn;
+wire TxAbortIn;
+wire PerPacketPad;
+wire PadOut;
+wire PerPacketCrcEn;
+wire CrcEnOut;
+wire TxStartFrmOut;
+wire TxEndFrmOut;
+wire ReceivedPauseFrm;
+wire ControlFrmAddressOK;
+wire RxStatusWriteLatched_sync2;
+wire LateCollision;
+wire DeferIndication;
+wire LateCollLatched;
+wire DeferLatched;
+wire RstDeferLatched;
+wire CarrierSenseLost;
+
+wire temp_wb_ack_o;
+wire [31:0] temp_wb_dat_o;
+wire temp_wb_err_o;
+
+`ifdef ETH_REGISTERED_OUTPUTS
+ reg temp_wb_ack_o_reg;
+ reg [31:0] temp_wb_dat_o_reg;
+ reg temp_wb_err_o_reg;
+`endif
+
+//assign DWord = &wb_sel_i;
+assign ByteSelected = |wb_sel_i;
+assign RegCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[3]; // 0x0 - 0x3FF
+assign RegCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[2]; // 0x0 - 0x3FF
+assign RegCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[1]; // 0x0 - 0x3FF
+assign RegCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[0]; // 0x0 - 0x3FF
+assign BDCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[3]; // 0x400 - 0x7FF
+assign BDCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[2]; // 0x400 - 0x7FF
+assign BDCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[1]; // 0x400 - 0x7FF
+assign BDCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[0]; // 0x400 - 0x7FF
+assign CsMiss = wb_stb_i & wb_cyc_i & ByteSelected & wb_adr_i[11]; // 0x800 - 0xfFF
+assign temp_wb_dat_o = ((|RegCs) & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
+assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~ByteSelected | CsMiss);
+
+`ifdef ETH_REGISTERED_OUTPUTS
+ assign wb_ack_o = temp_wb_ack_o_reg;
+ assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
+ assign wb_err_o = temp_wb_err_o_reg;
+`else
+ assign wb_ack_o = temp_wb_ack_o;
+ assign wb_dat_o[31:0] = temp_wb_dat_o;
+ assign wb_err_o = temp_wb_err_o;
+`endif
+
+`ifdef ETH_AVALON_BUS
+ // As Avalon has no corresponding "error" signal, I (erroneously) will
+ // send an ack to Avalon, even when accessing undefined memory. This
+ // is a grey area in Avalon vs. Wishbone specs: My understanding
+ // is that Avalon expects all memory addressable by the addr bus feeding
+ // a slave to be, at the very minimum, readable.
+ assign temp_wb_ack_o = (|RegCs) | BDAck | CsMiss;
+`else // WISHBONE
+ assign temp_wb_ack_o = (|RegCs) | BDAck;
+`endif
+
+`ifdef ETH_REGISTERED_OUTPUTS
+ always @ (posedge wb_clk_i or posedge wb_rst_i)
+ begin
+ if(wb_rst_i)
+ begin
+ temp_wb_ack_o_reg <=#Tp 1'b0;
+ temp_wb_dat_o_reg <=#Tp 32'h0;
+ temp_wb_err_o_reg <=#Tp 1'b0;
+ end
+ else
+ begin
+ temp_wb_ack_o_reg <=#Tp temp_wb_ack_o & ~temp_wb_ack_o_reg;
+ temp_wb_dat_o_reg <=#Tp temp_wb_dat_o;
+ temp_wb_err_o_reg <=#Tp temp_wb_err_o & ~temp_wb_err_o_reg;
+ end
+ end
+`endif
+
+
+// Connecting Ethernet registers
+eth_registers ethreg1
+(
+ .DataIn(wb_dat_i), .Address(wb_adr_i[9:2]), .Rw(wb_we_i),
+ .Cs(RegCs), .Clk(wb_clk_i), .Reset(wb_rst_i),
+ .DataOut(RegDataOut), .r_RecSmall(r_RecSmall),
+ .r_Pad(r_Pad), .r_HugEn(r_HugEn), .r_CrcEn(r_CrcEn),
+ .r_DlyCrcEn(r_DlyCrcEn), .r_FullD(r_FullD),
+ .r_ExDfrEn(r_ExDfrEn), .r_NoBckof(r_NoBckof), .r_LoopBck(r_LoopBck),
+ .r_IFG(r_IFG), .r_Pro(r_Pro), .r_Iam(),
+ .r_Bro(r_Bro), .r_NoPre(r_NoPre), .r_TxEn(r_TxEn),
+ .r_RxEn(r_RxEn), .Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ),
+ .RxB_IRQ(RxB_IRQ), .TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
+ .r_IPGT(r_IPGT),
+ .r_IPGR1(r_IPGR1), .r_IPGR2(r_IPGR2), .r_MinFL(r_MinFL),
+ .r_MaxFL(r_MaxFL), .r_MaxRet(r_MaxRet), .r_CollValid(r_CollValid),
+ .r_TxFlow(r_TxFlow), .r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll),
+ .r_MiiNoPre(r_MiiNoPre), .r_ClkDiv(r_ClkDiv),
+ .r_WCtrlData(r_WCtrlData), .r_RStat(r_RStat), .r_ScanStat(r_ScanStat),
+ .r_RGAD(r_RGAD), .r_FIAD(r_FIAD), .r_CtrlData(r_CtrlData),
+ .NValid_stat(NValid_stat), .Busy_stat(Busy_stat),
+ .LinkFail(LinkFail), .r_MAC(r_MAC), .WCtrlDataStart(WCtrlDataStart),
+ .RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg), .Prsd(Prsd),
+ .r_TxBDNum(r_TxBDNum), .int_o(int_o),
+ .r_HASH0(r_HASH0), .r_HASH1(r_HASH1), .r_TxPauseRq(r_TxPauseRq),
+ .r_TxPauseTV(r_TxPauseTV), .RstTxPauseRq(RstTxPauseRq), .TxCtrlEndFrm(TxCtrlEndFrm),
+ .StartTxDone(StartTxDone), .TxClk(mtx_clk_pad_i), .RxClk(mrx_clk_pad_i),
+ .SetPauseTimer(SetPauseTimer)
+
+);
+
+
+
+wire [7:0] RxData;
+wire RxValid;
+wire RxStartFrm;
+wire RxEndFrm;
+wire RxAbort;
+
+wire WillTransmit; // Will transmit (to RxEthMAC)
+wire ResetCollision; // Reset Collision (for synchronizing collision)
+wire [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC)
+wire WillSendControlFrame;
+wire ReceiveEnd;
+wire ReceivedPacketGood;
+wire ReceivedLengthOK;
+wire InvalidSymbol;
+wire LatchedCrcError;
+wire RxLateCollision;
+wire [3:0] RetryCntLatched;
+wire [3:0] RetryCnt;
+wire StartTxAbort;
+wire MaxCollisionOccured;
+wire RetryLimit;
+wire StatePreamble;
+wire [1:0] StateData;
+
+// Connecting MACControl
+eth_maccontrol maccontrol1
+(
+ .MTxClk(mtx_clk_pad_i), .TPauseRq(TPauseRq),
+ .TxPauseTV(r_TxPauseTV), .TxDataIn(TxData),
+ .TxStartFrmIn(TxStartFrm), .TxEndFrmIn(TxEndFrm),
+ .TxUsedDataIn(TxUsedDataIn), .TxDoneIn(TxDoneIn),
+ .TxAbortIn(TxAbortIn), .MRxClk(mrx_clk_pad_i),
+ .RxData(RxData), .RxValid(RxValid),
+ .RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
+ .ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood),
+ .TxFlow(r_TxFlow),
+ .RxFlow(r_RxFlow), .DlyCrcEn(r_DlyCrcEn),
+ .MAC(r_MAC), .PadIn(r_Pad | PerPacketPad),
+ .PadOut(PadOut), .CrcEnIn(r_CrcEn | PerPacketCrcEn),
+ .CrcEnOut(CrcEnOut), .TxReset(wb_rst_i),
+ .RxReset(wb_rst_i), .ReceivedLengthOK(ReceivedLengthOK),
+ .TxDataOut(TxDataOut), .TxStartFrmOut(TxStartFrmOut),
+ .TxEndFrmOut(TxEndFrmOut), .TxUsedDataOut(TxUsedData),
+ .TxDoneOut(TxDone), .TxAbortOut(TxAbort),
+ .WillSendControlFrame(WillSendControlFrame), .TxCtrlEndFrm(TxCtrlEndFrm),
+ .ReceivedPauseFrm(ReceivedPauseFrm), .ControlFrmAddressOK(ControlFrmAddressOK),
+ .SetPauseTimer(SetPauseTimer),
+ .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2), .r_PassAll(r_PassAll)
+);
+
+
+
+wire TxCarrierSense; // Synchronized CarrierSense (to Tx clock)
+wire Collision; // Synchronized Collision
+
+reg CarrierSense_Tx1;
+reg CarrierSense_Tx2;
+reg Collision_Tx1;
+reg Collision_Tx2;
+
+reg RxEnSync; // Synchronized Receive Enable
+reg WillTransmit_q;
+reg WillTransmit_q2;
+
+
+
+// Muxed MII receive data valid
+assign MRxDV_Lb = r_LoopBck? mtxen_pad_o : mrxdv_pad_i & RxEnSync;
+
+// Muxed MII Receive Error
+assign MRxErr_Lb = r_LoopBck? mtxerr_pad_o : mrxerr_pad_i & RxEnSync;
+
+// Muxed MII Receive Data
+assign MRxD_Lb[3:0] = r_LoopBck? mtxd_pad_o[3:0] : mrxd_pad_i[3:0];
+
+
+
+// Connecting TxEthMAC
+eth_txethmac txethmac1
+(
+ .MTxClk(mtx_clk_pad_i), .Reset(wb_rst_i), .CarrierSense(TxCarrierSense),
+ .Collision(Collision), .TxData(TxDataOut), .TxStartFrm(TxStartFrmOut),
+ .TxUnderRun(TxUnderRun), .TxEndFrm(TxEndFrmOut), .Pad(PadOut),
+ .MinFL(r_MinFL), .CrcEn(CrcEnOut), .FullD(r_FullD),
+ .HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn), .IPGT(r_IPGT),
+ .IPGR1(r_IPGR1), .IPGR2(r_IPGR2), .CollValid(r_CollValid),
+ .MaxRet(r_MaxRet), .NoBckof(r_NoBckof), .ExDfrEn(r_ExDfrEn),
+ .MaxFL(r_MaxFL), .MTxEn(mtxen_pad_o), .MTxD(mtxd_pad_o),
+ .MTxErr(mtxerr_pad_o), .TxUsedData(TxUsedDataIn), .TxDone(TxDoneIn),
+ .TxRetry(TxRetry), .TxAbort(TxAbortIn), .WillTransmit(WillTransmit),
+ .ResetCollision(ResetCollision), .RetryCnt(RetryCnt), .StartTxDone(StartTxDone),
+ .StartTxAbort(StartTxAbort), .MaxCollisionOccured(MaxCollisionOccured), .LateCollision(LateCollision),
+ .DeferIndication(DeferIndication), .StatePreamble(StatePreamble), .StateData(StateData)
+);
+
+
+
+
+wire [15:0] RxByteCnt;
+wire RxByteCntEq0;
+wire RxByteCntGreat2;
+wire RxByteCntMaxFrame;
+wire RxCrcError;
+wire RxStateIdle;
+wire RxStatePreamble;
+wire RxStateSFD;
+wire [1:0] RxStateData;
+wire AddressMiss;
+
+
+
+// Connecting RxEthMAC
+eth_rxethmac rxethmac1
+(
+ .MRxClk(mrx_clk_pad_i), .MRxDV(MRxDV_Lb), .MRxD(MRxD_Lb),
+ .Transmitting(Transmitting), .HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn),
+ .MaxFL(r_MaxFL), .r_IFG(r_IFG), .Reset(wb_rst_i),
+ .RxData(RxData), .RxValid(RxValid), .RxStartFrm(RxStartFrm),
+ .RxEndFrm(RxEndFrm), .ByteCnt(RxByteCnt),
+ .ByteCntEq0(RxByteCntEq0), .ByteCntGreat2(RxByteCntGreat2), .ByteCntMaxFrame(RxByteCntMaxFrame),
+ .CrcError(RxCrcError), .StateIdle(RxStateIdle), .StatePreamble(RxStatePreamble),
+ .StateSFD(RxStateSFD), .StateData(RxStateData),
+ .MAC(r_MAC), .r_Pro(r_Pro), .r_Bro(r_Bro),
+ .r_HASH0(r_HASH0), .r_HASH1(r_HASH1), .RxAbort(RxAbort),
+ .AddressMiss(AddressMiss), .PassAll(r_PassAll), .ControlFrmAddressOK(ControlFrmAddressOK)
+);
+
+
+// MII Carrier Sense Synchronization
+always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ begin
+ CarrierSense_Tx1 <= #Tp 1'b0;
+ CarrierSense_Tx2 <= #Tp 1'b0;
+ end
+ else
+ begin
+ CarrierSense_Tx1 <= #Tp mcrs_pad_i;
+ CarrierSense_Tx2 <= #Tp CarrierSense_Tx1;
+ end
+end
+
+assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2;
+
+
+// MII Collision Synchronization
+always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ begin
+ Collision_Tx1 <= #Tp 1'b0;
+ Collision_Tx2 <= #Tp 1'b0;
+ end
+ else
+ begin
+ Collision_Tx1 <= #Tp mcoll_pad_i;
+ if(ResetCollision)
+ Collision_Tx2 <= #Tp 1'b0;
+ else
+ if(Collision_Tx1)
+ Collision_Tx2 <= #Tp 1'b1;
+ end
+end
+
+
+// Synchronized Collision
+assign Collision = ~r_FullD & Collision_Tx2;
+
+
+
+// Delayed WillTransmit
+always @ (posedge mrx_clk_pad_i)
+begin
+ WillTransmit_q <= #Tp WillTransmit;
+ WillTransmit_q2 <= #Tp WillTransmit_q;
+end
+
+
+assign Transmitting = ~r_FullD & WillTransmit_q2;
+
+
+
+// Synchronized Receive Enable
+always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ RxEnSync <= #Tp 1'b0;
+ else
+ if(~mrxdv_pad_i)
+ RxEnSync <= #Tp r_RxEn;
+end
+
+
+
+// Synchronizing WillSendControlFrame to WB_CLK;
+always @ (posedge wb_clk_i or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ WillSendControlFrame_sync1 <= 1'b0;
+ else
+ WillSendControlFrame_sync1 <=#Tp WillSendControlFrame;
+end
+
+always @ (posedge wb_clk_i or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ WillSendControlFrame_sync2 <= 1'b0;
+ else
+ WillSendControlFrame_sync2 <=#Tp WillSendControlFrame_sync1;
+end
+
+always @ (posedge wb_clk_i or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ WillSendControlFrame_sync3 <= 1'b0;
+ else
+ WillSendControlFrame_sync3 <=#Tp WillSendControlFrame_sync2;
+end
+
+always @ (posedge wb_clk_i or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ RstTxPauseRq <= 1'b0;
+ else
+ RstTxPauseRq <=#Tp WillSendControlFrame_sync2 & ~WillSendControlFrame_sync3;
+end
+
+
+
+
+// TX Pause request Synchronization
+always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ begin
+ TxPauseRq_sync1 <= #Tp 1'b0;
+ TxPauseRq_sync2 <= #Tp 1'b0;
+ TxPauseRq_sync3 <= #Tp 1'b0;
+ end
+ else
+ begin
+ TxPauseRq_sync1 <= #Tp (r_TxPauseRq & r_TxFlow);
+ TxPauseRq_sync2 <= #Tp TxPauseRq_sync1;
+ TxPauseRq_sync3 <= #Tp TxPauseRq_sync2;
+ end
+end
+
+
+always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ TPauseRq <= #Tp 1'b0;
+ else
+ TPauseRq <= #Tp TxPauseRq_sync2 & (~TxPauseRq_sync3);
+end
+
+
+wire LatchedMRxErr;
+reg RxAbort_latch;
+reg RxAbort_sync1;
+reg RxAbort_wb;
+reg RxAbortRst_sync1;
+reg RxAbortRst;
+
+// Synchronizing RxAbort to the WISHBONE clock
+always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ RxAbort_latch <= #Tp 1'b0;
+ else if(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr & ~InvalidSymbol | (ReceivedPauseFrm & (~r_PassAll)))
+ RxAbort_latch <= #Tp 1'b1;
+ else if(RxAbortRst)
+ RxAbort_latch <= #Tp 1'b0;
+end
+
+always @ (posedge wb_clk_i or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ begin
+ RxAbort_sync1 <= #Tp 1'b0;
+ RxAbort_wb <= #Tp 1'b0;
+ RxAbort_wb <= #Tp 1'b0;
+ end
+ else
+ begin
+ RxAbort_sync1 <= #Tp RxAbort_latch;
+ RxAbort_wb <= #Tp RxAbort_sync1;
+ end
+end
+
+always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ begin
+ RxAbortRst_sync1 <= #Tp 1'b0;
+ RxAbortRst <= #Tp 1'b0;
+ end
+ else
+ begin
+ RxAbortRst_sync1 <= #Tp RxAbort_wb;
+ RxAbortRst <= #Tp RxAbortRst_sync1;
+ end
+end
+
+
+
+// Connecting Wishbone module
+eth_wishbone wishbone
+(
+ .WB_CLK_I(wb_clk_i), .WB_DAT_I(wb_dat_i),
+ .WB_DAT_O(BD_WB_DAT_O),
+
+ // WISHBONE slave
+ .WB_ADR_I(wb_adr_i[9:2]), .WB_WE_I(wb_we_i),
+ .BDCs(BDCs), .WB_ACK_O(BDAck),
+
+ .Reset(wb_rst_i),
+
+ // WISHBONE master
+ .m_wb_adr_o(m_wb_adr_tmp), .m_wb_sel_o(m_wb_sel_o), .m_wb_we_o(m_wb_we_o),
+ .m_wb_dat_i(m_wb_dat_i), .m_wb_dat_o(m_wb_dat_o), .m_wb_cyc_o(m_wb_cyc_o),
+ .m_wb_stb_o(m_wb_stb_o), .m_wb_ack_i(m_wb_ack_i), .m_wb_err_i(m_wb_err_i),
+
+`ifdef ETH_WISHBONE_B3
+ .m_wb_cti_o(m_wb_cti_o), .m_wb_bte_o(m_wb_bte_o),
+`endif
+
+
+ //TX
+ .MTxClk(mtx_clk_pad_i), .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm),
+ .TxUsedData(TxUsedData), .TxData(TxData),
+ .TxRetry(TxRetry), .TxAbort(TxAbort), .TxUnderRun(TxUnderRun),
+ .TxDone(TxDone),
+ .PerPacketCrcEn(PerPacketCrcEn), .PerPacketPad(PerPacketPad),
+
+ // Register
+ .r_TxEn(r_TxEn), .r_RxEn(r_RxEn), .r_TxBDNum(r_TxBDNum),
+ .r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll),
+
+ //RX
+ .MRxClk(mrx_clk_pad_i), .RxData(RxData), .RxValid(RxValid),
+ .RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
+ .Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ), .RxB_IRQ(RxB_IRQ),
+ .TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
+
+ .RxAbort(RxAbort_wb), .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2),
+
+ .InvalidSymbol(InvalidSymbol), .LatchedCrcError(LatchedCrcError), .RxLength(RxByteCnt),
+ .RxLateCollision(RxLateCollision), .ShortFrame(ShortFrame), .DribbleNibble(DribbleNibble),
+ .ReceivedPacketTooBig(ReceivedPacketTooBig), .LoadRxStatus(LoadRxStatus), .RetryCntLatched(RetryCntLatched),
+ .RetryLimit(RetryLimit), .LateCollLatched(LateCollLatched), .DeferLatched(DeferLatched),
+ .RstDeferLatched(RstDeferLatched),
+ .CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood), .AddressMiss(AddressMiss),
+ .ReceivedPauseFrm(ReceivedPauseFrm)
+
+`ifdef ETH_BIST
+ ,
+ .mbist_si_i (mbist_si_i),
+ .mbist_so_o (mbist_so_o),
+ .mbist_ctrl_i (mbist_ctrl_i)
+`endif
+);
+
+assign m_wb_adr_o = {m_wb_adr_tmp, 2'h0};
+
+// Connecting MacStatus module
+eth_macstatus macstatus1
+(
+ .MRxClk(mrx_clk_pad_i), .Reset(wb_rst_i),
+ .ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood), .ReceivedLengthOK(ReceivedLengthOK),
+ .RxCrcError(RxCrcError), .MRxErr(MRxErr_Lb), .MRxDV(MRxDV_Lb),
+ .RxStateSFD(RxStateSFD), .RxStateData(RxStateData), .RxStatePreamble(RxStatePreamble),
+ .RxStateIdle(RxStateIdle), .Transmitting(Transmitting), .RxByteCnt(RxByteCnt),
+ .RxByteCntEq0(RxByteCntEq0), .RxByteCntGreat2(RxByteCntGreat2), .RxByteCntMaxFrame(RxByteCntMaxFrame),
+ .InvalidSymbol(InvalidSymbol),
+ .MRxD(MRxD_Lb), .LatchedCrcError(LatchedCrcError), .Collision(mcoll_pad_i),
+ .CollValid(r_CollValid), .RxLateCollision(RxLateCollision), .r_RecSmall(r_RecSmall),
+ .r_MinFL(r_MinFL), .r_MaxFL(r_MaxFL), .ShortFrame(ShortFrame),
+ .DribbleNibble(DribbleNibble), .ReceivedPacketTooBig(ReceivedPacketTooBig), .r_HugEn(r_HugEn),
+ .LoadRxStatus(LoadRxStatus), .RetryCnt(RetryCnt), .StartTxDone(StartTxDone),
+ .StartTxAbort(StartTxAbort), .RetryCntLatched(RetryCntLatched), .MTxClk(mtx_clk_pad_i),
+ .MaxCollisionOccured(MaxCollisionOccured), .RetryLimit(RetryLimit), .LateCollision(LateCollision),
+ .LateCollLatched(LateCollLatched), .DeferIndication(DeferIndication), .DeferLatched(DeferLatched),
+ .RstDeferLatched(RstDeferLatched),
+ .TxStartFrm(TxStartFrmOut), .StatePreamble(StatePreamble), .StateData(StateData),
+ .CarrierSense(CarrierSense_Tx2), .CarrierSenseLost(CarrierSenseLost), .TxUsedData(TxUsedDataIn),
+ .LatchedMRxErr(LatchedMRxErr), .Loopback(r_LoopBck), .r_FullD(r_FullD)
+);
+
+
+endmodule
rtl/verilog/ethmac/eth_top.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rtl/verilog/ethmac/eth_transmitcontrol.v
===================================================================
--- rtl/verilog/ethmac/eth_transmitcontrol.v (nonexistent)
+++ rtl/verilog/ethmac/eth_transmitcontrol.v (revision 409)
@@ -0,0 +1,326 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// eth_transmitcontrol.v ////
+//// ////
+//// This file is part of the Ethernet IP core project ////
+//// http://www.opencores.org/project,ethmac ////
+//// ////
+//// Author(s): ////
+//// - Igor Mohor (igorM@opencores.org) ////
+//// ////
+//// All additional information is avaliable in the Readme.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.5 2002/11/19 17:37:32 mohor
+// When control frame (PAUSE) was sent, status was written in the
+// eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
+// Only TXC interrupt is set.
+//
+// Revision 1.4 2002/01/23 10:28:16 mohor
+// Link in the header changed.
+//
+// Revision 1.3 2001/10/19 08:43:51 mohor
+// eth_timescale.v changed to timescale.v This is done because of the
+// simulation of the few cores in a one joined project.
+//
+// Revision 1.2 2001/09/11 14:17:00 mohor
+// Few little NCSIM warnings fixed.
+//
+// Revision 1.1 2001/08/06 14:44:29 mohor
+// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
+// Include files fixed to contain no path.
+// File names and module names changed ta have a eth_ prologue in the name.
+// File eth_timescale.v is used to define timescale
+// All pin names on the top module are changed to contain _I, _O or _OE at the end.
+// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
+// and Mdo_OE. The bidirectional signal must be created on the top level. This
+// is done due to the ASIC tools.
+//
+// Revision 1.1 2001/07/30 21:23:42 mohor
+// Directory structure changed. Files checked and joind together.
+//
+// Revision 1.1 2001/07/03 12:51:54 mohor
+// Initial release of the MAC Control module.
+//
+//
+//
+//
+//
+//
+
+
+`include "timescale.v"
+
+
+module eth_transmitcontrol (MTxClk, TxReset, TxUsedDataIn, TxUsedDataOut, TxDoneIn, TxAbortIn,
+ TxStartFrmIn, TPauseRq, TxUsedDataOutDetected, TxFlow, DlyCrcEn,
+ TxPauseTV, MAC, TxCtrlStartFrm, TxCtrlEndFrm, SendingCtrlFrm, CtrlMux,
+ ControlData, WillSendControlFrame, BlockTxDone
+ );
+
+parameter Tp = 1;
+
+
+input MTxClk;
+input TxReset;
+input TxUsedDataIn;
+input TxUsedDataOut;
+input TxDoneIn;
+input TxAbortIn;
+input TxStartFrmIn;
+input TPauseRq;
+input TxUsedDataOutDetected;
+input TxFlow;
+input DlyCrcEn;
+input [15:0] TxPauseTV;
+input [47:0] MAC;
+
+output TxCtrlStartFrm;
+output TxCtrlEndFrm;
+output SendingCtrlFrm;
+output CtrlMux;
+output [7:0] ControlData;
+output WillSendControlFrame;
+output BlockTxDone;
+
+reg SendingCtrlFrm;
+reg CtrlMux;
+reg WillSendControlFrame;
+reg [3:0] DlyCrcCnt;
+reg [5:0] ByteCnt;
+reg ControlEnd_q;
+reg [7:0] MuxedCtrlData;
+reg TxCtrlStartFrm;
+reg TxCtrlStartFrm_q;
+reg TxCtrlEndFrm;
+reg [7:0] ControlData;
+reg TxUsedDataIn_q;
+reg BlockTxDone;
+
+wire IncrementDlyCrcCnt;
+wire ResetByteCnt;
+wire IncrementByteCnt;
+wire ControlEnd;
+wire IncrementByteCntBy2;
+wire EnableCnt;
+
+
+// A command for Sending the control frame is active (latched)
+always @ (posedge MTxClk or posedge TxReset)
+begin
+ if(TxReset)
+ WillSendControlFrame <= 1'b0;
+ else
+ if(TxCtrlEndFrm & CtrlMux)
+ WillSendControlFrame <= 1'b0;
+ else
+ if(TPauseRq & TxFlow)
+ WillSendControlFrame <= 1'b1;
+end
+
+
+// Generation of the transmit control packet start frame
+always @ (posedge MTxClk or posedge TxReset)
+begin
+ if(TxReset)
+ TxCtrlStartFrm <= 1'b0;
+ else
+ if(TxUsedDataIn_q & CtrlMux)
+ TxCtrlStartFrm <= 1'b0;
+ else
+ if(WillSendControlFrame & ~TxUsedDataOut & (TxDoneIn | TxAbortIn | TxStartFrmIn | (~TxUsedDataOutDetected)))
+ TxCtrlStartFrm <= 1'b1;
+end
+
+
+
+// Generation of the transmit control packet end frame
+always @ (posedge MTxClk or posedge TxReset)
+begin
+ if(TxReset)
+ TxCtrlEndFrm <= 1'b0;
+ else
+ if(ControlEnd | ControlEnd_q)
+ TxCtrlEndFrm <= 1'b1;
+ else
+ TxCtrlEndFrm <= 1'b0;
+end
+
+
+// Generation of the multiplexer signal (controls muxes for switching between
+// normal and control packets)
+always @ (posedge MTxClk or posedge TxReset)
+begin
+ if(TxReset)
+ CtrlMux <= 1'b0;
+ else
+ if(WillSendControlFrame & ~TxUsedDataOut)
+ CtrlMux <= 1'b1;
+ else
+ if(TxDoneIn)
+ CtrlMux <= 1'b0;
+end
+
+
+
+// Generation of the Sending Control Frame signal (enables padding and CRC)
+always @ (posedge MTxClk or posedge TxReset)
+begin
+ if(TxReset)
+ SendingCtrlFrm <= 1'b0;
+ else
+ if(WillSendControlFrame & TxCtrlStartFrm)
+ SendingCtrlFrm <= 1'b1;
+ else
+ if(TxDoneIn)
+ SendingCtrlFrm <= 1'b0;
+end
+
+
+always @ (posedge MTxClk or posedge TxReset)
+begin
+ if(TxReset)
+ TxUsedDataIn_q <= 1'b0;
+ else
+ TxUsedDataIn_q <= TxUsedDataIn;
+end
+
+
+
+// Generation of the signal that will block sending the Done signal to the eth_wishbone module
+// While sending the control frame
+always @ (posedge MTxClk or posedge TxReset)
+begin
+ if(TxReset)
+ BlockTxDone <= 1'b0;
+ else
+ if(TxCtrlStartFrm)
+ BlockTxDone <= 1'b1;
+ else
+ if(TxStartFrmIn)
+ BlockTxDone <= 1'b0;
+end
+
+
+always @ (posedge MTxClk)
+begin
+ ControlEnd_q <= ControlEnd;
+ TxCtrlStartFrm_q <= TxCtrlStartFrm;
+end
+
+
+assign IncrementDlyCrcCnt = CtrlMux & TxUsedDataIn & ~DlyCrcCnt[2];
+
+
+// Delayed CRC counter
+always @ (posedge MTxClk or posedge TxReset)
+begin
+ if(TxReset)
+ DlyCrcCnt <= 4'h0;
+ else
+ if(ResetByteCnt)
+ DlyCrcCnt <= 4'h0;
+ else
+ if(IncrementDlyCrcCnt)
+ DlyCrcCnt <= DlyCrcCnt + 1'b1;
+end
+
+
+assign ResetByteCnt = TxReset | (~TxCtrlStartFrm & (TxDoneIn | TxAbortIn));
+assign IncrementByteCnt = CtrlMux & (TxCtrlStartFrm & ~TxCtrlStartFrm_q & ~TxUsedDataIn | TxUsedDataIn & ~ControlEnd);
+assign IncrementByteCntBy2 = CtrlMux & TxCtrlStartFrm & (~TxCtrlStartFrm_q) & TxUsedDataIn; // When TxUsedDataIn and CtrlMux are set at the same time
+
+assign EnableCnt = (~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0]));
+// Byte counter
+always @ (posedge MTxClk or posedge TxReset)
+begin
+ if(TxReset)
+ ByteCnt <= 6'h0;
+ else
+ if(ResetByteCnt)
+ ByteCnt <= 6'h0;
+ else
+ if(IncrementByteCntBy2 & EnableCnt)
+ ByteCnt <= (ByteCnt[5:0] ) + 2'h2;
+ else
+ if(IncrementByteCnt & EnableCnt)
+ ByteCnt <= (ByteCnt[5:0] ) + 1'b1;
+end
+
+
+assign ControlEnd = ByteCnt[5:0] == 6'h22;
+
+
+// Control data generation (goes to the TxEthMAC module)
+always @ (ByteCnt or DlyCrcEn or MAC or TxPauseTV or DlyCrcCnt)
+begin
+ case(ByteCnt)
+ 6'h0: if(~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0]))
+ MuxedCtrlData[7:0] = 8'h01; // Reserved Multicast Address
+ else
+ MuxedCtrlData[7:0] = 8'h0;
+ 6'h2: MuxedCtrlData[7:0] = 8'h80;
+ 6'h4: MuxedCtrlData[7:0] = 8'hC2;
+ 6'h6: MuxedCtrlData[7:0] = 8'h00;
+ 6'h8: MuxedCtrlData[7:0] = 8'h00;
+ 6'hA: MuxedCtrlData[7:0] = 8'h01;
+ 6'hC: MuxedCtrlData[7:0] = MAC[47:40];
+ 6'hE: MuxedCtrlData[7:0] = MAC[39:32];
+ 6'h10: MuxedCtrlData[7:0] = MAC[31:24];
+ 6'h12: MuxedCtrlData[7:0] = MAC[23:16];
+ 6'h14: MuxedCtrlData[7:0] = MAC[15:8];
+ 6'h16: MuxedCtrlData[7:0] = MAC[7:0];
+ 6'h18: MuxedCtrlData[7:0] = 8'h88; // Type/Length
+ 6'h1A: MuxedCtrlData[7:0] = 8'h08;
+ 6'h1C: MuxedCtrlData[7:0] = 8'h00; // Opcode
+ 6'h1E: MuxedCtrlData[7:0] = 8'h01;
+ 6'h20: MuxedCtrlData[7:0] = TxPauseTV[15:8]; // Pause timer value
+ 6'h22: MuxedCtrlData[7:0] = TxPauseTV[7:0];
+ default: MuxedCtrlData[7:0] = 8'h0;
+ endcase
+end
+
+
+// Latched Control data
+always @ (posedge MTxClk or posedge TxReset)
+begin
+ if(TxReset)
+ ControlData[7:0] <= 8'h0;
+ else
+ if(~ByteCnt[0])
+ ControlData[7:0] <= MuxedCtrlData[7:0];
+end
+
+
+
+endmodule
rtl/verilog/ethmac/eth_transmitcontrol.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rtl/verilog/ethmac/eth_macstatus.v
===================================================================
--- rtl/verilog/ethmac/eth_macstatus.v (nonexistent)
+++ rtl/verilog/ethmac/eth_macstatus.v (revision 409)
@@ -0,0 +1,425 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// eth_macstatus.v ////
+//// ////
+//// This file is part of the Ethernet IP core project ////
+//// http://www.opencores.org/project,ethmac ////
+//// ////
+//// Author(s): ////
+//// - Igor Mohor (igorM@opencores.org) ////
+//// ////
+//// All additional information is available in the Readme.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001, 2002 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.16 2005/02/21 10:42:11 igorm
+// Defer indication fixed.
+//
+// Revision 1.15 2003/01/30 13:28:19 tadejm
+// Defer indication changed.
+//
+// Revision 1.14 2002/11/22 01:57:06 mohor
+// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
+// synchronized.
+//
+// Revision 1.13 2002/11/13 22:30:58 tadejm
+// Late collision is reported only when not in the full duplex.
+// Sample is taken (for status) as soon as MRxDV is not valid (regardless
+// of the received byte cnt).
+//
+// Revision 1.12 2002/09/12 14:50:16 mohor
+// CarrierSenseLost bug fixed when operating in full duplex mode.
+//
+// Revision 1.11 2002/09/04 18:38:03 mohor
+// CarrierSenseLost status is not set when working in loopback mode.
+//
+// Revision 1.10 2002/07/25 18:17:46 mohor
+// InvalidSymbol generation changed.
+//
+// Revision 1.9 2002/04/22 13:51:44 mohor
+// Short frame and ReceivedLengthOK were not detected correctly.
+//
+// Revision 1.8 2002/02/18 10:40:17 mohor
+// Small fixes.
+//
+// Revision 1.7 2002/02/15 17:07:39 mohor
+// Status was not written correctly when frames were discarted because of
+// address mismatch.
+//
+// Revision 1.6 2002/02/11 09:18:21 mohor
+// Tx status is written back to the BD.
+//
+// Revision 1.5 2002/02/08 16:21:54 mohor
+// Rx status is written back to the BD.
+//
+// Revision 1.4 2002/01/23 10:28:16 mohor
+// Link in the header changed.
+//
+// Revision 1.3 2001/10/19 08:43:51 mohor
+// eth_timescale.v changed to timescale.v This is done because of the
+// simulation of the few cores in a one joined project.
+//
+// Revision 1.2 2001/09/11 14:17:00 mohor
+// Few little NCSIM warnings fixed.
+//
+// Revision 1.1 2001/08/06 14:44:29 mohor
+// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
+// Include files fixed to contain no path.
+// File names and module names changed ta have a eth_ prologue in the name.
+// File eth_timescale.v is used to define timescale
+// All pin names on the top module are changed to contain _I, _O or _OE at the end.
+// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
+// and Mdo_OE. The bidirectional signal must be created on the top level. This
+// is done due to the ASIC tools.
+//
+// Revision 1.1 2001/07/30 21:23:42 mohor
+// Directory structure changed. Files checked and joind together.
+//
+//
+//
+//
+//
+
+`include "timescale.v"
+
+
+module eth_macstatus(
+ MRxClk, Reset, ReceivedLengthOK, ReceiveEnd, ReceivedPacketGood, RxCrcError,
+ MRxErr, MRxDV, RxStateSFD, RxStateData, RxStatePreamble, RxStateIdle, Transmitting,
+ RxByteCnt, RxByteCntEq0, RxByteCntGreat2, RxByteCntMaxFrame,
+ InvalidSymbol, MRxD, LatchedCrcError, Collision, CollValid, RxLateCollision,
+ r_RecSmall, r_MinFL, r_MaxFL, ShortFrame, DribbleNibble, ReceivedPacketTooBig, r_HugEn,
+ LoadRxStatus, StartTxDone, StartTxAbort, RetryCnt, RetryCntLatched, MTxClk, MaxCollisionOccured,
+ RetryLimit, LateCollision, LateCollLatched, DeferIndication, DeferLatched, RstDeferLatched, TxStartFrm,
+ StatePreamble, StateData, CarrierSense, CarrierSenseLost, TxUsedData, LatchedMRxErr, Loopback,
+ r_FullD
+ );
+
+
+
+parameter Tp = 1;
+
+
+input MRxClk;
+input Reset;
+input RxCrcError;
+input MRxErr;
+input MRxDV;
+
+input RxStateSFD;
+input [1:0] RxStateData;
+input RxStatePreamble;
+input RxStateIdle;
+input Transmitting;
+input [15:0] RxByteCnt;
+input RxByteCntEq0;
+input RxByteCntGreat2;
+input RxByteCntMaxFrame;
+input [3:0] MRxD;
+input Collision;
+input [5:0] CollValid;
+input r_RecSmall;
+input [15:0] r_MinFL;
+input [15:0] r_MaxFL;
+input r_HugEn;
+input StartTxDone;
+input StartTxAbort;
+input [3:0] RetryCnt;
+input MTxClk;
+input MaxCollisionOccured;
+input LateCollision;
+input DeferIndication;
+input TxStartFrm;
+input StatePreamble;
+input [1:0] StateData;
+input CarrierSense;
+input TxUsedData;
+input Loopback;
+input r_FullD;
+
+
+output ReceivedLengthOK;
+output ReceiveEnd;
+output ReceivedPacketGood;
+output InvalidSymbol;
+output LatchedCrcError;
+output RxLateCollision;
+output ShortFrame;
+output DribbleNibble;
+output ReceivedPacketTooBig;
+output LoadRxStatus;
+output [3:0] RetryCntLatched;
+output RetryLimit;
+output LateCollLatched;
+output DeferLatched;
+input RstDeferLatched;
+output CarrierSenseLost;
+output LatchedMRxErr;
+
+
+reg ReceiveEnd;
+
+reg LatchedCrcError;
+reg LatchedMRxErr;
+reg LoadRxStatus;
+reg InvalidSymbol;
+reg [3:0] RetryCntLatched;
+reg RetryLimit;
+reg LateCollLatched;
+reg DeferLatched;
+reg CarrierSenseLost;
+
+wire TakeSample;
+wire SetInvalidSymbol; // Invalid symbol was received during reception in 100Mbps
+
+// Crc error
+always @ (posedge MRxClk or posedge Reset)
+begin
+ if(Reset)
+ LatchedCrcError <= 1'b0;
+ else
+ if(RxStateSFD)
+ LatchedCrcError <= 1'b0;
+ else
+ if(RxStateData[0])
+ LatchedCrcError <= RxCrcError & ~RxByteCntEq0;
+end
+
+
+// LatchedMRxErr
+always @ (posedge MRxClk or posedge Reset)
+begin
+ if(Reset)
+ LatchedMRxErr <= 1'b0;
+ else
+ if(MRxErr & MRxDV & (RxStatePreamble | RxStateSFD | (|RxStateData) | RxStateIdle & ~Transmitting))
+ LatchedMRxErr <= 1'b1;
+ else
+ LatchedMRxErr <= 1'b0;
+end
+
+
+// ReceivedPacketGood
+assign ReceivedPacketGood = ~LatchedCrcError;
+
+
+// ReceivedLengthOK
+assign ReceivedLengthOK = RxByteCnt[15:0] >= r_MinFL[15:0] & RxByteCnt[15:0] <= r_MaxFL[15:0];
+
+
+
+
+
+// Time to take a sample
+//assign TakeSample = |RxStateData & ~MRxDV & RxByteCntGreat2 |
+assign TakeSample = (|RxStateData) & (~MRxDV) |
+ RxStateData[0] & MRxDV & RxByteCntMaxFrame;
+
+
+// LoadRxStatus
+always @ (posedge MRxClk or posedge Reset)
+begin
+ if(Reset)
+ LoadRxStatus <= 1'b0;
+ else
+ LoadRxStatus <= TakeSample;
+end
+
+
+
+// ReceiveEnd
+always @ (posedge MRxClk or posedge Reset)
+begin
+ if(Reset)
+ ReceiveEnd <= 1'b0;
+ else
+ ReceiveEnd <= LoadRxStatus;
+end
+
+
+// Invalid Symbol received during 100Mbps mode
+assign SetInvalidSymbol = MRxDV & MRxErr & MRxD[3:0] == 4'he;
+
+
+// InvalidSymbol
+always @ (posedge MRxClk or posedge Reset)
+begin
+ if(Reset)
+ InvalidSymbol <= 1'b0;
+ else
+ if(LoadRxStatus & ~SetInvalidSymbol)
+ InvalidSymbol <= 1'b0;
+ else
+ if(SetInvalidSymbol)
+ InvalidSymbol <= 1'b1;
+end
+
+
+// Late Collision
+
+reg RxLateCollision;
+reg RxColWindow;
+// Collision Window
+always @ (posedge MRxClk or posedge Reset)
+begin
+ if(Reset)
+ RxLateCollision <= 1'b0;
+ else
+ if(LoadRxStatus)
+ RxLateCollision <= 1'b0;
+ else
+ if(Collision & (~r_FullD) & (~RxColWindow | r_RecSmall))
+ RxLateCollision <= 1'b1;
+end
+
+// Collision Window
+always @ (posedge MRxClk or posedge Reset)
+begin
+ if(Reset)
+ RxColWindow <= 1'b1;
+ else
+ if(~Collision & RxByteCnt[5:0] == CollValid[5:0] & RxStateData[1])
+ RxColWindow <= 1'b0;
+ else
+ if(RxStateIdle)
+ RxColWindow <= 1'b1;
+end
+
+
+// ShortFrame
+reg ShortFrame;
+always @ (posedge MRxClk or posedge Reset)
+begin
+ if(Reset)
+ ShortFrame <= 1'b0;
+ else
+ if(LoadRxStatus)
+ ShortFrame <= 1'b0;
+ else
+ if(TakeSample)
+ ShortFrame <= RxByteCnt[15:0] < r_MinFL[15:0];
+end
+
+
+// DribbleNibble
+reg DribbleNibble;
+always @ (posedge MRxClk or posedge Reset)
+begin
+ if(Reset)
+ DribbleNibble <= 1'b0;
+ else
+ if(RxStateSFD)
+ DribbleNibble <= 1'b0;
+ else
+ if(~MRxDV & RxStateData[1])
+ DribbleNibble <= 1'b1;
+end
+
+
+reg ReceivedPacketTooBig;
+always @ (posedge MRxClk or posedge Reset)
+begin
+ if(Reset)
+ ReceivedPacketTooBig <= 1'b0;
+ else
+ if(LoadRxStatus)
+ ReceivedPacketTooBig <= 1'b0;
+ else
+ if(TakeSample)
+ ReceivedPacketTooBig <= ~r_HugEn & RxByteCnt[15:0] > r_MaxFL[15:0];
+end
+
+
+
+// Latched Retry counter for tx status
+always @ (posedge MTxClk or posedge Reset)
+begin
+ if(Reset)
+ RetryCntLatched <= 4'h0;
+ else
+ if(StartTxDone | StartTxAbort)
+ RetryCntLatched <= RetryCnt;
+end
+
+
+// Latched Retransmission limit
+always @ (posedge MTxClk or posedge Reset)
+begin
+ if(Reset)
+ RetryLimit <= 1'h0;
+ else
+ if(StartTxDone | StartTxAbort)
+ RetryLimit <= MaxCollisionOccured;
+end
+
+
+// Latched Late Collision
+always @ (posedge MTxClk or posedge Reset)
+begin
+ if(Reset)
+ LateCollLatched <= 1'b0;
+ else
+ if(StartTxDone | StartTxAbort)
+ LateCollLatched <= LateCollision;
+end
+
+
+
+// Latched Defer state
+always @ (posedge MTxClk or posedge Reset)
+begin
+ if(Reset)
+ DeferLatched <= 1'b0;
+ else
+ if(DeferIndication)
+ DeferLatched <= 1'b1;
+ else
+ if(RstDeferLatched)
+ DeferLatched <= 1'b0;
+end
+
+
+// CarrierSenseLost
+always @ (posedge MTxClk or posedge Reset)
+begin
+ if(Reset)
+ CarrierSenseLost <= 1'b0;
+ else
+ if((StatePreamble | (|StateData)) & ~CarrierSense & ~Loopback & ~Collision & ~r_FullD)
+ CarrierSenseLost <= 1'b1;
+ else
+ if(TxStartFrm)
+ CarrierSenseLost <= 1'b0;
+end
+
+
+endmodule
rtl/verilog/ethmac/eth_macstatus.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rtl/verilog/ethmac/eth_registers.v
===================================================================
--- rtl/verilog/ethmac/eth_registers.v (nonexistent)
+++ rtl/verilog/ethmac/eth_registers.v (revision 409)
@@ -0,0 +1,1188 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// eth_registers.v ////
+//// ////
+//// This file is part of the Ethernet IP core project ////
+//// http://www.opencores.org/project,ethmac ////
+//// ////
+//// Author(s): ////
+//// - Igor Mohor (igorM@opencores.org) ////
+//// ////
+//// All additional information is avaliable in the Readme.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001, 2002 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.28 2004/04/26 15:26:23 igorm
+// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
+// previous update of the core.
+// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
+// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
+// register. (thanks to Mathias and Torbjorn)
+// - Multicast reception was fixed. Thanks to Ulrich Gries
+//
+// Revision 1.27 2004/04/26 11:42:17 igorm
+// TX_BD_NUM_Wr error fixed. Error was entered with the last check-in.
+//
+// Revision 1.26 2003/11/12 18:24:59 tadejm
+// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
+//
+// Revision 1.25 2003/04/18 16:26:25 mohor
+// RxBDAddress was updated also when value to r_TxBDNum was written with
+// greater value than allowed.
+//
+// Revision 1.24 2002/11/22 01:57:06 mohor
+// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
+// synchronized.
+//
+// Revision 1.23 2002/11/19 18:13:49 mohor
+// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
+//
+// Revision 1.22 2002/11/14 18:37:20 mohor
+// r_Rst signal does not reset any module any more and is removed from the design.
+//
+// Revision 1.21 2002/09/10 10:35:23 mohor
+// Ethernet debug registers removed.
+//
+// Revision 1.20 2002/09/04 18:40:25 mohor
+// ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
+// the control frames connected.
+//
+// Revision 1.19 2002/08/19 16:01:40 mohor
+// Only values smaller or equal to 0x80 can be written to TX_BD_NUM register.
+// r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.
+//
+// Revision 1.18 2002/08/16 22:28:23 mohor
+// Syntax error fixed.
+//
+// Revision 1.17 2002/08/16 22:23:03 mohor
+// Syntax error fixed.
+//
+// Revision 1.16 2002/08/16 22:14:22 mohor
+// Synchronous reset added to all registers. Defines used for width. r_MiiMRst
+// changed from bit position 10 to 9.
+//
+// Revision 1.15 2002/08/14 18:26:37 mohor
+// LinkFailRegister is reflecting the status of the PHY's link fail status bit.
+//
+// Revision 1.14 2002/04/22 14:03:44 mohor
+// Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
+// or not.
+//
+// Revision 1.13 2002/02/26 16:18:09 mohor
+// Reset values are passed to registers through parameters
+//
+// Revision 1.12 2002/02/17 13:23:42 mohor
+// Define missmatch fixed.
+//
+// Revision 1.11 2002/02/16 14:03:44 mohor
+// Registered trimmed. Unused registers removed.
+//
+// Revision 1.10 2002/02/15 11:08:25 mohor
+// File format fixed a bit.
+//
+// Revision 1.9 2002/02/14 20:19:41 billditt
+// Modified for Address Checking,
+// addition of eth_addrcheck.v
+//
+// Revision 1.8 2002/02/12 17:01:19 mohor
+// HASH0 and HASH1 registers added.
+
+// Revision 1.7 2002/01/23 10:28:16 mohor
+// Link in the header changed.
+//
+// Revision 1.6 2001/12/05 15:00:16 mohor
+// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
+// instead of the number of RX descriptors).
+//
+// Revision 1.5 2001/12/05 10:22:19 mohor
+// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
+//
+// Revision 1.4 2001/10/19 08:43:51 mohor
+// eth_timescale.v changed to timescale.v This is done because of the
+// simulation of the few cores in a one joined project.
+//
+// Revision 1.3 2001/10/18 12:07:11 mohor
+// Status signals changed, Adress decoding changed, interrupt controller
+// added.
+//
+// Revision 1.2 2001/09/24 15:02:56 mohor
+// Defines changed (All precede with ETH_). Small changes because some
+// tools generate warnings when two operands are together. Synchronization
+// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
+// demands).
+//
+// Revision 1.1 2001/08/06 14:44:29 mohor
+// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
+// Include files fixed to contain no path.
+// File names and module names changed ta have a eth_ prologue in the name.
+// File eth_timescale.v is used to define timescale
+// All pin names on the top module are changed to contain _I, _O or _OE at the end.
+// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
+// and Mdo_OE. The bidirectional signal must be created on the top level. This
+// is done due to the ASIC tools.
+//
+// Revision 1.2 2001/08/02 09:25:31 mohor
+// Unconnected signals are now connected.
+//
+// Revision 1.1 2001/07/30 21:23:42 mohor
+// Directory structure changed. Files checked and joind together.
+//
+//
+//
+//
+//
+//
+
+`include "ethmac_defines.v"
+`include "timescale.v"
+
+
+module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
+ r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
+ r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG,
+ r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn,
+ TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
+ r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
+ r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
+ r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
+ r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
+ LinkFail, r_MAC, WCtrlDataStart, RStatStart,
+ UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, int_o,
+ r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm,
+ dbg_dat, // jb
+ StartTxDone, TxClk, RxClk, SetPauseTimer
+ );
+
+parameter Tp = 1;
+
+input [31:0] DataIn;
+input [7:0] Address;
+
+input Rw;
+input [3:0] Cs;
+input Clk;
+input Reset;
+
+input WCtrlDataStart;
+input RStatStart;
+
+input UpdateMIIRX_DATAReg;
+input [15:0] Prsd;
+
+output [31:0] DataOut;
+reg [31:0] DataOut;
+
+output r_RecSmall;
+output r_Pad;
+output r_HugEn;
+output r_CrcEn;
+output r_DlyCrcEn;
+output r_FullD;
+output r_ExDfrEn;
+output r_NoBckof;
+output r_LoopBck;
+output r_IFG;
+output r_Pro;
+output r_Iam;
+output r_Bro;
+output r_NoPre;
+output r_TxEn;
+output r_RxEn;
+output [31:0] r_HASH0;
+output [31:0] r_HASH1;
+
+input TxB_IRQ;
+input TxE_IRQ;
+input RxB_IRQ;
+input RxE_IRQ;
+input Busy_IRQ;
+
+output [6:0] r_IPGT;
+
+output [6:0] r_IPGR1;
+
+output [6:0] r_IPGR2;
+
+output [15:0] r_MinFL;
+output [15:0] r_MaxFL;
+
+output [3:0] r_MaxRet;
+output [5:0] r_CollValid;
+
+output r_TxFlow;
+output r_RxFlow;
+output r_PassAll;
+
+output r_MiiNoPre;
+output [7:0] r_ClkDiv;
+
+output r_WCtrlData;
+output r_RStat;
+output r_ScanStat;
+
+output [4:0] r_RGAD;
+output [4:0] r_FIAD;
+
+output [15:0]r_CtrlData;
+
+
+input NValid_stat;
+input Busy_stat;
+input LinkFail;
+
+output [47:0]r_MAC;
+output [7:0] r_TxBDNum;
+output int_o;
+output [15:0]r_TxPauseTV;
+output r_TxPauseRq;
+input RstTxPauseRq;
+input TxCtrlEndFrm;
+input StartTxDone;
+input TxClk;
+input RxClk;
+input SetPauseTimer;
+
+input [31:0] dbg_dat; // debug data input - JB
+
+
+reg irq_txb;
+reg irq_txe;
+reg irq_rxb;
+reg irq_rxe;
+reg irq_busy;
+reg irq_txc;
+reg irq_rxc;
+
+reg SetTxCIrq_txclk;
+reg SetTxCIrq_sync1, SetTxCIrq_sync2, SetTxCIrq_sync3;
+reg SetTxCIrq;
+reg ResetTxCIrq_sync1, ResetTxCIrq_sync2;
+
+reg SetRxCIrq_rxclk;
+reg SetRxCIrq_sync1, SetRxCIrq_sync2, SetRxCIrq_sync3;
+reg SetRxCIrq;
+reg ResetRxCIrq_sync1;
+reg ResetRxCIrq_sync2;
+reg ResetRxCIrq_sync3;
+
+wire [3:0] Write = Cs & {4{Rw}};
+wire Read = (|Cs) & ~Rw;
+
+wire MODER_Sel = (Address == `ETH_MODER_ADR );
+wire INT_SOURCE_Sel = (Address == `ETH_INT_SOURCE_ADR );
+wire INT_MASK_Sel = (Address == `ETH_INT_MASK_ADR );
+wire IPGT_Sel = (Address == `ETH_IPGT_ADR );
+wire IPGR1_Sel = (Address == `ETH_IPGR1_ADR );
+wire IPGR2_Sel = (Address == `ETH_IPGR2_ADR );
+wire PACKETLEN_Sel = (Address == `ETH_PACKETLEN_ADR );
+wire COLLCONF_Sel = (Address == `ETH_COLLCONF_ADR );
+
+wire CTRLMODER_Sel = (Address == `ETH_CTRLMODER_ADR );
+wire MIIMODER_Sel = (Address == `ETH_MIIMODER_ADR );
+wire MIICOMMAND_Sel = (Address == `ETH_MIICOMMAND_ADR );
+wire MIIADDRESS_Sel = (Address == `ETH_MIIADDRESS_ADR );
+wire MIITX_DATA_Sel = (Address == `ETH_MIITX_DATA_ADR );
+wire MAC_ADDR0_Sel = (Address == `ETH_MAC_ADDR0_ADR );
+wire MAC_ADDR1_Sel = (Address == `ETH_MAC_ADDR1_ADR );
+wire HASH0_Sel = (Address == `ETH_HASH0_ADR );
+wire HASH1_Sel = (Address == `ETH_HASH1_ADR );
+wire TXCTRL_Sel = (Address == `ETH_TX_CTRL_ADR );
+wire RXCTRL_Sel = (Address == `ETH_RX_CTRL_ADR );
+wire DBG_REG_Sel = (Address == `ETH_DBG_ADR ); // JB
+wire TX_BD_NUM_Sel = (Address == `ETH_TX_BD_NUM_ADR );
+
+
+
+wire [2:0] MODER_Wr;
+wire [0:0] INT_SOURCE_Wr;
+wire [0:0] INT_MASK_Wr;
+wire [0:0] IPGT_Wr;
+wire [0:0] IPGR1_Wr;
+wire [0:0] IPGR2_Wr;
+wire [3:0] PACKETLEN_Wr;
+wire [2:0] COLLCONF_Wr;
+wire [0:0] CTRLMODER_Wr;
+wire [1:0] MIIMODER_Wr;
+wire [0:0] MIICOMMAND_Wr;
+wire [1:0] MIIADDRESS_Wr;
+wire [1:0] MIITX_DATA_Wr;
+wire MIIRX_DATA_Wr;
+wire [3:0] MAC_ADDR0_Wr;
+wire [1:0] MAC_ADDR1_Wr;
+wire [3:0] HASH0_Wr;
+wire [3:0] HASH1_Wr;
+wire [2:0] TXCTRL_Wr;
+wire [0:0] TX_BD_NUM_Wr;
+
+assign MODER_Wr[0] = Write[0] & MODER_Sel;
+assign MODER_Wr[1] = Write[1] & MODER_Sel;
+assign MODER_Wr[2] = Write[2] & MODER_Sel;
+assign INT_SOURCE_Wr[0] = Write[0] & INT_SOURCE_Sel;
+assign INT_MASK_Wr[0] = Write[0] & INT_MASK_Sel;
+assign IPGT_Wr[0] = Write[0] & IPGT_Sel;
+assign IPGR1_Wr[0] = Write[0] & IPGR1_Sel;
+assign IPGR2_Wr[0] = Write[0] & IPGR2_Sel;
+assign PACKETLEN_Wr[0] = Write[0] & PACKETLEN_Sel;
+assign PACKETLEN_Wr[1] = Write[1] & PACKETLEN_Sel;
+assign PACKETLEN_Wr[2] = Write[2] & PACKETLEN_Sel;
+assign PACKETLEN_Wr[3] = Write[3] & PACKETLEN_Sel;
+assign COLLCONF_Wr[0] = Write[0] & COLLCONF_Sel;
+assign COLLCONF_Wr[1] = 1'b0; // Not used
+assign COLLCONF_Wr[2] = Write[2] & COLLCONF_Sel;
+
+assign CTRLMODER_Wr[0] = Write[0] & CTRLMODER_Sel;
+assign MIIMODER_Wr[0] = Write[0] & MIIMODER_Sel;
+assign MIIMODER_Wr[1] = Write[1] & MIIMODER_Sel;
+assign MIICOMMAND_Wr[0] = Write[0] & MIICOMMAND_Sel;
+assign MIIADDRESS_Wr[0] = Write[0] & MIIADDRESS_Sel;
+assign MIIADDRESS_Wr[1] = Write[1] & MIIADDRESS_Sel;
+assign MIITX_DATA_Wr[0] = Write[0] & MIITX_DATA_Sel;
+assign MIITX_DATA_Wr[1] = Write[1] & MIITX_DATA_Sel;
+assign MIIRX_DATA_Wr = UpdateMIIRX_DATAReg;
+assign MAC_ADDR0_Wr[0] = Write[0] & MAC_ADDR0_Sel;
+assign MAC_ADDR0_Wr[1] = Write[1] & MAC_ADDR0_Sel;
+assign MAC_ADDR0_Wr[2] = Write[2] & MAC_ADDR0_Sel;
+assign MAC_ADDR0_Wr[3] = Write[3] & MAC_ADDR0_Sel;
+assign MAC_ADDR1_Wr[0] = Write[0] & MAC_ADDR1_Sel;
+assign MAC_ADDR1_Wr[1] = Write[1] & MAC_ADDR1_Sel;
+assign HASH0_Wr[0] = Write[0] & HASH0_Sel;
+assign HASH0_Wr[1] = Write[1] & HASH0_Sel;
+assign HASH0_Wr[2] = Write[2] & HASH0_Sel;
+assign HASH0_Wr[3] = Write[3] & HASH0_Sel;
+assign HASH1_Wr[0] = Write[0] & HASH1_Sel;
+assign HASH1_Wr[1] = Write[1] & HASH1_Sel;
+assign HASH1_Wr[2] = Write[2] & HASH1_Sel;
+assign HASH1_Wr[3] = Write[3] & HASH1_Sel;
+assign TXCTRL_Wr[0] = Write[0] & TXCTRL_Sel;
+assign TXCTRL_Wr[1] = Write[1] & TXCTRL_Sel;
+assign TXCTRL_Wr[2] = Write[2] & TXCTRL_Sel;
+assign TX_BD_NUM_Wr[0] = Write[0] & TX_BD_NUM_Sel & (DataIn<='h80);
+
+
+
+wire [31:0] MODEROut;
+wire [31:0] INT_SOURCEOut;
+wire [31:0] INT_MASKOut;
+wire [31:0] IPGTOut;
+wire [31:0] IPGR1Out;
+wire [31:0] IPGR2Out;
+wire [31:0] PACKETLENOut;
+wire [31:0] COLLCONFOut;
+wire [31:0] CTRLMODEROut;
+wire [31:0] MIIMODEROut;
+wire [31:0] MIICOMMANDOut;
+wire [31:0] MIIADDRESSOut;
+wire [31:0] MIITX_DATAOut;
+wire [31:0] MIIRX_DATAOut;
+wire [31:0] MIISTATUSOut;
+wire [31:0] MAC_ADDR0Out;
+wire [31:0] MAC_ADDR1Out;
+wire [31:0] TX_BD_NUMOut;
+wire [31:0] HASH0Out;
+wire [31:0] HASH1Out;
+wire [31:0] TXCTRLOut;
+wire [31:0] DBGOut; // JB
+
+// MODER Register
+eth_register #(`ETH_MODER_WIDTH_0, `ETH_MODER_DEF_0) MODER_0
+ (
+ .DataIn (DataIn[`ETH_MODER_WIDTH_0 - 1:0]),
+ .DataOut (MODEROut[`ETH_MODER_WIDTH_0 - 1:0]),
+ .Write (MODER_Wr[0]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (1'b0)
+ );
+eth_register #(`ETH_MODER_WIDTH_1, `ETH_MODER_DEF_1) MODER_1
+ (
+ .DataIn (DataIn[`ETH_MODER_WIDTH_1 + 7:8]),
+ .DataOut (MODEROut[`ETH_MODER_WIDTH_1 + 7:8]),
+ .Write (MODER_Wr[1]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (1'b0)
+ );
+eth_register #(`ETH_MODER_WIDTH_2, `ETH_MODER_DEF_2) MODER_2
+ (
+ .DataIn (DataIn[`ETH_MODER_WIDTH_2 + 15:16]),
+ .DataOut (MODEROut[`ETH_MODER_WIDTH_2 + 15:16]),
+ .Write (MODER_Wr[2]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (1'b0)
+ );
+assign MODEROut[31:`ETH_MODER_WIDTH_2 + 16] = 0;
+
+// INT_MASK Register
+eth_register #(`ETH_INT_MASK_WIDTH_0, `ETH_INT_MASK_DEF_0) INT_MASK_0
+ (
+ .DataIn (DataIn[`ETH_INT_MASK_WIDTH_0 - 1:0]),
+ .DataOut (INT_MASKOut[`ETH_INT_MASK_WIDTH_0 - 1:0]),
+ .Write (INT_MASK_Wr[0]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (1'b0)
+ );
+assign INT_MASKOut[31:`ETH_INT_MASK_WIDTH_0] = 0;
+
+// IPGT Register
+eth_register #(`ETH_IPGT_WIDTH_0, `ETH_IPGT_DEF_0) IPGT_0
+ (
+ .DataIn (DataIn[`ETH_IPGT_WIDTH_0 - 1:0]),
+ .DataOut (IPGTOut[`ETH_IPGT_WIDTH_0 - 1:0]),
+ .Write (IPGT_Wr[0]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (1'b0)
+ );
+assign IPGTOut[31:`ETH_IPGT_WIDTH_0] = 0;
+
+// IPGR1 Register
+eth_register #(`ETH_IPGR1_WIDTH_0, `ETH_IPGR1_DEF_0) IPGR1_0
+ (
+ .DataIn (DataIn[`ETH_IPGR1_WIDTH_0 - 1:0]),
+ .DataOut (IPGR1Out[`ETH_IPGR1_WIDTH_0 - 1:0]),
+ .Write (IPGR1_Wr[0]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (1'b0)
+ );
+assign IPGR1Out[31:`ETH_IPGR1_WIDTH_0] = 0;
+
+// IPGR2 Register
+eth_register #(`ETH_IPGR2_WIDTH_0, `ETH_IPGR2_DEF_0) IPGR2_0
+ (
+ .DataIn (DataIn[`ETH_IPGR2_WIDTH_0 - 1:0]),
+ .DataOut (IPGR2Out[`ETH_IPGR2_WIDTH_0 - 1:0]),
+ .Write (IPGR2_Wr[0]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (1'b0)
+ );
+assign IPGR2Out[31:`ETH_IPGR2_WIDTH_0] = 0;
+
+// PACKETLEN Register
+eth_register #(`ETH_PACKETLEN_WIDTH_0, `ETH_PACKETLEN_DEF_0) PACKETLEN_0
+ (
+ .DataIn (DataIn[`ETH_PACKETLEN_WIDTH_0 - 1:0]),
+ .DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_0 - 1:0]),
+ .Write (PACKETLEN_Wr[0]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (1'b0)
+ );
+eth_register #(`ETH_PACKETLEN_WIDTH_1, `ETH_PACKETLEN_DEF_1) PACKETLEN_1
+ (
+ .DataIn (DataIn[`ETH_PACKETLEN_WIDTH_1 + 7:8]),
+ .DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_1 + 7:8]),
+ .Write (PACKETLEN_Wr[1]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (1'b0)
+ );
+eth_register #(`ETH_PACKETLEN_WIDTH_2, `ETH_PACKETLEN_DEF_2) PACKETLEN_2
+ (
+ .DataIn (DataIn[`ETH_PACKETLEN_WIDTH_2 + 15:16]),
+ .DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_2 + 15:16]),
+ .Write (PACKETLEN_Wr[2]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (1'b0)
+ );
+eth_register #(`ETH_PACKETLEN_WIDTH_3, `ETH_PACKETLEN_DEF_3) PACKETLEN_3
+ (
+ .DataIn (DataIn[`ETH_PACKETLEN_WIDTH_3 + 23:24]),
+ .DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_3 + 23:24]),
+ .Write (PACKETLEN_Wr[3]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (1'b0)
+ );
+
+// COLLCONF Register
+eth_register #(`ETH_COLLCONF_WIDTH_0, `ETH_COLLCONF_DEF_0) COLLCONF_0
+ (
+ .DataIn (DataIn[`ETH_COLLCONF_WIDTH_0 - 1:0]),
+ .DataOut (COLLCONFOut[`ETH_COLLCONF_WIDTH_0 - 1:0]),
+ .Write (COLLCONF_Wr[0]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (1'b0)
+ );
+eth_register #(`ETH_COLLCONF_WIDTH_2, `ETH_COLLCONF_DEF_2) COLLCONF_2
+ (
+ .DataIn (DataIn[`ETH_COLLCONF_WIDTH_2 + 15:16]),
+ .DataOut (COLLCONFOut[`ETH_COLLCONF_WIDTH_2 + 15:16]),
+ .Write (COLLCONF_Wr[2]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (1'b0)
+ );
+assign COLLCONFOut[15:`ETH_COLLCONF_WIDTH_0] = 0;
+assign COLLCONFOut[31:`ETH_COLLCONF_WIDTH_2 + 16] = 0;
+
+// TX_BD_NUM Register
+eth_register #(`ETH_TX_BD_NUM_WIDTH_0, `ETH_TX_BD_NUM_DEF_0) TX_BD_NUM_0
+ (
+ .DataIn (DataIn[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]),
+ .DataOut (TX_BD_NUMOut[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]),
+ .Write (TX_BD_NUM_Wr[0]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (1'b0)
+ );
+assign TX_BD_NUMOut[31:`ETH_TX_BD_NUM_WIDTH_0] = 0;
+
+// CTRLMODER Register
+eth_register #(`ETH_CTRLMODER_WIDTH_0, `ETH_CTRLMODER_DEF_0) CTRLMODER_0
+ (
+ .DataIn (DataIn[`ETH_CTRLMODER_WIDTH_0 - 1:0]),
+ .DataOut (CTRLMODEROut[`ETH_CTRLMODER_WIDTH_0 - 1:0]),
+ .Write (CTRLMODER_Wr[0]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (1'b0)
+ );
+assign CTRLMODEROut[31:`ETH_CTRLMODER_WIDTH_0] = 0;
+
+// MIIMODER Register
+eth_register #(`ETH_MIIMODER_WIDTH_0, `ETH_MIIMODER_DEF_0) MIIMODER_0
+ (
+ .DataIn (DataIn[`ETH_MIIMODER_WIDTH_0 - 1:0]),
+ .DataOut (MIIMODEROut[`ETH_MIIMODER_WIDTH_0 - 1:0]),
+ .Write (MIIMODER_Wr[0]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (1'b0)
+ );
+eth_register #(`ETH_MIIMODER_WIDTH_1, `ETH_MIIMODER_DEF_1) MIIMODER_1
+ (
+ .DataIn (DataIn[`ETH_MIIMODER_WIDTH_1 + 7:8]),
+ .DataOut (MIIMODEROut[`ETH_MIIMODER_WIDTH_1 + 7:8]),
+ .Write (MIIMODER_Wr[1]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (1'b0)
+ );
+assign MIIMODEROut[31:`ETH_MIIMODER_WIDTH_1 + 8] = 0;
+
+// MIICOMMAND Register
+eth_register #(1, 0) MIICOMMAND0
+ (
+ .DataIn (DataIn[0]),
+ .DataOut (MIICOMMANDOut[0]),
+ .Write (MIICOMMAND_Wr[0]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (1'b0)
+ );
+eth_register #(1, 0) MIICOMMAND1
+ (
+ .DataIn (DataIn[1]),
+ .DataOut (MIICOMMANDOut[1]),
+ .Write (MIICOMMAND_Wr[0]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (RStatStart)
+ );
+eth_register #(1, 0) MIICOMMAND2
+ (
+ .DataIn (DataIn[2]),
+ .DataOut (MIICOMMANDOut[2]),
+ .Write (MIICOMMAND_Wr[0]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (WCtrlDataStart)
+ );
+assign MIICOMMANDOut[31:`ETH_MIICOMMAND_WIDTH_0] = 29'h0;
+
+// MIIADDRESSRegister
+eth_register #(`ETH_MIIADDRESS_WIDTH_0, `ETH_MIIADDRESS_DEF_0) MIIADDRESS_0
+ (
+ .DataIn (DataIn[`ETH_MIIADDRESS_WIDTH_0 - 1:0]),
+ .DataOut (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_0 - 1:0]),
+ .Write (MIIADDRESS_Wr[0]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (1'b0)
+ );
+eth_register #(`ETH_MIIADDRESS_WIDTH_1, `ETH_MIIADDRESS_DEF_1) MIIADDRESS_1
+ (
+ .DataIn (DataIn[`ETH_MIIADDRESS_WIDTH_1 + 7:8]),
+ .DataOut (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_1 + 7:8]),
+ .Write (MIIADDRESS_Wr[1]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (1'b0)
+ );
+assign MIIADDRESSOut[7:`ETH_MIIADDRESS_WIDTH_0] = 0;
+assign MIIADDRESSOut[31:`ETH_MIIADDRESS_WIDTH_1 + 8] = 0;
+
+// MIITX_DATA Register
+eth_register #(`ETH_MIITX_DATA_WIDTH_0, `ETH_MIITX_DATA_DEF_0) MIITX_DATA_0
+ (
+ .DataIn (DataIn[`ETH_MIITX_DATA_WIDTH_0 - 1:0]),
+ .DataOut (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_0 - 1:0]),
+ .Write (MIITX_DATA_Wr[0]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (1'b0)
+ );
+eth_register #(`ETH_MIITX_DATA_WIDTH_1, `ETH_MIITX_DATA_DEF_1) MIITX_DATA_1
+ (
+ .DataIn (DataIn[`ETH_MIITX_DATA_WIDTH_1 + 7:8]),
+ .DataOut (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_1 + 7:8]),
+ .Write (MIITX_DATA_Wr[1]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (1'b0)
+ );
+assign MIITX_DATAOut[31:`ETH_MIITX_DATA_WIDTH_1 + 8] = 0;
+
+// MIIRX_DATA Register
+eth_register #(`ETH_MIIRX_DATA_WIDTH, `ETH_MIIRX_DATA_DEF) MIIRX_DATA
+ (
+ .DataIn (Prsd[`ETH_MIIRX_DATA_WIDTH-1:0]),
+ .DataOut (MIIRX_DATAOut[`ETH_MIIRX_DATA_WIDTH-1:0]),
+ .Write (MIIRX_DATA_Wr), // not written from WB
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (1'b0)
+ );
+assign MIIRX_DATAOut[31:`ETH_MIIRX_DATA_WIDTH] = 0;
+
+// MAC_ADDR0 Register
+eth_register #(`ETH_MAC_ADDR0_WIDTH_0, `ETH_MAC_ADDR0_DEF_0) MAC_ADDR0_0
+ (
+ .DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]),
+ .DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]),
+ .Write (MAC_ADDR0_Wr[0]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (1'b0)
+ );
+eth_register #(`ETH_MAC_ADDR0_WIDTH_1, `ETH_MAC_ADDR0_DEF_1) MAC_ADDR0_1
+ (
+ .DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]),
+ .DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]),
+ .Write (MAC_ADDR0_Wr[1]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (1'b0)
+ );
+eth_register #(`ETH_MAC_ADDR0_WIDTH_2, `ETH_MAC_ADDR0_DEF_2) MAC_ADDR0_2
+ (
+ .DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]),
+ .DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]),
+ .Write (MAC_ADDR0_Wr[2]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (1'b0)
+ );
+eth_register #(`ETH_MAC_ADDR0_WIDTH_3, `ETH_MAC_ADDR0_DEF_3) MAC_ADDR0_3
+ (
+ .DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]),
+ .DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]),
+ .Write (MAC_ADDR0_Wr[3]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (1'b0)
+ );
+
+// MAC_ADDR1 Register
+eth_register #(`ETH_MAC_ADDR1_WIDTH_0, `ETH_MAC_ADDR1_DEF_0) MAC_ADDR1_0
+ (
+ .DataIn (DataIn[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]),
+ .DataOut (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]),
+ .Write (MAC_ADDR1_Wr[0]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (1'b0)
+ );
+eth_register #(`ETH_MAC_ADDR1_WIDTH_1, `ETH_MAC_ADDR1_DEF_1) MAC_ADDR1_1
+ (
+ .DataIn (DataIn[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]),
+ .DataOut (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]),
+ .Write (MAC_ADDR1_Wr[1]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (1'b0)
+ );
+assign MAC_ADDR1Out[31:`ETH_MAC_ADDR1_WIDTH_1 + 8] = 0;
+
+// RXHASH0 Register
+eth_register #(`ETH_HASH0_WIDTH_0, `ETH_HASH0_DEF_0) RXHASH0_0
+ (
+ .DataIn (DataIn[`ETH_HASH0_WIDTH_0 - 1:0]),
+ .DataOut (HASH0Out[`ETH_HASH0_WIDTH_0 - 1:0]),
+ .Write (HASH0_Wr[0]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (1'b0)
+ );
+eth_register #(`ETH_HASH0_WIDTH_1, `ETH_HASH0_DEF_1) RXHASH0_1
+ (
+ .DataIn (DataIn[`ETH_HASH0_WIDTH_1 + 7:8]),
+ .DataOut (HASH0Out[`ETH_HASH0_WIDTH_1 + 7:8]),
+ .Write (HASH0_Wr[1]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (1'b0)
+ );
+eth_register #(`ETH_HASH0_WIDTH_2, `ETH_HASH0_DEF_2) RXHASH0_2
+ (
+ .DataIn (DataIn[`ETH_HASH0_WIDTH_2 + 15:16]),
+ .DataOut (HASH0Out[`ETH_HASH0_WIDTH_2 + 15:16]),
+ .Write (HASH0_Wr[2]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (1'b0)
+ );
+eth_register #(`ETH_HASH0_WIDTH_3, `ETH_HASH0_DEF_3) RXHASH0_3
+ (
+ .DataIn (DataIn[`ETH_HASH0_WIDTH_3 + 23:24]),
+ .DataOut (HASH0Out[`ETH_HASH0_WIDTH_3 + 23:24]),
+ .Write (HASH0_Wr[3]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (1'b0)
+ );
+
+// RXHASH1 Register
+eth_register #(`ETH_HASH1_WIDTH_0, `ETH_HASH1_DEF_0) RXHASH1_0
+ (
+ .DataIn (DataIn[`ETH_HASH1_WIDTH_0 - 1:0]),
+ .DataOut (HASH1Out[`ETH_HASH1_WIDTH_0 - 1:0]),
+ .Write (HASH1_Wr[0]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (1'b0)
+ );
+eth_register #(`ETH_HASH1_WIDTH_1, `ETH_HASH1_DEF_1) RXHASH1_1
+ (
+ .DataIn (DataIn[`ETH_HASH1_WIDTH_1 + 7:8]),
+ .DataOut (HASH1Out[`ETH_HASH1_WIDTH_1 + 7:8]),
+ .Write (HASH1_Wr[1]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (1'b0)
+ );
+eth_register #(`ETH_HASH1_WIDTH_2, `ETH_HASH1_DEF_2) RXHASH1_2
+ (
+ .DataIn (DataIn[`ETH_HASH1_WIDTH_2 + 15:16]),
+ .DataOut (HASH1Out[`ETH_HASH1_WIDTH_2 + 15:16]),
+ .Write (HASH1_Wr[2]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (1'b0)
+ );
+eth_register #(`ETH_HASH1_WIDTH_3, `ETH_HASH1_DEF_3) RXHASH1_3
+ (
+ .DataIn (DataIn[`ETH_HASH1_WIDTH_3 + 23:24]),
+ .DataOut (HASH1Out[`ETH_HASH1_WIDTH_3 + 23:24]),
+ .Write (HASH1_Wr[3]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (1'b0)
+ );
+
+// TXCTRL Register
+eth_register #(`ETH_TX_CTRL_WIDTH_0, `ETH_TX_CTRL_DEF_0) TXCTRL_0
+ (
+ .DataIn (DataIn[`ETH_TX_CTRL_WIDTH_0 - 1:0]),
+ .DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_0 - 1:0]),
+ .Write (TXCTRL_Wr[0]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (1'b0)
+ );
+eth_register #(`ETH_TX_CTRL_WIDTH_1, `ETH_TX_CTRL_DEF_1) TXCTRL_1
+ (
+ .DataIn (DataIn[`ETH_TX_CTRL_WIDTH_1 + 7:8]),
+ .DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_1 + 7:8]),
+ .Write (TXCTRL_Wr[1]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (1'b0)
+ );
+eth_register #(`ETH_TX_CTRL_WIDTH_2, `ETH_TX_CTRL_DEF_2) TXCTRL_2 // Request bit is synchronously reset
+ (
+ .DataIn (DataIn[`ETH_TX_CTRL_WIDTH_2 + 15:16]),
+ .DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_2 + 15:16]),
+ .Write (TXCTRL_Wr[2]),
+ .Clk (Clk),
+ .Reset (Reset),
+ .SyncReset (RstTxPauseRq)
+ );
+assign TXCTRLOut[31:`ETH_TX_CTRL_WIDTH_2 + 16] = 0;
+
+
+
+// Reading data from registers
+always @ (Address or Read or MODEROut or INT_SOURCEOut or
+ INT_MASKOut or IPGTOut or IPGR1Out or IPGR2Out or
+ PACKETLENOut or COLLCONFOut or CTRLMODEROut or MIIMODEROut or
+ MIICOMMANDOut or MIIADDRESSOut or MIITX_DATAOut or MIIRX_DATAOut or
+ MIISTATUSOut or MAC_ADDR0Out or MAC_ADDR1Out or TX_BD_NUMOut or
+ HASH0Out or HASH1Out or TXCTRLOut
+ )
+begin
+ if(Read) // read
+ begin
+ case(Address)
+ `ETH_MODER_ADR : DataOut<=MODEROut;
+ `ETH_INT_SOURCE_ADR : DataOut<=INT_SOURCEOut;
+ `ETH_INT_MASK_ADR : DataOut<=INT_MASKOut;
+ `ETH_IPGT_ADR : DataOut<=IPGTOut;
+ `ETH_IPGR1_ADR : DataOut<=IPGR1Out;
+ `ETH_IPGR2_ADR : DataOut<=IPGR2Out;
+ `ETH_PACKETLEN_ADR : DataOut<=PACKETLENOut;
+ `ETH_COLLCONF_ADR : DataOut<=COLLCONFOut;
+ `ETH_CTRLMODER_ADR : DataOut<=CTRLMODEROut;
+ `ETH_MIIMODER_ADR : DataOut<=MIIMODEROut;
+ `ETH_MIICOMMAND_ADR : DataOut<=MIICOMMANDOut;
+ `ETH_MIIADDRESS_ADR : DataOut<=MIIADDRESSOut;
+ `ETH_MIITX_DATA_ADR : DataOut<=MIITX_DATAOut;
+ `ETH_MIIRX_DATA_ADR : DataOut<=MIIRX_DATAOut;
+ `ETH_MIISTATUS_ADR : DataOut<=MIISTATUSOut;
+ `ETH_MAC_ADDR0_ADR : DataOut<=MAC_ADDR0Out;
+ `ETH_MAC_ADDR1_ADR : DataOut<=MAC_ADDR1Out;
+ `ETH_TX_BD_NUM_ADR : DataOut<=TX_BD_NUMOut;
+ `ETH_HASH0_ADR : DataOut<=HASH0Out;
+ `ETH_HASH1_ADR : DataOut<=HASH1Out;
+ `ETH_TX_CTRL_ADR : DataOut<=TXCTRLOut;
+ `ETH_DBG_ADR : DataOut<=dbg_dat; // debug data out -- JB
+ default: DataOut<=32'h0;
+ endcase
+ end
+ else
+ DataOut<=32'h0;
+end
+
+
+assign r_RecSmall = MODEROut[16];
+assign r_Pad = MODEROut[15];
+assign r_HugEn = MODEROut[14];
+assign r_CrcEn = MODEROut[13];
+assign r_DlyCrcEn = MODEROut[12];
+// assign r_Rst = MODEROut[11]; This signal is not used any more
+assign r_FullD = MODEROut[10];
+assign r_ExDfrEn = MODEROut[9];
+assign r_NoBckof = MODEROut[8];
+assign r_LoopBck = MODEROut[7];
+assign r_IFG = MODEROut[6];
+assign r_Pro = MODEROut[5];
+assign r_Iam = MODEROut[4];
+assign r_Bro = MODEROut[3];
+assign r_NoPre = MODEROut[2];
+assign r_TxEn = MODEROut[1] & (TX_BD_NUMOut>0); // Transmission is enabled when there is at least one TxBD.
+assign r_RxEn = MODEROut[0] & (TX_BD_NUMOut<'h80); // Reception is enabled when there is at least one RxBD.
+
+assign r_IPGT[6:0] = IPGTOut[6:0];
+
+assign r_IPGR1[6:0] = IPGR1Out[6:0];
+
+assign r_IPGR2[6:0] = IPGR2Out[6:0];
+
+assign r_MinFL[15:0] = PACKETLENOut[31:16];
+assign r_MaxFL[15:0] = PACKETLENOut[15:0];
+
+assign r_MaxRet[3:0] = COLLCONFOut[19:16];
+assign r_CollValid[5:0] = COLLCONFOut[5:0];
+
+assign r_TxFlow = CTRLMODEROut[2];
+assign r_RxFlow = CTRLMODEROut[1];
+assign r_PassAll = CTRLMODEROut[0];
+
+assign r_MiiNoPre = MIIMODEROut[8];
+assign r_ClkDiv[7:0] = MIIMODEROut[7:0];
+
+assign r_WCtrlData = MIICOMMANDOut[2];
+assign r_RStat = MIICOMMANDOut[1];
+assign r_ScanStat = MIICOMMANDOut[0];
+
+assign r_RGAD[4:0] = MIIADDRESSOut[12:8];
+assign r_FIAD[4:0] = MIIADDRESSOut[4:0];
+
+assign r_CtrlData[15:0] = MIITX_DATAOut[15:0];
+
+assign MIISTATUSOut[31:`ETH_MIISTATUS_WIDTH] = 0;
+assign MIISTATUSOut[2] = NValid_stat ;
+assign MIISTATUSOut[1] = Busy_stat ;
+assign MIISTATUSOut[0] = LinkFail ;
+
+assign r_MAC[31:0] = MAC_ADDR0Out[31:0];
+assign r_MAC[47:32] = MAC_ADDR1Out[15:0];
+assign r_HASH1[31:0] = HASH1Out;
+assign r_HASH0[31:0] = HASH0Out;
+
+assign r_TxBDNum[7:0] = TX_BD_NUMOut[7:0];
+
+assign r_TxPauseTV[15:0] = TXCTRLOut[15:0];
+assign r_TxPauseRq = TXCTRLOut[16];
+
+
+// Synchronizing TxC Interrupt
+always @ (posedge TxClk or posedge Reset)
+begin
+ if(Reset)
+ SetTxCIrq_txclk <= 1'b0;
+ else
+ if(TxCtrlEndFrm & StartTxDone & r_TxFlow)
+ SetTxCIrq_txclk <= 1'b1;
+ else
+ if(ResetTxCIrq_sync2)
+ SetTxCIrq_txclk <= 1'b0;
+end
+
+
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ SetTxCIrq_sync1 <= 1'b0;
+ else
+ SetTxCIrq_sync1 <= SetTxCIrq_txclk;
+end
+
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ SetTxCIrq_sync2 <= 1'b0;
+ else
+ SetTxCIrq_sync2 <= SetTxCIrq_sync1;
+end
+
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ SetTxCIrq_sync3 <= 1'b0;
+ else
+ SetTxCIrq_sync3 <= SetTxCIrq_sync2;
+end
+
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ SetTxCIrq <= 1'b0;
+ else
+ SetTxCIrq <= SetTxCIrq_sync2 & ~SetTxCIrq_sync3;
+end
+
+always @ (posedge TxClk or posedge Reset)
+begin
+ if(Reset)
+ ResetTxCIrq_sync1 <= 1'b0;
+ else
+ ResetTxCIrq_sync1 <= SetTxCIrq_sync2;
+end
+
+always @ (posedge TxClk or posedge Reset)
+begin
+ if(Reset)
+ ResetTxCIrq_sync2 <= 1'b0;
+ else
+ ResetTxCIrq_sync2 <= SetTxCIrq_sync1;
+end
+
+
+// Synchronizing RxC Interrupt
+always @ (posedge RxClk or posedge Reset)
+begin
+ if(Reset)
+ SetRxCIrq_rxclk <= 1'b0;
+ else
+ if(SetPauseTimer & r_RxFlow)
+ SetRxCIrq_rxclk <= 1'b1;
+ else
+ if(ResetRxCIrq_sync2 & (~ResetRxCIrq_sync3))
+ SetRxCIrq_rxclk <= 1'b0;
+end
+
+
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ SetRxCIrq_sync1 <= 1'b0;
+ else
+ SetRxCIrq_sync1 <= SetRxCIrq_rxclk;
+end
+
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ SetRxCIrq_sync2 <= 1'b0;
+ else
+ SetRxCIrq_sync2 <= SetRxCIrq_sync1;
+end
+
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ SetRxCIrq_sync3 <= 1'b0;
+ else
+ SetRxCIrq_sync3 <= SetRxCIrq_sync2;
+end
+
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ SetRxCIrq <= 1'b0;
+ else
+ SetRxCIrq <= SetRxCIrq_sync2 & ~SetRxCIrq_sync3;
+end
+
+always @ (posedge RxClk or posedge Reset)
+begin
+ if(Reset)
+ ResetRxCIrq_sync1 <= 1'b0;
+ else
+ ResetRxCIrq_sync1 <= SetRxCIrq_sync2;
+end
+
+always @ (posedge RxClk or posedge Reset)
+begin
+ if(Reset)
+ ResetRxCIrq_sync2 <= 1'b0;
+ else
+ ResetRxCIrq_sync2 <= ResetRxCIrq_sync1;
+end
+
+always @ (posedge RxClk or posedge Reset)
+begin
+ if(Reset)
+ ResetRxCIrq_sync3 <= 1'b0;
+ else
+ ResetRxCIrq_sync3 <= ResetRxCIrq_sync2;
+end
+
+
+
+// Interrupt generation
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ irq_txb <= 1'b0;
+ else
+ if(TxB_IRQ)
+ irq_txb <= 1'b1;
+ else
+ if(INT_SOURCE_Wr[0] & DataIn[0])
+ irq_txb <= 1'b0;
+end
+
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ irq_txe <= 1'b0;
+ else
+ if(TxE_IRQ)
+ irq_txe <= 1'b1;
+ else
+ if(INT_SOURCE_Wr[0] & DataIn[1])
+ irq_txe <= 1'b0;
+end
+
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ irq_rxb <= 1'b0;
+ else
+ if(RxB_IRQ)
+ irq_rxb <= 1'b1;
+ else
+ if(INT_SOURCE_Wr[0] & DataIn[2])
+ irq_rxb <= 1'b0;
+end
+
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ irq_rxe <= 1'b0;
+ else
+ if(RxE_IRQ)
+ irq_rxe <= 1'b1;
+ else
+ if(INT_SOURCE_Wr[0] & DataIn[3])
+ irq_rxe <= 1'b0;
+end
+
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ irq_busy <= 1'b0;
+ else
+ if(Busy_IRQ)
+ irq_busy <= 1'b1;
+ else
+ if(INT_SOURCE_Wr[0] & DataIn[4])
+ irq_busy <= 1'b0;
+end
+
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ irq_txc <= 1'b0;
+ else
+ if(SetTxCIrq)
+ irq_txc <= 1'b1;
+ else
+ if(INT_SOURCE_Wr[0] & DataIn[5])
+ irq_txc <= 1'b0;
+end
+
+always @ (posedge Clk or posedge Reset)
+begin
+ if(Reset)
+ irq_rxc <= 1'b0;
+ else
+ if(SetRxCIrq)
+ irq_rxc <= 1'b1;
+ else
+ if(INT_SOURCE_Wr[0] & DataIn[6])
+ irq_rxc <= 1'b0;
+end
+
+// Generating interrupt signal
+assign int_o = irq_txb & INT_MASKOut[0] |
+ irq_txe & INT_MASKOut[1] |
+ irq_rxb & INT_MASKOut[2] |
+ irq_rxe & INT_MASKOut[3] |
+ irq_busy & INT_MASKOut[4] |
+ irq_txc & INT_MASKOut[5] |
+ irq_rxc & INT_MASKOut[6] ;
+
+// For reading interrupt status
+assign INT_SOURCEOut = {{(32-`ETH_INT_SOURCE_WIDTH_0){1'b0}}, irq_rxc, irq_txc, irq_busy, irq_rxe, irq_rxb, irq_txe, irq_txb};
+
+
+
+endmodule
rtl/verilog/ethmac/eth_registers.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rtl/verilog/ethmac/eth_crc.v
===================================================================
--- rtl/verilog/ethmac/eth_crc.v (nonexistent)
+++ rtl/verilog/ethmac/eth_crc.v (revision 409)
@@ -0,0 +1,145 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// eth_crc.v ////
+//// ////
+//// This file is part of the Ethernet IP core project ////
+//// http://www.opencores.org/project,ethmac ////
+//// ////
+//// Author(s): ////
+//// - Igor Mohor (igorM@opencores.org) ////
+//// - Novan Hartadi (novan@vlsi.itb.ac.id) ////
+//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////
+//// ////
+//// All additional information is avaliable in the Readme.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.2 2001/10/19 08:43:51 mohor
+// eth_timescale.v changed to timescale.v This is done because of the
+// simulation of the few cores in a one joined project.
+//
+// Revision 1.1 2001/08/06 14:44:29 mohor
+// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
+// Include files fixed to contain no path.
+// File names and module names changed ta have a eth_ prologue in the name.
+// File eth_timescale.v is used to define timescale
+// All pin names on the top module are changed to contain _I, _O or _OE at the end.
+// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
+// and Mdo_OE. The bidirectional signal must be created on the top level. This
+// is done due to the ASIC tools.
+//
+// Revision 1.1 2001/07/30 21:23:42 mohor
+// Directory structure changed. Files checked and joind together.
+//
+// Revision 1.3 2001/06/19 18:16:40 mohor
+// TxClk changed to MTxClk (as discribed in the documentation).
+// Crc changed so only one file can be used instead of two.
+//
+// Revision 1.2 2001/06/19 10:38:07 mohor
+// Minor changes in header.
+//
+// Revision 1.1 2001/06/19 10:27:57 mohor
+// TxEthMAC initial release.
+//
+//
+//
+
+
+`include "timescale.v"
+
+module eth_crc (Clk, Reset, Data, Enable, Initialize, Crc, CrcError);
+
+
+parameter Tp = 1;
+
+input Clk;
+input Reset;
+input [3:0] Data;
+input Enable;
+input Initialize;
+
+output [31:0] Crc;
+output CrcError;
+
+reg [31:0] Crc;
+
+wire [31:0] CrcNext;
+
+
+assign CrcNext[0] = Enable & (Data[0] ^ Crc[28]);
+assign CrcNext[1] = Enable & (Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29]);
+assign CrcNext[2] = Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30]);
+assign CrcNext[3] = Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31]);
+assign CrcNext[4] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[0];
+assign CrcNext[5] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[1];
+assign CrcNext[6] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[ 2];
+assign CrcNext[7] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[3];
+assign CrcNext[8] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[4];
+assign CrcNext[9] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[5];
+assign CrcNext[10] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[6];
+assign CrcNext[11] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[7];
+assign CrcNext[12] = (Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30])) ^ Crc[8];
+assign CrcNext[13] = (Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31])) ^ Crc[9];
+assign CrcNext[14] = (Enable & (Data[3] ^ Data[2] ^ Crc[30] ^ Crc[31])) ^ Crc[10];
+assign CrcNext[15] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[11];
+assign CrcNext[16] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[12];
+assign CrcNext[17] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[13];
+assign CrcNext[18] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[14];
+assign CrcNext[19] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[15];
+assign CrcNext[20] = Crc[16];
+assign CrcNext[21] = Crc[17];
+assign CrcNext[22] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[18];
+assign CrcNext[23] = (Enable & (Data[1] ^ Data[0] ^ Crc[29] ^ Crc[28])) ^ Crc[19];
+assign CrcNext[24] = (Enable & (Data[2] ^ Data[1] ^ Crc[30] ^ Crc[29])) ^ Crc[20];
+assign CrcNext[25] = (Enable & (Data[3] ^ Data[2] ^ Crc[31] ^ Crc[30])) ^ Crc[21];
+assign CrcNext[26] = (Enable & (Data[3] ^ Data[0] ^ Crc[31] ^ Crc[28])) ^ Crc[22];
+assign CrcNext[27] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[23];
+assign CrcNext[28] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[24];
+assign CrcNext[29] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[25];
+assign CrcNext[30] = Crc[26];
+assign CrcNext[31] = Crc[27];
+
+
+always @ (posedge Clk or posedge Reset)
+begin
+ if (Reset)
+ Crc <= 32'hffffffff;
+ else
+ if(Initialize)
+ Crc <= 32'hffffffff;
+ else
+ Crc <= CrcNext;
+end
+
+assign CrcError = Crc[31:0] != 32'hc704dd7b; // CRC not equal to magic number
+
+endmodule
rtl/verilog/ethmac/eth_crc.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rtl/verilog/ethmac/eth_rxstatem.v
===================================================================
--- rtl/verilog/ethmac/eth_rxstatem.v (nonexistent)
+++ rtl/verilog/ethmac/eth_rxstatem.v (revision 409)
@@ -0,0 +1,196 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// eth_rxstatem.v ////
+//// ////
+//// This file is part of the Ethernet IP core project ////
+//// http://www.opencores.org/project,ethmac ////
+//// ////
+//// Author(s): ////
+//// - Igor Mohor (igorM@opencores.org) ////
+//// - Novan Hartadi (novan@vlsi.itb.ac.id) ////
+//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////
+//// ////
+//// All additional information is avaliable in the Readme.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.5 2002/01/23 10:28:16 mohor
+// Link in the header changed.
+//
+// Revision 1.4 2001/10/19 08:43:51 mohor
+// eth_timescale.v changed to timescale.v This is done because of the
+// simulation of the few cores in a one joined project.
+//
+// Revision 1.3 2001/10/18 12:07:11 mohor
+// Status signals changed, Adress decoding changed, interrupt controller
+// added.
+//
+// Revision 1.2 2001/09/11 14:17:00 mohor
+// Few little NCSIM warnings fixed.
+//
+// Revision 1.1 2001/08/06 14:44:29 mohor
+// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
+// Include files fixed to contain no path.
+// File names and module names changed ta have a eth_ prologue in the name.
+// File eth_timescale.v is used to define timescale
+// All pin names on the top module are changed to contain _I, _O or _OE at the end.
+// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
+// and Mdo_OE. The bidirectional signal must be created on the top level. This
+// is done due to the ASIC tools.
+//
+// Revision 1.1 2001/07/30 21:23:42 mohor
+// Directory structure changed. Files checked and joind together.
+//
+// Revision 1.2 2001/07/03 12:55:41 mohor
+// Minor changes because of the synthesys warnings.
+//
+//
+// Revision 1.1 2001/06/27 21:26:19 mohor
+// Initial release of the RxEthMAC module.
+//
+//
+//
+//
+
+
+`include "timescale.v"
+
+
+module eth_rxstatem (MRxClk, Reset, MRxDV, ByteCntEq0, ByteCntGreat2, Transmitting, MRxDEq5, MRxDEqD,
+ IFGCounterEq24, ByteCntMaxFrame, StateData, StateIdle, StatePreamble, StateSFD,
+ StateDrop
+ );
+
+parameter Tp = 1;
+
+input MRxClk;
+input Reset;
+input MRxDV;
+input ByteCntEq0;
+input ByteCntGreat2;
+input MRxDEq5;
+input Transmitting;
+input MRxDEqD;
+input IFGCounterEq24;
+input ByteCntMaxFrame;
+
+output [1:0] StateData;
+output StateIdle;
+output StateDrop;
+output StatePreamble;
+output StateSFD;
+
+reg StateData0;
+reg StateData1;
+reg StateIdle;
+reg StateDrop;
+reg StatePreamble;
+reg StateSFD;
+
+wire StartIdle;
+wire StartDrop;
+wire StartData0;
+wire StartData1;
+wire StartPreamble;
+wire StartSFD;
+
+
+// Defining the next state
+assign StartIdle = ~MRxDV & (StateDrop | StatePreamble | StateSFD | (|StateData));
+
+assign StartPreamble = MRxDV & ~MRxDEq5 & (StateIdle & ~Transmitting);
+
+assign StartSFD = MRxDV & MRxDEq5 & (StateIdle & ~Transmitting | StatePreamble);
+
+assign StartData0 = MRxDV & (StateSFD & MRxDEqD & IFGCounterEq24 | StateData1);
+
+assign StartData1 = MRxDV & StateData0 & (~ByteCntMaxFrame);
+
+assign StartDrop = MRxDV & (StateIdle & Transmitting | StateSFD & ~IFGCounterEq24 & MRxDEqD
+ | StateData0 & ByteCntMaxFrame
+ );
+
+// Rx State Machine
+always @ (posedge MRxClk or posedge Reset)
+begin
+ if(Reset)
+ begin
+ StateIdle <= 1'b0;
+ StateDrop <= 1'b1;
+ StatePreamble <= 1'b0;
+ StateSFD <= 1'b0;
+ StateData0 <= 1'b0;
+ StateData1 <= 1'b0;
+ end
+ else
+ begin
+ if(StartPreamble | StartSFD | StartDrop)
+ StateIdle <= 1'b0;
+ else
+ if(StartIdle)
+ StateIdle <= 1'b1;
+
+ if(StartIdle)
+ StateDrop <= 1'b0;
+ else
+ if(StartDrop)
+ StateDrop <= 1'b1;
+
+ if(StartSFD | StartIdle | StartDrop)
+ StatePreamble <= 1'b0;
+ else
+ if(StartPreamble)
+ StatePreamble <= 1'b1;
+
+ if(StartPreamble | StartIdle | StartData0 | StartDrop)
+ StateSFD <= 1'b0;
+ else
+ if(StartSFD)
+ StateSFD <= 1'b1;
+
+ if(StartIdle | StartData1 | StartDrop)
+ StateData0 <= 1'b0;
+ else
+ if(StartData0)
+ StateData0 <= 1'b1;
+
+ if(StartIdle | StartData0 | StartDrop)
+ StateData1 <= 1'b0;
+ else
+ if(StartData1)
+ StateData1 <= 1'b1;
+ end
+end
+
+assign StateData[1:0] = {StateData1, StateData0};
+
+endmodule
rtl/verilog/ethmac/eth_rxstatem.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rtl/verilog/ethmac/eth_txstatem.v
===================================================================
--- rtl/verilog/ethmac/eth_txstatem.v (nonexistent)
+++ rtl/verilog/ethmac/eth_txstatem.v (revision 409)
@@ -0,0 +1,284 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// eth_txstatem.v ////
+//// ////
+//// This file is part of the Ethernet IP core project ////
+//// http://www.opencores.org/project,ethmac ////
+//// ////
+//// Author(s): ////
+//// - Igor Mohor (igorM@opencores.org) ////
+//// - Novan Hartadi (novan@vlsi.itb.ac.id) ////
+//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////
+//// ////
+//// All additional information is avaliable in the Readme.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.5 2002/10/30 12:54:50 mohor
+// State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.
+//
+// Revision 1.4 2002/01/23 10:28:16 mohor
+// Link in the header changed.
+//
+// Revision 1.3 2001/10/19 08:43:51 mohor
+// eth_timescale.v changed to timescale.v This is done because of the
+// simulation of the few cores in a one joined project.
+//
+// Revision 1.2 2001/09/11 14:17:00 mohor
+// Few little NCSIM warnings fixed.
+//
+// Revision 1.1 2001/08/06 14:44:29 mohor
+// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
+// Include files fixed to contain no path.
+// File names and module names changed ta have a eth_ prologue in the name.
+// File eth_timescale.v is used to define timescale
+// All pin names on the top module are changed to contain _I, _O or _OE at the end.
+// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
+// and Mdo_OE. The bidirectional signal must be created on the top level. This
+// is done due to the ASIC tools.
+//
+// Revision 1.1 2001/07/30 21:23:42 mohor
+// Directory structure changed. Files checked and joind together.
+//
+// Revision 1.3 2001/06/19 18:16:40 mohor
+// TxClk changed to MTxClk (as discribed in the documentation).
+// Crc changed so only one file can be used instead of two.
+//
+// Revision 1.2 2001/06/19 10:38:07 mohor
+// Minor changes in header.
+//
+// Revision 1.1 2001/06/19 10:27:57 mohor
+// TxEthMAC initial release.
+//
+//
+//
+//
+
+
+`include "timescale.v"
+
+
+module eth_txstatem (MTxClk, Reset, ExcessiveDefer, CarrierSense, NibCnt, IPGT, IPGR1,
+ IPGR2, FullD, TxStartFrm, TxEndFrm, TxUnderRun, Collision, UnderRun,
+ StartTxDone, TooBig, NibCntEq7, NibCntEq15, MaxFrame, Pad, CrcEn,
+ NibbleMinFl, RandomEq0, ColWindow, RetryMax, NoBckof, RandomEqByteCnt,
+ StateIdle, StateIPG, StatePreamble, StateData, StatePAD, StateFCS,
+ StateJam, StateJam_q, StateBackOff, StateDefer, StartFCS, StartJam,
+ StartBackoff, StartDefer, DeferIndication, StartPreamble, StartData, StartIPG
+ );
+
+parameter Tp = 1;
+
+input MTxClk;
+input Reset;
+input ExcessiveDefer;
+input CarrierSense;
+input [6:0] NibCnt;
+input [6:0] IPGT;
+input [6:0] IPGR1;
+input [6:0] IPGR2;
+input FullD;
+input TxStartFrm;
+input TxEndFrm;
+input TxUnderRun;
+input Collision;
+input UnderRun;
+input StartTxDone;
+input TooBig;
+input NibCntEq7;
+input NibCntEq15;
+input MaxFrame;
+input Pad;
+input CrcEn;
+input NibbleMinFl;
+input RandomEq0;
+input ColWindow;
+input RetryMax;
+input NoBckof;
+input RandomEqByteCnt;
+
+
+output StateIdle; // Idle state
+output StateIPG; // IPG state
+output StatePreamble; // Preamble state
+output [1:0] StateData; // Data state
+output StatePAD; // PAD state
+output StateFCS; // FCS state
+output StateJam; // Jam state
+output StateJam_q; // Delayed Jam state
+output StateBackOff; // Backoff state
+output StateDefer; // Defer state
+
+output StartFCS; // FCS state will be activated in next clock
+output StartJam; // Jam state will be activated in next clock
+output StartBackoff; // Backoff state will be activated in next clock
+output StartDefer; // Defer state will be activated in next clock
+output DeferIndication;
+output StartPreamble; // Preamble state will be activated in next clock
+output [1:0] StartData; // Data state will be activated in next clock
+output StartIPG; // IPG state will be activated in next clock
+
+wire StartIdle; // Idle state will be activated in next clock
+wire StartPAD; // PAD state will be activated in next clock
+
+
+reg StateIdle;
+reg StateIPG;
+reg StatePreamble;
+reg [1:0] StateData;
+reg StatePAD;
+reg StateFCS;
+reg StateJam;
+reg StateJam_q;
+reg StateBackOff;
+reg StateDefer;
+reg Rule1;
+
+
+// Defining the next state
+assign StartIPG = StateDefer & ~ExcessiveDefer & ~CarrierSense;
+
+assign StartIdle = StateIPG & (Rule1 & NibCnt[6:0] >= IPGT | ~Rule1 & NibCnt[6:0] >= IPGR2);
+
+assign StartPreamble = StateIdle & TxStartFrm & ~CarrierSense;
+
+assign StartData[0] = ~Collision & (StatePreamble & NibCntEq15 | StateData[1] & ~TxEndFrm);
+
+assign StartData[1] = ~Collision & StateData[0] & ~TxUnderRun & ~MaxFrame;
+
+assign StartPAD = ~Collision & StateData[1] & TxEndFrm & Pad & ~NibbleMinFl;
+
+assign StartFCS = ~Collision & StateData[1] & TxEndFrm & (~Pad | Pad & NibbleMinFl) & CrcEn
+ | ~Collision & StatePAD & NibbleMinFl & CrcEn;
+
+assign StartJam = (Collision | UnderRun) & ((StatePreamble & NibCntEq15) | (|StateData[1:0]) | StatePAD | StateFCS);
+
+assign StartBackoff = StateJam & ~RandomEq0 & ColWindow & ~RetryMax & NibCntEq7 & ~NoBckof;
+
+assign StartDefer = StateIPG & ~Rule1 & CarrierSense & NibCnt[6:0] <= IPGR1 & NibCnt[6:0] != IPGR2
+ | StateIdle & CarrierSense
+ | StateJam & NibCntEq7 & (NoBckof | RandomEq0 | ~ColWindow | RetryMax)
+ | StateBackOff & (TxUnderRun | RandomEqByteCnt)
+ | StartTxDone | TooBig;
+
+assign DeferIndication = StateIdle & CarrierSense;
+
+// Tx State Machine
+always @ (posedge MTxClk or posedge Reset)
+begin
+ if(Reset)
+ begin
+ StateIPG <= 1'b0;
+ StateIdle <= 1'b0;
+ StatePreamble <= 1'b0;
+ StateData[1:0] <= 2'b0;
+ StatePAD <= 1'b0;
+ StateFCS <= 1'b0;
+ StateJam <= 1'b0;
+ StateJam_q <= 1'b0;
+ StateBackOff <= 1'b0;
+ StateDefer <= 1'b1;
+ end
+ else
+ begin
+ StateData[1:0] <= StartData[1:0];
+ StateJam_q <= StateJam;
+
+ if(StartDefer | StartIdle)
+ StateIPG <= 1'b0;
+ else
+ if(StartIPG)
+ StateIPG <= 1'b1;
+
+ if(StartDefer | StartPreamble)
+ StateIdle <= 1'b0;
+ else
+ if(StartIdle)
+ StateIdle <= 1'b1;
+
+ if(StartData[0] | StartJam)
+ StatePreamble <= 1'b0;
+ else
+ if(StartPreamble)
+ StatePreamble <= 1'b1;
+
+ if(StartFCS | StartJam)
+ StatePAD <= 1'b0;
+ else
+ if(StartPAD)
+ StatePAD <= 1'b1;
+
+ if(StartJam | StartDefer)
+ StateFCS <= 1'b0;
+ else
+ if(StartFCS)
+ StateFCS <= 1'b1;
+
+ if(StartBackoff | StartDefer)
+ StateJam <= 1'b0;
+ else
+ if(StartJam)
+ StateJam <= 1'b1;
+
+ if(StartDefer)
+ StateBackOff <= 1'b0;
+ else
+ if(StartBackoff)
+ StateBackOff <= 1'b1;
+
+ if(StartIPG)
+ StateDefer <= 1'b0;
+ else
+ if(StartDefer)
+ StateDefer <= 1'b1;
+ end
+end
+
+
+// This sections defines which interpack gap rule to use
+always @ (posedge MTxClk or posedge Reset)
+begin
+ if(Reset)
+ Rule1 <= 1'b0;
+ else
+ begin
+ if(StateIdle | StateBackOff)
+ Rule1 <= 1'b0;
+ else
+ if(StatePreamble | FullD)
+ Rule1 <= 1'b1;
+ end
+end
+
+
+
+endmodule
rtl/verilog/ethmac/eth_txstatem.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rtl/verilog/ethmac/eth_rxaddrcheck.v
===================================================================
--- rtl/verilog/ethmac/eth_rxaddrcheck.v (nonexistent)
+++ rtl/verilog/ethmac/eth_rxaddrcheck.v (revision 409)
@@ -0,0 +1,207 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// eth_rxaddrcheck.v ////
+//// ////
+//// This file is part of the Ethernet IP core project ////
+//// http://www.opencores.org/cores/ethmac/ ////
+//// ////
+//// Author(s): ////
+//// - Bill Dittenhofer (billditt@aol.com) ////
+//// ////
+//// All additional information is avaliable in the Readme.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.8 2002/11/19 17:34:52 mohor
+// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
+// that a frame was received because of the promiscous mode.
+//
+// Revision 1.7 2002/09/04 18:41:06 mohor
+// Bug when last byte of destination address was not checked fixed.
+//
+// Revision 1.6 2002/03/20 15:14:11 mohor
+// When in promiscous mode some frames were not received correctly. Fixed.
+//
+// Revision 1.5 2002/03/02 21:06:32 mohor
+// Log info was missing.
+//
+//
+// Revision 1.1 2002/02/08 12:51:54 ditt
+// Initial release of the ethernet addresscheck module.
+//
+//
+//
+//
+//
+
+
+`include "timescale.v"
+
+
+module eth_rxaddrcheck(MRxClk, Reset, RxData, Broadcast ,r_Bro ,r_Pro,
+ ByteCntEq2, ByteCntEq3, ByteCntEq4, ByteCntEq5,
+ ByteCntEq6, ByteCntEq7, HASH0, HASH1,
+ CrcHash, CrcHashGood, StateData, RxEndFrm,
+ Multicast, MAC, RxAbort, AddressMiss, PassAll,
+ ControlFrmAddressOK
+ );
+
+parameter Tp = 1;
+
+ input MRxClk;
+ input Reset;
+ input [7:0] RxData;
+ input Broadcast;
+ input r_Bro;
+ input r_Pro;
+ input ByteCntEq2;
+ input ByteCntEq3;
+ input ByteCntEq4;
+ input ByteCntEq5;
+ input ByteCntEq6;
+ input ByteCntEq7;
+ input [31:0] HASH0;
+ input [31:0] HASH1;
+ input [5:0] CrcHash;
+ input CrcHashGood;
+ input Multicast;
+ input [47:0] MAC;
+ input [1:0] StateData;
+ input RxEndFrm;
+ input PassAll;
+ input ControlFrmAddressOK;
+
+ output RxAbort;
+ output AddressMiss;
+
+ wire BroadcastOK;
+ wire ByteCntEq2;
+ wire ByteCntEq3;
+ wire ByteCntEq4;
+ wire ByteCntEq5;
+ wire RxAddressInvalid;
+ wire RxCheckEn;
+ wire HashBit;
+ wire [31:0] IntHash;
+ reg [7:0] ByteHash;
+ reg MulticastOK;
+ reg UnicastOK;
+ reg RxAbort;
+ reg AddressMiss;
+
+assign RxAddressInvalid = ~(UnicastOK | BroadcastOK | MulticastOK | r_Pro);
+
+assign BroadcastOK = Broadcast & ~r_Bro;
+
+assign RxCheckEn = | StateData;
+
+ // Address Error Reported at end of address cycle
+ // RxAbort clears after one cycle
+
+always @ (posedge MRxClk or posedge Reset)
+begin
+ if(Reset)
+ RxAbort <= 1'b0;
+ else if(RxAddressInvalid & ByteCntEq7 & RxCheckEn)
+ RxAbort <= 1'b1;
+ else
+ RxAbort <= 1'b0;
+end
+
+
+// This ff holds the "Address Miss" information that is written to the RX BD status.
+always @ (posedge MRxClk or posedge Reset)
+begin
+ if(Reset)
+ AddressMiss <= 1'b0;
+ else if(ByteCntEq7 & RxCheckEn)
+ AddressMiss <= (~(UnicastOK | BroadcastOK | MulticastOK | (PassAll & ControlFrmAddressOK)));
+end
+
+
+// Hash Address Check, Multicast
+always @ (posedge MRxClk or posedge Reset)
+begin
+ if(Reset)
+ MulticastOK <= 1'b0;
+ else if(RxEndFrm | RxAbort)
+ MulticastOK <= 1'b0;
+ else if(CrcHashGood & Multicast)
+ MulticastOK <= HashBit;
+end
+
+
+// Address Detection (unicast)
+// start with ByteCntEq2 due to delay of addres from RxData
+always @ (posedge MRxClk or posedge Reset)
+begin
+ if(Reset)
+ UnicastOK <= 1'b0;
+ else
+ if(RxCheckEn & ByteCntEq2)
+ UnicastOK <= RxData[7:0] == MAC[47:40];
+ else
+ if(RxCheckEn & ByteCntEq3)
+ UnicastOK <= ( RxData[7:0] == MAC[39:32]) & UnicastOK;
+ else
+ if(RxCheckEn & ByteCntEq4)
+ UnicastOK <= ( RxData[7:0] == MAC[31:24]) & UnicastOK;
+ else
+ if(RxCheckEn & ByteCntEq5)
+ UnicastOK <= ( RxData[7:0] == MAC[23:16]) & UnicastOK;
+ else
+ if(RxCheckEn & ByteCntEq6)
+ UnicastOK <= ( RxData[7:0] == MAC[15:8]) & UnicastOK;
+ else
+ if(RxCheckEn & ByteCntEq7)
+ UnicastOK <= ( RxData[7:0] == MAC[7:0]) & UnicastOK;
+ else
+ if(RxEndFrm | RxAbort)
+ UnicastOK <= 1'b0;
+end
+
+assign IntHash = (CrcHash[5])? HASH1 : HASH0;
+
+always@(CrcHash or IntHash)
+begin
+ case(CrcHash[4:3])
+ 2'b00: ByteHash = IntHash[7:0];
+ 2'b01: ByteHash = IntHash[15:8];
+ 2'b10: ByteHash = IntHash[23:16];
+ 2'b11: ByteHash = IntHash[31:24];
+ endcase
+end
+
+assign HashBit = ByteHash[CrcHash[2:0]];
+
+
+endmodule
rtl/verilog/ethmac/eth_rxaddrcheck.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: rtl/verilog/ethmac/xilinx_dist_ram_16x32.v
===================================================================
--- rtl/verilog/ethmac/xilinx_dist_ram_16x32.v (nonexistent)
+++ rtl/verilog/ethmac/xilinx_dist_ram_16x32.v (revision 409)
@@ -0,0 +1,50 @@
+module xilinx_dist_ram_16x32
+(
+ data_out,
+ we,
+ data_in,
+ read_address,
+ write_address,
+ wclk
+);
+ output [31:0] data_out;
+ input we, wclk;
+ input [31:0] data_in;
+ input [3:0] write_address, read_address;
+
+ wire [3:0] waddr = write_address ;
+ wire [3:0] raddr = read_address ;
+
+ RAM16X1D ram00 (.DPO(data_out[0]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[0]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
+ RAM16X1D ram01 (.DPO(data_out[1]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[1]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
+ RAM16X1D ram02 (.DPO(data_out[2]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[2]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
+ RAM16X1D ram03 (.DPO(data_out[3]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[3]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
+ RAM16X1D ram04 (.DPO(data_out[4]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[4]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
+ RAM16X1D ram05 (.DPO(data_out[5]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[5]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
+ RAM16X1D ram06 (.DPO(data_out[6]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[6]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
+ RAM16X1D ram07 (.DPO(data_out[7]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[7]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
+ RAM16X1D ram08 (.DPO(data_out[8]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[8]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
+ RAM16X1D ram09 (.DPO(data_out[9]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[9]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
+ RAM16X1D ram10 (.DPO(data_out[10]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[10]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
+ RAM16X1D ram11 (.DPO(data_out[11]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[11]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
+ RAM16X1D ram12 (.DPO(data_out[12]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[12]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
+ RAM16X1D ram13 (.DPO(data_out[13]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[13]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
+ RAM16X1D ram14 (.DPO(data_out[14]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[14]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
+ RAM16X1D ram15 (.DPO(data_out[15]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[15]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
+ RAM16X1D ram16 (.DPO(data_out[16]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[16]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
+ RAM16X1D ram17 (.DPO(data_out[17]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[17]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
+ RAM16X1D ram18 (.DPO(data_out[18]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[18]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
+ RAM16X1D ram19 (.DPO(data_out[19]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[19]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
+ RAM16X1D ram20 (.DPO(data_out[20]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[20]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
+ RAM16X1D ram21 (.DPO(data_out[21]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[21]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
+ RAM16X1D ram22 (.DPO(data_out[22]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[22]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
+ RAM16X1D ram23 (.DPO(data_out[23]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[23]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
+ RAM16X1D ram24 (.DPO(data_out[24]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[24]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
+ RAM16X1D ram25 (.DPO(data_out[25]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[25]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
+ RAM16X1D ram26 (.DPO(data_out[26]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[26]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
+ RAM16X1D ram27 (.DPO(data_out[27]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[27]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
+ RAM16X1D ram28 (.DPO(data_out[28]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[28]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
+ RAM16X1D ram29 (.DPO(data_out[29]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[29]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
+ RAM16X1D ram30 (.DPO(data_out[30]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[30]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
+ RAM16X1D ram31 (.DPO(data_out[31]), .SPO(), .A0(waddr[0]), .A1(waddr[1]), .A2(waddr[2]), .A3(waddr[3]), .D(data_in[31]), .DPRA0(raddr[0]), .DPRA1(raddr[1]), .DPRA2(raddr[2]), .DPRA3(raddr[3]), .WCLK(wclk), .WE(we));
+endmodule
rtl/verilog/ethmac/xilinx_dist_ram_16x32.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: doc/orpsoc.texi
===================================================================
--- doc/orpsoc.texi (revision 408)
+++ doc/orpsoc.texi (revision 409)
@@ -605,6 +605,20 @@
The same set of options for RTL tests available in the reference design should available in this build. @xref{Running A Set Of Specific Reference Design RTL Tests}.
+Options specific to the ORDB1A3PE1500 build.
+
+@table @code
+
+@item PRELOAD_RAM
+Set to '1' to enable loading of the software image into RAM at the beginning of simulation.
+
+If the chosen bootROM program (set via a define in software header file in the board's @code{sw/board/include} path) will jump straight to RAM to begin execution, then the software image will need to be in RAM for the simulation to work. This define @emph{must} be used in that case for the simulation to do anything.
+
+
+@end table
+
+
+
@node ORDB1A3PE1500 Synthesis
@subsection Synthesis
/sw/tests/eth/board/eth-ping.c
File deleted
/sw/tests/eth/board/Makefile
File deleted
/sw/tests/eth/board/eth-phy-mii.h
File deleted
/sw/tests/eth/board/open-eth.h
File deleted
/sw/tests/eth/sim/eth-rxtx.c
File deleted
/sw/tests/eth/sim/eth-rx.c
File deleted
/sw/tests/eth/sim/eth-tx.c
File deleted
/sw/tests/eth/sim/Makefile
File deleted
/sw/tests/ethmac/board/ethmac-ping.c
0,0 → 1,1964
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Interrupt-driven Ethernet MAC test code for use on board //// |
//// //// |
//// Description //// |
//// Controllable ping program - also responds to ARP requests //// |
//// //// |
//// Author(s): //// |
//// - jb, jb@orsoc.se, with parts taken from Linux kernel //// |
//// open_eth driver. //// |
//// //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
#include "cpu-utils.h" |
//#include "spr-defs.h" |
#include "board.h" |
#include "int.h" |
#include "uart.h" |
#include "ethmac.h" |
#include "printf.h" |
#include "eth-phy-mii.h" |
|
volatile unsigned tx_done; |
static int next_tx_buf_num; |
|
//#define OUR_IP_BYTES 0xc0,0xa8,0x64,0x9b // 192.168.100.155 |
//#define OUR_IP_LONG 0xc0a8649b |
|
//#define OUR_IP_BYTES 0xc0,0xa8,0x0,0x14 // 192.168.0.20 |
//#define OUR_IP_LONG 0xc0a80014 |
|
#define OUR_IP_BYTES 0xc0,0xa8,0x1,0x2 // 192.168.1.2 |
#define OUR_IP_LONG 0xc0a80102 |
|
static char our_ip[4] = {OUR_IP_BYTES}; |
|
//#define DEST_IP_BYTES 0xc0,0xa8,0x64,0x69 // 192 .168.100.105 |
#define DEST_IP_BYTES 0xc0,0xa8,0x01,0x08 // 192 .168.1.8 |
|
/* Functions in this file */ |
void ethmac_setup(void); |
void oeth_printregs(void); |
void ethphy_init(void); |
void oeth_dump_bds(); |
/* Interrupt functions */ |
void oeth_interrupt(void); |
static void oeth_rx(void); |
static void oeth_tx(void); |
|
#define NEVER_PRINT_PACKET 1 |
|
#define DISABLE_PRINTF 0 |
|
#if DISABLE_PRINTF==1 |
#undef printf |
#endif |
/* Let the ethernet packets use a space beginning here for buffering */ |
#define ETH_BUFF_BASE 0x01000000 |
|
|
#define RXBUFF_PREALLOC 1 |
#define TXBUFF_PREALLOC 1 |
//#undef RXBUFF_PREALLOC |
//#undef TXBUFF_PREALLOC |
|
/* The transmitter timeout |
*/ |
#define TX_TIMEOUT (2*HZ) |
|
/* Buffer number (must be 2^n) |
*/ |
#define OETH_RXBD_NUM 8 |
#define OETH_TXBD_NUM 8 |
#define OETH_RXBD_NUM_MASK (OETH_RXBD_NUM-1) |
#define OETH_TXBD_NUM_MASK (OETH_TXBD_NUM-1) |
|
/* Buffer size |
*/ |
#define OETH_RX_BUFF_SIZE 2048 |
#define OETH_TX_BUFF_SIZE 2048 |
|
/* OR32 Page size def */ |
#define PAGE_SHIFT 13 |
#define PAGE_SIZE (1UL << PAGE_SHIFT) |
|
/* How many buffers per page |
*/ |
#define OETH_RX_BUFF_PPGAE (PAGE_SIZE/OETH_RX_BUFF_SIZE) |
#define OETH_TX_BUFF_PPGAE (PAGE_SIZE/OETH_TX_BUFF_SIZE) |
|
/* How many pages is needed for buffers |
*/ |
#define OETH_RX_BUFF_PAGE_NUM (OETH_RXBD_NUM/OETH_RX_BUFF_PPGAE) |
#define OETH_TX_BUFF_PAGE_NUM (OETH_TXBD_NUM/OETH_TX_BUFF_PPGAE) |
|
/* Buffer size (if not XXBUF_PREALLOC |
*/ |
#define MAX_FRAME_SIZE 0x600 |
//#define MAX_FRAME_SIZE 2500 |
|
/* The buffer descriptors track the ring buffers. |
*/ |
struct oeth_private { |
//struct sk_buff* rx_skbuff[OETH_RXBD_NUM]; |
//struct sk_buff* tx_skbuff[OETH_TXBD_NUM]; |
|
unsigned short tx_next;/* Next buffer to be sent */ |
unsigned short tx_last;/* Next buffer to be checked if packet sent */ |
unsigned short tx_full;/* Buffer ring fuul indicator */ |
unsigned short rx_cur; /* Next buffer to be checked if packet received */ |
|
oeth_regs *regs; /* Address of controller registers. */ |
oeth_bd *rx_bd_base; /* Address of Rx BDs. */ |
oeth_bd *tx_bd_base; /* Address of Tx BDs. */ |
|
// struct net_device_stats stats; |
}; |
|
|
void oeth_printregs(void) |
{ |
volatile oeth_regs *regs; |
regs = (oeth_regs *)(OETH_REG_BASE); |
|
printf("Oeth regs: Mode Register : 0x%lx\n", |
(unsigned long) regs->moder); /* Mode Register */ |
printf("Oeth regs: Interrupt Source Register 0x%lx\n", |
(unsigned long) regs->int_src); /* Interrupt Source Register */ |
printf("Oeth regs: Interrupt Mask Register 0x%lx\n", |
(unsigned long) regs->int_mask); /* Interrupt Mask Register */ |
printf("Oeth regs: Back to Bak Inter Packet Gap Register 0x%lx\n", |
(unsigned long) regs->ipgt); /* Back to Bak Inter Packet Gap Register */ |
printf("Oeth regs: Non Back to Back Inter Packet Gap Register 1 0x%lx\n", |
(unsigned long) regs->ipgr1); /* Non Back to Back Inter Packet Gap Register 1 */ |
printf("Oeth regs: Non Back to Back Inter Packet Gap Register 2 0x%lx\n", |
(unsigned long) regs->ipgr2); /* Non Back to Back Inter Packet Gap Register 2 */ |
printf("Oeth regs: Packet Length Register (min. and max.) 0x%lx\n", |
(unsigned long) regs->packet_len); /* Packet Length Register (min. and max.) */ |
printf("Oeth regs: Collision and Retry Configuration Register 0x%lx\n", |
(unsigned long) regs->collconf); /* Collision and Retry Configuration Register */ |
printf("Oeth regs: Transmit Buffer Descriptor Number Register 0x%lx\n", |
(unsigned long) regs->tx_bd_num); /* Transmit Buffer Descriptor Number Register */ |
printf("Oeth regs: Control Module Mode Register 0x%lx\n", |
(unsigned long) regs->ctrlmoder); /* Control Module Mode Register */ |
printf("Oeth regs: MII Mode Register 0x%lx\n", |
(unsigned long) regs->miimoder); /* MII Mode Register */ |
printf("Oeth regs: MII Command Register 0x%lx\n", |
(unsigned long) regs->miicommand); /* MII Command Register */ |
printf("Oeth regs: MII Address Register 0x%lx\n", |
(unsigned long) regs->miiaddress); /* MII Address Register */ |
printf("Oeth regs: MII Transmit Data Register 0x%lx\n", |
(unsigned long) regs->miitx_data); /* MII Transmit Data Register */ |
printf("Oeth regs: MII Receive Data Register 0x%lx\n", |
(unsigned long) regs->miirx_data); /* MII Receive Data Register */ |
printf("Oeth regs: MII Status Register 0x%lx\n", |
(unsigned long) regs->miistatus); /* MII Status Register */ |
printf("Oeth regs: MAC Individual Address Register 0 0x%lx\n", |
(unsigned long) regs->mac_addr0); /* MAC Individual Address Register 0 */ |
printf("Oeth regs: MAC Individual Address Register 1 0x%lx\n", |
(unsigned long) regs->mac_addr1); /* MAC Individual Address Register 1 */ |
printf("Oeth regs: Hash Register 0 0x%lx\n", |
(unsigned long) regs->hash_addr0); /* Hash Register 0 */ |
printf("Oeth regs: Hash Register 1 0x%lx\n", |
(unsigned long) regs->hash_addr1); /* Hash Register 1 */ |
|
} |
|
static int last_char; |
|
void spin_cursor(void) |
{ |
#ifdef RTLSIM |
return; |
#endif |
volatile unsigned int i; // So the loop doesn't get optimised away |
printf(" \r"); |
if (last_char == 0) |
printf("/"); |
else if (last_char == 1) |
printf("-"); |
else if (last_char == 2) |
printf("\\"); |
else if (last_char == 3) |
printf("|"); |
else if (last_char == 4) |
printf("/"); |
else if (last_char == 5) |
printf("-"); |
else if (last_char == 6) |
printf("\\"); |
else if (last_char == 7) |
{ |
printf("|"); |
last_char=-1; |
} |
|
last_char++; |
|
for(i=0;i<150000;i++); |
|
} |
|
#define PHYNUM 7 |
|
/* Scan the MIIM bus for PHYs */ |
void scan_ethphys(void) |
{ |
unsigned int phynum,regnum, i; |
|
volatile oeth_regs *regs; |
regs = (oeth_regs *)(OETH_REG_BASE); |
|
regs->miitx_data = 0; |
|
for(phynum=0;phynum<32;phynum++) |
{ |
for (regnum=0;regnum<8;regnum++) |
{ |
printf("scan_ethphys: phy %d r%d ",phynum, regnum); |
|
/* Now actually perform the read on the MIIM bus*/ |
regs->miiaddress = (regnum << 8) | phynum; /* Basic Control Register */ |
regs->miicommand = OETH_MIICOMMAND_RSTAT; |
|
while(!(regs->miistatus & OETH_MIISTATUS_BUSY)); /* Wait for command to be registered*/ |
|
regs->miicommand = 0; |
|
while(regs->miistatus & OETH_MIISTATUS_BUSY); |
|
printf("%x\n",regs->miirx_data); |
} |
} |
} |
|
|
/* Scan the MIIM bus for PHYs */ |
void scan_ethphy(unsigned int phynum) |
{ |
unsigned int regnum, i; |
|
volatile oeth_regs *regs; |
regs = (oeth_regs *)(OETH_REG_BASE); |
|
regs->miitx_data = 0; |
|
for (regnum=0;regnum<29;regnum++) |
{ |
printf("scan_ethphy%d: r%x ",phynum, regnum); |
|
/* Now actually perform the read on the MIIM bus*/ |
regs->miiaddress = (regnum << 8) | phynum; /* Basic Control Register */ |
regs->miicommand = OETH_MIICOMMAND_RSTAT; |
|
while(!(regs->miistatus & OETH_MIISTATUS_BUSY)); /* Wait for command to be registered*/ |
|
regs->miicommand = 0; |
|
while(regs->miistatus & OETH_MIISTATUS_BUSY); |
|
printf("%x\n",regs->miirx_data); |
} |
|
} |
|
|
|
void ethmac_scanstatus(void) |
{ |
volatile oeth_regs *regs; |
regs = (oeth_regs *)(OETH_REG_BASE); |
|
|
printf("Oeth: regs->miistatus %x regs->miirx_data %x\n",regs->miistatus, regs->miirx_data); |
regs->miiaddress = 0; |
regs->miitx_data = 0; |
regs->miicommand = OETH_MIICOMMAND_SCANSTAT; |
printf("Oeth: regs->miiaddress %x regs->miicommand %x\n",regs->miiaddress, regs->miicommand); |
//regs->miicommand = 0; |
volatile int i; for(i=0;i<1000;i++); |
while(regs->miistatus & OETH_MIISTATUS_BUSY) ; |
//spin_cursor(); |
//printf("\r"); |
//or32_exit(0); |
} |
|
void |
eth_mii_write(char phynum, short regnum, short data) |
{ |
static volatile oeth_regs *regs = (oeth_regs *)(OETH_REG_BASE); |
regs->miiaddress = (regnum << 8) | phynum; |
regs->miitx_data = data; |
regs->miicommand = OETH_MIICOMMAND_WCTRLDATA; |
regs->miicommand = 0; |
while(regs->miistatus & OETH_MIISTATUS_BUSY); |
} |
|
short |
eth_mii_read(char phynum, short regnum) |
{ |
static volatile oeth_regs *regs = (oeth_regs *)(OETH_REG_BASE); |
regs->miiaddress = (regnum << 8) | phynum; |
regs->miicommand = OETH_MIICOMMAND_RSTAT; |
regs->miicommand = 0; |
while(regs->miistatus & OETH_MIISTATUS_BUSY); |
|
return regs->miirx_data; |
} |
|
|
void |
ethphy_reset(int phynum) |
{ |
eth_mii_write(phynum, MII_BMCR, |
(eth_mii_read(phynum,MII_BMCR)|BMCR_RESET)); |
} |
|
|
void |
ethphy_reneg(int phynum) |
{ |
eth_mii_write(phynum, MII_BMCR, |
(eth_mii_read(phynum,MII_BMCR)|BMCR_ANRESTART)); |
} |
|
void |
ethphy_set_10mbit(int phynum) |
{ |
// Hardset PHY to just use 10Mbit mode |
short cr = eth_mii_read(phynum, MII_BMCR); |
cr &= ~BMCR_ANENABLE; // Clear auto negotiate bit |
cr &= ~BMCR_SPEED100; // Clear fast eth. bit |
eth_mii_write(phynum, MII_BMCR, cr); |
} |
|
void |
ethphy_set_100mbit(int phynum) |
{ |
// Hardset PHY to just use 10Mbit mode |
short cr = eth_mii_read(phynum, MII_BMCR); |
cr &= !BMCR_ANENABLE; // Clear auto negotiate bit |
cr |= BMCR_SPEED100; // Clear fast eth. bit |
eth_mii_write(phynum, MII_BMCR, cr); |
} |
|
void |
ethphy_set_autoneg(int phynum) |
{ |
// Hardset PHY to just use 10Mbit mode |
short cr = eth_mii_read(phynum, MII_BMCR); |
cr |= BMCR_ANENABLE; // Clear auto negotiate bit |
eth_mii_write(phynum, MII_BMCR, cr); |
} |
|
|
|
void m88e111_config_init(int phyaddr) |
{ |
short ctl; |
short adv; |
#if 1 |
// Soft reset |
eth_mii_write(phyaddr, MII_BMCR, BMCR_RESET); |
while(eth_mii_read(phyaddr, MII_BMCR) & BMCR_RESET); |
|
ctl = eth_mii_read(phyaddr, MII_BMCR); |
ctl &= ~(BMCR_SPD2); |
eth_mii_write(phyaddr, MII_BMCR, ctl); |
|
eth_mii_read(phyaddr, MII_ADVERTISE); |
adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_1000XFULL |
|ADVERTISE_1000XHALF | ADVERTISE_1000XPAUSE | |
ADVERTISE_1000XPSE_ASYM); |
adv |= ADVERTISE_10HALF; |
adv |= ADVERTISE_10FULL; |
adv |= ADVERTISE_100HALF; |
adv |= ADVERTISE_100FULL; |
eth_mii_write(phyaddr, MII_ADVERTISE, adv); |
// Disable gigabit??? |
adv = eth_mii_read(phyaddr, MII_M1011_PHY_SPEC_CONTROL); |
adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP | |
MII_1000BASETCONTROL_HALFDUPLEXCAP); |
eth_mii_write(phyaddr, MII_M1011_PHY_SPEC_CONTROL, adv); |
// Even more disable gigabit?! |
adv = eth_mii_read(phyaddr, MII_CTRL1000); |
adv &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); |
eth_mii_write(phyaddr, MII_CTRL1000, adv); |
|
// Restart autoneg |
printf("Resetting phy...\n"); |
eth_mii_write(phyaddr, MII_BMCR, BMCR_RESET); |
ctl = eth_mii_read(phyaddr, MII_BMCR); |
ctl |= (BMCR_ANENABLE | BMCR_ANRESTART); |
eth_mii_write(phyaddr, MII_BMCR, ctl); |
#endif |
|
#if 0 |
// Adapted from kernel: drivers/net/phy/marvell.c |
// Soft reset |
eth_mii_write(phyaddr, MII_BMCR, BMCR_RESET); |
|
eth_mii_write(phyaddr, 0x1d, 0x1f); |
eth_mii_write(phyaddr, 0x1e, 0x200c); |
eth_mii_write(phyaddr, 0x1d, 0x5); |
eth_mii_write(phyaddr, 0x1e, 0); |
eth_mii_write(phyaddr, 0x1e, 0x100); |
#define MII_M1011_PHY_SCR 0x10 |
#define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060 |
eth_mii_write(phyaddr, MII_M1011_PHY_SCR, |
MII_M1011_PHY_SCR_AUTO_CROSS); |
#define MII_M1111_PHY_LED_CONTROL 0x18 |
#define MII_M1111_PHY_LED_DIRECT 0x4100 |
eth_mii_write(phyaddr, MII_M1111_PHY_LED_CONTROL, |
MII_M1111_PHY_LED_DIRECT); |
|
adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | |
ADVERTISE_PAUSE_ASYM); |
adv |= ADVERTISE_10HALF; |
adv |= ADVERTISE_10FULL; |
adv |= ADVERTISE_100HALF; |
adv |= ADVERTISE_100FULL; |
adv |= ADVERTISE_PAUSE_CAP; |
adv |= ADVERTISE_PAUSE_ASYM; |
eth_mii_write(phyaddr, MII_ADVERTISE, adv); |
|
|
ctl = eth_mii_read(phyaddr, MII_BMCR); |
ctl |= (BMCR_ANENABLE | BMCR_ANRESTART); |
eth_mii_write(phyaddr, MII_BMCR, ctl); |
|
#endif |
|
#if 0 |
ctl = eth_mii_read(phyaddr, MII_BMCR); |
ctl &= ~(BMCR_ANENABLE); // Disable autoneg... |
// Try forcing config |
ctl = BMCR_SPEED100 | BMCR_FULLDPLX; |
eth_mii_write(phyaddr, MII_BMCR, ctl); |
|
|
|
|
#endif |
|
} |
|
|
void ethphy_print_status(int phyaddr) |
{ |
short regnum, ctl; |
int bitnum; |
int bitset; |
printf("phyaddr %d\n",phyaddr); |
for (regnum = 0;regnum<16; regnum++) |
{ |
ctl = eth_mii_read(phyaddr, regnum); |
printf("\treg 0x%x: ", regnum); |
switch(regnum) |
{ |
case 0: |
printf("basic control\n"); |
for(bitnum = 0; bitnum<16;bitnum++) |
{ |
bitset = !!(ctl & (1<<bitnum)); |
switch(bitnum) |
{ |
case 0: |
printf("\t\tbit%d:\t%d \t(disable transmitter)\n",bitnum,bitset); |
break; |
case 6: |
printf("\t\tbit%d:\t%d \t(msb speed (1000))\n",bitnum,bitset); |
break; |
case 7: |
printf("\t\tbit%d:\t%d \t(collision test)\n",bitnum,bitset); |
break; |
case 8: |
printf("\t\tbit%d:\t%d \t(duplex mode)\n",bitnum,bitset); |
break; |
case 9: |
printf("\t\tbit%d:\t%d \t(restart autoneg)\n",bitnum,bitset); |
break; |
case 10: |
printf("\t\tbit%d:\t%d \t(isloate)\n",bitnum,bitset); |
break; |
case 11: |
printf("\t\tbit%d:\t%d \t(power down)\n",bitnum,bitset); |
break; |
case 12: |
printf("\t\tbit%d:\t%d \t(autoneg enable)\n",bitnum,bitset); |
break; |
case 13: |
printf("\t\tbit%d:\t%d \t(speed select)\n",bitnum,bitset); |
break; |
case 14: |
printf("\t\tbit%d:\t%d \t(loop back)\n",bitnum,bitset); |
break; |
case 15: |
printf("\t\tbit%d:\t%d \t(reset)\n",bitnum,bitset); |
break; |
default: |
break; |
} |
} |
break; |
case 1: |
printf("basic status\n"); |
for(bitnum = 0; bitnum<16;bitnum++) |
{ |
bitset = !!(ctl & (1<<bitnum)); |
switch(bitnum) |
{ |
case 0: |
printf("\t\tbit%d:\t%d \t(extend capability)\n",bitnum,bitset); |
break; |
case 1: |
printf("\t\tbit%d:\t%d \t(jabber detect)\n",bitnum,bitset); |
break; |
case 2: |
printf("\t\tbit%d:\t%d \t(link status)\n",bitnum,bitset); |
break; |
case 3: |
printf("\t\tbit%d:\t%d \t(autoneg capability)\n",bitnum,bitset); |
break; |
case 4: |
printf("\t\tbit%d:\t%d \t(remote fault)\n",bitnum,bitset); |
break; |
case 5: |
printf("\t\tbit%d:\t%d \t(autoneg complete)\n",bitnum,bitset); |
break; |
case 6: |
printf("\t\tbit%d:\t%d \t(no preamble)\n",bitnum,bitset); |
break; |
case 11: |
printf("\t\tbit%d:\t%d \t(10base-t half dup.)\n",bitnum,bitset); |
break; |
case 12: |
printf("\t\tbit%d:\t%d \t(10base-t full dup.)\n",bitnum,bitset); |
break; |
case 13: |
printf("\t\tbit%d:\t%d \t(100base-t half dup.)\n",bitnum,bitset); |
break; |
case 14: |
printf("\t\tbit%d:\t%d \t(100base-t full dup.)\n",bitnum,bitset); |
break; |
case 15: |
printf("\t\tbit%d:\t%d \t(100base-t4)\n",bitnum,bitset); |
break; |
default: |
break; |
|
} |
} |
break; |
case 4: |
printf("autoneg advertise reg\n"); |
for(bitnum = 0; bitnum<16;bitnum++) |
{ |
bitset = !!(ctl & (1<<bitnum)); |
switch(bitnum) |
{ |
case 5: |
printf("\t\tbit%d:\t%d \t(10mbps cap.)\n",bitnum,bitset); |
break; |
case 6: |
printf("\t\tbit%d:\t%d \t(10base-5 full dup. cap.)\n",bitnum,bitset); |
break; |
case 7: |
printf("\t\tbit%d:\t%d \t(100base-tx cap.)\n",bitnum,bitset); |
break; |
case 8: |
printf("\t\tbit%d:\t%d \t(100base-tx full dup. cap.)\n",bitnum,bitset); |
break; |
case 9: |
printf("\t\tbit%d:\t%d \t(100base-t4 cap.)\n",bitnum,bitset); |
break; |
case 10: |
printf("\t\tbit%d:\t%d \t(pause cap.)\n",bitnum,bitset); |
break; |
case 13: |
printf("\t\tbit%d:\t%d \t(remote fault sup.)\n",bitnum,bitset); |
break; |
case 15: |
printf("\t\tbit%d:\t%d \t(next page cap.)\n",bitnum,bitset); |
break; |
|
default: |
break; |
} |
} |
break; |
case 5: |
printf("autoneg link partner ability\n"); |
for(bitnum = 0; bitnum<16;bitnum++) |
{ |
bitset = !!(ctl & (1<<bitnum)); |
switch(bitnum) |
{ |
case 5: |
printf("\t\tbit%d:\t%d \t(10mbps cap.)\n",bitnum,bitset); |
break; |
case 6: |
printf("\t\tbit%d:\t%d \t(10base-5 full dup. cap.)\n",bitnum,bitset); |
break; |
case 7: |
printf("\t\tbit%d:\t%d \t(100base-tx cap.)\n",bitnum,bitset); |
break; |
case 8: |
printf("\t\tbit%d:\t%d \t(100base-tx full dup. cap.)\n",bitnum,bitset); |
break; |
case 9: |
printf("\t\tbit%d:\t%d \t(100base-t4 cap.)\n",bitnum,bitset); |
break; |
case 10: |
printf("\t\tbit%d:\t%d \t(pause cap bit0)\n",bitnum,bitset); |
break; |
case 11: |
printf("\t\tbit%d:\t%d \t(pause cap bit1)\n",bitnum,bitset); |
break; |
|
case 13: |
printf("\t\tbit%d:\t%d \t(remote fault sup.)\n",bitnum,bitset); |
break; |
case 14: |
printf("\t\tbit%d:\t%d \t(acknowledge)\n",bitnum,bitset); |
break; |
case 15: |
printf("\t\tbit%d:\t%d \t(next page cap.)\n",bitnum,bitset); |
break; |
|
default: |
break; |
} |
} |
break; |
case 9: |
printf("1000mbit advertise\n"); |
for(bitnum = 0; bitnum<16;bitnum++) |
{ |
bitset = !!(ctl & (1<<bitnum)); |
switch(bitnum) |
{ |
case 8: |
printf("\t\tbit%d:\t%d \t(1000base-t half dup)\n",bitnum,bitset); |
break; |
case 9: |
printf("\t\tbit%d:\t%d \t(1000base-t full dup)\n",bitnum,bitset); |
break; |
default: |
break; |
} |
} |
break; |
case 0xf: |
printf("extended status\n"); |
for(bitnum = 0; bitnum<16;bitnum++) |
{ |
bitset = !!(ctl & (1<<bitnum)); |
switch(bitnum) |
{ |
case 12: |
printf("\t\tbit%d:\t%d \t(1000mb half dup.)\n",bitnum,bitset); |
break; |
case 13: |
printf("\t\tbit%d:\t%d \t(1000mb full dup.)\n",bitnum,bitset); |
break; |
default: |
break; |
} |
} |
break; |
/* case 1: |
for(bitnum = 0; bitnum<16;bitnum++) |
{ |
bitset = !!(ctl & (1<<bitnum)); |
switch(bitnum) |
{ |
case 0: |
printf("\t\tbit%d:\t%d \t()\n",bitnum,bitset); |
break; |
default: |
break; |
} |
} |
break; |
*/ |
default: |
printf("ignored\n"); |
break; |
} |
} |
|
|
|
} |
|
void ethphy_init(void) |
{ |
|
/* Init the Alaska 88E1111 Phy */ |
char alaska88e1111_ml501_phynum = 0x7; |
m88e111_config_init(alaska88e1111_ml501_phynum); |
|
return; |
|
/* Init, reset */ |
short ctl = eth_mii_read(alaska88e1111_ml501_phynum, MII_BMCR); |
ctl &= ~(BMCR_FULLDPLX|BMCR_SPEED100|BMCR_SPD2|BMCR_ANENABLE); |
ctl |= BMCR_SPEED100; // 100MBit |
ctl |= BMCR_FULLDPLX; // Full duplex |
eth_mii_write(alaska88e1111_ml501_phynum, MII_BMCR, ctl); |
|
// Setup Autoneg |
short adv = eth_mii_read(alaska88e1111_ml501_phynum, MII_ADVERTISE); |
adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_1000XFULL |
|ADVERTISE_1000XHALF | ADVERTISE_1000XPAUSE | |
ADVERTISE_1000XPSE_ASYM); |
adv |= ADVERTISE_10HALF; |
adv |= ADVERTISE_10FULL; |
adv |= ADVERTISE_100HALF; |
adv |= ADVERTISE_100FULL; |
eth_mii_write(alaska88e1111_ml501_phynum, MII_ADVERTISE, adv); |
// Disable gigabit??? |
adv = eth_mii_read(alaska88e1111_ml501_phynum, MII_M1011_PHY_SPEC_CONTROL); |
adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP | |
MII_1000BASETCONTROL_HALFDUPLEXCAP); |
eth_mii_write(alaska88e1111_ml501_phynum, MII_M1011_PHY_SPEC_CONTROL, adv); |
// Even more disable gigabit?! |
adv = eth_mii_read(alaska88e1111_ml501_phynum, MII_CTRL1000); |
adv &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); |
eth_mii_write(alaska88e1111_ml501_phynum, MII_CTRL1000, adv); |
|
// Restart autoneg |
printf("Resetting phy...\n"); |
ctl = eth_mii_read(alaska88e1111_ml501_phynum, MII_BMCR); |
ctl |= (BMCR_ANENABLE | BMCR_ANRESTART); |
eth_mii_write(alaska88e1111_ml501_phynum, MII_BMCR, ctl); |
|
printf("\nOeth: PHY control reg: 0x%.4x\n", |
eth_mii_read(alaska88e1111_ml501_phynum, MII_BMCR)); |
printf("Oeth: PHY control reg: 0x%.4x\n", |
eth_mii_read(alaska88e1111_ml501_phynum, MII_BMSR)); |
printf("Oeth: PHY id0: 0x%.4x\n", |
eth_mii_read(alaska88e1111_ml501_phynum, MII_PHYSID1)); |
printf("Oeth: PHY id1: 0x%.4x\n", |
eth_mii_read(alaska88e1111_ml501_phynum, MII_PHYSID2)); |
printf("Oeth: PHY adv: 0x%.4x\n", |
eth_mii_read(alaska88e1111_ml501_phynum, MII_ADVERTISE)); |
printf("Oeth: PHY lpa: 0x%.4x\n", |
eth_mii_read(alaska88e1111_ml501_phynum, MII_LPA)); |
printf("Oeth: PHY physpec: 0x%.4x\n", |
eth_mii_read(alaska88e1111_ml501_phynum, MII_M1011_PHY_SPEC_CONTROL)); |
printf("Oeth: PHY expansion: 0x%.4x\n", |
eth_mii_read(alaska88e1111_ml501_phynum, MII_EXPANSION )); |
printf("Oeth: PHY ctrl1000: 0x%.4x\n", |
eth_mii_read(alaska88e1111_ml501_phynum, MII_CTRL1000)); |
printf("Oeth: PHY stat1000: 0x%.4x\n", |
eth_mii_read(alaska88e1111_ml501_phynum, MII_STAT1000)); |
printf("Oeth: PHY estatus: 0x%.4x\n", |
eth_mii_read(alaska88e1111_ml501_phynum, MII_ESTATUS)); |
|
|
} |
|
|
void ethmac_setup(void) |
{ |
// from arch/or32/drivers/open_eth.c |
volatile oeth_regs *regs; |
|
regs = (oeth_regs *)(OETH_REG_BASE); |
|
/*printf("\nbefore reset\n\n"); |
oeth_printregs();*/ |
|
/* Reset MII mode module */ |
regs->miimoder = OETH_MIIMODER_RST; /* MII Reset ON */ |
regs->miimoder &= ~OETH_MIIMODER_RST; /* MII Reset OFF */ |
regs->miimoder = 0x64; /* Clock divider for MII Management interface */ |
|
/* Reset the controller. |
*/ |
regs->moder = OETH_MODER_RST; /* Reset ON */ |
regs->moder &= ~OETH_MODER_RST; /* Reset OFF */ |
|
//printf("\nafter reset\n\n"); |
//oeth_printregs(); |
|
/* Setting TXBD base to OETH_TXBD_NUM. |
*/ |
regs->tx_bd_num = OETH_TXBD_NUM; |
|
|
/* Set min/max packet length |
*/ |
//regs->packet_len = 0x00400600; |
regs->packet_len = (0x0040 << 16) | (MAX_FRAME_SIZE & 0xffff); |
|
/* Set IPGT register to recomended value |
*/ |
regs->ipgt = 0x12; |
|
/* Set IPGR1 register to recomended value |
*/ |
regs->ipgr1 = 0x0000000c; |
|
/* Set IPGR2 register to recomended value |
*/ |
regs->ipgr2 = 0x00000012; |
|
/* Set COLLCONF register to recomended value |
*/ |
regs->collconf = 0x000f003f; |
|
/* Set control module mode |
*/ |
#if 0 |
regs->ctrlmoder = OETH_CTRLMODER_TXFLOW | OETH_CTRLMODER_RXFLOW; |
#else |
regs->ctrlmoder = 0; |
#endif |
|
/* Clear MIIM registers */ |
regs->miitx_data = 0; |
regs->miiaddress = 0; |
regs->miicommand = 0; |
|
regs->mac_addr1 = ETH_MACADDR0 << 8 | ETH_MACADDR1; |
regs->mac_addr0 = ETH_MACADDR2 << 24 | ETH_MACADDR3 << 16 | ETH_MACADDR4 << 8 | ETH_MACADDR5; |
|
/* Clear all pending interrupts |
*/ |
regs->int_src = 0xffffffff; |
|
/* Promisc, IFG, CRCEn |
*/ |
regs->moder |= OETH_MODER_PRO | OETH_MODER_PAD | OETH_MODER_IFG | OETH_MODER_CRCEN | OETH_MODER_FULLD; |
|
/* Enable interrupt sources. |
*/ |
|
regs->int_mask = OETH_INT_MASK_TXB | |
OETH_INT_MASK_TXE | |
OETH_INT_MASK_RXF | |
OETH_INT_MASK_RXE | |
OETH_INT_MASK_BUSY | |
OETH_INT_MASK_TXC | |
OETH_INT_MASK_RXC; |
#ifndef RTLSIM |
printf("\nafter config\n\n"); |
oeth_printregs(); |
#endif |
// Buffer setup stuff |
volatile oeth_bd *tx_bd, *rx_bd; |
int i,j,k; |
|
/* Initialize TXBD pointer |
*/ |
tx_bd = (volatile oeth_bd *)OETH_BD_BASE; |
|
/* Initialize RXBD pointer |
*/ |
rx_bd = ((volatile oeth_bd *)OETH_BD_BASE) + OETH_TXBD_NUM; |
|
/* Preallocated ethernet buffer setup */ |
unsigned long mem_addr = ETH_BUFF_BASE; /* Defined at top */ |
|
/* Setup for TX buffers*/ |
for(i = 0, k = 0; i < OETH_TX_BUFF_PAGE_NUM; i++) { |
for(j = 0; j < OETH_TX_BUFF_PPGAE; j++, k++) { |
//tx_bd[k].len_status = OETH_TX_BD_PAD | OETH_TX_BD_CRC | OETH_RX_BD_IRQ; |
tx_bd[k].len_status = OETH_TX_BD_PAD | OETH_TX_BD_CRC; |
tx_bd[k].addr = mem_addr; |
mem_addr += OETH_TX_BUFF_SIZE; |
} |
} |
tx_bd[OETH_TXBD_NUM - 1].len_status |= OETH_TX_BD_WRAP; |
|
/* Setup for RX buffers */ |
for(i = 0, k = 0; i < OETH_RX_BUFF_PAGE_NUM; i++) { |
for(j = 0; j < OETH_RX_BUFF_PPGAE; j++, k++) { |
rx_bd[k].len_status = OETH_RX_BD_EMPTY | OETH_RX_BD_IRQ; /* Enable interrupt */ |
rx_bd[k].addr = mem_addr; |
mem_addr += OETH_RX_BUFF_SIZE; |
} |
} |
rx_bd[OETH_RXBD_NUM - 1].len_status |= OETH_RX_BD_WRAP; /* Final buffer has wrap bit set */ |
|
/* Enable receiver and transmiter |
*/ |
regs->moder |= OETH_MODER_RXEN | OETH_MODER_TXEN; |
|
next_tx_buf_num = 0; // init tx buffer pointer |
|
return; |
} |
|
void |
ethmac_togglehugen(void) |
{ |
|
volatile oeth_regs *regs; |
regs = (oeth_regs *)(OETH_REG_BASE); |
|
regs->moder ^= OETH_MODER_HUGEN; // Toggle huge packet enable |
|
if (regs->moder & OETH_MODER_HUGEN) // If we just enabled huge packets |
regs->packet_len = (0x0040 << 16) | (((64*1024)-4) & 0xffff); |
else |
// back to normal |
regs->packet_len = (0x0040 << 16) | (MAX_FRAME_SIZE & 0xffff); |
|
return; |
|
} |
|
void |
oeth_reset_tx_bd_pointer(void) |
{ |
printf("Resetting TX BD pointer\n"); |
// from arch/or32/drivers/open_eth.c |
volatile oeth_regs *regs; |
regs = (oeth_regs *)(OETH_REG_BASE); |
|
// Toggle TXEN bit, resetting TX BD number |
regs->moder &= OETH_MODER_TXEN; |
regs->moder |= OETH_MODER_TXEN; |
|
next_tx_buf_num = 0; // init tx buffer pointer |
|
} |
|
|
|
/* Find the next available transmit buffer */ |
struct oeth_bd* get_next_tx_bd() |
{ |
|
int i; |
volatile oeth_bd *tx_bd; |
tx_bd = (volatile oeth_bd *)OETH_BD_BASE; /* Search from beginning*/ |
|
/* Go through the TX buffs, search for unused one */ |
for(i = next_tx_buf_num; i < OETH_TXBD_NUM; i++) { |
|
if(!(tx_bd[i].len_status & OETH_TX_BD_READY)) /* Looking for buffer NOT ready for transmit. ie we can manipulate it */ |
{ |
#if NEVER_PRINT_PACKET==0 |
printf("Oeth: Using TX_bd at 0x%lx\n",(unsigned long)&tx_bd[i]); |
#endif |
if (next_tx_buf_num == OETH_TXBD_NUM-1) next_tx_buf_num = 0; |
else next_tx_buf_num++; |
|
return (struct oeth_bd*) &tx_bd[i]; |
} |
|
if ((i == OETH_TXBD_NUM-1) && (next_tx_buf_num != 0)) |
i = 0; |
|
} |
|
printf("No free tx buffers\n"); |
/* Set to null our returned buffer */ |
tx_bd = (volatile oeth_bd *) 0; |
return (struct oeth_bd*) tx_bd; |
|
} |
|
/* print packet contents */ |
static void |
oeth_print_packet(unsigned long add, int len) |
{ |
#if NEVER_PRINT_PACKET==1 |
return; |
#endif |
|
int truncate = (len > 256); |
int length_to_print = truncate ? 256 : len; |
|
int i; |
printf("\nipacket: add = %lx len = %d\n", add, len); |
for(i = 0; i < length_to_print; i++) { |
if(!(i % 8)) |
printf(" "); |
if(!(i % 16)) |
printf("\n"); |
printf(" %.2x", *(((unsigned char *)add) + i)); |
|
} |
printf("\n"); |
|
if (truncate) |
printf("\ttruncated....\n"); |
|
} |
|
/* Setup buffer descriptors with data */ |
/* length is in BYTES */ |
void tx_packet(void* data, int length) |
{ |
volatile oeth_regs *regs; |
regs = (oeth_regs *)(OETH_REG_BASE); |
|
volatile oeth_bd *tx_bd; |
volatile int i; |
|
|
tx_bd = (volatile oeth_bd *)OETH_BD_BASE; |
tx_bd = (struct oeth_bd*) &tx_bd[next_tx_buf_num]; |
|
/*if((tx_bd = (volatile oeth_bd *) get_next_tx_bd()) == NULL) |
{ |
printf("No more TX buffers available\n"); |
return; |
} |
*/ |
#if NEVER_PRINT_PACKET==0 |
printf("Oeth: Using TX_bd buffer address: 0x%lx\n",(unsigned long) tx_bd->addr); |
#endif |
|
/* Clear all of the status flags. |
*/ |
tx_bd->len_status &= ~OETH_TX_BD_STATS; |
|
/* If the frame is short, tell CPM to pad it. |
*/ |
#define ETH_ZLEN 60 /* Min. octets in frame sans FCS */ |
if (length <= ETH_ZLEN) |
tx_bd->len_status |= OETH_TX_BD_PAD; |
else |
tx_bd->len_status &= ~OETH_TX_BD_PAD; |
|
//printf("Oeth: Copying %d bytes from 0x%lx to TX_bd buffer at 0x%lx\n",length,(unsigned long) data,(unsigned long) tx_bd->addr); |
|
/* Copy the data into the transmit buffer, byte at a time */ |
char* data_p = (char*) data; |
char* data_b = (char*) tx_bd->addr; |
for(i=0;i<length;i++) |
{ |
data_b[i] = data_p[i]; |
} |
//printf("Oeth: Data copied to buffer\n"); |
|
/* Set the length of the packet's data in the buffer descriptor */ |
tx_bd->len_status = (tx_bd->len_status & 0x0000ffff) | |
((length&0xffff) << 16); |
|
//oeth_print_packet(tx_bd->addr, (tx_bd->len_status >> 16)); |
|
/* Send it on its way. Tell controller its ready, interrupt when sent |
* and to put the CRC on the end. |
*/ |
tx_bd->len_status |= (OETH_TX_BD_READY | OETH_TX_BD_CRC | OETH_TX_BD_IRQ); |
|
next_tx_buf_num = (next_tx_buf_num + 1) & OETH_TXBD_NUM_MASK; |
|
return; |
|
|
} |
|
/* enable RX, loop waiting for arrived packets and print them out */ |
void oeth_monitor_rx(void) |
{ |
volatile oeth_regs *regs; |
regs = (oeth_regs *)(OETH_REG_BASE); |
|
/* Set RXEN in MAC MODER */ |
regs->moder = OETH_MODER_RXEN | regs->moder; |
|
|
volatile oeth_bd *rx_bd; |
rx_bd = ((volatile oeth_bd *)OETH_BD_BASE) + OETH_TXBD_NUM; |
|
volatile int i; |
|
for(i=0;i<OETH_RXBD_NUM;i++) |
{ |
if (!(rx_bd[i].len_status & OETH_RX_BD_EMPTY)) /* Not empty */ |
{ |
// Something in this buffer! |
printf("Oeth: RX in buf %d - len_status: 0x%lx\n",i, rx_bd[i].len_status); |
oeth_print_packet(rx_bd[i].addr, rx_bd[i].len_status >> 16); |
/* Clear recieved bit */ |
rx_bd[i].len_status |= OETH_RX_BD_EMPTY; |
printf("\t end of packet\n\n"); |
} |
} |
} |
|
/* Print out all buffer descriptors */ |
void oeth_dump_bds() |
{ |
unsigned long* bd_base = (unsigned long*) OETH_BD_BASE; |
|
int i; |
for(i=0;i<OETH_TXBD_NUM;i++) |
{ |
printf("oeth: tx_bd%d: len_status: %lx ",i,*bd_base++); |
printf("addr: %lx\n", *bd_base++); |
} |
|
for(i=0;i<OETH_RXBD_NUM;i++) |
{ |
printf("oeth: rx_bd%d: len_status: %lx ",i,*bd_base++); |
printf("addr: %lx\n", *bd_base++); |
} |
|
} |
|
|
|
char broadcast_ping_packet[] = { |
0xff,0xff,0xff,0xff,0xff,0xff, /*SRC MAC*/ |
0x00, 0x12, 0x34, 0x56, 0x78, 0x9a, /*SRC MAC*/ |
0x08,0x00, |
0x45, |
0x00, |
// 0x00,0x54, /* length */ |
0x01,0x1c, /* length */ |
0x00,0x00, |
0x40, |
0x00, |
0x40, |
0x01, |
0xee,0xf5, |
OUR_IP_BYTES, /* Source IP */ |
0xc0,0xa8,0x64,0xff, /* Dest. IP */ |
/* ICMP Message body */ |
0x08,0x00,0x7d,0x65,0xa7,0x20,0x00,0x01,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14, |
15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39, |
40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64, |
65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89, |
90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110, |
111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129, |
130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148, |
149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167, |
168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186, |
187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205, |
206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224, |
225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243, |
244,245,246,247,248,249,250,251,252,253,254,255}; |
|
|
char big_ping_packet[] = { |
0x00, 0x24, 0xe8, 0x91, 0x7c, 0x0d, /*DST MAC*/ |
//0xff,0xff,0xff,0xff,0xff,0xff, /*SRC MAC*/ |
0x00, 0x12, 0x34, 0x56, 0x78, 0x9a, /*SRC MAC*/ |
0x08,0x00, |
0x45, |
0x00, |
0x05,0xdc, /* length */ |
0x00,0x00, |
0x40, |
0x00, |
0x40, |
0x01, |
0xea,0xcb, /* Header checksum */ |
OUR_IP_BYTES, /* Source IP */ |
DEST_IP_BYTES, /* Dest. IP */ |
/* ICMP Message body */ |
0x08,0x00, /* Type */ |
0x04,0x48, /* ICMP checksum */ |
0x02,0x00, /* Identifier */ |
0x3a,0x00, /* sequence number */ |
0x61,0x62,0x63,0x64,0x65,0x66,0x67, |
0x68,0x69,0x6a,0x6b,0x6c,0x6d,0x6e,0x6f,0x70,0x71,0x72,0x73,0x74,0x75,0x76, |
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0x68,0x69,0x6a,0x6b,0x6c,0x6d,0x6e,0x6f,0x70,0x71,0x72,0x73,0x74,0x75,0x76, |
0x77,0x61,0x62,0x63,0x64,0x65,0x66,0x67,0x68,0x69,0x6a,0x6b,0x6c,0x6d,0x6e, |
0x6f,0x70,0x71,0x72,0x73,0x74,0x75,0x76,0x77,0x61,0x62,0x63,0x64,0x65,0x66, |
0x67,0x68,0x69,0x6a,0x6b,0x6c,0x6d,0x6e,0x6f,0x70,0x71,0x72,0x73,0x74,0x75, |
0x76,0x77,0x61,0x62,0x63,0x64,0x65,0x66,0x67,0x68,0x69,0x6a,0x6b,0x6c,0x6d, |
0x6e,0x6f,0x70,0x71,0x72,0x73,0x74,0x75,0x76,0x77}; |
|
|
/* This should be 98 bytes big */ |
char ping_packet[] = { |
0x00, 0x24, 0xe8, 0x91, 0x7c, 0x0d, /*DST MAC*/ |
//0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /*DST MAC*/ |
0x00, 0x12, 0x34, 0x56, 0x78, 0x9a, /*SRC MAC*/ |
0x08, 0x00, /*TYPE*/ |
/* IP */ |
0x45, /* Version, header length*/ |
0x00, /* Differentiated services field */ |
0x00, 0x54, /* Total length */ |
0x00, 0x00, /* Identification */ |
0x40, /* Flags */ |
0x00, /* Fragment offset */ |
0x40, /* Time to live */ |
0x01, /* Protocol (0x01 = ICMP */ |
0xf0, 0x53, /* Header checksum */ |
//0xc0, 0xa8, 0x64, 0xDE, /* Source IP */ |
OUR_IP_BYTES, /* Source IP */ |
DEST_IP_BYTES, /* Dest. IP */ |
/* ICMP Message body */ |
0x08, 0x00, 0x9a, 0xd4, 0xc8, 0x18, 0x00, 0x01, 0xd9, 0x8c, 0x54, |
0x4a, 0x7b, 0x37, 0x01, 0x00, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, |
0x0e, 0x0f, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, |
0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23, |
0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, |
0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37 |
}; |
|
void send_test_packet() |
{ |
|
/*Send packet */ |
//tx_packet((void*) ping_packet, 102); |
tx_packet((void*) broadcast_ping_packet, 102); |
|
} |
|
|
/* The interrupt handler. |
*/ |
void |
oeth_interrupt(void) |
{ |
|
volatile oeth_regs *regs; |
regs = (oeth_regs *)(OETH_REG_BASE); |
|
uint int_events; |
int serviced; |
|
serviced = 0; |
|
/* Get the interrupt events that caused us to be here. |
*/ |
int_events = regs->int_src; |
regs->int_src = int_events; |
|
|
/* Indicate busy */ |
if (int_events & OETH_INT_BUSY) |
{ |
printf("\tBusy flag\n"); |
/* |
printf("\n=tx_ | %x | %x | %x | %x | %x | %x | %x | %x\n", |
((oeth_bd *)(OETH_BD_BASE))->len_status, |
((oeth_bd *)(OETH_BD_BASE+8))->len_status, |
((oeth_bd *)(OETH_BD_BASE+16))->len_status, |
((oeth_bd *)(OETH_BD_BASE+24))->len_status, |
((oeth_bd *)(OETH_BD_BASE+32))->len_status, |
((oeth_bd *)(OETH_BD_BASE+40))->len_status, |
((oeth_bd *)(OETH_BD_BASE+48))->len_status, |
((oeth_bd *)(OETH_BD_BASE+56))->len_status); |
*/ |
printf("=rx_ | %x | %x | %x | %x | %x | %x | %x | %x\n", |
((oeth_bd *)(OETH_BD_BASE+64))->len_status, |
((oeth_bd *)(OETH_BD_BASE+64+8))->len_status, |
((oeth_bd *)(OETH_BD_BASE+64+16))->len_status, |
((oeth_bd *)(OETH_BD_BASE+64+24))->len_status, |
((oeth_bd *)(OETH_BD_BASE+64+32))->len_status, |
((oeth_bd *)(OETH_BD_BASE+64+40))->len_status, |
((oeth_bd *)(OETH_BD_BASE+64+48))->len_status, |
((oeth_bd *)(OETH_BD_BASE+64+56))->len_status); |
|
printf("=int | txb %d | txe %d | rxb %d | rxe %d | busy %d\n", |
(int_events & OETH_INT_TXB) > 0, |
(int_events & OETH_INT_TXE) > 0, |
(int_events & OETH_INT_RXF) > 0, |
(int_events & OETH_INT_RXE) > 0, |
(int_events & OETH_INT_BUSY) > 0); |
} |
|
/* Handle receive event in its own function. |
*/ |
if (int_events & (OETH_INT_RXF | OETH_INT_RXE)) { |
serviced |= 0x1; |
oeth_rx(); |
} |
|
/* Handle transmit event in its own function. |
*/ |
if (int_events & (OETH_INT_TXB | OETH_INT_TXE)) { |
serviced |= 0x2; |
oeth_tx(); |
serviced |= 0x2; |
|
} |
|
return; |
} |
|
// ARP stuff |
|
typedef unsigned long IPaddr_t; |
|
/* |
* Ethernet header |
*/ |
typedef struct { |
unsigned char et_dest[6]; /* Destination node */ |
unsigned char et_src[6]; /* Source node */ |
unsigned short et_protlen; /* Protocol or length */ |
unsigned char et_dsap; /* 802 DSAP */ |
unsigned char et_ssap; /* 802 SSAP */ |
unsigned char et_ctl; /* 802 control */ |
unsigned char et_snap1; /* SNAP */ |
unsigned char et_snap2; |
unsigned char et_snap3; |
unsigned short et_prot; /* 802 protocol */ |
} Ethernet_t; |
|
#define ETHER_HDR_SIZE 14 /* Ethernet header size */ |
#define E802_HDR_SIZE 22 /* 802 ethernet header size */ |
#define PROT_IP 0x0800 /* IP protocol */ |
#define PROT_ARP 0x0806 /* IP ARP protocol */ |
#define PROT_RARP 0x8035 /* IP ARP protocol */ |
|
|
/* |
* Internet Protocol (IP) header. |
*/ |
typedef struct { |
unsigned char ip_hl_v; /* header length and version*/ |
unsigned char ip_tos; /* type of service */ |
unsigned short ip_len; /* total length */ |
unsigned short ip_id; /* identification */ |
unsigned short ip_off; /* fragment offset field */ |
unsigned char ip_ttl; /* time to live */ |
unsigned char ip_p; /* protocol */ |
unsigned short ip_sum; /* checksum */ |
IPaddr_t ip_src; /* Source IP address */ |
IPaddr_t ip_dst; /* Destination IP address */ |
unsigned short udp_src; /* UDP source port */ |
unsigned short udp_dst; /* UDP destination port */ |
unsigned short udp_len; /* Length of UDP packet */ |
unsigned short udp_xsum; /* Checksum */ |
} IP_t; |
|
#define IP_HDR_SIZE_NO_UDP (sizeof (IP_t) - 8) |
#define IP_HDR_SIZE (sizeof (IP_t)) |
|
#define IPPROTO_ICMP 1 /* Internet Control Message Protocol */ |
#define IPPROTO_UDP 17 /* User Datagram Protocol */ |
|
|
/* |
* ICMP stuff (just enough to handle (host) redirect messages) |
*/ |
#define ICMP_REDIRECT 5 /* Redirect (change route) */ |
|
/* Codes for REDIRECT. */ |
#define ICMP_REDIR_NET 0 /* Redirect Net */ |
#define ICMP_REDIR_HOST 1 /* Redirect Host */ |
|
#define ICMP_TYPE_ECHO_REPLY 0x00 |
#define ICMP_TYPE_ECHO_REQ 0x08 |
|
unsigned char ip_reply_packet[0x600] __attribute__ ((aligned (4))); // Save space for a full ICMP reply packet |
|
typedef struct { |
unsigned char type; |
unsigned char code; |
unsigned short checksum; |
union { |
struct { |
unsigned short id; |
unsigned short sequence; |
} echo; |
unsigned long gateway; |
struct { |
unsigned short __unused; |
unsigned short mtu; |
} frag; |
} un; |
} ICMP_t; |
|
// From http://lkml.indiana.edu/hypermail/linux/kernel/9612.3/0060.html |
unsigned short calculate_checksum(char* dats, unsigned int len) |
{ |
unsigned int itr; |
unsigned long accum = 0; |
unsigned long longsum; |
|
// Sum all pairs of data |
for(itr=0;itr<(len & ~0x1);itr+=2) |
accum += (unsigned long)(((dats[itr]<<8)&0xff00)|(dats[itr+1]&0x00ff)); |
|
if (len & 0x1) // Do leftover |
accum += (unsigned long) ((dats[itr-1]<<8)&0xff00); |
|
longsum = (unsigned long) (accum & 0xffff); |
longsum += (unsigned long) (accum >> 16); // Sum the carries |
longsum += (longsum >> 16); |
return (unsigned short)((longsum ^ 0xffff) & 0xffff); |
|
} |
|
void |
packet_check_icmp_header(void * pkt) |
{ |
Ethernet_t * eth_pkt; |
IP_t * ip; |
ICMP_t * icmp; |
|
unsigned int zero = 0; |
|
eth_pkt = (Ethernet_t *) pkt; |
|
// Check it's for our MAC |
char* eth_pkt_dst_mac = (char*) eth_pkt; |
if (!( |
((eth_pkt_dst_mac[0] == (char) ETH_MACADDR0) && // Either our MAC |
(eth_pkt_dst_mac[1] == (char) ETH_MACADDR1) && |
(eth_pkt_dst_mac[2] == (char) ETH_MACADDR2) && |
(eth_pkt_dst_mac[3] == (char) ETH_MACADDR3) && |
(eth_pkt_dst_mac[4] == (char) ETH_MACADDR4) && |
(eth_pkt_dst_mac[5] == (char) ETH_MACADDR5)) || |
((eth_pkt_dst_mac[0] == (char) 0xff) && // or broadcast MAC |
(eth_pkt_dst_mac[1] == (char) 0xff) && |
(eth_pkt_dst_mac[2] == (char) 0xff) && |
(eth_pkt_dst_mac[3] == (char) 0xff) && |
(eth_pkt_dst_mac[4] == (char) 0xff) && |
(eth_pkt_dst_mac[5] == (char) 0xff)) |
) |
) |
|
return ; |
|
// Check it's an IP packet |
if (!(eth_pkt->et_protlen == PROT_IP)) |
return ; |
|
pkt += ETHER_HDR_SIZE; // Skip eth header stuff |
|
ip = (IP_t*) pkt; |
|
// Check if this is an ICMP packet |
if (!(ip->ip_p == IPPROTO_ICMP)) |
return ; |
|
// Check if this is for our IP, get pointer to the DST IP part of IP header |
// which is end of IP section - 4 bytes |
char * internet_protocol_adr = ((unsigned char*)ip + (IP_HDR_SIZE_NO_UDP-4)); |
|
if (!((internet_protocol_adr[0] == our_ip[0]) && |
(internet_protocol_adr[1] == our_ip[1]) && |
(internet_protocol_adr[2] == our_ip[2]) && |
(internet_protocol_adr[3] == our_ip[3]))) |
return ; |
|
pkt += IP_HDR_SIZE_NO_UDP; |
|
icmp = (ICMP_t*) pkt; |
|
// Currently we only support replying to echo (ping) requests |
|
// Check for ICMP echo request type |
if (!(icmp->type == ICMP_TYPE_ECHO_REQ)) |
return; |
|
// Go ahead and construct a response packet |
// Setup pointers |
Ethernet_t * reply_pkt = (Ethernet_t *) &ip_reply_packet[0]; |
IP_t * reply_IP = (IP_t*) &ip_reply_packet[ETHER_HDR_SIZE]; |
ICMP_t * reply_ICMP = (ICMP_t*) &ip_reply_packet[ETHER_HDR_SIZE+ |
IP_HDR_SIZE_NO_UDP]; |
// Setup Ethernet header |
// Copy source MAC to destination MAC |
memcpy( (void*)&reply_pkt->et_dest , (void*)ð_pkt->et_src , 6); |
reply_pkt->et_src[0] = ETH_MACADDR0; |
reply_pkt->et_src[1] = ETH_MACADDR1; |
reply_pkt->et_src[2] = ETH_MACADDR2; |
reply_pkt->et_src[3] = ETH_MACADDR3; |
reply_pkt->et_src[4] = ETH_MACADDR4; |
reply_pkt->et_src[5] = ETH_MACADDR5; |
reply_pkt->et_protlen = PROT_IP; |
|
// IP header |
reply_IP->ip_hl_v = 0x45; // version 4, 20 byte long header, not 100% on this! |
reply_IP->ip_tos = 0x00 ; // ToS (DSCP) - usually used for QoS, set to 0 |
unsigned short ip_indicated_length; |
// First copy total length indicated in received IP header to a variable, we |
// need it again later... |
memcpy ((void*)&ip_indicated_length, (void*)&ip->ip_len, 2); |
// Now copy into reply IP packet |
memcpy ((void*)&reply_IP->ip_len, (void*)&ip_indicated_length, 2); |
memcpy ((void*)&reply_IP->ip_id, (void*)&ip->ip_id, 2); // Copy ID |
reply_IP->ip_ttl = 0x40; // Packet TTL - 64, typical value |
reply_IP->ip_p = IPPROTO_ICMP; // Duh, this is an ICMP echo reply |
// Clear header checksum for now |
|
memcpy ((void*)&reply_IP->ip_sum, (void*)&zero, 2); |
memcpy ((void*)&reply_IP->ip_src, (void*)&our_ip[0], 4); // Copy in our IP |
// "...return to sender... budupbadah address ....KNOWN ..." |
// WTF this memcpy() fails with alignment error...(?!?!) |
//memcpy (&reply_IP->ip_dst, &ip->ip_src, sizeof(IPaddr_t)); |
//...OK then, do it manually..... |
unsigned char *ptr1, *ptr2; |
ptr1 = &reply_IP->ip_dst; ptr2 = &ip->ip_src; |
ptr1[0] = ptr2[0]; |
ptr1[1] = ptr2[1]; |
ptr1[2] = ptr2[2]; |
ptr1[3] = ptr2[3]; |
|
// Now calculate the CRC, probably move this to a fuction.... |
unsigned short ip_sum = 0; // Initialise checksum value to 0 |
int itr; |
char* sum_data_ptr = (char*)reply_IP; |
ip_sum = calculate_checksum(sum_data_ptr,IP_HDR_SIZE_NO_UDP); |
/* |
for(itr=0;itr<IP_HDR_SIZE_NO_UDP;itr+=2) |
ip_sum += (((sum_data_ptr[itr]<<8)&0xff00)|(sum_data_ptr[itr+1]&0x00ff)); |
while (ip_sum>>16) |
ip_sum = (ip_sum & 0xffff) + (ip_sum>>16); |
ip_sum = ~ip_sum; |
*/ |
|
memcpy ((void*)&reply_IP->ip_sum, (void*)&ip_sum, 2); |
|
// |
// Now construct ICMP part of packet |
// |
reply_ICMP->type = ICMP_TYPE_ECHO_REPLY; // ping response type |
reply_ICMP->code = icmp->code; // ICMP code same as sender (is this right?) |
|
// Clear ICMP checksum for now |
memcpy ((void*)&reply_ICMP->checksum, (void*)&zero, 2); |
|
// |
// Simply copy in the data from the received packet |
// Figure out how much there is after the checksum |
// It should be : |
// length_from_received_IP_header - IP_header_length - initial_ICMP_packet_dat |
// |
unsigned long icmp_data_length = ip_indicated_length - IP_HDR_SIZE_NO_UDP - 4; |
memcpy ((void*)&reply_ICMP->un,(void*)&icmp->un, icmp_data_length); |
|
// Now calculate checksum for ICMP data |
unsigned short icmp_sum = 0; |
sum_data_ptr = (char*)reply_ICMP; |
icmp_sum = calculate_checksum(sum_data_ptr,icmp_data_length+4); |
|
memcpy ((void*)&reply_ICMP->checksum, (void*)&icmp_sum, 2); |
|
// All done! |
|
tx_packet((void*)ip_reply_packet,ETHER_HDR_SIZE+ip_indicated_length); |
|
} |
|
|
|
/* |
* Address Resolution Protocol (ARP) header. |
*/ |
typedef struct |
{ |
unsigned short ar_hrd; /* Format of hardware address */ |
# define ARP_ETHER 1 /* Ethernet hardware address */ |
unsigned short ar_pro; /* Format of protocol address */ |
unsigned char ar_hln; /* Length of hardware address */ |
unsigned char ar_pln; /* Length of protocol address */ |
unsigned short ar_op; /* Operation */ |
# define ARPOP_REQUEST 1 /* Request to resolve address */ |
# define ARPOP_REPLY 2 /* Response to previous request */ |
|
# define RARPOP_REQUEST 3 /* Request to resolve address */ |
# define RARPOP_REPLY 4 /* Response to previous request */ |
|
/* |
* The remaining fields are variable in size, according to |
* the sizes above, and are defined as appropriate for |
* specific hardware/protocol combinations. |
*/ |
unsigned char ar_data[0]; |
#if 0 |
unsigned char ar_sha[]; /* Sender hardware address */ |
unsigned char ar_spa[]; /* Sender protocol address */ |
unsigned char ar_tha[]; /* Target hardware address */ |
unsigned char ar_tpa[]; /* Target protocol address */ |
#endif /* 0 */ |
} ARP_t; |
|
#define ARP_HDR_SIZE (8+20) /* Size assuming ethernet */ |
|
char arp_reply_packet[(ETHER_HDR_SIZE + ARP_HDR_SIZE)]; |
|
void |
packet_check_arp_header(void * pkt) |
{ |
Ethernet_t * eth_pkt; |
|
ARP_t * arp; |
|
//printf("packet_check_arp_header: pkt data at 0x%.8x\n",(unsigned long) pkt); |
eth_pkt = (Ethernet_t *) pkt; |
|
if (eth_pkt->et_protlen == 0x0806) |
{ |
// Is an ARP request |
// Check the IP |
pkt += ETHER_HDR_SIZE; // Skip eth header stuff |
//printf("Is ARP protocol\npkt header now at 0x%.8x\n",pkt); |
|
arp = (ARP_t*) pkt; |
|
if (arp->ar_hrd == ARP_ETHER && arp->ar_op == ARPOP_REQUEST) |
{ |
// Skip forward to the target I.P address |
|
char * internet_protocol_adr = (((unsigned long)&arp->ar_data[0]) + (arp->ar_hln * 2) + (arp->ar_pln)); |
|
//printf("Is ARP ethernet request\ncheck adr at 0x%.8x\n",internet_protocol_adr); |
if ((internet_protocol_adr[0] == our_ip[0]) && |
(internet_protocol_adr[1] == our_ip[1]) && |
(internet_protocol_adr[2] == our_ip[2]) && |
(internet_protocol_adr[3] == our_ip[3])) |
{ |
//printf("Got valid ARP request\n"); |
// Send ARP reply |
|
Ethernet_t * reply_pkt = (Ethernet_t *)&arp_reply_packet[0]; |
ARP_t * reply_arp = (ARP_t*)&arp_reply_packet[ETHER_HDR_SIZE]; |
memcpy( (void*)&reply_pkt->et_dest , (void*)ð_pkt->et_src , 6); |
reply_pkt->et_src[0] = ETH_MACADDR0; |
reply_pkt->et_src[1] = ETH_MACADDR1; |
reply_pkt->et_src[2] = ETH_MACADDR2; |
reply_pkt->et_src[3] = ETH_MACADDR3; |
reply_pkt->et_src[4] = ETH_MACADDR4; |
reply_pkt->et_src[5] = ETH_MACADDR5; |
reply_pkt->et_protlen = 0x0806; |
// ARP part of packet |
reply_arp->ar_hrd = ARP_ETHER; |
reply_arp->ar_pro = 0x0800; // IP Protocol |
reply_arp->ar_hln = 0x06; |
reply_arp->ar_pln = 0x04; |
reply_arp->ar_op = ARPOP_REPLY; |
// My MAC |
memcpy( (void*)&reply_arp->ar_data[0] , (void*)&reply_pkt->et_src , 6); |
// My IP |
memcpy( (void*)&reply_arp->ar_data[6] , (void*)&our_ip , 4); |
// Their MAC |
memcpy( (void*)&reply_arp->ar_data[10] , (void*)ð_pkt->et_src , 6); |
// Their IP |
char * their_internet_protocol_adr = |
(((unsigned long)&arp->ar_data[0]) + arp->ar_hln ); |
memcpy( (void*)&reply_arp->ar_data[16] , (void*)&their_internet_protocol_adr[0] , 4); |
|
tx_packet((void*)arp_reply_packet,(ETHER_HDR_SIZE+ARP_HDR_SIZE) ); |
|
} |
} |
} |
} |
|
|
|
static void |
oeth_rx(void) |
{ |
volatile oeth_regs *regs; |
regs = (oeth_regs *)(OETH_REG_BASE); |
|
volatile oeth_bd *rx_bdp; |
int pkt_len, i; |
int bad = 0; |
|
rx_bdp = ((oeth_bd *)OETH_BD_BASE) + OETH_TXBD_NUM; |
|
#if NEVER_PRINT_PACKET==0 |
printf("rx"); |
#endif |
|
/* Find RX buffers marked as having received data */ |
for(i = 0; i < OETH_RXBD_NUM; i++) |
{ |
if(!(rx_bdp[i].len_status & OETH_RX_BD_EMPTY)){ /* Looking for NOT empty buffers desc. */ |
/* Check status for errors. |
*/ |
if (rx_bdp[i].len_status & (OETH_RX_BD_TOOLONG | OETH_RX_BD_SHORT)) { |
bad = 1; |
} |
if (rx_bdp[i].len_status & OETH_RX_BD_DRIBBLE) { |
bad = 1; |
} |
if (rx_bdp[i].len_status & OETH_RX_BD_CRCERR) { |
bad = 1; |
} |
if (rx_bdp[i].len_status & OETH_RX_BD_OVERRUN) { |
bad = 1; |
} |
if (rx_bdp[i].len_status & OETH_RX_BD_MISS) { |
|
} |
if (rx_bdp[i].len_status & OETH_RX_BD_LATECOL) { |
bad = 1; |
} |
|
if (bad) { |
rx_bdp[i].len_status &= ~OETH_RX_BD_STATS; |
rx_bdp[i].len_status |= OETH_RX_BD_EMPTY; |
|
continue; |
} |
else { |
|
/* Process the incoming frame. |
*/ |
pkt_len = rx_bdp[i].len_status >> 16; |
|
/* Do something here with the data - copy it into userspace, perhaps. */ |
// See if it's an ARP packet |
packet_check_arp_header((void *)rx_bdp[i].addr ); |
// See if it's an ICMP echo request |
packet_check_icmp_header((void *)rx_bdp[i].addr ); |
#if NEVER_PRINT_PACKET==0 |
oeth_print_packet(rx_bdp[i].addr, rx_bdp[i].len_status >> 16); |
printf("\t end of packet\n\n"); |
#endif |
/* finish up */ |
rx_bdp[i].len_status &= ~OETH_RX_BD_STATS; /* Clear stats */ |
rx_bdp[i].len_status |= OETH_RX_BD_EMPTY; /* Mark RX BD as empty */ |
|
|
} |
} |
} |
} |
|
|
|
static void |
oeth_tx(void) |
{ |
volatile oeth_bd *tx_bd; |
int i; |
#if NEVER_PRINT_PACKET==0 |
printf("tx"); |
#endif |
tx_bd = (volatile oeth_bd *)OETH_BD_BASE; /* Search from beginning*/ |
|
/* Go through the TX buffs, search for one that was just sent */ |
for(i = 0; i < OETH_TXBD_NUM; i++) |
{ |
/* Looking for buffer NOT ready for transmit. and IRQ enabled */ |
if( (!(tx_bd[i].len_status & (OETH_TX_BD_READY))) && (tx_bd[i].len_status & (OETH_TX_BD_IRQ)) ) |
{ |
//oeth_print_packet(tx_bd[i].addr, (tx_bd[i].len_status >> 16)); |
/* Single threaded so no chance we have detected a buffer that has had its IRQ bit set but not its BD_READ flag. Maybe this won't work in linux */ |
tx_bd[i].len_status &= ~OETH_TX_BD_IRQ; |
|
/* Probably good to check for TX errors here */ |
|
#if NEVER_PRINT_PACKET==0 |
printf("T%d",i); |
#endif |
|
} |
} |
return; |
} |
|
|
int main () |
{ |
|
/* Initialise vector handler */ |
int_init(); |
|
/* Install ethernet interrupt handler, it is enabled here too */ |
int_add(ETH0_IRQ, oeth_interrupt, 0); |
|
/* Enable interrupts */ |
cpu_enable_user_interrupts(); |
|
last_char=0; /* Variable init for spin_cursor() */ |
next_tx_buf_num = 4; /* init for tx buffer counter */ |
|
#ifndef RTLSIM |
uart_init(DEFAULT_UART); // init the UART before we can printf |
printf("\n\teth ping program\n\n"); |
printf("\n\tboard IP: %d.%d.%d.%d\n",our_ip[0]&0xff,our_ip[1]&0xff, |
our_ip[2]&0xff,our_ip[3]&0xff); |
#endif |
|
ethmac_setup(); /* Configure MAC, TX/RX BDs and enable RX and TX in MODER */ |
|
//scan_ethphys(); /* Scan MIIM bus for PHYs */ |
//jb ethphy_init(); /* Attempt reset and configuration of PHY via MIIM */ |
//ethmac_scanstatus(); /* Enable scanning of status register via MIIM */ |
|
/* clear tx_done, the tx interrupt handler will set it when it's been transmitted */ |
tx_done = 0; |
|
|
#ifndef RTLSIM |
/* Loop, monitoring user input from TTY */ |
while(1) |
{ |
char c; |
|
while(!uart_check_for_char(DEFAULT_UART)) |
{ |
spin_cursor(); |
oeth_monitor_rx(); |
} |
|
c = uart_getc(DEFAULT_UART); |
|
if (c == 's') |
tx_packet((void*) ping_packet, 98); |
if (c == 'S') |
tx_packet((void*)big_ping_packet, 1514); |
if (c == 'h') |
scan_ethphys(); |
if (c == 'i') |
ethphy_init(); |
if (c == 'p') |
oeth_printregs(); |
if (c == '0') |
scan_ethphy(0); |
if (c == '1') |
scan_ethphy(1); |
if (c == '7') |
{ |
scan_ethphy(7); |
ethphy_print_status(7); |
} |
if (c == 'r') |
ethphy_reset(0); |
if (c == 'R') |
oeth_reset_tx_bd_pointer(); |
if (c == 'n') |
ethphy_reneg(0); |
if (c == 'N') |
ethphy_set_autoneg(0); |
if (c == 'm') |
ethmac_togglehugen(); |
if (c == 't') |
ethphy_set_10mbit(0); |
if ( c == 'b' ) |
{ |
printf("\n\t---\n"); |
oeth_dump_bds(); |
printf("\t---\n"); |
} |
|
} |
|
|
|
#endif |
|
} |
/sw/tests/ethmac/board/Makefile
0,0 → 1,13
SW_ROOT=../../.. |
|
include $(SW_ROOT)/Makefile.inc |
|
%.dis: %.elf |
$(Q)$(OR32_OBJDUMP) -d $< > $@ |
|
%.bin: %.elf |
$(Q)$(OR32_OBJCOPY) -O binary $< $@ |
|
clean: |
$(Q)rm -f *.elf *.bin *.vmem *.flashin *.dis |
|
/sw/tests/ethmac/sim/ethmac-rxtx.c
0,0 → 1,774
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Interrupt-driven Ethernet MAC transmit test code //// |
//// //// |
//// Description //// |
//// Send packets while receiving packets //// |
//// //// |
//// Test data comes from pre-calculated array of random values, //// |
//// MAC TX buffer pointers are set to addresses in this array, //// |
//// saving copying the data around before transfers. //// |
//// //// |
//// Author(s): //// |
//// - jb, jb@orsoc.se, with parts taken from Linux kernel //// |
//// open_eth driver. //// |
//// //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
#include "or32-utils.h" |
#include "spr-defs.h" |
#include "board.h" |
#include "int.h" |
//#include "uart.h" // comment this out, UART uses simulation putc() |
#include "open-eth.h" |
#include "printf.h" |
#include "eth-phy-mii.h" |
|
volatile unsigned tx_done; |
volatile unsigned rx_done; |
static int next_tx_buf_num; |
|
/* Functions in this file */ |
void ethmac_setup(void); |
/* Interrupt functions */ |
void oeth_interrupt(void); |
static void oeth_rx(void); |
static void oeth_tx(void); |
|
/* Defining RTLSIM turns off use of real printf'ing to save time in simulation */ |
#define RTLSIM |
|
#ifdef RTLSIM |
#define printk |
#else |
#define printk printf |
#endif |
/* Let the ethernet packets use a space beginning here for buffering */ |
#define ETH_BUFF_BASE 0x01000000 |
|
|
#define RXBUFF_PREALLOC 1 |
#define TXBUFF_PREALLOC 1 |
//#undef RXBUFF_PREALLOC |
//#undef TXBUFF_PREALLOC |
|
/* The transmitter timeout |
*/ |
#define TX_TIMEOUT (2*HZ) |
|
/* Buffer number (must be 2^n) |
*/ |
#define OETH_RXBD_NUM 16 |
#define OETH_TXBD_NUM 16 |
#define OETH_RXBD_NUM_MASK (OETH_RXBD_NUM-1) |
#define OETH_TXBD_NUM_MASK (OETH_TXBD_NUM-1) |
|
/* Buffer size |
*/ |
#define OETH_RX_BUFF_SIZE 0x600-4 |
#define OETH_TX_BUFF_SIZE 0x600-4 |
|
/* OR32 Page size def */ |
#define PAGE_SHIFT 13 |
#define PAGE_SIZE (1UL << PAGE_SHIFT) |
|
/* How many buffers per page |
*/ |
#define OETH_RX_BUFF_PPGAE (PAGE_SIZE/OETH_RX_BUFF_SIZE) |
#define OETH_TX_BUFF_PPGAE (PAGE_SIZE/OETH_TX_BUFF_SIZE) |
|
/* How many pages is needed for buffers |
*/ |
#define OETH_RX_BUFF_PAGE_NUM (OETH_RXBD_NUM/OETH_RX_BUFF_PPGAE) |
#define OETH_TX_BUFF_PAGE_NUM (OETH_TXBD_NUM/OETH_TX_BUFF_PPGAE) |
|
/* Buffer size (if not XXBUF_PREALLOC |
*/ |
#define MAX_FRAME_SIZE 1518 |
|
/* The buffer descriptors track the ring buffers. |
*/ |
struct oeth_private { |
//struct sk_buff* rx_skbuff[OETH_RXBD_NUM]; |
//struct sk_buff* tx_skbuff[OETH_TXBD_NUM]; |
|
unsigned short tx_next; /* Next buffer to be sent */ |
unsigned short tx_last; /* Next buffer to be checked if packet sent */ |
unsigned short tx_full; /* Buffer ring fuul indicator */ |
unsigned short rx_cur; /* Next buffer to be checked if packet |
received */ |
|
oeth_regs *regs; /* Address of controller registers. */ |
oeth_bd *rx_bd_base; /* Address of Rx BDs. */ |
oeth_bd *tx_bd_base; /* Address of Tx BDs. */ |
|
// struct net_device_stats stats; |
}; |
|
#define PHYNUM 7 |
|
// Data array of data to transmit, tx_data_array[] |
#include "eth-rxtx-data.h" |
int tx_data_pointer; |
|
/* Scan the MIIM bus for PHYs */ |
void scan_ethphys(void) |
{ |
unsigned int phynum,regnum, i; |
|
volatile oeth_regs *regs; |
regs = (oeth_regs *)(OETH_REG_BASE); |
|
regs->miitx_data = 0; |
|
for(phynum=0;phynum<32;phynum++) |
{ |
for (regnum=0;regnum<8;regnum++) |
{ |
printk("scan_ethphys: phy %d r%d ",phynum, regnum); |
|
/* Now actually perform the read on the MIIM bus*/ |
regs->miiaddress = (regnum << 8) | phynum; |
regs->miicommand = OETH_MIICOMMAND_RSTAT; |
/* Wait for command to be registered*/ |
while(!(regs->miistatus & OETH_MIISTATUS_BUSY)); |
|
regs->miicommand = 0; |
|
while(regs->miistatus & OETH_MIISTATUS_BUSY); |
|
printk("%x\n",regs->miirx_data); |
} |
} |
} |
|
|
|
void ethmac_scanstatus(void) |
{ |
volatile oeth_regs *regs; |
regs = (oeth_regs *)(OETH_REG_BASE); |
|
|
printk("Oeth: regs->miistatus %x regs->miirx_data %x\n",regs->miistatus, regs->miirx_data); |
regs->miiaddress = 0; |
regs->miitx_data = 0; |
regs->miicommand = OETH_MIICOMMAND_SCANSTAT; |
printk("Oeth: regs->miiaddress %x regs->miicommand %x\n",regs->miiaddress, regs->miicommand); |
//regs->miicommand = 0; |
volatile int i; for(i=0;i<1000;i++); |
while(regs->miistatus & OETH_MIISTATUS_BUSY) ; |
//spin_cursor(); |
//printk("\r"); |
//or32_exit(0); |
} |
|
void |
eth_mii_write(char phynum, short regnum, short data) |
{ |
static volatile oeth_regs *regs = (oeth_regs *)(OETH_REG_BASE); |
regs->miiaddress = (regnum << 8) | phynum; |
regs->miitx_data = data; |
regs->miicommand = OETH_MIICOMMAND_WCTRLDATA; |
regs->miicommand = 0; |
while(regs->miistatus & OETH_MIISTATUS_BUSY); |
} |
|
short |
eth_mii_read(char phynum, short regnum) |
{ |
static volatile oeth_regs *regs = (oeth_regs *)(OETH_REG_BASE); |
regs->miiaddress = (regnum << 8) | phynum; |
regs->miicommand = OETH_MIICOMMAND_RSTAT; |
regs->miicommand = 0; |
while(regs->miistatus & OETH_MIISTATUS_BUSY); |
|
return regs->miirx_data; |
} |
|
|
|
// Wait here until all packets have been transmitted |
void wait_until_all_tx_clear(void) |
{ |
|
int i; |
volatile oeth_bd *tx_bd; |
tx_bd = (volatile oeth_bd *)OETH_BD_BASE; /* Search from beginning*/ |
|
int some_tx_waiting = 1; |
|
while (some_tx_waiting) |
{ |
some_tx_waiting = 0; |
/* Go through the TX buffs, search for unused one */ |
for(i = 0; i < OETH_TXBD_NUM; i++) { |
|
if((tx_bd[i].len_status & OETH_TX_BD_READY)) // Looking for buffer ready for transmit |
some_tx_waiting = 1; |
|
} |
} |
} |
|
|
void |
ethphy_set_10mbit(int phynum) |
{ |
wait_until_all_tx_clear(); |
// Hardset PHY to just use 10Mbit mode |
short cr = eth_mii_read(phynum, MII_BMCR); |
cr &= ~BMCR_ANENABLE; // Clear auto negotiate bit |
cr &= ~BMCR_SPEED100; // Clear fast eth. bit |
eth_mii_write(phynum, MII_BMCR, cr); |
} |
|
|
void |
ethphy_set_100mbit(int phynum) |
{ |
wait_until_all_tx_clear(); |
// Hardset PHY to just use 100Mbit mode |
short cr = eth_mii_read(phynum, MII_BMCR); |
cr |= BMCR_ANENABLE; // Clear auto negotiate bit |
cr |= BMCR_SPEED100; // Clear fast eth. bit |
eth_mii_write(phynum, MII_BMCR, cr); |
} |
|
|
void ethmac_setup(void) |
{ |
// from arch/or32/drivers/open_eth.c |
volatile oeth_regs *regs; |
|
regs = (oeth_regs *)(OETH_REG_BASE); |
|
/* Reset MII mode module */ |
regs->miimoder = OETH_MIIMODER_RST; /* MII Reset ON */ |
regs->miimoder &= ~OETH_MIIMODER_RST; /* MII Reset OFF */ |
regs->miimoder = 0x64; /* Clock divider for MII Management interface */ |
|
/* Reset the controller. |
*/ |
regs->moder = OETH_MODER_RST; /* Reset ON */ |
regs->moder &= ~OETH_MODER_RST; /* Reset OFF */ |
|
/* Setting TXBD base to OETH_TXBD_NUM. |
*/ |
regs->tx_bd_num = OETH_TXBD_NUM; |
|
|
/* Set min/max packet length |
*/ |
regs->packet_len = 0x00400600; |
|
/* Set IPGT register to recomended value |
*/ |
regs->ipgt = 0x12; |
|
/* Set IPGR1 register to recomended value |
*/ |
regs->ipgr1 = 0x0000000c; |
|
/* Set IPGR2 register to recomended value |
*/ |
regs->ipgr2 = 0x00000012; |
|
/* Set COLLCONF register to recomended value |
*/ |
regs->collconf = 0x000f003f; |
|
/* Set control module mode |
*/ |
#if 0 |
regs->ctrlmoder = OETH_CTRLMODER_TXFLOW | OETH_CTRLMODER_RXFLOW; |
#else |
regs->ctrlmoder = 0; |
#endif |
|
/* Clear MIIM registers */ |
regs->miitx_data = 0; |
regs->miiaddress = 0; |
regs->miicommand = 0; |
|
regs->mac_addr1 = ETH_MACADDR0 << 8 | ETH_MACADDR1; |
regs->mac_addr0 = ETH_MACADDR2 << 24 | ETH_MACADDR3 << 16 | ETH_MACADDR4 << 8 | ETH_MACADDR5; |
|
/* Clear all pending interrupts |
*/ |
regs->int_src = 0xffffffff; |
|
/* Promisc, IFG, CRCEn |
*/ |
regs->moder |= OETH_MODER_PRO | OETH_MODER_PAD | OETH_MODER_IFG | OETH_MODER_CRCEN | OETH_MODER_FULLD; |
|
/* Enable interrupt sources. |
*/ |
|
regs->int_mask = OETH_INT_MASK_TXB | |
OETH_INT_MASK_TXE | |
OETH_INT_MASK_RXF | |
OETH_INT_MASK_RXE | |
OETH_INT_MASK_BUSY | |
OETH_INT_MASK_TXC | |
OETH_INT_MASK_RXC; |
|
// Buffer setup stuff |
volatile oeth_bd *tx_bd, *rx_bd; |
int i,j,k; |
|
/* Initialize TXBD pointer |
*/ |
tx_bd = (volatile oeth_bd *)OETH_BD_BASE; |
|
/* Initialize RXBD pointer |
*/ |
rx_bd = ((volatile oeth_bd *)OETH_BD_BASE) + OETH_TXBD_NUM; |
|
/* Preallocated ethernet buffer setup */ |
unsigned long mem_addr = ETH_BUFF_BASE; /* Defined at top */ |
|
// Setup TX Buffers |
for(i = 0; i < OETH_TXBD_NUM; i++) { |
//tx_bd[i].len_status = OETH_TX_BD_PAD | OETH_TX_BD_CRC | OETH_RX_BD_IRQ; |
tx_bd[i].len_status = OETH_TX_BD_PAD | OETH_TX_BD_CRC; |
tx_bd[i].addr = mem_addr; |
mem_addr += OETH_TX_BUFF_SIZE; |
} |
tx_bd[OETH_TXBD_NUM - 1].len_status |= OETH_TX_BD_WRAP; |
|
// Setup RX buffers |
for(i = 0; i < OETH_RXBD_NUM; i++) { |
rx_bd[i].len_status = OETH_RX_BD_EMPTY | OETH_RX_BD_IRQ; // Init. with IRQ |
rx_bd[i].addr = mem_addr; |
mem_addr += OETH_RX_BUFF_SIZE; |
} |
rx_bd[OETH_RXBD_NUM - 1].len_status |= OETH_RX_BD_WRAP; // Last buffer wraps |
|
/* Enable JUST the transmiter |
*/ |
regs->moder &= ~(OETH_MODER_RXEN | OETH_MODER_TXEN); |
regs->moder |= /*OETH_MODER_RXEN |*/ OETH_MODER_TXEN; |
|
next_tx_buf_num = 0; // init tx buffer pointer |
|
return; |
} |
|
// Enable RX in ethernet MAC |
void |
oeth_enable_rx(void) |
{ |
volatile oeth_regs *regs; |
regs = (oeth_regs *)(OETH_REG_BASE); |
regs->moder |= OETH_MODER_RXEN; |
} |
|
// Disable RX in ethernet MAC |
void |
oeth_disable_rx(void) |
{ |
volatile oeth_regs *regs; |
regs = (oeth_regs *)(OETH_REG_BASE); |
regs->moder &= ~(OETH_MODER_RXEN); |
} |
|
|
/* Setup buffer descriptors with data */ |
/* length is in BYTES */ |
void tx_packet(void* data, int length) |
{ |
volatile oeth_regs *regs; |
regs = (oeth_regs *)(OETH_REG_BASE); |
|
volatile oeth_bd *tx_bd; |
volatile int i; |
|
tx_bd = (volatile oeth_bd *)OETH_BD_BASE; |
tx_bd = (struct oeth_bd*) &tx_bd[next_tx_buf_num]; |
|
// If it's in use - wait |
while ((tx_bd->len_status & OETH_TX_BD_IRQ)); |
|
/* Clear all of the status flags. |
*/ |
tx_bd->len_status &= ~OETH_TX_BD_STATS; |
|
/* If the frame is short, tell CPM to pad it. |
*/ |
#define ETH_ZLEN 60 /* Min. octets in frame sans FCS */ |
if (length <= ETH_ZLEN) |
tx_bd->len_status |= OETH_TX_BD_PAD; |
else |
tx_bd->len_status &= ~OETH_TX_BD_PAD; |
|
#ifdef _ETH_RXTX_DATA_H_ |
// Set the address pointer to the place |
// in memory where the data is and transmit from there |
|
tx_bd->addr = (char*) &tx_data_array[tx_data_pointer&~(0x3)]; |
|
tx_data_pointer += length + 1; |
if (tx_data_pointer > (255*1024)) |
tx_data_pointer = 0; |
|
|
#else |
if (data){ |
//Copy the data into the transmit buffer, byte at a time |
char* data_p = (char*) data; |
char* data_b = (char*) tx_bd->addr; |
for(i=0;i<length;i++) |
{ |
data_b[i] = data_p[i]; |
} |
} |
#endif |
|
/* Set the length of the packet's data in the buffer descriptor */ |
tx_bd->len_status = (tx_bd->len_status & 0x0000ffff) | |
((length&0xffff) << 16); |
|
/* Send it on its way. Tell controller its ready, interrupt when sent |
* and to put the CRC on the end. |
*/ |
tx_bd->len_status |= (OETH_TX_BD_READY | OETH_TX_BD_CRC | OETH_TX_BD_IRQ); |
|
next_tx_buf_num = (next_tx_buf_num + 1) & OETH_TXBD_NUM_MASK; |
|
return; |
|
|
} |
|
/* The interrupt handler. |
*/ |
void |
oeth_interrupt(void) |
{ |
|
volatile oeth_regs *regs; |
regs = (oeth_regs *)(OETH_REG_BASE); |
|
uint int_events; |
int serviced; |
|
serviced = 0; |
|
/* Get the interrupt events that caused us to be here. |
*/ |
int_events = regs->int_src; |
regs->int_src = int_events; |
|
/* Handle receive event in its own function. |
*/ |
if (int_events & (OETH_INT_RXF | OETH_INT_RXE)) { |
serviced |= 0x1; |
oeth_rx(); |
} |
|
/* Handle transmit event in its own function. |
*/ |
if (int_events & (OETH_INT_TXB | OETH_INT_TXE)) { |
serviced |= 0x2; |
oeth_tx(); |
serviced |= 0x2; |
|
} |
|
/* Check for receive busy, i.e. packets coming but no place to |
* put them. |
*/ |
if (int_events & OETH_INT_BUSY) { |
serviced |= 0x4; |
if (!(int_events & (OETH_INT_RXF | OETH_INT_RXE))) |
oeth_rx(); |
} |
|
return; |
} |
|
|
|
static void |
oeth_rx(void) |
{ |
volatile oeth_regs *regs; |
regs = (oeth_regs *)(OETH_REG_BASE); |
|
volatile oeth_bd *rx_bdp; |
int pkt_len, i; |
int bad = 0; |
|
rx_bdp = ((oeth_bd *)OETH_BD_BASE) + OETH_TXBD_NUM; |
|
printk("r"); |
|
|
/* Find RX buffers marked as having received data */ |
for(i = 0; i < OETH_RXBD_NUM; i++) |
{ |
bad=0; |
if(!(rx_bdp[i].len_status & OETH_RX_BD_EMPTY)){ /* Looking for NOT empty buffers desc. */ |
/* Check status for errors. |
*/ |
if (rx_bdp[i].len_status & (OETH_RX_BD_TOOLONG | OETH_RX_BD_SHORT)) { |
bad = 1; |
report(0xbaad0001); |
} |
if (rx_bdp[i].len_status & OETH_RX_BD_DRIBBLE) { |
bad = 1; |
report(0xbaad0002); |
} |
if (rx_bdp[i].len_status & OETH_RX_BD_CRCERR) { |
bad = 1; |
report(0xbaad0003); |
} |
if (rx_bdp[i].len_status & OETH_RX_BD_OVERRUN) { |
bad = 1; |
report(0xbaad0004); |
} |
if (rx_bdp[i].len_status & OETH_RX_BD_MISS) { |
report(0xbaad0005); |
} |
if (rx_bdp[i].len_status & OETH_RX_BD_LATECOL) { |
bad = 1; |
report(0xbaad0006); |
} |
if (bad) { |
rx_bdp[i].len_status &= ~OETH_RX_BD_STATS; |
rx_bdp[i].len_status |= OETH_RX_BD_EMPTY; |
exit(0xbaaaaaad); |
|
continue; |
} |
else { |
/* Process the incoming frame. |
*/ |
pkt_len = rx_bdp[i].len_status >> 16; |
|
/* finish up */ |
rx_bdp[i].len_status &= ~OETH_RX_BD_STATS; /* Clear stats */ |
rx_bdp[i].len_status |= OETH_RX_BD_EMPTY; /* Mark RX BD as empty */ |
rx_done++; |
} |
} |
} |
} |
|
|
|
static void |
oeth_tx(void) |
{ |
volatile oeth_bd *tx_bd; |
int i; |
|
tx_bd = (volatile oeth_bd *)OETH_BD_BASE; /* Search from beginning*/ |
|
/* Go through the TX buffs, search for one that was just sent */ |
for(i = 0; i < OETH_TXBD_NUM; i++) |
{ |
/* Looking for buffer NOT ready for transmit. and IRQ enabled */ |
if( (!(tx_bd[i].len_status & (OETH_TX_BD_READY))) && (tx_bd[i].len_status & (OETH_TX_BD_IRQ)) ) |
{ |
/* Single threaded so no chance we have detected a buffer that has had its IRQ bit set but not its BD_READ flag. Maybe this won't work in linux */ |
tx_bd[i].len_status &= ~OETH_TX_BD_IRQ; |
|
/* Probably good to check for TX errors here */ |
|
/* set our test variable */ |
tx_done++; |
|
printk("T%d",i); |
|
} |
} |
return; |
} |
|
// A function and defines to fill and transmit a packet |
#define MAX_TX_BUFFER 1532 |
static char tx_buffer[MAX_TX_BUFFER]; |
static unsigned long tx_data = 0x26fab2f2; |
static inline char gen_next_tx_byte(void) |
{ |
// Bit of LFSR action |
tx_data = ((~(((((tx_data&(1<<25))>>25)^((tx_data&(1<<13))>>13))^((tx_data&(1<<2))>>2)))&0x01) | (tx_data<<1)); |
//tx_data =(!((tx_data>>26) ^ (tx_data>>14) ^ (tx_data>>5) ^ (tx_data>>3)) & 0x1) | (tx_data<<1); |
return (char) tx_data & 0xff; |
} |
|
void |
fill_and_tx_packet(int size) |
{ |
int i; |
char tx_byte; |
|
|
volatile oeth_regs *regs; |
regs = (oeth_regs *)(OETH_REG_BASE); |
|
volatile oeth_bd *tx_bd; |
|
//tx_bd = (volatile oeth_bd *)OETH_BD_BASE; |
tx_bd = (volatile oeth_bd*) &tx_bd[next_tx_buf_num]; |
|
|
// If it's in use - wait |
while ((tx_bd->len_status & OETH_TX_BD_IRQ)); |
|
#ifndef _ETH_RXTX_DATA_H_ |
/* Copy the data into the transmit buffer, byte at a time */ |
char* data_b = (char*) tx_bd->addr; |
for(i=0;i<size;i++) |
{ |
data_b[i] = gen_next_tx_byte(); |
} |
#endif |
|
tx_packet((void*)0, size); |
} |
|
|
// Loop to check if a number is prime by doing mod divide of the number |
// to test by every number less than it |
int |
is_prime_number(unsigned long n) |
{ |
unsigned long c; |
if (n < 2) return 0; |
for(c=2;c<n;c++) |
if ((n % c) == 0) |
return 0; |
return 1; |
} |
|
|
//#define WAIT_PACKET_TX(x) while(tx_done<x) |
#define WAIT_PACKET_TX(x) |
|
int main () |
{ |
tx_data_pointer = 0; |
/* Initialise handler vector */ |
int_init(); |
|
/* Install ethernet interrupt handler, it is enabled here too */ |
int_add(ETH0_IRQ, oeth_interrupt, 0); |
|
/* Enable interrupts in supervisor register */ |
mtspr (SPR_SR, mfspr (SPR_SR) | SPR_SR_IEE); |
|
ethmac_setup(); /* Configure MAC, TX/RX BDs and enable RX and TX in MODER */ |
|
/* clear tx_done, the tx interrupt handler will set it when it's been |
transmitted */ |
tx_done = 0; |
rx_done = 0; |
|
printf("Start of large txdata buffer: 0x%x\n", |
(unsigned long)&tx_data_array[0]); |
printf("Slut of large txdata buffer: 0x%x\n", |
(unsigned long)&tx_data_array[262144]); |
|
|
ethphy_set_100mbit(0); |
|
oeth_enable_rx(); |
|
#define ETH_TX_MIN_PACKET_SIZE 512 |
#define ETH_TX_NUM_PACKETS (ETH_TX_MIN_PACKET_SIZE + 32) |
|
#define CALCULATE_PRIMES 0 |
|
char prime_check_results[2048]; |
unsigned long num_to_check; |
for(num_to_check=ETH_TX_MIN_PACKET_SIZE; |
num_to_check<ETH_TX_NUM_PACKETS; |
num_to_check++) |
{ |
fill_and_tx_packet(num_to_check); |
#if CALCULATE_PRIMES==1 |
prime_check_results[num_to_check-5] |
= (char) is_prime_number(num_to_check); |
report(num_to_check | (0x1e<<24)); |
report(prime_check_results[num_to_check-5] | (0x2e<<24)); |
#endif |
} |
|
oeth_disable_rx(); |
|
// Now for 10mbit mode... |
ethphy_set_10mbit(0); |
|
oeth_enable_rx(); |
|
for(num_to_check=ETH_TX_MIN_PACKET_SIZE; |
num_to_check<ETH_TX_NUM_PACKETS; |
num_to_check++) |
{ |
fill_and_tx_packet(num_to_check); |
#if CALCULATE_PRIMES==1 |
prime_check_results[num_to_check+(OETH_TX_BUFF_SIZE-5)] |
= (char) is_prime_number(num_to_check+OETH_TX_BUFF_SIZE); |
report(num_to_check | (0x1e<<24)); |
report(prime_check_results[num_to_check+(OETH_TX_BUFF_SIZE-5)] |
| (0x2e<<24) |
); |
#endif |
} |
|
oeth_disable_rx(); |
|
// Go back to 100-mbit mode |
ethphy_set_100mbit(0); |
|
oeth_enable_rx(); |
|
for(num_to_check=ETH_TX_MIN_PACKET_SIZE; |
num_to_check<ETH_TX_NUM_PACKETS; |
num_to_check++) |
{ |
fill_and_tx_packet(num_to_check); |
#if CALCULATE_PRIMES==1 |
prime_check_results[num_to_check+(OETH_TX_BUFF_SIZE-5)] |
= (char) is_prime_number(num_to_check+OETH_TX_BUFF_SIZE); |
report(num_to_check | (0x1e<<24)); |
report(prime_check_results[num_to_check+(OETH_TX_BUFF_SIZE-5)] |
| (0x2e<<24) |
); |
#endif |
} |
|
|
exit(0x8000000d); |
|
|
} |
/sw/tests/ethmac/sim/ethmac-rx.c
0,0 → 1,552
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Interrupt-driven Ethernet MAC test code //// |
//// //// |
//// Description //// |
//// Do ethernet receive path testing //// |
//// Relies on testbench to provide simulus - expects at least //// |
//// 256 packets to be sent. //// |
//// //// |
//// Author(s): //// |
//// - jb, jb@orsoc.se, with parts taken from Linux kernel //// |
//// open_eth driver. //// |
//// //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
#include "cpu-utils.h" |
//#include "spr-defs.h" |
#include "board.h" |
#include "int.h" |
#include "uart.h" |
#include "ethmac.h" |
#include "printf.h" |
#include "eth-phy-mii.h" |
|
volatile unsigned tx_done; |
volatile unsigned rx_done; |
|
/* Functions in this file */ |
void ethmac_setup(void); |
void ethphy_init(void); |
void oeth_dump_bds(); |
/* Interrupt functions */ |
void oeth_interrupt(void); |
static void oeth_rx(void); |
static void oeth_tx(void); |
|
/* Defining RTLSIM turns off use of real printf'ing to save time in simulation */ |
#define RTLSIM |
|
#ifdef RTLSIM |
#define printk |
#else |
#define printk printf |
#endif |
/* Let the ethernet packets use a space beginning here for buffering */ |
#define ETH_BUFF_BASE 0x01000000 |
|
|
#define RXBUFF_PREALLOC 1 |
#define TXBUFF_PREALLOC 1 |
//#undef RXBUFF_PREALLOC |
//#undef TXBUFF_PREALLOC |
|
/* The transmitter timeout |
*/ |
#define TX_TIMEOUT (2*HZ) |
|
/* Buffer number (must be 2^n) |
*/ |
#define OETH_RXBD_NUM 16 |
#define OETH_TXBD_NUM 16 |
#define OETH_RXBD_NUM_MASK (OETH_RXBD_NUM-1) |
#define OETH_TXBD_NUM_MASK (OETH_TXBD_NUM-1) |
|
/* Buffer size |
*/ |
#define OETH_RX_BUFF_SIZE 0x600 |
#define OETH_TX_BUFF_SIZE 0x600 |
|
/* Buffer size (if not XXBUF_PREALLOC |
*/ |
#define MAX_FRAME_SIZE 1518 |
|
/* The buffer descriptors track the ring buffers. |
*/ |
struct oeth_private { |
//struct sk_buff* rx_skbuff[OETH_RXBD_NUM]; |
//struct sk_buff* tx_skbuff[OETH_TXBD_NUM]; |
|
unsigned short tx_next; /* Next buffer to be sent */ |
unsigned short tx_last; /* Next buffer to be checked if packet sent */ |
unsigned short tx_full; /* Buffer ring fuul indicator */ |
unsigned short rx_cur; /* Next buffer to be checked if packet received */ |
|
oeth_regs *regs; /* Address of controller registers. */ |
oeth_bd *rx_bd_base; /* Address of Rx BDs. */ |
oeth_bd *tx_bd_base; /* Address of Tx BDs. */ |
|
// struct net_device_stats stats; |
}; |
|
|
#define PHYNUM 7 |
|
/* Scan the MIIM bus for PHYs */ |
void scan_ethphys(void) |
{ |
unsigned int phynum,regnum, i; |
|
volatile oeth_regs *regs; |
regs = (oeth_regs *)(OETH_REG_BASE); |
|
regs->miitx_data = 0; |
|
for(phynum=0;phynum<32;phynum++) |
{ |
for (regnum=0;regnum<8;regnum++) |
{ |
printk("scan_ethphys: phy %d r%d ",phynum, regnum); |
|
/* Now actually perform the read on the MIIM bus*/ |
regs->miiaddress = (regnum << 8) | phynum; /* Basic Control Register */ |
regs->miicommand = OETH_MIICOMMAND_RSTAT; |
|
while(!(regs->miistatus & OETH_MIISTATUS_BUSY)); /* Wait for command to be registered*/ |
|
regs->miicommand = 0; |
|
while(regs->miistatus & OETH_MIISTATUS_BUSY); |
|
printk("%x\n",regs->miirx_data); |
} |
} |
} |
|
|
|
void ethmac_scanstatus(void) |
{ |
volatile oeth_regs *regs; |
regs = (oeth_regs *)(OETH_REG_BASE); |
|
|
printk("Oeth: regs->miistatus %x regs->miirx_data %x\n",regs->miistatus, regs->miirx_data); |
regs->miiaddress = 0; |
regs->miitx_data = 0; |
regs->miicommand = OETH_MIICOMMAND_SCANSTAT; |
printk("Oeth: regs->miiaddress %x regs->miicommand %x\n",regs->miiaddress, regs->miicommand); |
//regs->miicommand = 0; |
volatile int i; for(i=0;i<1000;i++); |
while(regs->miistatus & OETH_MIISTATUS_BUSY) ; |
//spin_cursor(); |
//printk("\r"); |
//or32_exit(0); |
} |
|
void |
eth_mii_write(char phynum, short regnum, short data) |
{ |
static volatile oeth_regs *regs = (oeth_regs *)(OETH_REG_BASE); |
regs->miiaddress = (regnum << 8) | phynum; |
regs->miitx_data = data; |
regs->miicommand = OETH_MIICOMMAND_WCTRLDATA; |
regs->miicommand = 0; |
while(regs->miistatus & OETH_MIISTATUS_BUSY); |
} |
|
short |
eth_mii_read(char phynum, short regnum) |
{ |
static volatile oeth_regs *regs = (oeth_regs *)(OETH_REG_BASE); |
regs->miiaddress = (regnum << 8) | phynum; |
regs->miicommand = OETH_MIICOMMAND_RSTAT; |
regs->miicommand = 0; |
while(regs->miistatus & OETH_MIISTATUS_BUSY); |
|
return regs->miirx_data; |
} |
|
void ethphy_init(void) |
{ |
|
/* Init the Alaska 88E1111 Phy */ |
char alaska88e1111_ml501_phynum = 0x7; |
|
/* Init, reset */ |
short ctl = eth_mii_read(alaska88e1111_ml501_phynum, MII_BMCR); |
ctl &= ~(BMCR_FULLDPLX|BMCR_SPEED100|BMCR_SPD2|BMCR_ANENABLE); |
ctl |= BMCR_SPEED100; // 100MBit |
ctl |= BMCR_FULLDPLX; // Full duplex |
eth_mii_write(alaska88e1111_ml501_phynum, MII_BMCR, ctl); |
|
// Setup Autoneg |
short adv = eth_mii_read(alaska88e1111_ml501_phynum, MII_ADVERTISE); |
adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_1000XFULL |
|ADVERTISE_1000XHALF | ADVERTISE_1000XPAUSE | |
ADVERTISE_1000XPSE_ASYM); |
adv |= ADVERTISE_10HALF; |
adv |= ADVERTISE_10FULL; |
adv |= ADVERTISE_100HALF; |
adv |= ADVERTISE_100FULL; |
eth_mii_write(alaska88e1111_ml501_phynum, MII_ADVERTISE, adv); |
// Disable gigabit??? |
adv = eth_mii_read(alaska88e1111_ml501_phynum, MII_M1011_PHY_SPEC_CONTROL); |
adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP | |
MII_1000BASETCONTROL_HALFDUPLEXCAP); |
eth_mii_write(alaska88e1111_ml501_phynum, MII_M1011_PHY_SPEC_CONTROL, adv); |
// Even more disable gigabit?! |
adv = eth_mii_read(alaska88e1111_ml501_phynum, MII_CTRL1000); |
adv &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); |
eth_mii_write(alaska88e1111_ml501_phynum, MII_CTRL1000, adv); |
|
// Restart autoneg |
printk("Resetting phy...\n"); |
ctl = eth_mii_read(alaska88e1111_ml501_phynum, MII_BMCR); |
ctl |= (BMCR_ANENABLE | BMCR_ANRESTART); |
eth_mii_write(alaska88e1111_ml501_phynum, MII_BMCR, ctl); |
|
|
} |
|
|
void ethmac_setup(void) |
{ |
// from arch/or32/drivers/open_eth.c |
volatile oeth_regs *regs; |
|
regs = (oeth_regs *)(OETH_REG_BASE); |
|
/* Reset MII mode module */ |
regs->miimoder = OETH_MIIMODER_RST; /* MII Reset ON */ |
regs->miimoder &= ~OETH_MIIMODER_RST; /* MII Reset OFF */ |
regs->miimoder = 0x64; /* Clock divider for MII Management interface */ |
|
/* Reset the controller. |
*/ |
regs->moder = OETH_MODER_RST; /* Reset ON */ |
regs->moder &= ~OETH_MODER_RST; /* Reset OFF */ |
|
/* Setting TXBD base to OETH_TXBD_NUM. |
*/ |
regs->tx_bd_num = OETH_TXBD_NUM; |
|
|
/* Set min/max packet length |
*/ |
regs->packet_len = 0x00400600; |
|
/* Set IPGT register to recomended value |
*/ |
regs->ipgt = 0x12; |
|
/* Set IPGR1 register to recomended value |
*/ |
regs->ipgr1 = 0x0000000c; |
|
/* Set IPGR2 register to recomended value |
*/ |
regs->ipgr2 = 0x00000012; |
|
/* Set COLLCONF register to recomended value |
*/ |
regs->collconf = 0x000f003f; |
|
/* Set control module mode |
*/ |
#if 0 |
regs->ctrlmoder = OETH_CTRLMODER_TXFLOW | OETH_CTRLMODER_RXFLOW; |
#else |
regs->ctrlmoder = 0; |
#endif |
|
/* Clear MIIM registers */ |
regs->miitx_data = 0; |
regs->miiaddress = 0; |
regs->miicommand = 0; |
|
regs->mac_addr1 = ETH_MACADDR0 << 8 | ETH_MACADDR1; |
regs->mac_addr0 = ETH_MACADDR2 << 24 | ETH_MACADDR3 << 16 | ETH_MACADDR4 << 8 | ETH_MACADDR5; |
|
/* Clear all pending interrupts |
*/ |
regs->int_src = 0xffffffff; |
|
/* Promisc, IFG, CRCEn |
*/ |
regs->moder |= OETH_MODER_PRO | OETH_MODER_PAD | OETH_MODER_IFG | OETH_MODER_CRCEN | OETH_MODER_FULLD; |
|
/* Enable interrupt sources. |
*/ |
|
regs->int_mask = OETH_INT_MASK_TXB | |
OETH_INT_MASK_TXE | |
OETH_INT_MASK_RXF | |
OETH_INT_MASK_RXE | |
OETH_INT_MASK_BUSY | |
OETH_INT_MASK_TXC | |
OETH_INT_MASK_RXC; |
|
// Buffer setup stuff |
volatile oeth_bd *tx_bd, *rx_bd; |
int i,j,k; |
|
/* Initialize TXBD pointer |
*/ |
tx_bd = (volatile oeth_bd *)OETH_BD_BASE; |
|
/* Initialize RXBD pointer |
*/ |
rx_bd = ((volatile oeth_bd *)OETH_BD_BASE) + OETH_TXBD_NUM; |
|
/* Preallocated ethernet buffer setup */ |
unsigned long mem_addr = ETH_BUFF_BASE; /* Defined at top */ |
|
// Setup TX Buffers |
for(i = 0; i < OETH_TXBD_NUM; i++) { |
//tx_bd[i].len_status = OETH_TX_BD_PAD | OETH_TX_BD_CRC | OETH_RX_BD_IRQ; |
tx_bd[i].len_status = OETH_TX_BD_PAD | OETH_TX_BD_CRC; |
tx_bd[i].addr = mem_addr; |
mem_addr += OETH_TX_BUFF_SIZE; |
} |
tx_bd[OETH_TXBD_NUM - 1].len_status |= OETH_TX_BD_WRAP; |
|
// Setup RX buffers |
for(i = 0; i < OETH_RXBD_NUM; i++) { |
rx_bd[i].len_status = OETH_RX_BD_EMPTY | OETH_RX_BD_IRQ; // Init. with IRQ |
rx_bd[i].addr = mem_addr; |
mem_addr += OETH_RX_BUFF_SIZE; |
} |
rx_bd[OETH_RXBD_NUM - 1].len_status |= OETH_RX_BD_WRAP; // Last buffer wraps |
|
/* Enable just the receiver |
*/ |
regs->moder &= ~(OETH_MODER_RXEN | OETH_MODER_TXEN); |
regs->moder |= OETH_MODER_RXEN /* | OETH_MODER_TXEN*/; |
|
return; |
} |
|
|
/* The interrupt handler. |
*/ |
void |
oeth_interrupt(void) |
{ |
|
volatile oeth_regs *regs; |
regs = (oeth_regs *)(OETH_REG_BASE); |
|
uint int_events; |
int serviced; |
|
serviced = 0; |
|
/* Get the interrupt events that caused us to be here. |
*/ |
int_events = regs->int_src; |
regs->int_src = int_events; |
|
|
/* Handle receive event in its own function. |
*/ |
if (int_events & (OETH_INT_RXF | OETH_INT_RXE)) { |
serviced |= 0x1; |
oeth_rx(); |
} |
|
/* Handle transmit event in its own function. |
*/ |
if (int_events & (OETH_INT_TXB | OETH_INT_TXE)) { |
serviced |= 0x2; |
oeth_tx(); |
serviced |= 0x2; |
|
} |
|
/* Check for receive busy, i.e. packets coming but no place to |
* put them. |
*/ |
if (int_events & OETH_INT_BUSY) { |
serviced |= 0x4; |
if (!(int_events & (OETH_INT_RXF | OETH_INT_RXE))) |
oeth_rx(); |
} |
|
return; |
} |
|
|
|
static void |
oeth_rx(void) |
{ |
volatile oeth_regs *regs; |
regs = (oeth_regs *)(OETH_REG_BASE); |
|
volatile oeth_bd *rx_bdp; |
int pkt_len, i; |
int bad = 0; |
|
rx_bdp = ((oeth_bd *)OETH_BD_BASE) + OETH_TXBD_NUM; |
|
printk("r"); |
|
/* Find RX buffers marked as having received data */ |
for(i = 0; i < OETH_RXBD_NUM; i++) |
{ |
bad=0; |
if(!(rx_bdp[i].len_status & OETH_RX_BD_EMPTY)){ /* Looking for NOT empty buffers desc. */ |
/* Check status for errors. |
*/ |
report(i); |
report(rx_bdp[i].len_status); |
if (rx_bdp[i].len_status & (OETH_RX_BD_TOOLONG | OETH_RX_BD_SHORT)) { |
bad = 1; |
report(0xbaad0001); |
} |
if (rx_bdp[i].len_status & OETH_RX_BD_DRIBBLE) { |
bad = 1; |
report(0xbaad0002); |
} |
if (rx_bdp[i].len_status & OETH_RX_BD_CRCERR) { |
bad = 1; |
report(0xbaad0003); |
} |
if (rx_bdp[i].len_status & OETH_RX_BD_OVERRUN) { |
bad = 1; |
report(0xbaad0004); |
} |
if (rx_bdp[i].len_status & OETH_RX_BD_MISS) { |
report(0xbaad0005); |
} |
if (rx_bdp[i].len_status & OETH_RX_BD_LATECOL) { |
bad = 1; |
report(0xbaad0006); |
} |
if (bad) { |
rx_bdp[i].len_status &= ~OETH_RX_BD_STATS; |
rx_bdp[i].len_status |= OETH_RX_BD_EMPTY; |
//exit(0xbaaaaaad); |
|
continue; |
} |
else { |
/* |
Process the incoming frame. |
*/ |
pkt_len = rx_bdp[i].len_status >> 16; |
|
/* finish up */ |
rx_bdp[i].len_status &= ~OETH_RX_BD_STATS; /* Clear stats */ |
rx_bdp[i].len_status |= OETH_RX_BD_EMPTY; /* Mark RX BD as empty */ |
rx_done++; |
report(rx_done); |
} |
} |
} |
} |
|
|
|
static void |
oeth_tx(void) |
{ |
volatile oeth_bd *tx_bd; |
int i; |
|
tx_bd = (volatile oeth_bd *)OETH_BD_BASE; /* Search from beginning*/ |
|
/* Go through the TX buffs, search for one that was just sent */ |
for(i = 0; i < OETH_TXBD_NUM; i++) |
{ |
/* Looking for buffer NOT ready for transmit. and IRQ enabled */ |
if( (!(tx_bd[i].len_status & (OETH_TX_BD_READY))) && (tx_bd[i].len_status & (OETH_TX_BD_IRQ)) ) |
{ |
/* Single threaded so no chance we have detected a buffer that has had its IRQ bit set but not its BD_READ flag. Maybe this won't work in linux */ |
tx_bd[i].len_status &= ~OETH_TX_BD_IRQ; |
|
/* Probably good to check for TX errors here */ |
|
/* set our test variable */ |
tx_done = 1; |
|
printk("T%d",i); |
|
} |
} |
return; |
} |
|
// Loop to check if a number is prime by doing mod divide of the number |
// to test by every number less than it |
int |
is_prime_number(unsigned long n) |
{ |
unsigned long c; |
if (n < 2) return 0; |
for(c=2;c<n;c++) |
if ((n % c) == 0) |
return 0; |
return 1; |
} |
|
int main () |
{ |
|
/* Initialise handler vector */ |
int_init(); |
|
/* Install ethernet interrupt handler, it is enabled here too */ |
int_add(ETH0_IRQ, oeth_interrupt, 0); |
|
/* Enable interrupts in supervisor register */ |
cpu_enable_user_interrupts(); |
|
rx_done = 0; |
|
ethmac_setup(); /* Configure MAC, TX/RX BDs and enable RX in MODER */ |
|
#define NUM_PRIMES_TO_CHECK 1000 |
|
char prime_check_results[NUM_PRIMES_TO_CHECK]; |
unsigned long num_to_check; |
|
for(num_to_check=2;num_to_check<NUM_PRIMES_TO_CHECK;num_to_check++) |
{ |
prime_check_results[num_to_check-2] |
= (char) is_prime_number(num_to_check); |
report(num_to_check | (0x1e<<24)); |
report(prime_check_results[num_to_check-2] | (0x2e<<24)); |
if (rx_done >= 255) // Check number of packets received, testbench |
// will hopefully send at least 256 packets |
exit(0x8000000d); |
} |
exit(0xbaaaaaad); |
} |
/sw/tests/ethmac/sim/ethmac-tx.c
0,0 → 1,859
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Interrupt-driven Ethernet MAC transmit test code //// |
//// //// |
//// Description //// |
//// Transmits packets, testing both 100mbit and 10mbit modes. //// |
//// Expects testbench to be checking each packet sent. //// |
//// Define, ETH_TX_TEST_LENGTH, set further down, controls how //// |
//// many packets the test will send. //// |
//// //// |
//// Test data comes from pre-calculated array of random values, //// |
//// MAC TX buffer pointers are set to addresses in this array, //// |
//// saving copying the data around before transfers. //// |
//// //// |
//// Author(s): //// |
//// - jb, jb@orsoc.se, with parts taken from Linux kernel //// |
//// open_eth driver. //// |
//// //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
#include "or32-utils.h" |
#include "spr-defs.h" |
#include "board.h" |
#include "int.h" |
#include "uart.h" |
#include "open-eth.h" |
#include "printf.h" |
#include "eth-phy-mii.h" |
|
volatile unsigned tx_done; |
volatile unsigned rx_done; |
static int next_tx_buf_num; |
|
/* Functions in this file */ |
void ethmac_setup(void); |
/* Interrupt functions */ |
void oeth_interrupt(void); |
static void oeth_rx(void); |
static void oeth_tx(void); |
|
/* Defining RTLSIM turns off use of real printf'ing to save time in simulation */ |
#define RTLSIM |
|
#ifdef RTLSIM |
#define printk |
#else |
#define printk printf |
#endif |
/* Let the ethernet packets use a space beginning here for buffering */ |
#define ETH_BUFF_BASE 0x01000000 |
|
|
#define RXBUFF_PREALLOC 1 |
#define TXBUFF_PREALLOC 1 |
//#undef RXBUFF_PREALLOC |
//#undef TXBUFF_PREALLOC |
|
/* The transmitter timeout |
*/ |
#define TX_TIMEOUT (2*HZ) |
|
/* Buffer number (must be 2^n) |
*/ |
#define OETH_RXBD_NUM 16 |
#define OETH_TXBD_NUM 16 |
#define OETH_RXBD_NUM_MASK (OETH_RXBD_NUM-1) |
#define OETH_TXBD_NUM_MASK (OETH_TXBD_NUM-1) |
|
/* Buffer size |
*/ |
#define OETH_RX_BUFF_SIZE 0x600 - 4 |
#define OETH_TX_BUFF_SIZE 0x600 - 4 |
|
/* OR32 Page size def */ |
#define PAGE_SHIFT 13 |
#define PAGE_SIZE (1UL << PAGE_SHIFT) |
|
/* How many buffers per page |
*/ |
#define OETH_RX_BUFF_PPGAE (PAGE_SIZE/OETH_RX_BUFF_SIZE) |
#define OETH_TX_BUFF_PPGAE (PAGE_SIZE/OETH_TX_BUFF_SIZE) |
|
/* How many pages is needed for buffers |
*/ |
#define OETH_RX_BUFF_PAGE_NUM (OETH_RXBD_NUM/OETH_RX_BUFF_PPGAE) |
#define OETH_TX_BUFF_PAGE_NUM (OETH_TXBD_NUM/OETH_TX_BUFF_PPGAE) |
|
/* Buffer size (if not XXBUF_PREALLOC |
*/ |
#define MAX_FRAME_SIZE 1518 |
|
/* The buffer descriptors track the ring buffers. |
*/ |
struct oeth_private { |
//struct sk_buff* rx_skbuff[OETH_RXBD_NUM]; |
//struct sk_buff* tx_skbuff[OETH_TXBD_NUM]; |
|
unsigned short tx_next; /* Next buffer to be sent */ |
unsigned short tx_last; /* Next buffer to be checked if packet sent */ |
unsigned short tx_full; /* Buffer ring fuul indicator */ |
unsigned short rx_cur; /* Next buffer to be checked if packet received */ |
|
oeth_regs *regs; /* Address of controller registers. */ |
oeth_bd *rx_bd_base; /* Address of Rx BDs. */ |
oeth_bd *tx_bd_base; /* Address of Tx BDs. */ |
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// struct net_device_stats stats; |
}; |
|
|
// Data array of data to transmit, tx_data_array[] |
#include "eth-rxtx-data.h" |
int tx_data_pointer; |
|
#define PHYNUM 7 |
|
void |
eth_mii_write(char phynum, short regnum, short data) |
{ |
static volatile oeth_regs *regs = (oeth_regs *)(OETH_REG_BASE); |
regs->miiaddress = (regnum << 8) | phynum; |
regs->miitx_data = data; |
regs->miicommand = OETH_MIICOMMAND_WCTRLDATA; |
regs->miicommand = 0; |
while(regs->miistatus & OETH_MIISTATUS_BUSY); |
} |
|
short |
eth_mii_read(char phynum, short regnum) |
{ |
static volatile oeth_regs *regs = (oeth_regs *)(OETH_REG_BASE); |
regs->miiaddress = (regnum << 8) | phynum; |
regs->miicommand = OETH_MIICOMMAND_RSTAT; |
regs->miicommand = 0; |
while(regs->miistatus & OETH_MIISTATUS_BUSY); |
|
return regs->miirx_data; |
} |
|
|
// Wait here until all packets have been transmitted |
void wait_until_all_tx_clear(void) |
{ |
|
int i; |
volatile oeth_bd *tx_bd; |
tx_bd = (volatile oeth_bd *)OETH_BD_BASE; /* Search from beginning*/ |
|
int some_tx_waiting = 1; |
|
while (some_tx_waiting) |
{ |
some_tx_waiting = 0; |
/* Go through the TX buffs, search for unused one */ |
for(i = 0; i < OETH_TXBD_NUM; i++) { |
|
if((tx_bd[i].len_status & OETH_TX_BD_READY)) // Looking for buffer ready for transmit |
some_tx_waiting = 1; |
|
} |
} |
|
} |
|
|
void |
ethphy_set_10mbit(int phynum) |
{ |
wait_until_all_tx_clear(); |
// Hardset PHY to just use 10Mbit mode |
short cr = eth_mii_read(phynum, MII_BMCR); |
cr &= ~BMCR_ANENABLE; // Clear auto negotiate bit |
cr &= ~BMCR_SPEED100; // Clear fast eth. bit |
eth_mii_write(phynum, MII_BMCR, cr); |
} |
|
|
void |
ethphy_set_100mbit(int phynum) |
{ |
wait_until_all_tx_clear(); |
// Hardset PHY to just use 100Mbit mode |
short cr = eth_mii_read(phynum, MII_BMCR); |
cr |= BMCR_ANENABLE; // Clear auto negotiate bit |
cr |= BMCR_SPEED100; // Clear fast eth. bit |
eth_mii_write(phynum, MII_BMCR, cr); |
} |
|
|
void ethmac_setup(void) |
{ |
// from arch/or32/drivers/open_eth.c |
volatile oeth_regs *regs; |
|
regs = (oeth_regs *)(OETH_REG_BASE); |
|
/* Reset MII mode module */ |
regs->miimoder = OETH_MIIMODER_RST; /* MII Reset ON */ |
regs->miimoder &= ~OETH_MIIMODER_RST; /* MII Reset OFF */ |
regs->miimoder = 0x64; /* Clock divider for MII Management interface */ |
|
/* Reset the controller. |
*/ |
regs->moder = OETH_MODER_RST; /* Reset ON */ |
regs->moder &= ~OETH_MODER_RST; /* Reset OFF */ |
|
/* Setting TXBD base to OETH_TXBD_NUM. |
*/ |
regs->tx_bd_num = OETH_TXBD_NUM; |
|
|
/* Set min/max packet length |
*/ |
regs->packet_len = 0x00400600; |
|
/* Set IPGT register to recomended value |
*/ |
regs->ipgt = 0x12; |
|
/* Set IPGR1 register to recomended value |
*/ |
regs->ipgr1 = 0x0000000c; |
|
/* Set IPGR2 register to recomended value |
*/ |
regs->ipgr2 = 0x00000012; |
|
/* Set COLLCONF register to recomended value |
*/ |
regs->collconf = 0x000f003f; |
|
/* Set control module mode |
*/ |
#if 0 |
regs->ctrlmoder = OETH_CTRLMODER_TXFLOW | OETH_CTRLMODER_RXFLOW; |
#else |
regs->ctrlmoder = 0; |
#endif |
|
/* Clear MIIM registers */ |
regs->miitx_data = 0; |
regs->miiaddress = 0; |
regs->miicommand = 0; |
|
regs->mac_addr1 = ETH_MACADDR0 << 8 | ETH_MACADDR1; |
regs->mac_addr0 = ETH_MACADDR2 << 24 | ETH_MACADDR3 << 16 | ETH_MACADDR4 << 8 | ETH_MACADDR5; |
|
/* Clear all pending interrupts |
*/ |
regs->int_src = 0xffffffff; |
|
/* Promisc, IFG, CRCEn |
*/ |
regs->moder |= OETH_MODER_PRO | OETH_MODER_PAD | OETH_MODER_IFG | OETH_MODER_CRCEN | OETH_MODER_FULLD; |
|
/* Enable interrupt sources. |
*/ |
|
regs->int_mask = OETH_INT_MASK_TXB | |
OETH_INT_MASK_TXE | |
OETH_INT_MASK_RXF | |
OETH_INT_MASK_RXE | |
OETH_INT_MASK_BUSY | |
OETH_INT_MASK_TXC | |
OETH_INT_MASK_RXC; |
|
// Buffer setup stuff |
volatile oeth_bd *tx_bd, *rx_bd; |
int i,j,k; |
|
/* Initialize TXBD pointer |
*/ |
tx_bd = (volatile oeth_bd *)OETH_BD_BASE; |
|
/* Initialize RXBD pointer |
*/ |
rx_bd = ((volatile oeth_bd *)OETH_BD_BASE) + OETH_TXBD_NUM; |
|
/* Preallocated ethernet buffer setup */ |
unsigned long mem_addr = ETH_BUFF_BASE; /* Defined at top */ |
|
// Setup TX Buffers |
for(i = 0; i < OETH_TXBD_NUM; i++) { |
//tx_bd[i].len_status = OETH_TX_BD_PAD | OETH_TX_BD_CRC | OETH_RX_BD_IRQ; |
tx_bd[i].len_status = OETH_TX_BD_PAD | OETH_TX_BD_CRC; |
tx_bd[i].addr = mem_addr; |
mem_addr += OETH_TX_BUFF_SIZE; |
} |
tx_bd[OETH_TXBD_NUM - 1].len_status |= OETH_TX_BD_WRAP; |
|
// Setup RX buffers |
for(i = 0; i < OETH_RXBD_NUM; i++) { |
rx_bd[i].len_status = OETH_RX_BD_EMPTY | OETH_RX_BD_IRQ; // Init. with IRQ |
rx_bd[i].addr = mem_addr; |
mem_addr += OETH_RX_BUFF_SIZE; |
} |
rx_bd[OETH_RXBD_NUM - 1].len_status |= OETH_RX_BD_WRAP; // Last buffer wraps |
|
/* Enable JUST the transmiter |
*/ |
regs->moder &= ~(OETH_MODER_RXEN | OETH_MODER_TXEN); |
regs->moder |= /*OETH_MODER_RXEN |*/ OETH_MODER_TXEN; |
|
next_tx_buf_num = 0; // init tx buffer pointer |
|
return; |
} |
|
|
|
/* Setup buffer descriptors with data */ |
/* length is in BYTES */ |
void tx_packet(void* data, int length) |
{ |
volatile oeth_regs *regs; |
regs = (oeth_regs *)(OETH_REG_BASE); |
|
volatile oeth_bd *tx_bd; |
volatile int i; |
|
tx_bd = (volatile oeth_bd *)OETH_BD_BASE; |
tx_bd = (struct oeth_bd*) &tx_bd[next_tx_buf_num]; |
|
// If it's in use - wait |
while ((tx_bd->len_status & OETH_TX_BD_IRQ)); |
|
/* Clear all of the status flags. |
*/ |
tx_bd->len_status &= ~OETH_TX_BD_STATS; |
|
/* If the frame is short, tell CPM to pad it. |
*/ |
#define ETH_ZLEN 60 /* Min. octets in frame sans FCS */ |
if (length <= ETH_ZLEN) |
tx_bd->len_status |= OETH_TX_BD_PAD; |
else |
tx_bd->len_status &= ~OETH_TX_BD_PAD; |
|
#ifdef _ETH_RXTX_DATA_H_ |
// Set the address pointer to the place |
// in memory where the data is and transmit from there |
|
tx_bd->addr = (char*) &tx_data_array[tx_data_pointer&~(0x3)]; |
|
tx_data_pointer += length; |
if (tx_data_pointer > (255*1024)) |
tx_data_pointer = 0; |
|
|
#else |
if (data){ |
//Copy the data into the transmit buffer, byte at a time |
char* data_p = (char*) data; |
char* data_b = (char*) tx_bd->addr; |
for(i=0;i<length;i++) |
{ |
data_b[i] = data_p[i]; |
} |
} |
#endif |
|
/* Set the length of the packet's data in the buffer descriptor */ |
tx_bd->len_status = (tx_bd->len_status & 0x0000ffff) | |
((length&0xffff) << 16); |
|
/* Send it on its way. Tell controller its ready, interrupt when sent |
* and to put the CRC on the end. |
*/ |
tx_bd->len_status |= (OETH_TX_BD_READY | OETH_TX_BD_CRC | OETH_TX_BD_IRQ); |
|
next_tx_buf_num = (next_tx_buf_num + 1) & OETH_TXBD_NUM_MASK; |
|
return; |
|
} |
|
/* enable RX, loop waiting for arrived packets and print them out */ |
void oeth_monitor_rx(void) |
{ |
volatile oeth_regs *regs; |
regs = (oeth_regs *)(OETH_REG_BASE); |
|
/* Set RXEN in MAC MODER */ |
regs->moder = OETH_MODER_RXEN | regs->moder; |
|
|
volatile oeth_bd *rx_bd; |
rx_bd = ((volatile oeth_bd *)OETH_BD_BASE) + OETH_TXBD_NUM; |
|
volatile int i; |
|
while (1) |
{ |
|
for(i=0;i<OETH_RXBD_NUM;i++) |
{ |
if (!(rx_bd[i].len_status & OETH_RX_BD_EMPTY)) /* Not empty */ |
{ |
// Something in this buffer! |
printk("Oeth: RX in buf %d - len_status: 0x%lx\n",i, rx_bd[i].len_status); |
/* Clear recieved bit */ |
rx_bd[i].len_status |= OETH_RX_BD_EMPTY; |
printk("\t end of packet\n\n"); |
} |
} |
} |
} |
|
|
char broadcast_ping_packet[] = { |
0xff,0xff,0xff,0xff,0xff,0xff, /*SRC MAC*/ |
0x00, 0x12, 0x34, 0x56, 0x78, 0x9a, /*SRC MAC*/ |
0x08,0x00, |
0x45, |
0x00, |
0x00,0x54, |
0x00,0x00, |
0x40, |
0x00, |
0x40, |
0x01, |
0xef,0xef, |
0xc0,0xa8,0x64,0x58, /* Source IP */ |
0xc0,0xa8,0x64,0xff, /* Dest. IP */ |
/* ICMP Message body */ |
0x08,0x00,0x7d,0x65,0xa7,0x20,0x00,0x01,0x68,0x25,0xa5,0x4a,0xcf,0x05,0x0c,0x00,0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e,0x1f,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37}; |
|
|
char big_broadcast_ping_packet[] = { |
0xff,0xff,0xff,0xff,0xff,0xff, /*SRC MAC*/ |
0x00, 0x12, 0x34, 0x56, 0x78, 0x9a, /*SRC MAC*/ |
0x08,0x00, |
0x45, |
0x00, |
// 0x00,0x54, /* length */ |
0x05,0x1c, /* length */ |
0x00,0x00, |
0x40, |
0x00, |
0x40, |
0x01, |
0xee,0xf5, |
0xc0,0xa8,0x64,0x9b, /* Source IP */ |
0xc0,0xa8,0x64,0xff, /* Dest. IP */ |
/* ICMP Message body */ |
0x08,0x00,0x7d,0x65,0xa7,0x20,0x00,0x01,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14, |
15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39, |
40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64, |
65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89, |
90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110, |
111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129, |
130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148, |
149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167, |
168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186, |
187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205, |
206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224, |
225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243, |
244,245,246,247,248,249,250,251,252,253,254,255, |
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14, |
15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39, |
40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64, |
65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89, |
90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110, |
111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129, |
130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148, |
149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167, |
168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186, |
187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205, |
206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224, |
225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243, |
244,245,246,247,248,249,250,251,252,253,254,255, |
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14, |
15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39, |
40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64, |
65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89, |
90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110, |
111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129, |
130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148, |
149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167, |
168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186, |
187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205, |
206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224, |
225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243, |
244,245,246,247,248,249,250,251,252,253,254,255, |
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14, |
15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39, |
40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64, |
65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89, |
90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110, |
111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129, |
130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148, |
149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167, |
168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186, |
187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205, |
206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224, |
225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243, |
244,245,246,247,248,249,250,251,252,253,254,255, |
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14, |
15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39, |
40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64, |
65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89, |
90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110, |
111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129, |
130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148, |
149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167, |
168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186, |
187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205, |
206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224, |
225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243, |
244,245,246,247,248,249,250,251,252,253,254,255}; |
|
|
/* This should be 98 bytes big */ |
char ping_packet[] = { |
0x00, 0x24, 0xe8, 0x91, 0x7c, 0x0d, /*DST MAC*/ |
//0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /*DST MAC*/ |
0x00, 0x12, 0x34, 0x56, 0x78, 0x9a, /*SRC MAC*/ |
0x08, 0x00, /*TYPE*/ |
/* IP */ |
0x45, /* Version, header length*/ |
0x00, /* Differentiated services field */ |
0x00, 0x54, /* Total length */ |
0x00, 0x00, /* Identification */ |
0x40, /* Flags */ |
0x00, /* Fragment offset */ |
0x40, /* Time to live */ |
0x01, /* Protocol (0x01 = ICMP */ |
0xef, 0xf3, /* Header checksum */ |
//0xc0, 0xa8, 0x64, 0xDE, /* Source IP */ |
0xc0, 0xa8, 0x0, 0x58, /* Source IP */ |
//0xa, 0x1, 0x1, 0x3, /* Source IP */ |
0xc0, 0xa8, 0x64, 0x69, /* Dest. IP */ |
0xc0, 0xa8, 0x0, 0xb, /* Dest. IP */ |
//0xa, 0x1, 0x1, 0x1, /* Dest. IP */ |
/* ICMP Message body */ |
0x08, 0x00, 0x9a, 0xd4, 0xc8, 0x18, 0x00, 0x01, 0xd9, 0x8c, 0x54, |
0x4a, 0x7b, 0x37, 0x01, 0x00, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, |
0x0e, 0x0f, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, |
0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23, |
0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, |
0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37 |
}; |
|
|
/* The interrupt handler. |
*/ |
void |
oeth_interrupt(void) |
{ |
|
volatile oeth_regs *regs; |
regs = (oeth_regs *)(OETH_REG_BASE); |
|
uint int_events; |
int serviced; |
|
serviced = 0; |
|
/* Get the interrupt events that caused us to be here. |
*/ |
int_events = regs->int_src; |
regs->int_src = int_events; |
|
|
#ifndef RTLSIM |
printk("."); |
|
printk("\n=tx_ | %x | %x | %x | %x | %x | %x | %x | %x\n", |
((oeth_bd *)(OETH_BD_BASE))->len_status, |
((oeth_bd *)(OETH_BD_BASE+8))->len_status, |
((oeth_bd *)(OETH_BD_BASE+16))->len_status, |
((oeth_bd *)(OETH_BD_BASE+24))->len_status, |
((oeth_bd *)(OETH_BD_BASE+32))->len_status, |
((oeth_bd *)(OETH_BD_BASE+40))->len_status, |
((oeth_bd *)(OETH_BD_BASE+48))->len_status, |
((oeth_bd *)(OETH_BD_BASE+56))->len_status); |
|
printk("=rx_ | %x | %x | %x | %x | %x | %x | %x | %x\n", |
((oeth_bd *)(OETH_BD_BASE+64))->len_status, |
((oeth_bd *)(OETH_BD_BASE+64+8))->len_status, |
((oeth_bd *)(OETH_BD_BASE+64+16))->len_status, |
((oeth_bd *)(OETH_BD_BASE+64+24))->len_status, |
((oeth_bd *)(OETH_BD_BASE+64+32))->len_status, |
((oeth_bd *)(OETH_BD_BASE+64+40))->len_status, |
((oeth_bd *)(OETH_BD_BASE+64+48))->len_status, |
((oeth_bd *)(OETH_BD_BASE+64+56))->len_status); |
|
printk("=int | txb %d | txe %d | rxb %d | rxe %d | busy %d\n", |
(int_events & OETH_INT_TXB) > 0, |
(int_events & OETH_INT_TXE) > 0, |
(int_events & OETH_INT_RXF) > 0, |
(int_events & OETH_INT_RXE) > 0, |
(int_events & OETH_INT_BUSY) > 0); |
#endif |
|
|
|
/* Handle receive event in its own function. |
*/ |
if (int_events & (OETH_INT_RXF | OETH_INT_RXE)) { |
serviced |= 0x1; |
oeth_rx(); |
} |
|
/* Handle transmit event in its own function. |
*/ |
if (int_events & (OETH_INT_TXB | OETH_INT_TXE)) { |
serviced |= 0x2; |
oeth_tx(); |
serviced |= 0x2; |
|
} |
|
/* Check for receive busy, i.e. packets coming but no place to |
* put them. |
*/ |
if (int_events & OETH_INT_BUSY) { |
serviced |= 0x4; |
#ifndef RTLSIM |
printk("b"); |
#endif |
if (!(int_events & (OETH_INT_RXF | OETH_INT_RXE))) |
oeth_rx(); |
} |
|
|
#if 0 |
if (serviced == 0) { |
void die(const char * str, struct pt_regs * regs, long err); |
int show_stack(unsigned long *esp); |
printk("!"); |
// printk("unserviced irq\n"); |
// show_stack(NULL); |
// die("unserviced irq\n", regs, 801); |
} |
#endif |
|
if (serviced == 0) |
printk("\neth interrupt called but nothing serviced\n"); |
|
else /* Something happened ... either RX or TX */ |
printk(" | serviced 0x%x\n", serviced); |
|
return; |
} |
|
|
|
static void |
oeth_rx(void) |
{ |
volatile oeth_regs *regs; |
regs = (oeth_regs *)(OETH_REG_BASE); |
|
volatile oeth_bd *rx_bdp; |
int pkt_len, i; |
int bad = 0; |
|
rx_bdp = ((oeth_bd *)OETH_BD_BASE) + OETH_TXBD_NUM; |
|
printk("r"); |
|
|
/* Find RX buffers marked as having received data */ |
for(i = 0; i < OETH_RXBD_NUM; i++) |
{ |
bad=0; |
if(!(rx_bdp[i].len_status & OETH_RX_BD_EMPTY)){ /* Looking for NOT empty buffers desc. */ |
/* Check status for errors. |
*/ |
if (rx_bdp[i].len_status & (OETH_RX_BD_TOOLONG | OETH_RX_BD_SHORT)) { |
bad = 1; |
report(0xbaad0001); |
} |
if (rx_bdp[i].len_status & OETH_RX_BD_DRIBBLE) { |
bad = 1; |
report(0xbaad0002); |
} |
if (rx_bdp[i].len_status & OETH_RX_BD_CRCERR) { |
bad = 1; |
report(0xbaad0003); |
} |
if (rx_bdp[i].len_status & OETH_RX_BD_OVERRUN) { |
bad = 1; |
report(0xbaad0004); |
} |
if (rx_bdp[i].len_status & OETH_RX_BD_MISS) { |
report(0xbaad0005); |
} |
if (rx_bdp[i].len_status & OETH_RX_BD_LATECOL) { |
bad = 1; |
report(0xbaad0006); |
} |
if (bad) { |
rx_bdp[i].len_status &= ~OETH_RX_BD_STATS; |
rx_bdp[i].len_status |= OETH_RX_BD_EMPTY; |
exit(0xbaaaaaad); |
|
continue; |
} |
else { |
/* Process the incoming frame. |
*/ |
pkt_len = rx_bdp[i].len_status >> 16; |
|
/* Do something here with the data - copy it into userspace, perhaps*/ |
printk("\t end of packet\n\n"); |
|
|
/* finish up */ |
rx_bdp[i].len_status &= ~OETH_RX_BD_STATS; /* Clear stats */ |
rx_bdp[i].len_status |= OETH_RX_BD_EMPTY; /* Mark RX BD as empty */ |
rx_done++; |
} |
} |
} |
} |
|
|
|
static void |
oeth_tx(void) |
{ |
volatile oeth_bd *tx_bd; |
int i; |
|
tx_bd = (volatile oeth_bd *)OETH_BD_BASE; /* Search from beginning*/ |
|
/* Go through the TX buffs, search for one that was just sent */ |
for(i = 0; i < OETH_TXBD_NUM; i++) |
{ |
/* Looking for buffer NOT ready for transmit. and IRQ enabled */ |
if( (!(tx_bd[i].len_status & (OETH_TX_BD_READY))) && (tx_bd[i].len_status & (OETH_TX_BD_IRQ)) ) |
{ |
/* Single threaded so no chance we have detected a buffer that has had its IRQ bit set but not its BD_READ flag. Maybe this won't work in linux */ |
tx_bd[i].len_status &= ~OETH_TX_BD_IRQ; |
|
/* Probably good to check for TX errors here */ |
|
/* set our test variable */ |
tx_done++; |
|
printk("T%d",i); |
|
} |
} |
return; |
} |
|
// A function and defines to fill and transmit a packet |
#define MAX_TX_BUFFER 1532 |
static char tx_buffer[MAX_TX_BUFFER]; |
static unsigned long tx_data = 0x2ef2e242; |
static inline char gen_next_tx_byte(void) |
{ |
// Bit of LFSR action |
tx_data = ((~(((((tx_data&(1<<25))>>25)^((tx_data&(1<<13))>>13))^((tx_data&(1<<2))>>2)))&0x01) | (tx_data<<1)); |
//tx_data++; |
return (char) tx_data & 0xff; |
} |
|
void |
fill_and_tx_packet(int size) |
{ |
int i; |
char tx_byte; |
|
|
volatile oeth_regs *regs; |
regs = (oeth_regs *)(OETH_REG_BASE); |
|
volatile oeth_bd *tx_bd; |
|
tx_bd = (volatile oeth_bd *)OETH_BD_BASE; |
tx_bd = (struct oeth_bd*) &tx_bd[next_tx_buf_num]; |
|
|
// If it's in use - wait |
while ((tx_bd->len_status & OETH_TX_BD_IRQ)); |
|
#ifndef _ETH_RXTX_DATA_H_ |
/* Copy the data into the transmit buffer, byte at a time */ |
char* data_b = (char*) tx_bd->addr; |
for(i=0;i<size;i++) |
{ |
data_b[i] = gen_next_tx_byte(); |
} |
#endif |
|
tx_packet((void*)0, size); |
} |
|
//#define WAIT_PACKET_TX(x) while(tx_done<x) |
#define WAIT_PACKET_TX(x) |
|
int main () |
{ |
tx_data_pointer = 0; |
|
/* Initialise handler vector */ |
int_init(); |
|
/* Install ethernet interrupt handler, it is enabled here too */ |
int_add(ETH0_IRQ, oeth_interrupt, 0); |
|
/* Enable interrupts in supervisor register */ |
mtspr (SPR_SR, mfspr (SPR_SR) | SPR_SR_IEE); |
|
ethmac_setup(); /* Configure MAC, TX/RX BDs and enable RX and TX in MODER */ |
|
/* clear tx_done, the tx interrupt handler will set it when it's been transmitted */ |
tx_done = 0; |
rx_done = 0; |
|
int i; |
ethphy_set_100mbit(0); |
|
#ifndef ETH_TX_TEST_LENGTH |
# define ETH_TX_TEST_LENGTH 128 |
//# define ETH_TX_TEST_LENGTH OETH_TX_BUFF_SIZE |
#endif |
|
for(i=5;i<ETH_TX_TEST_LENGTH;i+=1) |
fill_and_tx_packet(i); |
|
ethphy_set_10mbit(0); |
for(i=5;i<ETH_TX_TEST_LENGTH;i+=1) |
fill_and_tx_packet(i); |
|
exit(0x8000000d); |
|
|
} |
/sw/tests/ethmac/sim/Makefile
0,0 → 1,13
SW_ROOT=../../.. |
|
include $(SW_ROOT)/Makefile.inc |
|
%.dis: %.elf |
$(Q)$(OR32_OBJDUMP) -d $< > $@ |
|
%.bin: %.elf |
$(Q)$(OR32_OBJCOPY) -O binary $< $@ |
|
clean: |
$(Q)rm -f *.elf *.bin *.vmem *.flashin *.dis |
|
/sw/drivers/ethmac/ethmac.c
0,0 → 1,46
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Ethernet MAC driver functions //// |
//// //// |
//// Description //// |
//// A collection of functions to help control the OpenCores //// |
//// 10/100 ethernet mac (ethmac) core. //// |
//// //// |
//// //// |
//// Author(s): //// |
//// - Julius Baxter, julius@opencores.org //// |
//// - Parts taken from Linux kernel's open_eth driver. //// |
//// //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009,2010 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
/* Dummy function for now, just to make the driver compile */ |
void ethmac_init() |
{ |
return; |
} |
/sw/drivers/ethmac/include/eth-phy-mii.h
0,0 → 1,149
#ifndef _ETH_PHY_MII_H_ |
#define _ETH_PHY_MII_H_ |
/* Generic MII registers. */ |
|
#define MII_BMCR 0x00 /* Basic mode control register */ |
#define MII_BMSR 0x01 /* Basic mode status register */ |
#define MII_PHYSID1 0x02 /* PHYS ID 1 */ |
#define MII_PHYSID2 0x03 /* PHYS ID 2 */ |
#define MII_ADVERTISE 0x04 /* Advertisement control reg */ |
#define MII_LPA 0x05 /* Link partner ability reg */ |
#define MII_EXPANSION 0x06 /* Expansion register */ |
#define MII_CTRL1000 0x09 /* 1000BASE-T control */ |
#define MII_STAT1000 0x0a /* 1000BASE-T status */ |
#define MII_ESTATUS 0x0f /* Extended Status */ |
#define MII_DCOUNTER 0x12 /* Disconnect counter */ |
#define MII_FCSCOUNTER 0x13 /* False carrier counter */ |
#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ |
#define MII_RERRCOUNTER 0x15 /* Receive error counter */ |
#define MII_SREVISION 0x16 /* Silicon revision */ |
#define MII_RESV1 0x17 /* Reserved... */ |
#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */ |
#define MII_PHYADDR 0x19 /* PHY address */ |
#define MII_RESV2 0x1a /* Reserved... */ |
#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */ |
#define MII_NCONFIG 0x1c /* Network interface config */ |
|
/* Basic mode control register. */ |
#define BMCR_SPD2 0x0040 /* Gigabit enable? (bcm5411) */ |
#define BMCR_RESV 0x003f /* Unused... */ |
#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ |
#define BMCR_CTST 0x0080 /* Collision test */ |
#define BMCR_FULLDPLX 0x0100 /* Full duplex */ |
#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ |
#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */ |
#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */ |
#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ |
#define BMCR_SPEED100 0x2000 /* Select 100Mbps */ |
#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ |
#define BMCR_RESET 0x8000 /* Reset the DP83840 */ |
|
/* Basic mode status register. */ |
#define BMSR_ERCAP 0x0001 /* Ext-reg capability */ |
#define BMSR_JCD 0x0002 /* Jabber detected */ |
#define BMSR_LSTATUS 0x0004 /* Link status */ |
#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ |
#define BMSR_RFAULT 0x0010 /* Remote fault detected */ |
#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ |
#define BMSR_RESV 0x00c0 /* Unused... */ |
#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ |
#define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */ |
#define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */ |
#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ |
#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ |
#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ |
#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ |
#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */ |
|
/* Advertisement control register. */ |
#define ADVERTISE_SLCT 0x001f /* Selector bits */ |
#define ADVERTISE_CSMA 0x0001 /* Only selector supported */ |
#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ |
#define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */ |
#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ |
#define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */ |
#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ |
#define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */ |
#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ |
#define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */ |
#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ |
#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */ |
#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */ |
#define ADVERTISE_RESV 0x1000 /* Unused... */ |
#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ |
#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ |
#define ADVERTISE_NPAGE 0x8000 /* Next page bit */ |
|
#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ |
ADVERTISE_CSMA) |
#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ |
ADVERTISE_100HALF | ADVERTISE_100FULL) |
|
/* Link partner ability register. */ |
#define LPA_SLCT 0x001f /* Same as advertise selector */ |
#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */ |
#define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */ |
#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */ |
#define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */ |
#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */ |
#define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */ |
#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */ |
#define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym*/ |
#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */ |
#define LPA_PAUSE_CAP 0x0400 /* Can pause */ |
#define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */ |
#define LPA_RESV 0x1000 /* Unused... */ |
#define LPA_RFAULT 0x2000 /* Link partner faulted */ |
#define LPA_LPACK 0x4000 /* Link partner acked us */ |
#define LPA_NPAGE 0x8000 /* Next page bit */ |
|
#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) |
#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) |
|
/* Expansion register for auto-negotiation. */ |
#define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */ |
#define EXPANSION_LCWP 0x0002 /* Got new RX page code word */ |
#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */ |
#define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */ |
#define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */ |
#define EXPANSION_RESV 0xffe0 /* Unused... */ |
|
#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ |
#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ |
|
/* N-way test register. */ |
#define NWAYTEST_RESV1 0x00ff /* Unused... */ |
#define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */ |
#define NWAYTEST_RESV2 0xfe00 /* Unused... */ |
|
/* 1000BASE-T Control register */ |
#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */ |
#define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */ |
|
/* 1000BASE-T Status register */ |
#define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */ |
#define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */ |
#define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */ |
#define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */ |
|
/* 1000BT control (Marvell & BCM54xx at least) */ |
#define MII_1000BASETCONTROL 0x09 |
#define MII_1000BASETCONTROL_FULLDUPLEXCAP 0x0200 |
#define MII_1000BASETCONTROL_HALFDUPLEXCAP 0x0100 |
|
/* Marvell 88E1011 PHY control */ |
#define MII_M1011_PHY_SPEC_CONTROL 0x10 |
#define MII_M1011_PHY_SPEC_CONTROL_MANUAL_MDIX 0x20 |
#define MII_M1011_PHY_SPEC_CONTROL_AUTO_MDIX 0x40 |
|
/* Marvell 88E1011 PHY status */ |
#define MII_M1011_PHY_SPEC_STATUS 0x11 |
#define MII_M1011_PHY_SPEC_STATUS_1000 0x8000 |
#define MII_M1011_PHY_SPEC_STATUS_100 0x4000 |
#define MII_M1011_PHY_SPEC_STATUS_SPD_MASK 0xc000 |
#define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX 0x2000 |
#define MII_M1011_PHY_SPEC_STATUS_RESOLVED 0x0800 |
#define MII_M1011_PHY_SPEC_STATUS_TX_PAUSE 0x0008 |
#define MII_M1011_PHY_SPEC_STATUS_RX_PAUSE 0x0004 |
|
#endif |
/sw/drivers/ethmac/include/ethmac.h
0,0 → 1,195
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Ethernet MAC driver functions //// |
//// //// |
//// Description //// |
//// A collection of functions to help control the OpenCores //// |
//// 10/100 ethernet mac (ethmac) core. //// |
//// //// |
//// //// |
//// Author(s): //// |
//// - Julius Baxter, julius@opencores.org //// |
//// - Parts taken from Linux kernel's open_eth driver. //// |
//// //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009,2010 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
#ifndef _ETHMAC_H_ |
#define _ETHMAC_H |
typedef unsigned int uint; |
|
/* Ethernet configuration registers */ |
typedef struct _oeth_regs { |
uint moder; /* Mode Register */ |
uint int_src; /* Interrupt Source Register */ |
uint int_mask; /* Interrupt Mask Register */ |
uint ipgt; /* Back to Bak Inter Packet Gap Register */ |
uint ipgr1; /* Non Back to Back Inter Packet Gap Register 1 */ |
uint ipgr2; /* Non Back to Back Inter Packet Gap Register 2 */ |
uint packet_len; /* Packet Length Register (min. and max.) */ |
uint collconf; /* Collision and Retry Configuration Register */ |
uint tx_bd_num; /* Transmit Buffer Descriptor Number Register */ |
uint ctrlmoder; /* Control Module Mode Register */ |
uint miimoder; /* MII Mode Register */ |
uint miicommand; /* MII Command Register */ |
uint miiaddress; /* MII Address Register */ |
uint miitx_data; /* MII Transmit Data Register */ |
uint miirx_data; /* MII Receive Data Register */ |
uint miistatus; /* MII Status Register */ |
uint mac_addr0; /* MAC Individual Address Register 0 */ |
uint mac_addr1; /* MAC Individual Address Register 1 */ |
uint hash_addr0; /* Hash Register 0 */ |
uint hash_addr1; /* Hash Register 1 */ |
} oeth_regs; |
|
/* Ethernet buffer descriptor */ |
typedef struct _oeth_bd { |
#if 0 |
ushort len; /* Buffer length */ |
ushort status; /* Buffer status */ |
#else |
uint len_status; |
#endif |
uint addr; /* Buffer address */ |
} oeth_bd; |
|
// From board.h |
#define ETH_BASE_ADD ETH0_BASE |
|
#define OETH_REG_BASE ETH_BASE_ADD |
#define OETH_BD_BASE (ETH_BASE_ADD + 0x400) |
#define OETH_TOTAL_BD 128 |
#define OETH_MAXBUF_LEN 0x600 |
|
/* Tx BD */ |
#define OETH_TX_BD_READY 0x8000 /* Tx BD Ready */ |
#define OETH_TX_BD_IRQ 0x4000 /* Tx BD IRQ Enable */ |
#define OETH_TX_BD_WRAP 0x2000 /* Tx BD Wrap (last BD) */ |
#define OETH_TX_BD_PAD 0x1000 /* Tx BD Pad Enable */ |
#define OETH_TX_BD_CRC 0x0800 /* Tx BD CRC Enable */ |
|
#define OETH_TX_BD_UNDERRUN 0x0100 /* Tx BD Underrun Status */ |
#define OETH_TX_BD_RETRY 0x00F0 /* Tx BD Retry Status */ |
#define OETH_TX_BD_RETLIM 0x0008 /* Tx BD Retransmission Limit Status */ |
#define OETH_TX_BD_LATECOL 0x0004 /* Tx BD Late Collision Status */ |
#define OETH_TX_BD_DEFER 0x0002 /* Tx BD Defer Status */ |
#define OETH_TX_BD_CARRIER 0x0001 /* Tx BD Carrier Sense Lost Status */ |
#define OETH_TX_BD_STATS (OETH_TX_BD_UNDERRUN | \ |
OETH_TX_BD_RETRY | \ |
OETH_TX_BD_RETLIM | \ |
OETH_TX_BD_LATECOL | \ |
OETH_TX_BD_DEFER | \ |
OETH_TX_BD_CARRIER) |
|
/* Rx BD */ |
#define OETH_RX_BD_EMPTY 0x8000 /* Rx BD Empty */ |
#define OETH_RX_BD_IRQ 0x4000 /* Rx BD IRQ Enable */ |
#define OETH_RX_BD_WRAP 0x2000 /* Rx BD Wrap (last BD) */ |
|
#define OETH_RX_BD_MISS 0x0080 /* Rx BD Miss Status */ |
#define OETH_RX_BD_OVERRUN 0x0040 /* Rx BD Overrun Status */ |
#define OETH_RX_BD_INVSIMB 0x0020 /* Rx BD Invalid Symbol Status */ |
#define OETH_RX_BD_DRIBBLE 0x0010 /* Rx BD Dribble Nibble Status */ |
#define OETH_RX_BD_TOOLONG 0x0008 /* Rx BD Too Long Status */ |
#define OETH_RX_BD_SHORT 0x0004 /* Rx BD Too Short Frame Status */ |
#define OETH_RX_BD_CRCERR 0x0002 /* Rx BD CRC Error Status */ |
#define OETH_RX_BD_LATECOL 0x0001 /* Rx BD Late Collision Status */ |
#define OETH_RX_BD_STATS (OETH_RX_BD_MISS | \ |
OETH_RX_BD_OVERRUN | \ |
OETH_RX_BD_INVSIMB | \ |
OETH_RX_BD_DRIBBLE | \ |
OETH_RX_BD_TOOLONG | \ |
OETH_RX_BD_SHORT | \ |
OETH_RX_BD_CRCERR | \ |
OETH_RX_BD_LATECOL) |
|
/* MODER Register */ |
#define OETH_MODER_RXEN 0x00000001 /* Receive Enable */ |
#define OETH_MODER_TXEN 0x00000002 /* Transmit Enable */ |
#define OETH_MODER_NOPRE 0x00000004 /* No Preamble */ |
#define OETH_MODER_BRO 0x00000008 /* Reject Broadcast */ |
#define OETH_MODER_IAM 0x00000010 /* Use Individual Hash */ |
#define OETH_MODER_PRO 0x00000020 /* Promiscuous (receive all) */ |
#define OETH_MODER_IFG 0x00000040 /* Min. IFG not required */ |
#define OETH_MODER_LOOPBCK 0x00000080 /* Loop Back */ |
#define OETH_MODER_NOBCKOF 0x00000100 /* No Backoff */ |
#define OETH_MODER_EXDFREN 0x00000200 /* Excess Defer */ |
#define OETH_MODER_FULLD 0x00000400 /* Full Duplex */ |
#define OETH_MODER_RST 0x00000800 /* Reset MAC */ |
#define OETH_MODER_DLYCRCEN 0x00001000 /* Delayed CRC Enable */ |
#define OETH_MODER_CRCEN 0x00002000 /* CRC Enable */ |
#define OETH_MODER_HUGEN 0x00004000 /* Huge Enable */ |
#define OETH_MODER_PAD 0x00008000 /* Pad Enable */ |
#define OETH_MODER_RECSMALL 0x00010000 /* Receive Small */ |
|
/* Interrupt Source Register */ |
#define OETH_INT_TXB 0x00000001 /* Transmit Buffer IRQ */ |
#define OETH_INT_TXE 0x00000002 /* Transmit Error IRQ */ |
#define OETH_INT_RXF 0x00000004 /* Receive Frame IRQ */ |
#define OETH_INT_RXE 0x00000008 /* Receive Error IRQ */ |
#define OETH_INT_BUSY 0x00000010 /* Busy IRQ */ |
#define OETH_INT_TXC 0x00000020 /* Transmit Control Frame IRQ */ |
#define OETH_INT_RXC 0x00000040 /* Received Control Frame IRQ */ |
|
/* Interrupt Mask Register */ |
#define OETH_INT_MASK_TXB 0x00000001 /* Transmit Buffer IRQ Mask */ |
#define OETH_INT_MASK_TXE 0x00000002 /* Transmit Error IRQ Mask */ |
#define OETH_INT_MASK_RXF 0x00000004 /* Receive Frame IRQ Mask */ |
#define OETH_INT_MASK_RXE 0x00000008 /* Receive Error IRQ Mask */ |
#define OETH_INT_MASK_BUSY 0x00000010 /* Busy IRQ Mask */ |
#define OETH_INT_MASK_TXC 0x00000020 /* Transmit Control Frame IRQ Mask */ |
#define OETH_INT_MASK_RXC 0x00000040 /* Received Control Frame IRQ Mask */ |
|
/* Control Module Mode Register */ |
#define OETH_CTRLMODER_PASSALL 0x00000001 /* Pass Control Frames */ |
#define OETH_CTRLMODER_RXFLOW 0x00000002 /* Receive Control Flow Enable */ |
#define OETH_CTRLMODER_TXFLOW 0x00000004 /* Transmit Control Flow Enable */ |
|
/* MII Mode Register */ |
#define OETH_MIIMODER_CLKDIV 0x000000FF /* Clock Divider */ |
#define OETH_MIIMODER_NOPRE 0x00000100 /* No Preamble */ |
#define OETH_MIIMODER_RST 0x00000200 /* MIIM Reset */ |
|
/* MII Command Register */ |
#define OETH_MIICOMMAND_SCANSTAT 0x00000001 /* Scan Status */ |
#define OETH_MIICOMMAND_RSTAT 0x00000002 /* Read Status */ |
#define OETH_MIICOMMAND_WCTRLDATA 0x00000004 /* Write Control Data */ |
|
/* MII Address Register */ |
#define OETH_MIIADDRESS_FIAD 0x0000001F /* PHY Address */ |
#define OETH_MIIADDRESS_RGAD 0x00001F00 /* RGAD Address */ |
|
/* MII Status Register */ |
#define OETH_MIISTATUS_LINKFAIL 0x00000001 /* Link Fail */ |
#define OETH_MIISTATUS_BUSY 0x00000002 /* MII Busy */ |
#define OETH_MIISTATUS_NVALID 0x00000004 /* Data in MII Status Register is invalid */ |
|
/* Dummy function for now, just to make the driver compile */ |
void ethmac_init(); |
|
#endif |
/sw/drivers/ethmac/Makefile
0,0 → 1,8
SW_ROOT=../.. |
|
COMPILE_SRCS=ethmac.c |
|
include $(SW_ROOT)/Makefile.inc |
|
clean: |
$(Q)rm -f *.a *.o |
/boards/actel/ordb1a3pe1500/bench/verilog/include/eth_stim.v
47,7 → 47,7
// Is straight forward when using RTL design, but if using netlist then paths to |
// the RX/TX enabled bits depend on synthesis tool, etc, but ones here appear to |
// work with design put through Synplify, with hierarchy maintained. |
`define ETH_TOP dut.eth0 |
`define ETH_TOP dut.ethmac0 |
`define ETH_BD_RAM_PATH `ETH_TOP.wishbone.bd_ram |
`define ETH_MODER_PATH `ETH_TOP.ethreg1.MODER_0 |
|
/boards/actel/ordb1a3pe1500/rtl/verilog/include/eth_defines.v
File deleted
\ No newline at end of file
/boards/actel/ordb1a3pe1500/rtl/verilog/include/ethmac_defines.v
0,0 → 1,255
////////////////////////////////////////////////////////////////////// |
//// //// |
//// eth_defines.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
//// //// |
//// Modified by: //// |
//// - Julius Baxter (julius@opencores.org) //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2001, 2002 Authors //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
|
|
//`define ETH_BIST // Bist for usage with Virtual Silicon RAMS |
|
`define ETH_MBIST_CTRL_WIDTH 3 // width of MBIST control bus |
|
// Generic FIFO implementation - hopefully synthesizable with Synplify |
`define ETH_FIFO_GENERIC |
// Ethernet implemented in Xilinx Chips (uncomment following lines) |
// `define ETH_FIFO_XILINX // Use Xilinx distributed ram for tx and rx fifo |
// `define ETH_XILINX_RAMB4 // Selection of the used memory for Buffer descriptors |
// Core is going to be implemented in Virtex FPGA and contains Virtex |
// specific elements. |
|
// Ethernet implemented in Altera Chips (uncomment following lines) |
//`define ETH_ALTERA_ALTSYNCRAM |
|
// Ethernet implemented in ASIC with Virtual Silicon RAMs |
// `define ETH_VIRTUAL_SILICON_RAM // Virtual Silicon RAMS used storing buffer decriptors (ASIC implementation) |
|
// Ethernet implemented in ASIC with Artisan RAMs |
// `define ETH_ARTISAN_RAM // Artisan RAMS used storing buffer decriptors (ASIC implementation) |
|
// Uncomment when Avalon bus is used |
//`define ETH_AVALON_BUS |
|
`define ETH_MODER_ADR 8'h0 // 0x0 |
`define ETH_INT_SOURCE_ADR 8'h1 // 0x4 |
`define ETH_INT_MASK_ADR 8'h2 // 0x8 |
`define ETH_IPGT_ADR 8'h3 // 0xC |
`define ETH_IPGR1_ADR 8'h4 // 0x10 |
`define ETH_IPGR2_ADR 8'h5 // 0x14 |
`define ETH_PACKETLEN_ADR 8'h6 // 0x18 |
`define ETH_COLLCONF_ADR 8'h7 // 0x1C |
`define ETH_TX_BD_NUM_ADR 8'h8 // 0x20 |
`define ETH_CTRLMODER_ADR 8'h9 // 0x24 |
`define ETH_MIIMODER_ADR 8'hA // 0x28 |
`define ETH_MIICOMMAND_ADR 8'hB // 0x2C |
`define ETH_MIIADDRESS_ADR 8'hC // 0x30 |
`define ETH_MIITX_DATA_ADR 8'hD // 0x34 |
`define ETH_MIIRX_DATA_ADR 8'hE // 0x38 |
`define ETH_MIISTATUS_ADR 8'hF // 0x3C |
`define ETH_MAC_ADDR0_ADR 8'h10 // 0x40 |
`define ETH_MAC_ADDR1_ADR 8'h11 // 0x44 |
`define ETH_HASH0_ADR 8'h12 // 0x48 |
`define ETH_HASH1_ADR 8'h13 // 0x4C |
`define ETH_TX_CTRL_ADR 8'h14 // 0x50 |
`define ETH_RX_CTRL_ADR 8'h15 // 0x54 |
`define ETH_DBG_ADR 8'h16 // 0x58 |
|
|
`define ETH_MODER_DEF_0 8'h00 |
`define ETH_MODER_DEF_1 8'hA0 |
`define ETH_MODER_DEF_2 1'h0 |
`define ETH_INT_MASK_DEF_0 7'h0 |
`define ETH_IPGT_DEF_0 7'h12 |
`define ETH_IPGR1_DEF_0 7'h0C |
`define ETH_IPGR2_DEF_0 7'h12 |
`define ETH_PACKETLEN_DEF_0 8'h00 |
`define ETH_PACKETLEN_DEF_1 8'h06 |
`define ETH_PACKETLEN_DEF_2 8'h40 |
`define ETH_PACKETLEN_DEF_3 8'h00 |
`define ETH_COLLCONF_DEF_0 6'h3f |
`define ETH_COLLCONF_DEF_2 4'hF |
`define ETH_TX_BD_NUM_DEF_0 8'h40 |
`define ETH_CTRLMODER_DEF_0 3'h0 |
`define ETH_MIIMODER_DEF_0 8'h64 |
`define ETH_MIIMODER_DEF_1 1'h0 |
`define ETH_MIIADDRESS_DEF_0 5'h00 |
`define ETH_MIIADDRESS_DEF_1 5'h00 |
`define ETH_MIITX_DATA_DEF_0 8'h00 |
`define ETH_MIITX_DATA_DEF_1 8'h00 |
`define ETH_MIIRX_DATA_DEF 16'h0000 // not written from WB |
`define ETH_MAC_ADDR0_DEF_0 8'h00 |
`define ETH_MAC_ADDR0_DEF_1 8'h00 |
`define ETH_MAC_ADDR0_DEF_2 8'h00 |
`define ETH_MAC_ADDR0_DEF_3 8'h00 |
`define ETH_MAC_ADDR1_DEF_0 8'h00 |
`define ETH_MAC_ADDR1_DEF_1 8'h00 |
`define ETH_HASH0_DEF_0 8'h00 |
`define ETH_HASH0_DEF_1 8'h00 |
`define ETH_HASH0_DEF_2 8'h00 |
`define ETH_HASH0_DEF_3 8'h00 |
`define ETH_HASH1_DEF_0 8'h00 |
`define ETH_HASH1_DEF_1 8'h00 |
`define ETH_HASH1_DEF_2 8'h00 |
`define ETH_HASH1_DEF_3 8'h00 |
`define ETH_TX_CTRL_DEF_0 8'h00 // |
`define ETH_TX_CTRL_DEF_1 8'h00 // |
`define ETH_TX_CTRL_DEF_2 1'h0 // |
`define ETH_RX_CTRL_DEF_0 8'h00 |
`define ETH_RX_CTRL_DEF_1 8'h00 |
|
|
`define ETH_MODER_WIDTH_0 8 |
`define ETH_MODER_WIDTH_1 8 |
`define ETH_MODER_WIDTH_2 1 |
`define ETH_INT_SOURCE_WIDTH_0 7 |
`define ETH_INT_MASK_WIDTH_0 7 |
`define ETH_IPGT_WIDTH_0 7 |
`define ETH_IPGR1_WIDTH_0 7 |
`define ETH_IPGR2_WIDTH_0 7 |
`define ETH_PACKETLEN_WIDTH_0 8 |
`define ETH_PACKETLEN_WIDTH_1 8 |
`define ETH_PACKETLEN_WIDTH_2 8 |
`define ETH_PACKETLEN_WIDTH_3 8 |
`define ETH_COLLCONF_WIDTH_0 6 |
`define ETH_COLLCONF_WIDTH_2 4 |
`define ETH_TX_BD_NUM_WIDTH_0 8 |
`define ETH_CTRLMODER_WIDTH_0 3 |
`define ETH_MIIMODER_WIDTH_0 8 |
`define ETH_MIIMODER_WIDTH_1 1 |
`define ETH_MIICOMMAND_WIDTH_0 3 |
`define ETH_MIIADDRESS_WIDTH_0 5 |
`define ETH_MIIADDRESS_WIDTH_1 5 |
`define ETH_MIITX_DATA_WIDTH_0 8 |
`define ETH_MIITX_DATA_WIDTH_1 8 |
`define ETH_MIIRX_DATA_WIDTH 16 // not written from WB |
`define ETH_MIISTATUS_WIDTH 3 // not written from WB |
`define ETH_MAC_ADDR0_WIDTH_0 8 |
`define ETH_MAC_ADDR0_WIDTH_1 8 |
`define ETH_MAC_ADDR0_WIDTH_2 8 |
`define ETH_MAC_ADDR0_WIDTH_3 8 |
`define ETH_MAC_ADDR1_WIDTH_0 8 |
`define ETH_MAC_ADDR1_WIDTH_1 8 |
`define ETH_HASH0_WIDTH_0 8 |
`define ETH_HASH0_WIDTH_1 8 |
`define ETH_HASH0_WIDTH_2 8 |
`define ETH_HASH0_WIDTH_3 8 |
`define ETH_HASH1_WIDTH_0 8 |
`define ETH_HASH1_WIDTH_1 8 |
`define ETH_HASH1_WIDTH_2 8 |
`define ETH_HASH1_WIDTH_3 8 |
`define ETH_TX_CTRL_WIDTH_0 8 |
`define ETH_TX_CTRL_WIDTH_1 8 |
`define ETH_TX_CTRL_WIDTH_2 1 |
`define ETH_RX_CTRL_WIDTH_0 8 |
`define ETH_RX_CTRL_WIDTH_1 8 |
|
|
// Outputs are registered (uncomment when needed) |
`define ETH_REGISTERED_OUTPUTS |
|
// Settings for TX FIFO |
`define ETH_TX_FIFO_DATA_WIDTH 32 |
|
// Defines for ethernet TX fifo size - impacts FPGA resource usage |
//`define ETH_TX_FULL_PACKET_FIFO // Full 1500 byte TX buffer - uncomment this |
//`define ETH_TX_256BYTE_FIFO // 256 byte TX buffer - uncomment this |
//`define ETH_TX_512BYTE_FIFO // 512 byte TX buffer - uncomment this |
`define ETH_TX_1KBYTE_FIFO // 1024 byte TX buffer - uncomment this |
|
`ifdef ETH_TX_FULL_PACKET_FIFO |
`define ETH_TX_FIFO_CNT_WIDTH 11 |
`define ETH_TX_FIFO_DEPTH 375 |
`else |
`ifdef ETH_TX_1KBYTE_FIFO |
`define ETH_TX_FIFO_CNT_WIDTH 9 |
`define ETH_TX_FIFO_DEPTH 256 |
`else |
`ifdef ETH_TX_512BYTE_FIFO |
`define ETH_TX_FIFO_CNT_WIDTH 8 |
`define ETH_TX_FIFO_DEPTH 128 |
`else |
`ifdef ETH_TX_256BYTE_FIFO |
`define ETH_TX_FIFO_CNT_WIDTH 7 |
`define ETH_TX_FIFO_DEPTH 64 |
`else |
// Default is 64 bytes |
`define ETH_TX_FIFO_CNT_WIDTH 5 |
`define ETH_TX_FIFO_DEPTH 16 |
`endif |
`endif |
`endif // !`ifdef ETH_TX_512BYTE_FIFO |
`endif // !`ifdef ETH_TX_FULL_PACKET_FIFO |
|
|
|
// Settings for RX FIFO |
`define ETH_RX_FIFO_CNT_WIDTH 9 |
`define ETH_RX_FIFO_DEPTH 256 |
//`define ETH_RX_FIFO_CNT_WIDTH 8 |
//`define ETH_RX_FIFO_DEPTH 128 |
//`define ETH_RX_FIFO_CNT_WIDTH 7 |
//`define ETH_RX_FIFO_DEPTH 64 |
//`define ETH_RX_FIFO_CNT_WIDTH 6 |
//`define ETH_RX_FIFO_DEPTH 32 |
//`define ETH_RX_FIFO_CNT_WIDTH 5 |
//`define ETH_RX_FIFO_DEPTH 16 |
|
`define ETH_RX_FIFO_DATA_WIDTH 32 |
|
// Burst length |
`define BURST_4BEAT |
`ifdef BURST_4BEAT |
`define ETH_BURST_LENGTH 4 // Change also ETH_BURST_CNT_WIDTH |
`define ETH_BURST_CNT_WIDTH 3 // The counter must be width enough to count to ETH_BURST_LENGTH |
`endif |
|
//`define ETH_BURST_LENGTH 32 // Change also ETH_BURST_CNT_WIDTH |
//`define ETH_BURST_CNT_WIDTH 7 // The counter must be width enough to count to ETH_BURST_LENGTH |
|
// Undefine this to enable bursting for RX (writing to memory) |
`define ETH_RX_BURST_EN |
|
|
// WISHBONE interface is Revision B3 compliant (uncomment when needed) |
`define ETH_WISHBONE_B3 |
|
// Hack where the transmit logic polls each of the TX buffers instead of having to keep track of what's going on |
//`define TXBD_POLL |
|
// Define this to allow reading of the Wishbone control state machine on reg |
// address 0x58 |
`define WISHBONE_DEBUG |
/boards/actel/ordb1a3pe1500/rtl/verilog/orpsoc_top/orpsoc_top.v
1481,7 → 1481,7
assign eth0_rst_n_o = !wb_rst; |
`endif |
|
eth eth0 |
ethmac ethmac0 |
( |
// Wishbone Slave interface |
.wb_clk_i (wb_clk), |