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URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

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    /openrisc/trunk/orpsocv2
    from Rev 410 to Rev 411
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Rev 410 → Rev 411

/rtl/verilog/or1200/or1200_tt.v
41,49 → 41,6
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_tt.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// No update
//
// Revision 1.5 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.4 2002/03/29 15:16:56 lampret
// Some of the warnings fixed.
//
// Revision 1.3 2002/02/12 01:33:47 lampret
// No longer using async rst as sync reset for the counter.
//
// Revision 1.2 2002/01/28 01:16:00 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10 2001/11/13 10:00:49 lampret
// Fixed tick timer interrupt reporting by using TTCR[IP] bit.
//
// Revision 1.9 2001/11/10 03:43:57 lampret
// Fixed exceptions.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:10 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:23 lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
/sim/bin/definesgen.inc
36,3 → 36,7
$(Q)if [ ! -z $$SIM_QUIET ]; \
then echo "\`define SIM_QUIET" >> $@; \
fi
$(Q)for module in $(GATELEVEL_MODULES); do echo "\`define "$$module"_IS_GATELEVEL " >> $@; done
 
 
 
/sw/tests/ethmac/board/ethmac-ping.c
38,7 → 38,6
//////////////////////////////////////////////////////////////////////
 
#include "cpu-utils.h"
//#include "spr-defs.h"
#include "board.h"
#include "int.h"
#include "uart.h"
55,6 → 54,10
//#define OUR_IP_BYTES 0xc0,0xa8,0x0,0x14 // 192.168.0.20
//#define OUR_IP_LONG 0xc0a80014
 
 
//#define OUR_IP_BYTES 0xc0,0xa8,0x1,0x22 // 192.168.1.34
//#define OUR_IP_LONG 0xc0a80122
 
#define OUR_IP_BYTES 0xc0,0xa8,0x1,0x2 // 192.168.1.2
#define OUR_IP_LONG 0xc0a80102
 
72,14 → 75,12
void oeth_interrupt(void);
static void oeth_rx(void);
static void oeth_tx(void);
/* Function to calculate checksum of ping responses we send */
unsigned short calculate_checksum(char* dats, unsigned int len) ;
 
#define NEVER_PRINT_PACKET 1
// Global used to control whether we print out packets as we receive them
int print_packet_contents;
 
#define DISABLE_PRINTF 0
 
#if DISABLE_PRINTF==1
#undef printf
#endif
/* Let the ethernet packets use a space beginning here for buffering */
#define ETH_BUFF_BASE 0x01000000
 
95,8 → 96,8
 
/* Buffer number (must be 2^n)
*/
#define OETH_RXBD_NUM 8
#define OETH_TXBD_NUM 8
#define OETH_RXBD_NUM 32
#define OETH_TXBD_NUM 32
#define OETH_RXBD_NUM_MASK (OETH_RXBD_NUM-1)
#define OETH_TXBD_NUM_MASK (OETH_TXBD_NUM-1)
 
105,20 → 106,6
#define OETH_RX_BUFF_SIZE 2048
#define OETH_TX_BUFF_SIZE 2048
 
/* OR32 Page size def */
#define PAGE_SHIFT 13
#define PAGE_SIZE (1UL << PAGE_SHIFT)
 
/* How many buffers per page
*/
#define OETH_RX_BUFF_PPGAE (PAGE_SIZE/OETH_RX_BUFF_SIZE)
#define OETH_TX_BUFF_PPGAE (PAGE_SIZE/OETH_TX_BUFF_SIZE)
 
/* How many pages is needed for buffers
*/
#define OETH_RX_BUFF_PAGE_NUM (OETH_RXBD_NUM/OETH_RX_BUFF_PPGAE)
#define OETH_TX_BUFF_PAGE_NUM (OETH_TXBD_NUM/OETH_TX_BUFF_PPGAE)
 
/* Buffer size (if not XXBUF_PREALLOC
*/
#define MAX_FRAME_SIZE 0x600
851,7 → 838,8
regs->miicommand = 0;
regs->mac_addr1 = ETH_MACADDR0 << 8 | ETH_MACADDR1;
regs->mac_addr0 = ETH_MACADDR2 << 24 | ETH_MACADDR3 << 16 | ETH_MACADDR4 << 8 | ETH_MACADDR5;
regs->mac_addr0 = ETH_MACADDR2 << 24 | ETH_MACADDR3 << 16 |
ETH_MACADDR4 << 8 | ETH_MACADDR5;
/* Clear all pending interrupts
*/
859,7 → 847,8
/* Promisc, IFG, CRCEn
*/
regs->moder |= OETH_MODER_PRO | OETH_MODER_PAD | OETH_MODER_IFG | OETH_MODER_CRCEN | OETH_MODER_FULLD;
regs->moder |= OETH_MODER_PRO | OETH_MODER_PAD | OETH_MODER_IFG |
OETH_MODER_CRCEN | OETH_MODER_FULLD;
/* Enable interrupt sources.
*/
890,26 → 879,22
/* Preallocated ethernet buffer setup */
unsigned long mem_addr = ETH_BUFF_BASE; /* Defined at top */
 
/* Setup for TX buffers*/
for(i = 0, k = 0; i < OETH_TX_BUFF_PAGE_NUM; i++) {
for(j = 0; j < OETH_TX_BUFF_PPGAE; j++, k++) {
//tx_bd[k].len_status = OETH_TX_BD_PAD | OETH_TX_BD_CRC | OETH_RX_BD_IRQ;
tx_bd[k].len_status = OETH_TX_BD_PAD | OETH_TX_BD_CRC;
tx_bd[k].addr = mem_addr;
mem_addr += OETH_TX_BUFF_SIZE;
}
// Setup TX Buffers
for(i = 0; i < OETH_TXBD_NUM; i++) {
//tx_bd[i].len_status = OETH_TX_BD_PAD | OETH_TX_BD_CRC | OETH_RX_BD_IRQ;
tx_bd[i].len_status = OETH_TX_BD_PAD | OETH_TX_BD_CRC;
tx_bd[i].addr = mem_addr;
mem_addr += OETH_TX_BUFF_SIZE;
}
tx_bd[OETH_TXBD_NUM - 1].len_status |= OETH_TX_BD_WRAP;
 
/* Setup for RX buffers */
for(i = 0, k = 0; i < OETH_RX_BUFF_PAGE_NUM; i++) {
for(j = 0; j < OETH_RX_BUFF_PPGAE; j++, k++) {
rx_bd[k].len_status = OETH_RX_BD_EMPTY | OETH_RX_BD_IRQ; /* Enable interrupt */
rx_bd[k].addr = mem_addr;
mem_addr += OETH_RX_BUFF_SIZE;
}
// Setup RX buffers
for(i = 0; i < OETH_RXBD_NUM; i++) {
rx_bd[i].len_status = OETH_RX_BD_EMPTY | OETH_RX_BD_IRQ; // Init. with IRQ
rx_bd[i].addr = mem_addr;
mem_addr += OETH_RX_BUFF_SIZE;
}
rx_bd[OETH_RXBD_NUM - 1].len_status |= OETH_RX_BD_WRAP; /* Final buffer has wrap bit set */
rx_bd[OETH_RXBD_NUM - 1].len_status |= OETH_RX_BD_WRAP; // Last buffer wraps
 
/* Enable receiver and transmiter
*/
970,9 → 955,9
if(!(tx_bd[i].len_status & OETH_TX_BD_READY)) /* Looking for buffer NOT ready for transmit. ie we can manipulate it */
{
#if NEVER_PRINT_PACKET==0
printf("Oeth: Using TX_bd at 0x%lx\n",(unsigned long)&tx_bd[i]);
#endif
if (print_packet_contents)
printf("Oeth: Using TX_bd at 0x%lx\n",(unsigned long)&tx_bd[i]);
 
if (next_tx_buf_num == OETH_TXBD_NUM-1) next_tx_buf_num = 0;
else next_tx_buf_num++;
995,9 → 980,6
static void
oeth_print_packet(unsigned long add, int len)
{
#if NEVER_PRINT_PACKET==1
return;
#endif
 
int truncate = (len > 256);
int length_to_print = truncate ? 256 : len;
1039,9 → 1021,8
return;
}
*/
#if NEVER_PRINT_PACKET==0
printf("Oeth: Using TX_bd buffer address: 0x%lx\n",(unsigned long) tx_bd->addr);
#endif
if (print_packet_contents)
printf("Oeth: Using TX_bd buffer address: 0x%lx\n",(unsigned long) tx_bd->addr);
 
/* Clear all of the status flags.
*/
1777,9 → 1758,8
rx_bdp = ((oeth_bd *)OETH_BD_BASE) + OETH_TXBD_NUM;
#if NEVER_PRINT_PACKET==0
printf("rx");
#endif
if (print_packet_contents)
printf("rx");
/* Find RX buffers marked as having received data */
for(i = 0; i < OETH_RXBD_NUM; i++)
1823,10 → 1803,11
packet_check_arp_header((void *)rx_bdp[i].addr );
// See if it's an ICMP echo request
packet_check_icmp_header((void *)rx_bdp[i].addr );
#if NEVER_PRINT_PACKET==0
oeth_print_packet(rx_bdp[i].addr, rx_bdp[i].len_status >> 16);
printf("\t end of packet\n\n");
#endif
if (print_packet_contents)
{
oeth_print_packet(rx_bdp[i].addr, rx_bdp[i].len_status >> 16);
printf("\t end of packet\n\n");
}
/* finish up */
rx_bdp[i].len_status &= ~OETH_RX_BD_STATS; /* Clear stats */
rx_bdp[i].len_status |= OETH_RX_BD_EMPTY; /* Mark RX BD as empty */
1844,9 → 1825,9
{
volatile oeth_bd *tx_bd;
int i;
#if NEVER_PRINT_PACKET==0
printf("tx");
#endif
if (print_packet_contents)
printf("tx");
 
tx_bd = (volatile oeth_bd *)OETH_BD_BASE; /* Search from beginning*/
/* Go through the TX buffs, search for one that was just sent */
1861,10 → 1842,8
 
/* Probably good to check for TX errors here */
#if NEVER_PRINT_PACKET==0
printf("T%d",i);
#endif
if (print_packet_contents)
printf("T%d",i);
}
}
return;
1873,7 → 1852,9
 
int main ()
{
 
print_packet_contents = 0; // Default to not printing packet contents.
/* Initialise vector handler */
int_init();
 
1886,24 → 1867,17
last_char=0; /* Variable init for spin_cursor() */
next_tx_buf_num = 4; /* init for tx buffer counter */
 
#ifndef RTLSIM
uart_init(DEFAULT_UART); // init the UART before we can printf
printf("\n\teth ping program\n\n");
printf("\n\tboard IP: %d.%d.%d.%d\n",our_ip[0]&0xff,our_ip[1]&0xff,
our_ip[2]&0xff,our_ip[3]&0xff);
#endif
ethmac_setup(); /* Configure MAC, TX/RX BDs and enable RX and TX in MODER */
//scan_ethphys(); /* Scan MIIM bus for PHYs */
//jb ethphy_init(); /* Attempt reset and configuration of PHY via MIIM */
//ethphy_init(); /* Attempt reset and configuration of PHY via MIIM */
//ethmac_scanstatus(); /* Enable scanning of status register via MIIM */
 
/* clear tx_done, the tx interrupt handler will set it when it's been transmitted */
tx_done = 0;
 
#ifndef RTLSIM
/* Loop, monitoring user input from TTY */
while(1)
{
1912,7 → 1886,7
while(!uart_check_for_char(DEFAULT_UART))
{
spin_cursor();
oeth_monitor_rx();
//oeth_monitor_rx();
}
c = uart_getc(DEFAULT_UART);
1925,6 → 1899,8
scan_ethphys();
if (c == 'i')
ethphy_init();
if (c == 'P')
print_packet_contents = print_packet_contents ? 0 : 1;
if (c == 'p')
oeth_printregs();
if (c == '0')
1957,8 → 1933,4
 
}
 
 
 
#endif
 
}
/sw/tests/ethmac/sim/ethmac-rxtxcallresponse.c
0,0 → 1,681
//////////////////////////////////////////////////////////////////////
//// ////
//// Interrupt-driven Ethernet MAC transmit test code ////
//// ////
//// Description ////
//// Send packets while receiving packets ////
//// ////
//// Test data comes from pre-calculated array of random values, ////
//// MAC TX buffer pointers are set to addresses in this array, ////
//// saving copying the data around before transfers. ////
//// ////
//// Author(s): ////
//// - jb, jb@orsoc.se, with parts taken from Linux kernel ////
//// open_eth driver. ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
#include "cpu-utils.h"
#include "board.h"
#include "int.h"
#include "ethmac.h"
#include "eth-phy-mii.h"
 
volatile unsigned tx_done;
volatile unsigned rx_done;
static int next_tx_buf_num;
 
/* Functions in this file */
void ethmac_setup(void);
/* Interrupt functions */
void oeth_interrupt(void);
static void oeth_rx(void);
static void oeth_tx(void);
 
/* Let the ethernet packets use a space beginning here for buffering */
#define ETH_BUFF_BASE 0x01000000
 
 
#define RXBUFF_PREALLOC 1
#define TXBUFF_PREALLOC 1
//#undef RXBUFF_PREALLOC
//#undef TXBUFF_PREALLOC
 
/* The transmitter timeout
*/
#define TX_TIMEOUT (2*HZ)
 
/* Buffer number (must be 2^n)
*/
#define OETH_RXBD_NUM 16
#define OETH_TXBD_NUM 16
#define OETH_RXBD_NUM_MASK (OETH_RXBD_NUM-1)
#define OETH_TXBD_NUM_MASK (OETH_TXBD_NUM-1)
 
/* Buffer size
*/
#define OETH_RX_BUFF_SIZE 0x600-4
#define OETH_TX_BUFF_SIZE 0x600-4
 
/* Buffer size (if not XXBUF_PREALLOC
*/
#define MAX_FRAME_SIZE 1518
 
/* The buffer descriptors track the ring buffers.
*/
struct oeth_private {
//struct sk_buff* rx_skbuff[OETH_RXBD_NUM];
//struct sk_buff* tx_skbuff[OETH_TXBD_NUM];
 
unsigned short tx_next; /* Next buffer to be sent */
unsigned short tx_last; /* Next buffer to be checked if packet sent */
unsigned short tx_full; /* Buffer ring fuul indicator */
unsigned short rx_cur; /* Next buffer to be checked if packet
received */
oeth_regs *regs; /* Address of controller registers. */
oeth_bd *rx_bd_base; /* Address of Rx BDs. */
oeth_bd *tx_bd_base; /* Address of Tx BDs. */
// struct net_device_stats stats;
};
 
#define PHYNUM 7
 
// Data array of data to transmit, tx_data_array[]
//#include "eth-rxtx-data.h" // Not used
int tx_data_pointer;
 
void
eth_mii_write(char phynum, short regnum, short data)
{
static volatile oeth_regs *regs = (oeth_regs *)(OETH_REG_BASE);
regs->miiaddress = (regnum << 8) | phynum;
regs->miitx_data = data;
regs->miicommand = OETH_MIICOMMAND_WCTRLDATA;
regs->miicommand = 0;
while(regs->miistatus & OETH_MIISTATUS_BUSY);
}
 
short
eth_mii_read(char phynum, short regnum)
{
static volatile oeth_regs *regs = (oeth_regs *)(OETH_REG_BASE);
regs->miiaddress = (regnum << 8) | phynum;
regs->miicommand = OETH_MIICOMMAND_RSTAT;
regs->miicommand = 0;
while(regs->miistatus & OETH_MIISTATUS_BUSY);
return regs->miirx_data;
}
 
 
// Wait here until all packets have been transmitted
void
wait_until_all_tx_clear(void)
{
int i;
volatile oeth_bd *tx_bd;
tx_bd = (volatile oeth_bd *)OETH_BD_BASE; /* Search from beginning*/
 
int some_tx_waiting = 1;
while (some_tx_waiting)
{
some_tx_waiting = 0;
/* Go through the TX buffs, search for unused one */
for(i = 0; i < OETH_TXBD_NUM; i++) {
// Looking for buffer ready for transmit
if((tx_bd[i].len_status & OETH_TX_BD_READY))
some_tx_waiting = 1;
}
}
}
 
 
void
ethphy_set_10mbit(int phynum)
{
wait_until_all_tx_clear();
// Hardset PHY to just use 10Mbit mode
short cr = eth_mii_read(phynum, MII_BMCR);
cr &= ~BMCR_ANENABLE; // Clear auto negotiate bit
cr &= ~BMCR_SPEED100; // Clear fast eth. bit
eth_mii_write(phynum, MII_BMCR, cr);
}
 
 
void
ethphy_set_100mbit(int phynum)
{
wait_until_all_tx_clear();
// Hardset PHY to just use 100Mbit mode
short cr = eth_mii_read(phynum, MII_BMCR);
cr |= BMCR_ANENABLE; // Clear auto negotiate bit
cr |= BMCR_SPEED100; // Clear fast eth. bit
eth_mii_write(phynum, MII_BMCR, cr);
}
 
 
void
ethmac_setup(void)
{
// from arch/or32/drivers/open_eth.c
volatile oeth_regs *regs;
regs = (oeth_regs *)(OETH_REG_BASE);
/* Reset MII mode module */
regs->miimoder = OETH_MIIMODER_RST; /* MII Reset ON */
regs->miimoder &= ~OETH_MIIMODER_RST; /* MII Reset OFF */
regs->miimoder = 0x64; /* Clock divider for MII Management interface */
/* Reset the controller.
*/
regs->moder = OETH_MODER_RST; /* Reset ON */
regs->moder &= ~OETH_MODER_RST; /* Reset OFF */
/* Setting TXBD base to OETH_TXBD_NUM.
*/
regs->tx_bd_num = OETH_TXBD_NUM;
/* Set min/max packet length
*/
regs->packet_len = 0x00400600;
/* Set IPGT register to recomended value
*/
regs->ipgt = 0x12;
/* Set IPGR1 register to recomended value
*/
regs->ipgr1 = 0x0000000c;
/* Set IPGR2 register to recomended value
*/
regs->ipgr2 = 0x00000012;
/* Set COLLCONF register to recomended value
*/
regs->collconf = 0x000f003f;
/* Set control module mode
*/
#if 0
regs->ctrlmoder = OETH_CTRLMODER_TXFLOW | OETH_CTRLMODER_RXFLOW;
#else
regs->ctrlmoder = 0;
#endif
/* Clear MIIM registers */
regs->miitx_data = 0;
regs->miiaddress = 0;
regs->miicommand = 0;
regs->mac_addr1 = ETH_MACADDR0 << 8 | ETH_MACADDR1;
regs->mac_addr0 = ETH_MACADDR2 << 24 | ETH_MACADDR3 << 16 | ETH_MACADDR4 << 8 | ETH_MACADDR5;
/* Clear all pending interrupts
*/
regs->int_src = 0xffffffff;
/* Promisc, IFG, CRCEn
*/
regs->moder |= OETH_MODER_PRO | OETH_MODER_PAD | OETH_MODER_IFG | OETH_MODER_CRCEN | OETH_MODER_FULLD;
/* Enable interrupt sources.
*/
 
regs->int_mask = OETH_INT_MASK_TXB |
OETH_INT_MASK_TXE |
OETH_INT_MASK_RXF |
OETH_INT_MASK_RXE |
OETH_INT_MASK_BUSY |
OETH_INT_MASK_TXC |
OETH_INT_MASK_RXC;
 
// Buffer setup stuff
volatile oeth_bd *tx_bd, *rx_bd;
int i,j,k;
/* Initialize TXBD pointer
*/
tx_bd = (volatile oeth_bd *)OETH_BD_BASE;
/* Initialize RXBD pointer
*/
rx_bd = ((volatile oeth_bd *)OETH_BD_BASE) + OETH_TXBD_NUM;
/* Preallocated ethernet buffer setup */
unsigned long mem_addr = ETH_BUFF_BASE; /* Defined at top */
 
// Setup TX Buffers
for(i = 0; i < OETH_TXBD_NUM; i++) {
//tx_bd[i].len_status = OETH_TX_BD_PAD | OETH_TX_BD_CRC | OETH_RX_BD_IRQ;
tx_bd[i].len_status = OETH_TX_BD_PAD | OETH_TX_BD_CRC;
tx_bd[i].addr = mem_addr;
mem_addr += OETH_TX_BUFF_SIZE;
}
tx_bd[OETH_TXBD_NUM - 1].len_status |= OETH_TX_BD_WRAP;
 
// Setup RX buffers
for(i = 0; i < OETH_RXBD_NUM; i++) {
rx_bd[i].len_status = OETH_RX_BD_EMPTY | OETH_RX_BD_IRQ; // Init. with IRQ
rx_bd[i].addr = mem_addr;
mem_addr += OETH_RX_BUFF_SIZE;
}
rx_bd[OETH_RXBD_NUM - 1].len_status |= OETH_RX_BD_WRAP; // Last buffer wraps
 
/* Enable RX and TX in MAC
*/
regs->moder &= ~(OETH_MODER_RXEN | OETH_MODER_TXEN);
regs->moder |= OETH_MODER_RXEN | OETH_MODER_TXEN;
 
next_tx_buf_num = 0; // init tx buffer pointer
 
return;
}
 
// Enable RX in ethernet MAC
void
oeth_enable_rx(void)
{
volatile oeth_regs *regs;
regs = (oeth_regs *)(OETH_REG_BASE);
regs->moder |= OETH_MODER_RXEN;
}
 
// Disable RX in ethernet MAC
void
oeth_disable_rx(void)
{
volatile oeth_regs *regs;
regs = (oeth_regs *)(OETH_REG_BASE);
regs->moder &= ~(OETH_MODER_RXEN);
}
 
 
/* Setup buffer descriptors with data */
/* length is in BYTES */
void tx_packet(void* data, int length)
{
volatile oeth_regs *regs;
regs = (oeth_regs *)(OETH_REG_BASE);
volatile oeth_bd *tx_bd;
volatile int i;
 
tx_bd = (volatile oeth_bd *)OETH_BD_BASE;
tx_bd = (struct oeth_bd*) &tx_bd[next_tx_buf_num];
// If it's in use - wait
while ((tx_bd->len_status & OETH_TX_BD_IRQ));
 
/* Clear all of the status flags.
*/
tx_bd->len_status &= ~OETH_TX_BD_STATS;
/* If the frame is short, tell CPM to pad it.
*/
#define ETH_ZLEN 60 /* Min. octets in frame sans FCS */
if (length <= ETH_ZLEN)
tx_bd->len_status |= OETH_TX_BD_PAD;
else
tx_bd->len_status &= ~OETH_TX_BD_PAD;
#ifdef _ETH_RXTX_DATA_H_
// Set the address pointer to the place
// in memory where the data is and transmit from there
tx_bd->addr = (char*) &tx_data_array[tx_data_pointer&~(0x3)];
 
tx_data_pointer += length + 1;
if (tx_data_pointer > (255*1024))
tx_data_pointer = 0;
 
#else
if (data){
//Copy the data into the transmit buffer, byte at a time
char* data_p = (char*) data;
char* data_b = (char*) tx_bd->addr;
for(i=0;i<length;i++)
{
data_b[i] = data_p[i];
}
}
#endif
 
/* Set the length of the packet's data in the buffer descriptor */
tx_bd->len_status = (tx_bd->len_status & 0x0000ffff) |
((length&0xffff) << 16);
 
/* Send it on its way. Tell controller its ready, interrupt when sent
* and to put the CRC on the end.
*/
tx_bd->len_status |= (OETH_TX_BD_READY | OETH_TX_BD_CRC | OETH_TX_BD_IRQ);
next_tx_buf_num = (next_tx_buf_num + 1) & OETH_TXBD_NUM_MASK;
 
return;
 
 
}
 
/* The interrupt handler.
*/
void
oeth_interrupt(void)
{
 
volatile oeth_regs *regs;
regs = (oeth_regs *)(OETH_REG_BASE);
 
uint int_events;
int serviced;
serviced = 0;
/* Get the interrupt events that caused us to be here.
*/
int_events = regs->int_src;
regs->int_src = int_events;
 
/* Handle receive event in its own function.
*/
if (int_events & (OETH_INT_RXF | OETH_INT_RXE)) {
serviced |= 0x1;
oeth_rx();
}
 
/* Handle transmit event in its own function.
*/
if (int_events & (OETH_INT_TXB | OETH_INT_TXE)) {
serviced |= 0x2;
oeth_tx();
serviced |= 0x2;
}
 
/* Check for receive busy, i.e. packets coming but no place to
* put them.
*/
if (int_events & OETH_INT_BUSY) {
serviced |= 0x4;
if (!(int_events & (OETH_INT_RXF | OETH_INT_RXE)))
oeth_rx();
}
 
return;
}
 
 
 
static void
oeth_rx(void)
{
volatile oeth_regs *regs;
regs = (oeth_regs *)(OETH_REG_BASE);
 
volatile oeth_bd *rx_bdp;
int pkt_len, i;
int bad = 0;
rx_bdp = ((oeth_bd *)OETH_BD_BASE) + OETH_TXBD_NUM;
 
/* Find RX buffers marked as having received data */
for(i = 0; i < OETH_RXBD_NUM; i++)
{
bad=0;
if(!(rx_bdp[i].len_status & OETH_RX_BD_EMPTY)){ /* Looking for NOT empty buffers desc. */
/* Check status for errors.
*/
if (rx_bdp[i].len_status & (OETH_RX_BD_TOOLONG | OETH_RX_BD_SHORT)) {
bad = 1;
report(0xbaad0001);
}
if (rx_bdp[i].len_status & OETH_RX_BD_DRIBBLE) {
bad = 1;
report(0xbaad0002);
}
if (rx_bdp[i].len_status & OETH_RX_BD_CRCERR) {
bad = 1;
report(0xbaad0003);
}
if (rx_bdp[i].len_status & OETH_RX_BD_OVERRUN) {
bad = 1;
report(0xbaad0004);
}
if (rx_bdp[i].len_status & OETH_RX_BD_MISS) {
report(0xbaad0005);
}
if (rx_bdp[i].len_status & OETH_RX_BD_LATECOL) {
bad = 1;
report(0xbaad0006);
}
if (bad) {
rx_bdp[i].len_status &= ~OETH_RX_BD_STATS;
rx_bdp[i].len_status |= OETH_RX_BD_EMPTY;
exit(0xbaaaaaad);
continue;
}
else {
/* Process the incoming frame.
*/
pkt_len = rx_bdp[i].len_status >> 16;
/* finish up */
rx_bdp[i].len_status &= ~OETH_RX_BD_STATS; /* Clear stats */
rx_bdp[i].len_status |= OETH_RX_BD_EMPTY; /* Mark RX BD as empty */
rx_done++;
}
}
}
}
 
 
 
static void
oeth_tx(void)
{
volatile oeth_bd *tx_bd;
int i;
tx_bd = (volatile oeth_bd *)OETH_BD_BASE; /* Search from beginning*/
/* Go through the TX buffs, search for one that was just sent */
for(i = 0; i < OETH_TXBD_NUM; i++)
{
/* Looking for buffer NOT ready for transmit. and IRQ enabled */
if( (!(tx_bd[i].len_status & (OETH_TX_BD_READY))) && (tx_bd[i].len_status & (OETH_TX_BD_IRQ)) )
{
/* Single threaded so no chance we have detected a buffer that has had its IRQ bit set but not its BD_READ flag. Maybe this won't work in linux */
tx_bd[i].len_status &= ~OETH_TX_BD_IRQ;
 
/* Probably good to check for TX errors here */
/* set our test variable */
tx_done++;
 
}
}
return;
}
 
// A function and defines to fill and transmit a packet
#define MAX_TX_BUFFER 1532
static char tx_buffer[MAX_TX_BUFFER];
 
void
fill_and_tx_call_packet(int size, int response_time)
{
int i;
 
volatile oeth_regs *regs;
regs = (oeth_regs *)(OETH_REG_BASE);
volatile oeth_bd *tx_bd;
tx_bd = (volatile oeth_bd *)OETH_BD_BASE;
tx_bd = (volatile oeth_bd*) &tx_bd[next_tx_buf_num];
 
// If it's in use - wait
while ((tx_bd->len_status & OETH_TX_BD_IRQ));
 
// Use rand() function to generate data for transmission
// Assumption: ethernet buffer descriptors are 4byte aligned
char* data_b = (char*) tx_bd->addr;
// We will fill with words until there' less than a word to go
int words_to_fill = size / sizeof(unsigned int);
 
unsigned int* data_w = (unsigned int*) data_b;
 
// Put first word as size of packet, second as response time
data_w[0] = size;
data_w[1] = response_time;
 
for(i=2;i<words_to_fill;i++)
data_w[i] = rand();
 
// Point data_b to offset wher word fills ended
data_b += (words_to_fill * sizeof(unsigned int));
 
int leftover_size = size - (words_to_fill * sizeof(unsigned int));
 
for(i=0;i<leftover_size;i++)
{
data_b[i] = rand() & 0xff;
}
 
tx_packet((void*)0, size);
}
 
// Send a packet, the very first byte of which will be read by the testbench
// and used to indicate which test we'll use.
void
send_ethmac_rxtx_test_init_packet(char test)
{
char cmd_tx_buffer[40];
cmd_tx_buffer[0] = test;
tx_packet(cmd_tx_buffer, 40); // Smallest packet that can be sent (I think)
}
 
// Loop to check if a number is prime by doing mod divide of the number
// to test by every number less than it
int
is_prime_number(unsigned long n)
{
unsigned long c;
if (n < 2) return 0;
for(c=2;c<n;c++)
if ((n % c) == 0)
return 0;
return 1;
}
 
 
int
main ()
{
tx_data_pointer = 0;
 
/* Initialise handler vector */
int_init();
 
/* Install ethernet interrupt handler, it is enabled here too */
int_add(ETH0_IRQ, oeth_interrupt, 0);
 
/* Enable interrupts in supervisor register */
cpu_enable_user_interrupts();
 
/* Enable CPU timer */
cpu_enable_timer();
 
ethmac_setup(); /* Configure MAC, TX/RX BDs and enable RX and TX in MODER */
 
/* clear tx_done, the tx interrupt handler will set it when it's been
transmitted */
tx_done = 0;
rx_done = 0;
 
ethphy_set_100mbit(0);
send_ethmac_rxtx_test_init_packet(0x0); // 0x0 - call response test
#define ETH_TX_MIN_PACKET_SIZE 512
#define ETH_TX_NUM_PACKETS (ETH_TX_MIN_PACKET_SIZE + 20)
 
//int response_time = 150000; // Response time before response packet it sent
// back (should be in nanoseconds).
int response_time = 0;
unsigned long num_to_check;
for(num_to_check=ETH_TX_MIN_PACKET_SIZE;
num_to_check<ETH_TX_NUM_PACKETS;
num_to_check++)
fill_and_tx_call_packet(num_to_check, response_time);
 
// Wait a moment for the RX packet check to complete before switching off RX
for(num_to_check=0;num_to_check=1000;num_to_check++);
oeth_disable_rx();
 
// Now for 10mbit mode...
ethphy_set_10mbit(0);
 
oeth_enable_rx();
 
for(num_to_check=ETH_TX_MIN_PACKET_SIZE;
num_to_check<ETH_TX_NUM_PACKETS;
num_to_check++)
fill_and_tx_call_packet(num_to_check, response_time);
oeth_disable_rx();
 
// Go back to 100-mbit mode
ethphy_set_100mbit(0);
oeth_enable_rx();
 
for(num_to_check=ETH_TX_MIN_PACKET_SIZE;
num_to_check<ETH_TX_NUM_PACKETS;
num_to_check++)
fill_and_tx_call_packet(num_to_check, response_time);
 
exit(0x8000000d);
}
/sw/tests/ethmac/sim/ethmac-rxtx.c
41,13 → 41,10
//// ////
//////////////////////////////////////////////////////////////////////
 
#include "or32-utils.h"
#include "spr-defs.h"
#include "cpu-utils.h"
#include "board.h"
#include "int.h"
//#include "uart.h" // comment this out, UART uses simulation putc()
#include "open-eth.h"
#include "printf.h"
#include "ethmac.h"
#include "eth-phy-mii.h"
 
volatile unsigned tx_done;
61,14 → 58,6
static void oeth_rx(void);
static void oeth_tx(void);
 
/* Defining RTLSIM turns off use of real printf'ing to save time in simulation */
#define RTLSIM
 
#ifdef RTLSIM
#define printk
#else
#define printk printf
#endif
/* Let the ethernet packets use a space beginning here for buffering */
#define ETH_BUFF_BASE 0x01000000
 
94,20 → 83,6
#define OETH_RX_BUFF_SIZE 0x600-4
#define OETH_TX_BUFF_SIZE 0x600-4
 
/* OR32 Page size def */
#define PAGE_SHIFT 13
#define PAGE_SIZE (1UL << PAGE_SHIFT)
 
/* How many buffers per page
*/
#define OETH_RX_BUFF_PPGAE (PAGE_SIZE/OETH_RX_BUFF_SIZE)
#define OETH_TX_BUFF_PPGAE (PAGE_SIZE/OETH_TX_BUFF_SIZE)
 
/* How many pages is needed for buffers
*/
#define OETH_RX_BUFF_PAGE_NUM (OETH_RXBD_NUM/OETH_RX_BUFF_PPGAE)
#define OETH_TX_BUFF_PAGE_NUM (OETH_TXBD_NUM/OETH_TX_BUFF_PPGAE)
 
/* Buffer size (if not XXBUF_PREALLOC
*/
#define MAX_FRAME_SIZE 1518
134,61 → 109,10
#define PHYNUM 7
 
// Data array of data to transmit, tx_data_array[]
#include "eth-rxtx-data.h"
//#include "eth-rxtx-data.h" // Not used
int tx_data_pointer;
 
/* Scan the MIIM bus for PHYs */
void scan_ethphys(void)
{
unsigned int phynum,regnum, i;
volatile oeth_regs *regs;
regs = (oeth_regs *)(OETH_REG_BASE);
regs->miitx_data = 0;
for(phynum=0;phynum<32;phynum++)
{
for (regnum=0;regnum<8;regnum++)
{
printk("scan_ethphys: phy %d r%d ",phynum, regnum);
/* Now actually perform the read on the MIIM bus*/
regs->miiaddress = (regnum << 8) | phynum;
regs->miicommand = OETH_MIICOMMAND_RSTAT;
/* Wait for command to be registered*/
while(!(regs->miistatus & OETH_MIISTATUS_BUSY));
regs->miicommand = 0;
while(regs->miistatus & OETH_MIISTATUS_BUSY);
printk("%x\n",regs->miirx_data);
}
}
}
 
 
void ethmac_scanstatus(void)
{
volatile oeth_regs *regs;
regs = (oeth_regs *)(OETH_REG_BASE);
 
printk("Oeth: regs->miistatus %x regs->miirx_data %x\n",regs->miistatus, regs->miirx_data);
regs->miiaddress = 0;
regs->miitx_data = 0;
regs->miicommand = OETH_MIICOMMAND_SCANSTAT;
printk("Oeth: regs->miiaddress %x regs->miicommand %x\n",regs->miiaddress, regs->miicommand);
//regs->miicommand = 0;
volatile int i; for(i=0;i<1000;i++);
while(regs->miistatus & OETH_MIISTATUS_BUSY) ;
//spin_cursor();
//printk("\r");
//or32_exit(0);
}
 
void
eth_mii_write(char phynum, short regnum, short data)
{
215,9 → 139,9
 
 
// Wait here until all packets have been transmitted
void wait_until_all_tx_clear(void)
void
wait_until_all_tx_clear(void)
{
 
int i;
volatile oeth_bd *tx_bd;
tx_bd = (volatile oeth_bd *)OETH_BD_BASE; /* Search from beginning*/
230,7 → 154,8
/* Go through the TX buffs, search for unused one */
for(i = 0; i < OETH_TXBD_NUM; i++) {
if((tx_bd[i].len_status & OETH_TX_BD_READY)) // Looking for buffer ready for transmit
// Looking for buffer ready for transmit
if((tx_bd[i].len_status & OETH_TX_BD_READY))
some_tx_waiting = 1;
}
262,7 → 187,8
}
 
 
void ethmac_setup(void)
void
ethmac_setup(void)
{
// from arch/or32/drivers/open_eth.c
volatile oeth_regs *regs;
371,10 → 297,10
}
rx_bd[OETH_RXBD_NUM - 1].len_status |= OETH_RX_BD_WRAP; // Last buffer wraps
 
/* Enable JUST the transmiter
/* Enable RX and TX in MAC
*/
regs->moder &= ~(OETH_MODER_RXEN | OETH_MODER_TXEN);
regs->moder |= /*OETH_MODER_RXEN |*/ OETH_MODER_TXEN;
regs->moder |= OETH_MODER_RXEN | OETH_MODER_TXEN;
 
next_tx_buf_num = 0; // init tx buffer pointer
 
528,8 → 454,6
rx_bdp = ((oeth_bd *)OETH_BD_BASE) + OETH_TXBD_NUM;
printk("r");
 
/* Find RX buffers marked as having received data */
for(i = 0; i < OETH_RXBD_NUM; i++)
606,8 → 530,6
/* set our test variable */
tx_done++;
 
printk("T%d",i);
}
}
return;
616,46 → 538,56
// A function and defines to fill and transmit a packet
#define MAX_TX_BUFFER 1532
static char tx_buffer[MAX_TX_BUFFER];
static unsigned long tx_data = 0x26fab2f2;
static inline char gen_next_tx_byte(void)
{
// Bit of LFSR action
tx_data = ((~(((((tx_data&(1<<25))>>25)^((tx_data&(1<<13))>>13))^((tx_data&(1<<2))>>2)))&0x01) | (tx_data<<1));
//tx_data =(!((tx_data>>26) ^ (tx_data>>14) ^ (tx_data>>5) ^ (tx_data>>3)) & 0x1) | (tx_data<<1);
return (char) tx_data & 0xff;
}
 
void
fill_and_tx_packet(int size)
{
int i;
char tx_byte;
 
 
volatile oeth_regs *regs;
regs = (oeth_regs *)(OETH_REG_BASE);
volatile oeth_bd *tx_bd;
//tx_bd = (volatile oeth_bd *)OETH_BD_BASE;
tx_bd = (volatile oeth_bd *)OETH_BD_BASE;
tx_bd = (volatile oeth_bd*) &tx_bd[next_tx_buf_num];
 
 
// If it's in use - wait
while ((tx_bd->len_status & OETH_TX_BD_IRQ));
 
#ifndef _ETH_RXTX_DATA_H_
/* Copy the data into the transmit buffer, byte at a time */
// Use rand() function to generate data for transmission
// Assumption: ethernet buffer descriptors are 4byte aligned
char* data_b = (char*) tx_bd->addr;
for(i=0;i<size;i++)
// We will fill with words until there' less than a word to go
int words_to_fill = size / sizeof(unsigned int);
 
unsigned int* data_w = (unsigned int*) data_b;
 
for(i=0;i<words_to_fill;i++)
data_w[i] = rand();
 
// Point data_b to offset wher word fills ended
data_b += (words_to_fill * sizeof(unsigned int));
 
int leftover_size = size - (words_to_fill * sizeof(unsigned int));
 
for(i=0;i<leftover_size;i++)
{
data_b[i] = gen_next_tx_byte();
data_b[i] = rand() & 0xff;
}
#endif
 
tx_packet((void*)0, size);
}
 
// Send a packet, the very first byte of which will be read by the testbench
// and used to indicate which test we'll use.
void
send_ethmac_rxtx_test_init_packet(char test)
{
char cmd_tx_buffer[40];
cmd_tx_buffer[0] = test;
tx_packet(cmd_tx_buffer, 40); // Smallest packet that can be sent (I think)
}
 
// Loop to check if a number is prime by doing mod divide of the number
// to test by every number less than it
671,12 → 603,11
}
 
 
//#define WAIT_PACKET_TX(x) while(tx_done<x)
#define WAIT_PACKET_TX(x)
 
int main ()
int
main ()
{
tx_data_pointer = 0;
 
/* Initialise handler vector */
int_init();
 
684,8 → 615,11
int_add(ETH0_IRQ, oeth_interrupt, 0);
 
/* Enable interrupts in supervisor register */
mtspr (SPR_SR, mfspr (SPR_SR) | SPR_SR_IEE);
cpu_enable_user_interrupts();
 
/* Enable CPU timer */
cpu_enable_timer();
 
ethmac_setup(); /* Configure MAC, TX/RX BDs and enable RX and TX in MODER */
 
/* clear tx_done, the tx interrupt handler will set it when it's been
693,35 → 627,20
tx_done = 0;
rx_done = 0;
 
printf("Start of large txdata buffer: 0x%x\n",
(unsigned long)&tx_data_array[0]);
printf("Slut of large txdata buffer: 0x%x\n",
(unsigned long)&tx_data_array[262144]);
ethphy_set_100mbit(0);
 
 
ethphy_set_100mbit(0);
send_ethmac_rxtx_test_init_packet(0xff); // Test value of 0xFF
oeth_enable_rx();
//oeth_enable_rx();
 
#define ETH_TX_MIN_PACKET_SIZE 512
#define ETH_TX_NUM_PACKETS (ETH_TX_MIN_PACKET_SIZE + 32)
 
#define CALCULATE_PRIMES 0
 
char prime_check_results[2048];
unsigned long num_to_check;
for(num_to_check=ETH_TX_MIN_PACKET_SIZE;
num_to_check<ETH_TX_NUM_PACKETS;
num_to_check++)
{
fill_and_tx_packet(num_to_check);
#if CALCULATE_PRIMES==1
prime_check_results[num_to_check-5]
= (char) is_prime_number(num_to_check);
report(num_to_check | (0x1e<<24));
report(prime_check_results[num_to_check-5] | (0x2e<<24));
#endif
}
fill_and_tx_packet(num_to_check);
oeth_disable_rx();
 
733,18 → 652,8
for(num_to_check=ETH_TX_MIN_PACKET_SIZE;
num_to_check<ETH_TX_NUM_PACKETS;
num_to_check++)
{
fill_and_tx_packet(num_to_check);
#if CALCULATE_PRIMES==1
prime_check_results[num_to_check+(OETH_TX_BUFF_SIZE-5)]
= (char) is_prime_number(num_to_check+OETH_TX_BUFF_SIZE);
report(num_to_check | (0x1e<<24));
report(prime_check_results[num_to_check+(OETH_TX_BUFF_SIZE-5)]
| (0x2e<<24)
);
#endif
}
 
fill_and_tx_packet(num_to_check);
oeth_disable_rx();
 
// Go back to 100-mbit mode
755,20 → 664,8
for(num_to_check=ETH_TX_MIN_PACKET_SIZE;
num_to_check<ETH_TX_NUM_PACKETS;
num_to_check++)
{
fill_and_tx_packet(num_to_check);
#if CALCULATE_PRIMES==1
prime_check_results[num_to_check+(OETH_TX_BUFF_SIZE-5)]
= (char) is_prime_number(num_to_check+OETH_TX_BUFF_SIZE);
report(num_to_check | (0x1e<<24));
report(prime_check_results[num_to_check+(OETH_TX_BUFF_SIZE-5)]
| (0x2e<<24)
);
#endif
}
fill_and_tx_packet(num_to_check);
 
 
exit(0x8000000d);
 
}
/sw/tests/ethmac/sim/ethmac-rx.c
8,8 → 8,7
//// 256 packets to be sent. ////
//// ////
//// Author(s): ////
//// - jb, jb@orsoc.se, with parts taken from Linux kernel ////
//// open_eth driver. ////
//// - Julius Baxter, julius@opencores.org ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
40,12 → 39,9
//////////////////////////////////////////////////////////////////////
 
#include "cpu-utils.h"
//#include "spr-defs.h"
#include "board.h"
#include "int.h"
#include "uart.h"
#include "ethmac.h"
#include "printf.h"
#include "eth-phy-mii.h"
 
volatile unsigned tx_done;
53,29 → 49,19
 
/* Functions in this file */
void ethmac_setup(void);
void ethphy_init(void);
void oeth_dump_bds();
/* Interrupt functions */
void oeth_interrupt(void);
static void oeth_rx(void);
static void oeth_tx(void);
/* Function to calculate checksum of ping responses we send */
unsigned short calculate_checksum(char* dats, unsigned int len) ;
 
/* Defining RTLSIM turns off use of real printf'ing to save time in simulation */
#define RTLSIM
 
#ifdef RTLSIM
#define printk
#else
#define printk printf
#endif
/* Let the ethernet packets use a space beginning here for buffering */
#define ETH_BUFF_BASE 0x01000000
 
 
#define RXBUFF_PREALLOC 1
#define TXBUFF_PREALLOC 1
//#undef RXBUFF_PREALLOC
//#undef TXBUFF_PREALLOC
 
/* The transmitter timeout
*/
82,6 → 68,8
#define TX_TIMEOUT (2*HZ)
 
/* Buffer number (must be 2^n)
* Note: if changing these, must also change settings in eth_stim.v testbench
* file!
*/
#define OETH_RXBD_NUM 16
#define OETH_TXBD_NUM 16
116,126 → 104,10
};
 
 
char CHECKSUM_BUFFER[OETH_RX_BUFF_SIZE]; // Big enough to hold a packet
 
#define PHYNUM 7
 
/* Scan the MIIM bus for PHYs */
void scan_ethphys(void)
{
unsigned int phynum,regnum, i;
volatile oeth_regs *regs;
regs = (oeth_regs *)(OETH_REG_BASE);
regs->miitx_data = 0;
for(phynum=0;phynum<32;phynum++)
{
for (regnum=0;regnum<8;regnum++)
{
printk("scan_ethphys: phy %d r%d ",phynum, regnum);
/* Now actually perform the read on the MIIM bus*/
regs->miiaddress = (regnum << 8) | phynum; /* Basic Control Register */
regs->miicommand = OETH_MIICOMMAND_RSTAT;
while(!(regs->miistatus & OETH_MIISTATUS_BUSY)); /* Wait for command to be registered*/
regs->miicommand = 0;
while(regs->miistatus & OETH_MIISTATUS_BUSY);
printk("%x\n",regs->miirx_data);
}
}
}
 
 
void ethmac_scanstatus(void)
{
volatile oeth_regs *regs;
regs = (oeth_regs *)(OETH_REG_BASE);
 
printk("Oeth: regs->miistatus %x regs->miirx_data %x\n",regs->miistatus, regs->miirx_data);
regs->miiaddress = 0;
regs->miitx_data = 0;
regs->miicommand = OETH_MIICOMMAND_SCANSTAT;
printk("Oeth: regs->miiaddress %x regs->miicommand %x\n",regs->miiaddress, regs->miicommand);
//regs->miicommand = 0;
volatile int i; for(i=0;i<1000;i++);
while(regs->miistatus & OETH_MIISTATUS_BUSY) ;
//spin_cursor();
//printk("\r");
//or32_exit(0);
}
 
void
eth_mii_write(char phynum, short regnum, short data)
{
static volatile oeth_regs *regs = (oeth_regs *)(OETH_REG_BASE);
regs->miiaddress = (regnum << 8) | phynum;
regs->miitx_data = data;
regs->miicommand = OETH_MIICOMMAND_WCTRLDATA;
regs->miicommand = 0;
while(regs->miistatus & OETH_MIISTATUS_BUSY);
}
 
short
eth_mii_read(char phynum, short regnum)
{
static volatile oeth_regs *regs = (oeth_regs *)(OETH_REG_BASE);
regs->miiaddress = (regnum << 8) | phynum;
regs->miicommand = OETH_MIICOMMAND_RSTAT;
regs->miicommand = 0;
while(regs->miistatus & OETH_MIISTATUS_BUSY);
return regs->miirx_data;
}
void ethphy_init(void)
{
 
/* Init the Alaska 88E1111 Phy */
char alaska88e1111_ml501_phynum = 0x7;
 
/* Init, reset */
short ctl = eth_mii_read(alaska88e1111_ml501_phynum, MII_BMCR);
ctl &= ~(BMCR_FULLDPLX|BMCR_SPEED100|BMCR_SPD2|BMCR_ANENABLE);
ctl |= BMCR_SPEED100; // 100MBit
ctl |= BMCR_FULLDPLX; // Full duplex
eth_mii_write(alaska88e1111_ml501_phynum, MII_BMCR, ctl);
 
// Setup Autoneg
short adv = eth_mii_read(alaska88e1111_ml501_phynum, MII_ADVERTISE);
adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_1000XFULL
|ADVERTISE_1000XHALF | ADVERTISE_1000XPAUSE |
ADVERTISE_1000XPSE_ASYM);
adv |= ADVERTISE_10HALF;
adv |= ADVERTISE_10FULL;
adv |= ADVERTISE_100HALF;
adv |= ADVERTISE_100FULL;
eth_mii_write(alaska88e1111_ml501_phynum, MII_ADVERTISE, adv);
// Disable gigabit???
adv = eth_mii_read(alaska88e1111_ml501_phynum, MII_M1011_PHY_SPEC_CONTROL);
adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP |
MII_1000BASETCONTROL_HALFDUPLEXCAP);
eth_mii_write(alaska88e1111_ml501_phynum, MII_M1011_PHY_SPEC_CONTROL, adv);
// Even more disable gigabit?!
adv = eth_mii_read(alaska88e1111_ml501_phynum, MII_CTRL1000);
adv &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
eth_mii_write(alaska88e1111_ml501_phynum, MII_CTRL1000, adv);
 
// Restart autoneg
printk("Resetting phy...\n");
ctl = eth_mii_read(alaska88e1111_ml501_phynum, MII_BMCR);
ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
eth_mii_write(alaska88e1111_ml501_phynum, MII_BMCR, ctl);
 
}
 
 
void ethmac_setup(void)
{
// from arch/or32/drivers/open_eth.c
353,7 → 225,19
return;
}
 
void
ethmac_halt(void)
{
volatile oeth_regs *regs;
regs = (oeth_regs *)(OETH_REG_BASE);
 
// Disable receive and transmit
regs->moder &= ~(OETH_MODER_RXEN | OETH_MODER_TXEN);
 
}
 
 
/* The interrupt handler.
*/
void
416,13 → 300,12
rx_bdp = ((oeth_bd *)OETH_BD_BASE) + OETH_TXBD_NUM;
printk("r");
/* Find RX buffers marked as having received data */
for(i = 0; i < OETH_RXBD_NUM; i++)
{
bad=0;
if(!(rx_bdp[i].len_status & OETH_RX_BD_EMPTY)){ /* Looking for NOT empty buffers desc. */
/* Looking for buffer descriptors marked not empty */
if(!(rx_bdp[i].len_status & OETH_RX_BD_EMPTY)){
/* Check status for errors.
*/
report(i);
459,9 → 342,14
}
else {
/*
Process the incoming frame.
* Process the incoming frame.
*/
pkt_len = rx_bdp[i].len_status >> 16;
 
// Do a bit of work - ie. copy it, process it
memcpy(CHECKSUM_BUFFER, rx_bdp[i].addr, pkt_len);
report(0xc4eccccc);
report(calculate_checksum(CHECKSUM_BUFFER, pkt_len));
/* finish up */
rx_bdp[i].len_status &= ~OETH_RX_BD_STATS; /* Clear stats */
473,8 → 361,29
}
}
 
// Calculate checksum on received data.
// From http://lkml.indiana.edu/hypermail/linux/kernel/9612.3/0060.html
unsigned short calculate_checksum(char* dats, unsigned int len)
{
unsigned int itr;
unsigned long accum = 0;
unsigned long longsum;
// Sum all pairs of data
for(itr=0;itr<(len & ~0x1);itr+=2)
accum += (unsigned long)(((dats[itr]<<8)&0xff00)|(dats[itr+1]&0x00ff));
if (len & 0x1) // Do leftover
accum += (unsigned long) ((dats[itr-1]<<8)&0xff00);
 
longsum = (unsigned long) (accum & 0xffff);
longsum += (unsigned long) (accum >> 16); // Sum the carries
longsum += (longsum >> 16);
return (unsigned short)((longsum ^ 0xffff) & 0xffff);
}
 
 
static void
oeth_tx(void)
{
497,8 → 406,6
/* set our test variable */
tx_done = 1;
 
printk("T%d",i);
}
}
return;
517,7 → 424,8
return 1;
}
 
int main ()
int
main ()
{
/* Initialise handler vector */
528,25 → 436,38
 
/* Enable interrupts in supervisor register */
cpu_enable_user_interrupts();
 
/* Enable CPU timer */
cpu_enable_timer();
rx_done = 0;
ethmac_setup(); /* Configure MAC, TX/RX BDs and enable RX in MODER */
 
#define NUM_PRIMES_TO_CHECK 1000
#define RX_TEST_LENGTH_PACKETS 50
 
char prime_check_results[NUM_PRIMES_TO_CHECK];
unsigned long num_to_check;
 
for(num_to_check=2;num_to_check<NUM_PRIMES_TO_CHECK;num_to_check++)
{
prime_check_results[num_to_check-2]
= (char) is_prime_number(num_to_check);
report(num_to_check | (0x1e<<24));
report(prime_check_results[num_to_check-2] | (0x2e<<24));
if (rx_done >= 255) // Check number of packets received, testbench
// will hopefully send at least 256 packets
exit(0x8000000d);
}
exit(0xbaaaaaad);
for(num_to_check=2;num_to_check<NUM_PRIMES_TO_CHECK;num_to_check++)
{
prime_check_results[num_to_check-2]
= (char) is_prime_number(num_to_check);
report(num_to_check | (0x1e<<24));
report(prime_check_results[num_to_check-2] | (0x2e<<24));
// Check number of packets received, testbench will hopefully send at
// least this many packets
if (rx_done >= (RX_TEST_LENGTH_PACKETS - 1))
exit(0x8000000d);
}
 
ethmac_halt();
exit(0x8000000d);
 
//exit(0xbaaaaaad);
return 0;
}
/sw/tests/ethmac/sim/ethmac-tx.c
8,10 → 8,6
//// Define, ETH_TX_TEST_LENGTH, set further down, controls how ////
//// many packets the test will send. ////
//// ////
//// Test data comes from pre-calculated array of random values, ////
//// MAC TX buffer pointers are set to addresses in this array, ////
//// saving copying the data around before transfers. ////
//// ////
//// Author(s): ////
//// - jb, jb@orsoc.se, with parts taken from Linux kernel ////
//// open_eth driver. ////
44,13 → 40,10
//// ////
//////////////////////////////////////////////////////////////////////
 
#include "or32-utils.h"
#include "spr-defs.h"
#include "cpu-utils.h"
#include "board.h"
#include "int.h"
#include "uart.h"
#include "open-eth.h"
#include "printf.h"
#include "ethmac.h"
#include "eth-phy-mii.h"
 
volatile unsigned tx_done;
64,18 → 57,9
static void oeth_rx(void);
static void oeth_tx(void);
 
/* Defining RTLSIM turns off use of real printf'ing to save time in simulation */
#define RTLSIM
 
#ifdef RTLSIM
#define printk
#else
#define printk printf
#endif
/* Let the ethernet packets use a space beginning here for buffering */
#define ETH_BUFF_BASE 0x01000000
 
 
#define RXBUFF_PREALLOC 1
#define TXBUFF_PREALLOC 1
//#undef RXBUFF_PREALLOC
97,20 → 81,6
#define OETH_RX_BUFF_SIZE 0x600 - 4
#define OETH_TX_BUFF_SIZE 0x600 - 4
 
/* OR32 Page size def */
#define PAGE_SHIFT 13
#define PAGE_SIZE (1UL << PAGE_SHIFT)
 
/* How many buffers per page
*/
#define OETH_RX_BUFF_PPGAE (PAGE_SIZE/OETH_RX_BUFF_SIZE)
#define OETH_TX_BUFF_PPGAE (PAGE_SIZE/OETH_TX_BUFF_SIZE)
 
/* How many pages is needed for buffers
*/
#define OETH_RX_BUFF_PAGE_NUM (OETH_RXBD_NUM/OETH_RX_BUFF_PPGAE)
#define OETH_TX_BUFF_PAGE_NUM (OETH_TXBD_NUM/OETH_TX_BUFF_PPGAE)
 
/* Buffer size (if not XXBUF_PREALLOC
*/
#define MAX_FRAME_SIZE 1518
118,15 → 88,13
/* The buffer descriptors track the ring buffers.
*/
struct oeth_private {
//struct sk_buff* rx_skbuff[OETH_RXBD_NUM];
//struct sk_buff* tx_skbuff[OETH_TXBD_NUM];
 
unsigned short tx_next; /* Next buffer to be sent */
unsigned short tx_last; /* Next buffer to be checked if packet sent */
unsigned short tx_full; /* Buffer ring fuul indicator */
unsigned short rx_cur; /* Next buffer to be checked if packet received */
unsigned short tx_next;/* Next buffer to be sent */
unsigned short tx_last;/* Next buffer to be checked if packet sent */
unsigned short tx_full;/* Buffer ring fuul indicator */
unsigned short rx_cur; /* Next buffer to check if packet received */
oeth_regs *regs; /* Address of controller registers. */
oeth_regs *regs; /* Address of controller registers. */
oeth_bd *rx_bd_base; /* Address of Rx BDs. */
oeth_bd *tx_bd_base; /* Address of Tx BDs. */
135,8 → 103,8
 
 
// Data array of data to transmit, tx_data_array[]
#include "eth-rxtx-data.h"
int tx_data_pointer;
// Not included in ORPSoC - #include "eth-rxtx-data.h"
//int tx_data_pointer;
 
#define PHYNUM 7
 
400,174 → 368,6
 
}
 
/* enable RX, loop waiting for arrived packets and print them out */
void oeth_monitor_rx(void)
{
volatile oeth_regs *regs;
regs = (oeth_regs *)(OETH_REG_BASE);
 
/* Set RXEN in MAC MODER */
regs->moder = OETH_MODER_RXEN | regs->moder;
 
volatile oeth_bd *rx_bd;
rx_bd = ((volatile oeth_bd *)OETH_BD_BASE) + OETH_TXBD_NUM;
 
volatile int i;
while (1)
{
for(i=0;i<OETH_RXBD_NUM;i++)
{
if (!(rx_bd[i].len_status & OETH_RX_BD_EMPTY)) /* Not empty */
{
// Something in this buffer!
printk("Oeth: RX in buf %d - len_status: 0x%lx\n",i, rx_bd[i].len_status);
/* Clear recieved bit */
rx_bd[i].len_status |= OETH_RX_BD_EMPTY;
printk("\t end of packet\n\n");
}
}
}
}
 
 
char broadcast_ping_packet[] = {
0xff,0xff,0xff,0xff,0xff,0xff, /*SRC MAC*/
0x00, 0x12, 0x34, 0x56, 0x78, 0x9a, /*SRC MAC*/
0x08,0x00,
0x45,
0x00,
0x00,0x54,
0x00,0x00,
0x40,
0x00,
0x40,
0x01,
0xef,0xef,
0xc0,0xa8,0x64,0x58, /* Source IP */
0xc0,0xa8,0x64,0xff, /* Dest. IP */
/* ICMP Message body */
0x08,0x00,0x7d,0x65,0xa7,0x20,0x00,0x01,0x68,0x25,0xa5,0x4a,0xcf,0x05,0x0c,0x00,0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e,0x1f,0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37};
 
 
char big_broadcast_ping_packet[] = {
0xff,0xff,0xff,0xff,0xff,0xff, /*SRC MAC*/
0x00, 0x12, 0x34, 0x56, 0x78, 0x9a, /*SRC MAC*/
0x08,0x00,
0x45,
0x00,
// 0x00,0x54, /* length */
0x05,0x1c, /* length */
0x00,0x00,
0x40,
0x00,
0x40,
0x01,
0xee,0xf5,
0xc0,0xa8,0x64,0x9b, /* Source IP */
0xc0,0xa8,0x64,0xff, /* Dest. IP */
/* ICMP Message body */
0x08,0x00,0x7d,0x65,0xa7,0x20,0x00,0x01,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,
15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,
40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,
65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,
90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,
111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,
130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,
149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,
168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,
187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205,
206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,
225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,
244,245,246,247,248,249,250,251,252,253,254,255,
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,
15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,
40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,
65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,
90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,
111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,
130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,
149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,
168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,
187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205,
206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,
225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,
244,245,246,247,248,249,250,251,252,253,254,255,
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,
15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,
40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,
65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,
90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,
111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,
130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,
149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,
168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,
187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205,
206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,
225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,
244,245,246,247,248,249,250,251,252,253,254,255,
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,
15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,
40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,
65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,
90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,
111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,
130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,
149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,
168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,
187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205,
206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,
225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,
244,245,246,247,248,249,250,251,252,253,254,255,
0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,
15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,
40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,
65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,
90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,
111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127,128,129,
130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145,146,147,148,
149,150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165,166,167,
168,169,170,171,172,173,174,175,176,177,178,179,180,181,182,183,184,185,186,
187,188,189,190,191,192,193,194,195,196,197,198,199,200,201,202,203,204,205,
206,207,208,209,210,211,212,213,214,215,216,217,218,219,220,221,222,223,224,
225,226,227,228,229,230,231,232,233,234,235,236,237,238,239,240,241,242,243,
244,245,246,247,248,249,250,251,252,253,254,255};
 
 
/* This should be 98 bytes big */
char ping_packet[] = {
0x00, 0x24, 0xe8, 0x91, 0x7c, 0x0d, /*DST MAC*/
//0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /*DST MAC*/
0x00, 0x12, 0x34, 0x56, 0x78, 0x9a, /*SRC MAC*/
0x08, 0x00, /*TYPE*/
/* IP */
0x45, /* Version, header length*/
0x00, /* Differentiated services field */
0x00, 0x54, /* Total length */
0x00, 0x00, /* Identification */
0x40, /* Flags */
0x00, /* Fragment offset */
0x40, /* Time to live */
0x01, /* Protocol (0x01 = ICMP */
0xef, 0xf3, /* Header checksum */
//0xc0, 0xa8, 0x64, 0xDE, /* Source IP */
0xc0, 0xa8, 0x0, 0x58, /* Source IP */
//0xa, 0x1, 0x1, 0x3, /* Source IP */
0xc0, 0xa8, 0x64, 0x69, /* Dest. IP */
0xc0, 0xa8, 0x0, 0xb, /* Dest. IP */
//0xa, 0x1, 0x1, 0x1, /* Dest. IP */
/* ICMP Message body */
0x08, 0x00, 0x9a, 0xd4, 0xc8, 0x18, 0x00, 0x01, 0xd9, 0x8c, 0x54,
0x4a, 0x7b, 0x37, 0x01, 0x00, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d,
0x0e, 0x0f, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18,
0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23,
0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e,
0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37
};
 
 
/* The interrupt handler.
*/
void
588,39 → 388,6
regs->int_src = int_events;
 
 
#ifndef RTLSIM
printk(".");
printk("\n=tx_ | %x | %x | %x | %x | %x | %x | %x | %x\n",
((oeth_bd *)(OETH_BD_BASE))->len_status,
((oeth_bd *)(OETH_BD_BASE+8))->len_status,
((oeth_bd *)(OETH_BD_BASE+16))->len_status,
((oeth_bd *)(OETH_BD_BASE+24))->len_status,
((oeth_bd *)(OETH_BD_BASE+32))->len_status,
((oeth_bd *)(OETH_BD_BASE+40))->len_status,
((oeth_bd *)(OETH_BD_BASE+48))->len_status,
((oeth_bd *)(OETH_BD_BASE+56))->len_status);
printk("=rx_ | %x | %x | %x | %x | %x | %x | %x | %x\n",
((oeth_bd *)(OETH_BD_BASE+64))->len_status,
((oeth_bd *)(OETH_BD_BASE+64+8))->len_status,
((oeth_bd *)(OETH_BD_BASE+64+16))->len_status,
((oeth_bd *)(OETH_BD_BASE+64+24))->len_status,
((oeth_bd *)(OETH_BD_BASE+64+32))->len_status,
((oeth_bd *)(OETH_BD_BASE+64+40))->len_status,
((oeth_bd *)(OETH_BD_BASE+64+48))->len_status,
((oeth_bd *)(OETH_BD_BASE+64+56))->len_status);
 
printk("=int | txb %d | txe %d | rxb %d | rxe %d | busy %d\n",
(int_events & OETH_INT_TXB) > 0,
(int_events & OETH_INT_TXE) > 0,
(int_events & OETH_INT_RXF) > 0,
(int_events & OETH_INT_RXE) > 0,
(int_events & OETH_INT_BUSY) > 0);
#endif
/* Handle receive event in its own function.
*/
if (int_events & (OETH_INT_RXF | OETH_INT_RXE)) {
642,31 → 409,10
*/
if (int_events & OETH_INT_BUSY) {
serviced |= 0x4;
#ifndef RTLSIM
printk("b");
#endif
if (!(int_events & (OETH_INT_RXF | OETH_INT_RXE)))
oeth_rx();
}
 
 
#if 0
if (serviced == 0) {
void die(const char * str, struct pt_regs * regs, long err);
int show_stack(unsigned long *esp);
printk("!");
// printk("unserviced irq\n");
// show_stack(NULL);
// die("unserviced irq\n", regs, 801);
}
#endif
 
if (serviced == 0)
printk("\neth interrupt called but nothing serviced\n");
else /* Something happened ... either RX or TX */
printk(" | serviced 0x%x\n", serviced);
return;
}
 
684,8 → 430,6
rx_bdp = ((oeth_bd *)OETH_BD_BASE) + OETH_TXBD_NUM;
printk("r");
 
/* Find RX buffers marked as having received data */
for(i = 0; i < OETH_RXBD_NUM; i++)
730,8 → 474,6
pkt_len = rx_bdp[i].len_status >> 16;
/* Do something here with the data - copy it into userspace, perhaps*/
printk("\t end of packet\n\n");
 
/* finish up */
rx_bdp[i].len_status &= ~OETH_RX_BD_STATS; /* Clear stats */
766,8 → 508,6
/* set our test variable */
tx_done++;
 
printk("T%d",i);
}
}
return;
776,14 → 516,6
// A function and defines to fill and transmit a packet
#define MAX_TX_BUFFER 1532
static char tx_buffer[MAX_TX_BUFFER];
static unsigned long tx_data = 0x2ef2e242;
static inline char gen_next_tx_byte(void)
{
// Bit of LFSR action
tx_data = ((~(((((tx_data&(1<<25))>>25)^((tx_data&(1<<13))>>13))^((tx_data&(1<<2))>>2)))&0x01) | (tx_data<<1));
//tx_data++;
return (char) tx_data & 0xff;
}
 
void
fill_and_tx_packet(int size)
791,7 → 523,6
int i;
char tx_byte;
 
 
volatile oeth_regs *regs;
regs = (oeth_regs *)(OETH_REG_BASE);
800,16 → 531,29
tx_bd = (volatile oeth_bd *)OETH_BD_BASE;
tx_bd = (struct oeth_bd*) &tx_bd[next_tx_buf_num];
 
 
// If it's in use - wait
while ((tx_bd->len_status & OETH_TX_BD_IRQ));
 
#ifndef _ETH_RXTX_DATA_H_
/* Copy the data into the transmit buffer, byte at a time */
// Use rand() function to generate data for transmission
// Assumption: ethernet buffer descriptors are 4byte aligned
char* data_b = (char*) tx_bd->addr;
for(i=0;i<size;i++)
// We will fill with words until there' less than a word to go
int words_to_fill = size/ sizeof(unsigned int);
unsigned int* data_w = (unsigned int*) data_b;
 
for(i=0;i<words_to_fill;i++)
data_w[i] = rand();
 
// Point data_b to offset wher word fills ended
data_b += (words_to_fill * sizeof(unsigned int));
 
int leftover_size = size - (words_to_fill * sizeof(unsigned int));
 
for(i=0;i<leftover_size;i++)
{
data_b[i] = gen_next_tx_byte();
data_b[i] = rand()&0xff;
}
#endif
 
816,13 → 560,15
tx_packet((void*)0, size);
}
 
//#define WAIT_PACKET_TX(x) while(tx_done<x)
#define WAIT_PACKET_TX(x)
int
main ()
{
int i;
 
int main ()
{
#ifdef _ETH_RXTX_DATA_H_
tx_data_pointer = 0;
#endif
 
/* Initialise handler vector */
int_init();
 
830,7 → 576,7
int_add(ETH0_IRQ, oeth_interrupt, 0);
 
/* Enable interrupts in supervisor register */
mtspr (SPR_SR, mfspr (SPR_SR) | SPR_SR_IEE);
cpu_enable_user_interrupts();
ethmac_setup(); /* Configure MAC, TX/RX BDs and enable RX and TX in MODER */
 
838,19 → 584,23
tx_done = 0;
rx_done = 0;
 
int i;
ethphy_set_100mbit(0);
 
#ifndef ETH_TX_TEST_LENGTH
# define ETH_TX_TEST_LENGTH 128
# define ETH_TX_START_LENGTH 40
# define ETH_TX_TEST_LENGTH 1024
# define ETH_TX_TEST_LENGTH_INCREMENT 21
//# define ETH_TX_TEST_LENGTH OETH_TX_BUFF_SIZE
#endif
 
for(i=5;i<ETH_TX_TEST_LENGTH;i+=1)
for(i=ETH_TX_START_LENGTH;i<ETH_TX_TEST_LENGTH;
i+=ETH_TX_TEST_LENGTH_INCREMENT)
fill_and_tx_packet(i);
ethphy_set_10mbit(0);
for(i=5;i<ETH_TX_TEST_LENGTH;i+=1)
 
for(i=ETH_TX_START_LENGTH;i<ETH_TX_TEST_LENGTH;
i+=ETH_TX_TEST_LENGTH_INCREMENT)
fill_and_tx_packet(i);
exit(0x8000000d);
/sw/apps/dhry/dhry.c
182,10 → 182,10
/***************/
/* printf("%d", my_test2(Number_Of_Runs));*/
clear_timer_ticks(); // Clear tick timer counter
enable_timer(); // start OR1K tick timer
cpu_reset_timer_ticks(); // Clear tick timer counter
cpu_enable_timer(); // start OR1K tick timer
 
Begin_Time = get_timer_ticks();
Begin_Time = cpu_get_timer_ticks();
 
for (Run_Index = 1; Run_Index <= Number_Of_Runs; ++Run_Index)
{
273,7 → 273,7
/* Stop timer */
/**************/
End_Time = get_timer_ticks();
End_Time = cpu_get_timer_ticks();
 
/* printf ("Execution ends\n");
printf ("\n");
/sw/drivers/or1200/exceptions.c
41,7 → 41,7
 
extern void int_main();
 
void (*except_handlers[]) (void) = {0, // 0
void (*except_handlers[]) (void ) = {0, // 0
0, // 1
0, // 2
0, // 3
64,7 → 64,7
 
void
add_handler(unsigned long vector, void (*handler) (void))
add_handler(unsigned long vector, void (*handler) (void *))
{
except_handlers[vector] = handler;
}
/sw/drivers/or1200/or1200-utils.c
3,13 → 3,15
#include "board.h" // For timer rate (IN_CLK, TICKS_PER_SEC)
 
/* For writing into SPR. */
void mtspr(unsigned long spr, unsigned long value)
void
mtspr(unsigned long spr, unsigned long value)
{
asm("l.mtspr\t\t%0,%1,0": : "r" (spr), "r" (value));
}
 
/* For reading SPR. */
unsigned long mfspr(unsigned long spr)
unsigned long
mfspr(unsigned long spr)
{
unsigned long value;
asm("l.mfspr\t\t%0,%1,0" : "=r" (value) : "r" (spr));
17,7 → 19,8
}
 
/* Print out a character via simulator */
void sim_putc(unsigned char c)
void
sim_putc(unsigned char c)
{
asm("l.addi\tr3,%0,0": :"r" (c));
asm("l.nop %0": :"K" (NOP_PUTC));
24,7 → 27,8
}
 
/* print long */
void report(unsigned long value)
void
report(unsigned long value)
{
asm("l.addi\tr3,%0,0": :"r" (value));
asm("l.nop %0": :"K" (NOP_REPORT));
31,7 → 35,8
}
 
/* Loops/exits simulation */
void exit (int i)
void
exit (int i)
{
asm("l.add r3,r0,%0": : "r" (i));
asm("l.nop %0": :"K" (NOP_EXIT));
51,14 → 56,17
 
/* Tick timer functions */
/* Enable tick timer and interrupt generation */
void enable_timer(void)
void
cpu_enable_timer(void)
{
mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT | ((IN_CLK/TICKS_PER_SEC) & SPR_TTMR_PERIOD));
mtspr(SPR_SR, SPR_SR_TEE | mfspr(SPR_SR));
mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT | ((IN_CLK/TICKS_PER_SEC) & SPR_TTMR_PERIOD));
 
}
 
/* Disable tick timer and interrupt generation */
void disable_timer(void)
void
cpu_disable_timer(void)
{
// Disable timer: clear it all!
mtspr (SPR_SR, mfspr (SPR_SR) & ~SPR_SR_TEE);
67,7 → 75,9
}
 
/* Timer increment - called by interrupt routine */
void timer_tick(void)
/* Now actually done in interrupt vector code in crt0.S */
void
cpu_timer_tick(void)
{
timer_ticks++;
mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT | ((IN_CLK/TICKS_PER_SEC) & SPR_TTMR_PERIOD));
74,21 → 84,24
}
 
/* Reset tick counter */
void clear_timer_ticks(void)
void
cpu_reset_timer_ticks(void)
{
timer_ticks=0;
}
 
/* Get tick counter */
unsigned long get_timer_ticks(void)
unsigned long
cpu_get_timer_ticks(void)
{
return timer_ticks;
}
 
/* Wait for 10ms */
void wait_10ms(void)
void
cpu_sleep_10ms(void)
{
unsigned long first_time = get_timer_ticks();
while (first_time == get_timer_ticks());
unsigned long first_time = cpu_get_timer_ticks();
while (first_time == cpu_get_timer_ticks());
}
/sw/drivers/or1200/include/int.h
1,6 → 1,7
#ifndef _INT_H_
#define _INT_H_
/* Number of interrupt handlers */
 
/* Number of interrupt handlers - really depends on PIC width in OR1200*/
#define MAX_INT_HANDLERS 32
 
/* Handler entry */
13,7 → 14,7
int int_add(unsigned long vect, void (* handler)(void *), void *arg);
 
/* Add exception vector handler */
void add_handler(unsigned long vector, void (*handler) (void));
void add_handler(unsigned long vector, void (* handler) (void *));
 
/* Initialize routine */
int int_init();
/sw/drivers/or1200/include/or1200-utils.h
39,16 → 39,16
/* Variable keeping track of timer ticks */
extern unsigned long timer_ticks;
/* Enable tick timer and interrupt generation */
void enable_timer(void);
void cpu_enable_timer(void);
/* Disable tick timer and interrupt generation */
void disable_timer(void);
void cpu_disable_timer(void);
/* Timer increment - called by interrupt routine */
void timer_tick(void);
void cpu_timer_tick(void);
/* Reset tick counter */
void clear_timer_ticks(void);
void cpu_reset_timer_ticks(void);
/* Get tick counter */
unsigned long get_timer_ticks(void);
unsigned long cpu_get_timer_ticks(void);
/* Wait for 10ms */
void wait_10ms(void);
void cpu_sleep_10ms(void);
 
#endif
/boards/actel/ordb1a3pe1500/bench/verilog/include/eth_stim.v
52,7 → 52,7
`define ETH_MODER_PATH `ETH_TOP.ethreg1.MODER_0
 
`ifdef RTL_SIM
`ifdef eth_IS_GATELEVEL
`ifdef ethmac_IS_GATELEVEL
`define ETH_MODER_TXEN_BIT `ETH_MODER_PATH.r_TxEn;
`define ETH_MODER_RXEN_BIT `ETH_MODER_PATH.r_RxEn;
`else
72,8 → 72,15
integer lfsr_last_byte;
 
// Is number of ethernet packets to send if doing the eth-rx test.
parameter eth_stim_num_rx_only_tests = 256;
parameter eth_stim_num_rx_only_num_packets = 500; // Set to 0 for continuous RX
parameter eth_stim_num_rx_only_packet_size = 512;
parameter eth_stim_num_rx_only_packet_size_change = 2'b01; // 2'b01: Increment
parameter eth_stim_num_rx_only_packet_size_change_amount = 1;
parameter eth_stim_num_rx_only_IPG = 800000; // ns
 
// Do call/response test
reg eth_stim_do_rx_reponse_to_tx;
 
parameter num_tx_bds = 16;
parameter num_tx_bds_mask = 4'hf;
80,6 → 87,7
parameter num_rx_bds = 16;
parameter num_rx_bds_mask = 4'hf;
parameter max_eth_packet_size = 16'h0600;
 
// If running eth-rxtxbig test (sending and receiving maximum packets), then
// set this parameter to the max packet size, otherwise min packet size
//parameter rx_while_tx_min_packet_size = max_eth_packet_size;
140,7 → 148,11
lfsr_last_byte = 0;
eth_stim_waiting = 1;
expected_rxbd = num_tx_bds; // init this here
 
eth_stim_do_rx_reponse_to_tx = 0;
while (eth_stim_waiting) // Loop, waiting for enabling of MAC by software
begin
#100;
149,14 → 161,26
begin
if (eth_inject_errors)
begin
do_rx_only_stim(16, 0, 0);
do_rx_only_stim(128, 1'b1, 8);
do_rx_only_stim(256, 1'b1, 4);
do_rx_only_stim(16, 64, 0, 0);
do_rx_only_stim(128, 64, 1'b1, 8);
do_rx_only_stim(256, 64, 1'b1, 4);
eth_stim_waiting = 0;
end
else
begin
do_rx_only_stim(eth_stim_num_rx_only_tests, 0, 0);
//do_rx_only_stim(eth_stim_num_rx_only_num_packets,
//eth_stim_num_rx_only_packet_size, 0, 0);
 
// Call packet send loop directly. No error injection.
send_packet_loop(eth_stim_num_rx_only_num_packets,
eth_stim_num_rx_only_packet_size,
eth_stim_num_rx_only_packet_size_change,
eth_stim_num_rx_only_packet_size_change_amount,
eth_phy0.eth_speed, // Speed
eth_stim_num_rx_only_IPG, // IPG
48'h0012_3456_789a, 48'h0708_090A_0B0C, 1,
0, 0);
eth_stim_waiting = 0;
end
end // if (ethmac_rxen === 1'b1 & !(ethmac_txen===1'b1))
163,8 → 187,26
// If both RX and TX enabled
else if (ethmac_rxen === 1'b1 & ethmac_txen===1'b1)
begin
// If RX enable and TX enable
do_rx_while_tx_stim(1400);
// Both enabled - let's wait for the first packet transmitted
// to see what stimulus we should provide
while (num_tx_packets==1)
#1000;
 
$display("* ethmac RX/TX test request: %x", eth_phy0.tx_mem[0]);
// Check the first received byte's value
case (eth_phy0.tx_mem[0])
0:
begin
// kickoff call/response here
eth_stim_do_rx_reponse_to_tx = 1;
end
default:
begin
do_rx_while_tx_stim(1400);
end
endcase // case (eth_phy0.tx_mem[0])
eth_stim_waiting = 0;
end
end // while (eth_stim_waiting)
175,16 → 217,17
// Sends a set of packets at both speeds
task do_rx_only_stim;
input [31:0] num_packets;
input [31:0] start_packet_size;
input inject_errors;
input [31:0] inject_errors_mod;
begin
expected_rxbd = num_tx_bds; // init this here
for(speed_loop=1;speed_loop<3;speed_loop=speed_loop+1)
begin
send_packet_loop(num_packets, 64, 2'b01, 1, speed_loop[0], 10000,
send_packet_loop(num_packets, start_packet_size, 2'b01, 1,
speed_loop[0], 10000,
48'h0012_3456_789a, 48'h0708_090A_0B0C, 1,
inject_errors, inject_errors_mod);
202,7 → 245,6
integer j;
begin
expected_rxbd = num_tx_bds; // init this here
for(j=0;j<num_packets;j=j+1)
begin
269,32 → 311,103
end
endtask // do_rx_stim
 
// Registers used in detecting transmitted packets
reg eth_stim_tx_loop_keep_polling;
reg [31:0] ethmac_txbd_lenstat, ethmac_last_txbd_lenstat;
reg eth_stim_detected_packet_tx;
 
// If in call-response mode, whenever we receive a TX packet, we generate
// one and send it back
always @(negedge eth_stim_detected_packet_tx)
begin
if (eth_stim_do_rx_reponse_to_tx & ethmac_rxen)
// Continue if we are enabled
do_rx_response_to_tx();
end
// Generate RX packet in rsponse to TX packet
task do_rx_response_to_tx;
//input unused;
reg [31:0] IPG; // Inter-packet gap
reg [31:0] packet_size;
integer j;
begin
 
// Get packet size test wants us to send
packet_size = {eth_phy0.tx_mem[0],eth_phy0.tx_mem[1],
eth_phy0.tx_mem[2],eth_phy0.tx_mem[3]};
 
IPG = {eth_phy0.tx_mem[4],eth_phy0.tx_mem[5],
eth_phy0.tx_mem[6],eth_phy0.tx_mem[7]};
$display("do_rx_response_to_tx IPG = %0d", IPG);
if (packet_size == 0)
begin
// Constrained random sized packets
packet_size = $random;
while (packet_size > (max_eth_packet_size-4))
packet_size = packet_size / 2;
if (packet_size < 60)
packet_size = packet_size + 60;
end
$display("do_rx_response_to_tx packet_size = %0d", packet_size);
send_packet_loop(1, packet_size, 2'b01, 1, eth_phy0.eth_speed,
IPG, 48'h0012_3456_789a,
48'h0708_090A_0B0C, 1, 1'b0, 0);
// If RX enable went low, wait for it go high again
if (ethmac_rxen===1'b0)
begin
while (ethmac_rxen===1'b0)
begin
@(posedge ethmac_rxen);
#10000;
end
// RX disabled and when re-enabled we reset the buffer
// descriptor number
expected_rxbd = num_tx_bds;
 
end
 
end
endtask // do_rx_response_to_tx
 
//
// always@() to check the TX buffer descriptors
//
reg keep_polling;
reg [31:0] txbd_lenstat, last_txbd_lenstat;
reg detected_packet_tx;
always @(posedge ethmac_txen)
begin
last_txbd_lenstat = 0;
keep_polling=1;
ethmac_last_txbd_lenstat = 0;
eth_stim_tx_loop_keep_polling=1;
// Wait on the TxBD Ready bit
while(keep_polling)
while(eth_stim_tx_loop_keep_polling)
begin
#10;
get_bd_lenstat(expected_txbd, txbd_lenstat);
get_bd_lenstat(expected_txbd, ethmac_txbd_lenstat);
// Check if we've finished transmitting this BD
if (!txbd_lenstat[15] & last_txbd_lenstat[15])
if (!ethmac_txbd_lenstat[15] & ethmac_last_txbd_lenstat[15])
// Falling edge of TX BD Ready
detected_packet_tx = 1;
eth_stim_detected_packet_tx = 1;
 
last_txbd_lenstat = txbd_lenstat;
ethmac_last_txbd_lenstat = ethmac_txbd_lenstat;
// If TX en goes low then exit
if (!ethmac_txen)
keep_polling = 0;
else if (detected_packet_tx)
eth_stim_tx_loop_keep_polling = 0;
else if (eth_stim_detected_packet_tx)
begin
// Wait until the eth_phy has finished receiving it
while (eth_phy0.mtxen_i === 1'b1)
301,10 → 414,10
#10;
$display("(%t) Check TX packet: bd %d: 0x%h",$time,
expected_txbd, txbd_lenstat);
expected_txbd, ethmac_txbd_lenstat);
 
// Check the TXBD, see if the packet transmitted OK
if (txbd_lenstat[8] | txbd_lenstat[3])
if (ethmac_txbd_lenstat[8] | ethmac_txbd_lenstat[3])
begin
// Error occured
`TIME;
311,10 → 424,10
$display("*E TX Error of packet %0d detected.",
num_tx_packets);
$display(" TX BD %0d = 0x%h", expected_txbd,
txbd_lenstat);
if (txbd_lenstat[8])
ethmac_txbd_lenstat);
if (ethmac_txbd_lenstat[8])
$display(" Underrun in MAC during TX");
if (txbd_lenstat[3])
if (ethmac_txbd_lenstat[3])
$display(" Retransmission limit hit");
$finish;
321,8 → 434,8
end
else
begin
// Packet was OK, let's compare the contents we received
// with those that were meant to be transmitted
// Packet was OK, let's compare the contents we
// received with those that were meant to be transmitted
if (eth_stim_check_tx_packet_contents)
begin
check_tx_packet(expected_txbd);
329,11 → 442,11
expected_txbd = (expected_txbd + 1) &
num_tx_bds_mask;
num_tx_packets = num_tx_packets + 1;
detected_packet_tx = 0;
eth_stim_detected_packet_tx = 0;
end
end
end
end // while (keep_polling)
end // while (eth_stim_tx_loop_keep_polling)
end // always @ (posedge ethmac_txen)
 
348,7 → 461,8
reg [7:0] phy_byte;
reg [31:0] txpnt_wb; // Pointer in array to where data should be
reg [24:0] txpnt_sdram; // Index in array of shorts for data in SDRAM part
reg [24:0] txpnt_sdram; // Index in array of shorts for data in SDRAM
// part
reg [21:0] buffer;
reg [7:0] sdram_byte;
reg [31:0] tx_len_bd;
453,7 → 567,12
begin
error_type = 0;
error_this_time = 0;
 
if (num_packets == 0)
// Loop forever when num_packets is 0
num_packets = 32'h7fffffff;
if (speed & !(eth_phy0.control_bit14_10[13] === 1'b1))
begin
// write to phy's control register for 100Mbps
712,7 → 831,9
endtask // set_rx_addr_type
 
 
`ifdef eth_IS_GATELEVEL // Check if we're using a synthesized version of eth module
// Check if we're using a synthesized version of eth module
`ifdef ethmac_IS_GATELEVEL
 
// Get the length/status register of the ethernet buffer descriptor
task get_bd_lenstat;
input [31:0] bd_num;// Number of ethernet BD to check
778,7 → 899,7
end
endtask // get_bd_addr
 
`else // !`ifdef eth_IS_GATELEVEL
`else // !`ifdef ethmac_IS_GATELEVEL
// Get the length/status register of the ethernet buffer descriptor
task get_bd_lenstat;
806,12 → 927,14
always @*
begin
// Loop here waiting for a packet to be sent, or if we shouldn't
// check them at all.
// Loop here until:
// 1 - packets sent is not equal to packets checked (ie. some to check)
// 2 - we're explicitly disabled for some reason
// 3 - Receive has been disabled in the MAC
while((eth_rx_num_packets_sent == eth_rx_num_packets_checked) ||
!eth_stim_check_rx_packet_contents)
!eth_stim_check_rx_packet_contents || !(ethmac_rxen===1'b1))
#1000;
 
eth_rx_packet_length_to_check
= rx_packet_lengths[(eth_rx_num_packets_checked & 12'h3ff)];
899,9 → 1022,9
 
if (phy_byte !== sdram_byte)
begin
`TIME;
$display("*E Wrong byte (%d) of RX packet! phy = %h, ram = %h",
i, phy_byte, sdram_byte);
// `TIME;
$display("*E Wrong byte (%5d) of RX packet %5d! phy = %h, ram = %h",
i, eth_rx_num_packets_checked, phy_byte, sdram_byte);
failure = 1;
end
 
/boards/actel/ordb1a3pe1500/bench/verilog/orpsoc_testbench.v
487,15 → 487,11
.Dqm (sdram_dqm_pad_o_to_sdram));
`endif // `ifdef VERSATILE_SDRAM
 
initial
`ifdef VCD
reg vcd_go = 0;
always @(vcd_go)
begin
`ifndef SIM_QUIET
$display("\n* Starting simulation of design RTL.\n* Test: %s\n",
`TEST_NAME_STRING );
`endif
`ifdef VCD
`ifdef VCD_DELAY
#(`VCD_DELAY);
`endif
522,9 → 518,22
`define VCD_DEPTH 0
`endif
$dumpvars(`VCD_DEPTH);
end
`endif // `ifdef VCD
initial
begin
`ifndef SIM_QUIET
$display("\n* Starting simulation of design RTL.\n* Test: %s\n",
`TEST_NAME_STRING );
`endif
`ifdef VCD
vcd_go = 1;
`endif
end // initial begin
end // initial begin
`ifdef END_TIME
initial begin
/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/versatile_mem_ctrl_ip.v
39,130 → 39,135
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
//// ////
//// Description ////
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
//// counter ////
//// ////
//// To Do: ////
//// - add LFSR with more taps ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
module versatile_fifo_async_cmp ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
 
parameter ADDR_WIDTH = 4;
parameter N = ADDR_WIDTH-1;
 
parameter Q1 = 2'b00;
parameter Q2 = 2'b01;
parameter Q3 = 2'b11;
parameter Q4 = 2'b10;
 
parameter going_empty = 1'b0;
parameter going_full = 1'b1;
input [N:0] wptr, rptr;
output reg fifo_empty;
output fifo_full;
input wclk, rclk, rst;
wire direction;
reg direction_set, direction_clr;
wire async_empty, async_full;
wire fifo_full2;
reg fifo_empty2;
// direction_set
always @ (wptr[N:N-1] or rptr[N:N-1])
case ({wptr[N:N-1],rptr[N:N-1]})
{Q1,Q2} : direction_set <= 1'b1;
{Q2,Q3} : direction_set <= 1'b1;
{Q3,Q4} : direction_set <= 1'b1;
{Q4,Q1} : direction_set <= 1'b1;
default : direction_set <= 1'b0;
endcase
 
// direction_clear
always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
if (rst)
direction_clr <= 1'b1;
else
case ({wptr[N:N-1],rptr[N:N-1]})
{Q2,Q1} : direction_clr <= 1'b1;
{Q3,Q2} : direction_clr <= 1'b1;
{Q4,Q3} : direction_clr <= 1'b1;
{Q1,Q4} : direction_clr <= 1'b1;
default : direction_clr <= 1'b0;
endcase
 
`ifndef GENERATE_DIRECTION_AS_LATCH
dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
`endif
 
`ifdef GENERATE_DIRECTION_AS_LATCH
always @ (posedge direction_set or posedge direction_clr)
if (direction_clr)
direction <= going_empty;
else
direction <= going_full;
`endif
 
assign async_empty = (wptr == rptr) && (direction==going_empty);
assign async_full = (wptr == rptr) && (direction==going_full);
 
dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
 
/*
always @ (posedge wclk or posedge rst or posedge async_full)
if (rst)
{fifo_full, fifo_full2} <= 2'b00;
else if (async_full)
{fifo_full, fifo_full2} <= 2'b11;
else
{fifo_full, fifo_full2} <= {fifo_full2, async_full};
*/
always @ (posedge rclk or posedge async_empty)
if (async_empty)
{fifo_empty, fifo_empty2} <= 2'b11;
else
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty};
 
endmodule // async_comp
//////////////////////////////////////////////////////////////////////
//// ////
//// Versatile counter ////
//// ////
//// Description ////
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
//// counter ////
//// ////
//// To Do: ////
//// - add LFSR with more taps ////
//// ////
//// Author(s): ////
//// - Michael Unneback, unneback@opencores.org ////
//// ORSoC AB ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
module versatile_fifo_async_cmp ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
 
parameter ADDR_WIDTH = 4;
parameter N = ADDR_WIDTH-1;
 
parameter Q1 = 2'b00;
parameter Q2 = 2'b01;
parameter Q3 = 2'b11;
parameter Q4 = 2'b10;
 
parameter going_empty = 1'b0;
parameter going_full = 1'b1;
input [N:0] wptr, rptr;
output reg fifo_empty;
output fifo_full;
input wclk, rclk, rst;
 
`ifndef GENERATE_DIRECTION_AS_LATCH
wire direction;
`endif
`ifdef GENERATE_DIRECTION_AS_LATCH
reg direction;
`endif
reg direction_set, direction_clr;
wire async_empty, async_full;
wire fifo_full2;
reg fifo_empty2;
// direction_set
always @ (wptr[N:N-1] or rptr[N:N-1])
case ({wptr[N:N-1],rptr[N:N-1]})
{Q1,Q2} : direction_set <= 1'b1;
{Q2,Q3} : direction_set <= 1'b1;
{Q3,Q4} : direction_set <= 1'b1;
{Q4,Q1} : direction_set <= 1'b1;
default : direction_set <= 1'b0;
endcase
 
// direction_clear
always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
if (rst)
direction_clr <= 1'b1;
else
case ({wptr[N:N-1],rptr[N:N-1]})
{Q2,Q1} : direction_clr <= 1'b1;
{Q3,Q2} : direction_clr <= 1'b1;
{Q4,Q3} : direction_clr <= 1'b1;
{Q1,Q4} : direction_clr <= 1'b1;
default : direction_clr <= 1'b0;
endcase
 
`ifndef GENERATE_DIRECTION_AS_LATCH
dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
`endif
 
`ifdef GENERATE_DIRECTION_AS_LATCH
always @ (posedge direction_set or posedge direction_clr)
if (direction_clr)
direction <= going_empty;
else
direction <= going_full;
`endif
 
assign async_empty = (wptr == rptr) && (direction==going_empty);
assign async_full = (wptr == rptr) && (direction==going_full);
 
dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
 
/*
always @ (posedge wclk or posedge rst or posedge async_full)
if (rst)
{fifo_full, fifo_full2} <= 2'b00;
else if (async_full)
{fifo_full, fifo_full2} <= 2'b11;
else
{fifo_full, fifo_full2} <= {fifo_full2, async_full};
*/
always @ (posedge rclk or posedge async_empty)
if (async_empty)
{fifo_empty, fifo_empty2} <= 2'b11;
else
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty};
 
endmodule // async_comp
// async FIFO with multiple queues
 
module async_fifo_mq (
298,7 → 303,7
input we_b;
input clk_a, clk_b;
reg [(DATA_WIDTH-1):0] q_b;
reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0] `SYN;
reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
always @ (posedge clk_a)
begin
q_a <= ram[adr_a];
3474,10 → 3479,9
 
// Most of these defines have an effect on things in fsm_sdr_16.v
 
 
//`define MT48LC32M16 // 64MB part
`define MT48LC16M16 // 32MB part
//`define MT48LC4M16 // 8MB part
`define MT48LC16M16 // 32MB part
//`define MT48LC4M16 // 8MB part
 
// Define this to allow indication that a burst read is still going
// to the wishbone state machine, so it doesn't start emptying the
3493,7 → 3497,7
 
 
`ifdef MT48LC32M16
// using 1 of MT48LC16M16
// using 1 of MT48LC32M16
// SDRAM data width is 16
`define SDRAM_DATA_WIDTH 16
4100,6 → 4104,11
 
endmodule
`endif // !`ifdef ORIGINAL_EGRESS_FIFO
// true dual port RAM, sync
 
`ifdef ACTEL
`define SYN
`endif
module vfifo_dual_port_ram_dc_sw
(
d_a,
4119,7 → 4128,7
output [(DATA_WIDTH-1):0] q_b;
input clk_a, clk_b;
reg [(ADDR_WIDTH-1):0] adr_b_reg;
reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0]/*synthesis syn_ramstyle = "no_rw_check"*/ ;
reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
always @ (posedge clk_a)
if (we_a)
ram[adr_a] <= d_a;
/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/versatile_mem_ctrl.v
1072,7 → 1072,7
output [(DATA_WIDTH-1):0] q_b;
input clk_a, clk_b;
reg [(ADDR_WIDTH-1):0] adr_b_reg;
reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0] ;
reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
always @ (posedge clk_a)
if (we_a)
ram[adr_a] <= d_a;
/boards/actel/ordb1a3pe1500/sim/bin/Makefile
134,6 → 134,10
# This path is for the technology library
TECHNOLOGY_BACKEND_VERILOG_DIR=$(TECHNOLOGY_BACKEND_DIR)/rtl/verilog
 
# Synthesis directory for board
BOARD_SYN_DIR=$(BOARD_DIR)/syn/synplify
BOARD_SYN_OUT_DIR=$(BOARD_SYN_DIR)/out
 
# System software dir
COMMON_SW_DIR=$(PROJECT_ROOT)/sw
BOARD_SW_DIR=$(BOARD_DIR)/sw
208,6 → 212,11
#
# Verilog DUT source variables
#
 
# First consider any modules we'll use gatelevel descriptions of.
# These will have to be set on the command line
GATELEVEL_MODULES ?=
 
# First we get a list of modules in the RTL path of the board's path.
# Next we check which modules not in the board's RTL path are in the root RTL
# path (modules which can be commonly instantiated, but over which board
214,7 → 223,7
# build-specific versions take precedence.)
 
# Paths under board/***/rtl/verilog we wish to exclude when getting modules
BOARD_VERILOG_MODULES_EXCLUDE= include
BOARD_VERILOG_MODULES_EXCLUDE= include $(GATELEVEL_MODULES)
BOARD_VERILOG_MODULES_DIR_LIST=$(shell ls $(BOARD_RTL_VERILOG_DIR))
# Apply exclude to list of modules
BOARD_RTL_VERILOG_MODULES=$(filter-out $(BOARD_VERILOG_MODULES_EXCLUDE),$(BOARD_VERILOG_MODULES_DIR_LIST))
227,10 → 236,16
# Now get list of modules that we don't have a version of in the board path
COMMON_VERILOG_MODULES_EXCLUDE= include
COMMON_VERILOG_MODULES_EXCLUDE += $(BOARD_RTL_VERILOG_MODULES)
COMMON_VERILOG_MODULES_EXCLUDE += $(GATELEVEL_MODULES)
 
COMMON_RTL_VERILOG_MODULES_DIR_LIST=$(shell ls $(COMMON_RTL_VERILOG_DIR))
COMMON_RTL_VERILOG_MODULES=$(filter-out $(COMMON_VERILOG_MODULES_EXCLUDE), $(COMMON_RTL_VERILOG_MODULES_DIR_LIST))
 
 
# Add these to exclude their RTL directories from being included in scripts
 
 
 
# Rule for debugging this script
print-common-modules-exclude:
@echo echo; echo "\t### Common verilog modules being excluded due to board versions ###"; echo
355,6 → 370,10
$(Q)for module in $(BOARD_RTL_VERILOG_MODULES); do if [ -d $(BOARD_RTL_VERILOG_DIR)/$$module ]; then echo "-y " $(BOARD_RTL_VERILOG_DIR)/$$module >> $@; fi; done
$(Q)for module in $(COMMON_RTL_VERILOG_MODULES); do if [ -d $(COMMON_RTL_VERILOG_DIR)/$$module ]; then echo "-y " $(COMMON_RTL_VERILOG_DIR)/$$module >> $@; fi; done
$(Q)echo "-y " $(BOARD_BACKEND_VERILOG_DIR) >> $@;
$(Q)if [ ! -z "$$GATELEVEL_MODULES" ]; \
then echo "-y " $(BOARD_SYN_OUT_DIR) >> $@; \
echo "+libext+.vm" >> $@; \
fi
$(Q)echo >> $@
 
modelsim_bench.scr: $(BOARD_BENCH_VERILOG_SRC) $(COMMON_BENCH_VERILOG_SRC)
431,9 → 450,6
# Include the test-defines.v generation rule
include $(PROJECT_ROOT)/sim/bin/definesgen.inc
 
# $(Q)for module in $(GATELEVEL_MODULES); do echo "\`define "$$module"_IS_GATELEVEL " >> $@; done
# More possible test defines go here
 
#
# Software make rules (called recursively)
#
472,6 → 488,7
.PHONY : sw
sw: $(SIM_SW_IMAGE)
 
 
flash.in: $(SW_TEST_DIR)/$(TEST).flashin
$(Q)if [ -L $@ ]; then unlink $@; fi
$(Q)ln -s $< $@
490,6 → 507,14
$(Q) echo; echo "\t### Compiling software ###"; echo;
$(Q)$(MAKE) -C $(SW_TEST_DIR) $(TEST).vmem
 
# Create test software disassembly
 
sw-dis: $(SW_TEST_DIR)/$(TEST).dis
$(Q)cp -v $< .
 
$(SW_TEST_DIR)/$(TEST).dis:
$(Q)$(MAKE) -C $(SW_TEST_DIR) $(TEST).dis
 
#
# Cleaning rules
#
/boards/actel/ordb1a3pe1500/sw/bootrom/bootrom.v File deleted
/boards/actel/ordb1a3pe1500/syn/synplify/bin/Makefile
120,6 → 120,8
RTL_TOP ?= $(DESIGN_NAME)_top
EDIF_FILE ?=$(RTL_TOP).edn
EDIF_FILE_OUT ?= ../out/$(EDIF_FILE)
VLOG_NETLIST_FILE ?=$(RTL_TOP).vm
VLOG_NETLIST_FILE_OUT ?= ../out/$(VLOG_NETLIST_FILE)
# Synthesis params
#FREQ ?= 50.0000
FREQ ?= 125.000
161,7 → 163,7
 
 
 
all: print-config $(EDIF_FILE_OUT)
all: print-config $(EDIF_FILE_OUT) $(VLOG_NETLIST_FILE_OUT)
 
#create the work dir
$(SYN_WORK_DIR):
305,6 → 307,9
$(EDIF_FILE_OUT): $(SYN_WORK_DIR)/$(SYN_PROJ_NAME)/$(EDIF_FILE)
cp $^ $@
 
$(VLOG_NETLIST_FILE_OUT): $(SYN_WORK_DIR)/$(SYN_PROJ_NAME)/$(VLOG_NETLIST_FILE)
cp $^ $@
 
clean-all: clean-sw clean clean-edifs
 
clean-sw:

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