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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/orpsocv2
    from Rev 431 to Rev 435
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  •

Rev 431 → Rev 435

/bench/sysc/include/Or1200MonitorSC.h
117,7 → 117,7
bool logfile_name_provided;
bool logging_regs;
bool binary_log_format;
bool exit_perf_summary_enabled;
bool quiet;
bool monitor_for_crash;
int lookslikewevecrashed_count, crash_monitor_buffer_head;
#define CRASH_MONITOR_BUFFER_SIZE 32
/bench/sysc/src/Or1200MonitorSC.cpp
71,9 → 71,7
insn_count = insn_count_rst = 0;
cycle_count = cycle_count_rst = 0;
 
exit_perf_summary_enabled = true; // Simulation exit performance summary is
// on by default. Turn off with "-q" on the
// cmd line
quiet = false;
monitor_for_crash = false;
lookslikewevecrashed_count = crash_monitor_buffer_head = 0;
 
130,7 → 128,7
else if ((strcmp(argv[i], "-q")==0) ||
(strcmp(argv[i], "--quiet")==0))
{
exit_perf_summary_enabled = false;
quiet = true;
}
else if ((strcmp(argv[i], "-p")==0) ||
(strcmp(argv[i], "--profile")==0))
427,10 → 425,13
{
case NOP_EXIT:
r3 = accessor->getGpr (3);
ts = sc_time_stamp().to_seconds() * 1000000000.0;
std::cout << std::fixed << std::setprecision (2) << ts;
std::cout << " ns: Exiting (" << r3 << ")" << std::endl;
perfSummary();
if (!quiet)
{
ts = sc_time_stamp().to_seconds() * 1000000000.0;
std::cout << std::fixed << std::setprecision (2) << ts;
std::cout << " ns: Exiting (" << r3 << ")" << std::endl;
perfSummary();
}
if (logging_enabled) statusFile.close();
if (profiling_enabled) profileFile.close();
if (bus_trans_log_enabled) busTransLog.close();
440,41 → 441,57
break;
 
case NOP_REPORT:
ts = sc_time_stamp().to_seconds() * 1000000000.0;
r3 = accessor->getGpr (3);
std::cout << std::fixed << std::setprecision (2) << ts;
std::cout << " ns: report (" << hex << r3 << ")" << std::endl;
if (!quiet)
{
ts = sc_time_stamp().to_seconds() * 1000000000.0;
r3 = accessor->getGpr (3);
std::cout << std::fixed << std::setprecision (2) << ts;
std::cout << " ns: report (" << hex << r3 << ")" << std::endl;
}
break;
 
case NOP_PRINTF:
ts = sc_time_stamp().to_seconds() * 1000000000.0;
std::cout << std::fixed << std::setprecision (2) << ts;
std::cout << " ns: printf: ";
simPrintf(accessor->getGpr (4), accessor->getGpr (3));
ts = sc_time_stamp().to_seconds() * 1000000000.0;
std::cout << std::fixed << std::setprecision (2) << ts;
std::cout << " ns: printf: ";
simPrintf(accessor->getGpr (4), accessor->getGpr (3));
break;
 
case NOP_PUTC:
r3 = accessor->getGpr (3);
std::cout << (char)r3 << std::flush;
break;
r3 = accessor->getGpr (3);
std::cout << (char)r3 << std::flush;
break;
 
case NOP_CNT_RESET:
std::cout << "****************** counters reset ******************" << endl;
std::cout << "since last reset: cycles " << cycle_count - cycle_count_rst << ", insn #" << insn_count - insn_count_rst << endl;
std::cout << "****************** counters reset ******************" << endl;
cycle_count_rst = cycle_count;
insn_count_rst = insn_count;
/* 3 separate counters we'll use for various things */
if (!quiet)
{
std::cout << "****************** counters reset ******************" << endl;
std::cout << "since last reset: cycles " << cycle_count - cycle_count_rst << ", insn #" << insn_count - insn_count_rst << endl;
std::cout << "****************** counters reset ******************" << endl;
cycle_count_rst = cycle_count;
insn_count_rst = insn_count;
/* 3 separate counters we'll use for various things */
}
case NOP_CNT_RESET1:
std::cout << "**** counter1 cycles: " << std::setfill('0') << std::setw(10) << cycle_count - cycles_1 << " resetting ********" << endl;
cycles_1 = cycle_count;
if (!quiet)
{
std::cout << "**** counter1 cycles: " << std::setfill('0') << std::setw(10) << cycle_count - cycles_1 << " resetting ********" << endl;
cycles_1 = cycle_count;
}
break;
case NOP_CNT_RESET2:
std::cout << "**** counter2 cycles: " << std::setfill('0') << std::setw(10) << cycle_count - cycles_2 << " resetting ********" << endl;
cycles_2 = cycle_count;
if (!quiet)
{
std::cout << "**** counter2 cycles: " << std::setfill('0') << std::setw(10) << cycle_count - cycles_2 << " resetting ********" << endl;
cycles_2 = cycle_count;
}
break;
case NOP_CNT_RESET3:
std::cout << "**** counter3 cycles: " << std::setfill('0') << std::setw(10) << cycle_count - cycles_3 << " resetting ********" << endl;
cycles_3 = cycle_count;
if (!quiet)
{
std::cout << "**** counter3 cycles: " << std::setfill('0') << std::setw(10) << cycle_count - cycles_3 << " resetting ********" << endl;
cycles_3 = cycle_count;
}
break;
default:
break;
786,7 → 803,7
void
Or1200MonitorSC::perfSummary()
{
if (exit_perf_summary_enabled)
if (!quiet)
{
double ts;
ts = sc_time_stamp().to_seconds() * 1000000000.0;
/rtl/verilog/include/or1200_defines.v
360,7 → 360,7
// Implement multiply-and-accumulate
//
// By default MAC is implemented. To
// implement MAC, multiplier needs to be
// implement MAC, multiplier (non-serial) needs to be
// implemented.
//
`define OR1200_MAC_IMPLEMENTED
369,23 → 369,22
// Implement optional l.div/l.divu instructions
//
// By default divide instructions are not implemented
// to save area and increase clock frequency. or32 C/C++
// compiler can use soft library for division.
// to save area.
//
// To implement divide, both multiplier and MAC needs to be implemented.
//
`define OR1200_DIV_IMPLEMENTED
 
//
// Low power, slower multiplier
// Serial multiplier.
//
// Select between low-power (larger) multiplier
// and faster multiplier. The actual difference
// is only AND logic that prevents distribution
// of operands into the multiplier when instruction
// in execution is not multiply instruction
//`define OR1200_MULT_SERIAL
 
//
//`define OR1200_LOWPWR_MULT
// Serial divider.
// Uncomment to use a serial divider, otherwise will
// be a generic parallel implementation.
//
//`define OR1200_DIV_SERIAL
 
//
// Implement HW Single Precision FPU
464,8 → 463,8
`define OR1200_ALUOP_SHROT 4'd8
`define OR1200_ALUOP_DIV 4'd9
`define OR1200_ALUOP_DIVU 4'd10
/* Order not specifically defined. */
`define OR1200_ALUOP_IMM 4'd11
`define OR1200_ALUOP_MULU 4'd11
/* Values sent to ALU from decode unit - not strictly defined by ISA */
`define OR1200_ALUOP_MOVHI 4'd12
`define OR1200_ALUOP_COMP 4'd13
`define OR1200_ALUOP_MTSR 4'd14
/rtl/verilog/or1200/or1200_alu.v
195,9 → 195,6
`OR1200_ALUOP_OR : begin
result = a | b;
end
`OR1200_ALUOP_IMM : begin
result = b;
end
`OR1200_ALUOP_MOVHI : begin
if (macrc_op) begin
result = mult_mac_result;
211,7 → 208,8
`OR1200_ALUOP_DIV,
`OR1200_ALUOP_DIVU,
`endif
`OR1200_ALUOP_MUL : begin
`OR1200_ALUOP_MUL,
`OR1200_ALUOP_MULU : begin
result = mult_mac_result;
end
`endif
/rtl/verilog/or1200/or1200_cpu.v
312,7 → 312,7
wire [`OR1200_MACOP_WIDTH-1:0] id_mac_op;
wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
wire [31:0] mult_mac_result;
wire mac_stall;
wire mult_mac_stall;
wire [13:0] except_trig;
wire [13:0] except_stop;
wire genpc_refetch;
644,7 → 644,7
.mac_op(mac_op),
.alu_op(alu_op),
.result(mult_mac_result),
.mac_stall_r(mac_stall),
.mult_mac_stall(mult_mac_stall),
.spr_cs(spr_cs[`OR1200_SPR_GROUP_MAC]),
.spr_write(spr_we),
.spr_addr(spr_addr),
785,7 → 785,7
.force_dslot_fetch(force_dslot_fetch),
.abort_ex(abort_ex),
.du_stall(du_stall),
.mac_stall(mac_stall),
.mac_stall(mult_mac_stall),
.saving_if_insn(saving_if_insn),
.genpc_freeze(genpc_freeze),
.if_freeze(if_freeze),
/rtl/verilog/or1200/or1200_gmultp2_32x32.v
3,7 → 3,7
//// Generic 32x32 multiplier ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// http://www.opencores.org/project,or1k ////
//// ////
//// Description ////
//// Generic 32x32 multiplier with pipeline stages. ////
47,31 → 47,6
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// No update
//
// Revision 1.2 2002/07/31 02:04:35 lampret
// MAC now follows software convention (signed multiply instead of unsigned).
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.4 2001/12/04 05:02:35 lampret
// Added OR1200_GENERIC_MULTP2_32X32 and OR1200_ASIC_MULTP2_32X32
//
// Revision 1.3 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.2 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
/rtl/verilog/or1200/or1200_mult_mac.v
11,13 → 11,15
//// ////
//// To Do: ////
//// - make signed division better, w/o negating the operands ////
//// - implement non-serial divider that is synthesizable ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, lampret@opencores.org ////
//// - Julius Baxter, julius@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// Copyright (C) 2000, 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
56,278 → 58,391
`include "or1200_defines.v"
 
module or1200_mult_mac(
// Clock and reset
clk, rst,
// Clock and reset
clk, rst,
 
// Multiplier/MAC interface
ex_freeze, id_macrc_op, macrc_op, a, b, mac_op, alu_op, result, mac_stall_r,
// Multiplier/MAC interface
ex_freeze, id_macrc_op, macrc_op, a, b, mac_op, alu_op,
result, mult_mac_stall,
 
// SPR interface
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
);
// SPR interface
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
);
 
parameter width = `OR1200_OPERAND_WIDTH;
parameter width = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
//
// I/O
//
 
//
// Clock and reset
//
input clk;
input rst;
//
// Clock and reset
//
input clk;
input rst;
 
//
// Multiplier/MAC interface
//
input ex_freeze;
input id_macrc_op;
input macrc_op;
input [width-1:0] a;
input [width-1:0] b;
input [`OR1200_MACOP_WIDTH-1:0] mac_op;
input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
output [width-1:0] result;
output mac_stall_r;
//
// Multiplier/MAC interface
//
input ex_freeze;
input id_macrc_op;
input macrc_op;
input [width-1:0] a;
input [width-1:0] b;
input [`OR1200_MACOP_WIDTH-1:0] mac_op;
input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
output [width-1:0] result;
output mult_mac_stall;
 
//
// SPR interface
//
input spr_cs;
input spr_write;
input [31:0] spr_addr;
input [31:0] spr_dat_i;
output [31:0] spr_dat_o;
//
// SPR interface
//
input spr_cs;
input spr_write;
input [31:0] spr_addr;
input [31:0] spr_dat_i;
output [31:0] spr_dat_o;
 
//
// Internal wires and regs
//
//
// Internal wires and regs
//
reg [width-1:0] result;
`ifdef OR1200_MULT_IMPLEMENTED
reg [width-1:0] result;
reg [2*width-1:0] mul_prod_r;
reg [2*width-1:0] mul_prod_r;
wire alu_op_smul;
wire alu_op_umul;
wire alu_op_mul;
`ifdef OR1200_MULT_SERIAL
reg [5:0] serial_mul_cnt;
reg mul_free;
`endif
`else
wire [width-1:0] result;
wire [2*width-1:0] mul_prod_r;
wire [2*width-1:0] mul_prod_r;
`endif
wire [2*width-1:0] mul_prod;
wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
wire [2*width-1:0] mul_prod;
wire mul_stall;
wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
`ifdef OR1200_MAC_IMPLEMENTED
reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r1;
reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r2;
reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r3;
reg mac_stall_r;
reg [63:0] mac_r;
reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r1;
reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r2;
reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r3;
reg mac_stall_r;
reg [63:0] mac_r;
`else
wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r1;
wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r2;
wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r3;
wire mac_stall_r;
wire [63:0] mac_r;
wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r1;
wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r2;
wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r3;
wire mac_stall_r;
wire [63:0] mac_r;
`endif
wire [width-1:0] x;
wire [width-1:0] y;
wire spr_maclo_we;
wire spr_machi_we;
wire alu_op_div_divu;
wire alu_op_div;
reg div_free;
wire [width-1:0] x;
wire [width-1:0] y;
wire spr_maclo_we;
wire spr_machi_we;
wire alu_op_div;
wire alu_op_udiv;
wire alu_op_sdiv;
reg div_free;
wire div_stall;
`ifdef OR1200_DIV_IMPLEMENTED
wire [width-1:0] div_tmp;
reg [5:0] div_cntr;
`ifdef OR1200_DIV_SERIAL
reg [2*width-1:0] div_quot_r;
wire [width-1:0] div_tmp;
reg [5:0] div_cntr;
`else
reg [width-1:0] div_quot_r;
reg [width-1:0] div_quot_generic;
`endif
`endif
 
//
// Combinatorial logic
//
//
// Combinatorial logic
//
`ifdef OR1200_MULT_IMPLEMENTED
assign alu_op_smul = (alu_op == `OR1200_ALUOP_MUL);
assign alu_op_umul = (alu_op == `OR1200_ALUOP_MULU);
assign alu_op_mul = alu_op_smul | alu_op_umul;
`endif
`ifdef OR1200_MAC_IMPLEMENTED
assign spr_maclo_we = spr_cs & spr_write & spr_addr[`OR1200_MAC_ADDR];
assign spr_machi_we = spr_cs & spr_write & !spr_addr[`OR1200_MAC_ADDR];
assign spr_dat_o = spr_addr[`OR1200_MAC_ADDR] ? mac_r[31:0] : mac_r[63:32];
assign spr_maclo_we = spr_cs & spr_write & spr_addr[`OR1200_MAC_ADDR];
assign spr_machi_we = spr_cs & spr_write & !spr_addr[`OR1200_MAC_ADDR];
assign spr_dat_o = spr_addr[`OR1200_MAC_ADDR] ? mac_r[31:0] : mac_r[63:32];
`else
assign spr_maclo_we = 1'b0;
assign spr_machi_we = 1'b0;
assign spr_dat_o = 32'h0000_0000;
assign spr_maclo_we = 1'b0;
assign spr_machi_we = 1'b0;
assign spr_dat_o = 32'h0000_0000;
`endif
`ifdef OR1200_LOWPWR_MULT
assign x = (alu_op_div & a[31]) ? ~a + 1'b1 :
alu_op_div_divu | (alu_op == `OR1200_ALUOP_MUL) | (|mac_op) ?
a : 32'h0000_0000;
assign y = (alu_op_div & b[31]) ? ~b + 1'b1 :
alu_op_div_divu | (alu_op == `OR1200_ALUOP_MUL) | (|mac_op) ?
b : 32'h0000_0000;
`else
assign x = alu_op_div & a[31] ? ~a + 32'b1 : a;
assign y = alu_op_div & b[31] ? ~b + 32'b1 : b;
`endif
`ifdef OR1200_DIV_IMPLEMENTED
assign alu_op_div = (alu_op == `OR1200_ALUOP_DIV);
assign alu_op_div_divu = alu_op_div | (alu_op == `OR1200_ALUOP_DIVU);
assign div_tmp = mul_prod_r[63:32] - y;
assign alu_op_sdiv = (alu_op == `OR1200_ALUOP_DIV);
assign alu_op_udiv = (alu_op == `OR1200_ALUOP_DIVU);
assign alu_op_div = alu_op_sdiv | alu_op_udiv;
`else
assign alu_op_div = 1'b0;
assign alu_op_div_divu = 1'b0;
assign alu_op_udiv = 1'b0;
assign alu_op_sdiv = 1'b0;
assign alu_op_div = 1'b0;
`endif
 
`ifdef OR1200_MULT_IMPLEMENTED
assign x = (alu_op_sdiv | alu_op_smul) & a[31] ? ~a + 32'b1 :
alu_op_div | alu_op_mul | (|mac_op) ? a : 32'd0;
assign y = (alu_op_sdiv | alu_op_smul) & b[31] ? ~b + 32'b1 :
alu_op_div | alu_op_mul | (|mac_op) ? b : 32'd0;
 
//
// Select result of current ALU operation to be forwarded
// to next instruction and to WB stage
//
always @*
casez(alu_op) // synopsys parallel_case
`ifdef OR1200_DIV_IMPLEMENTED
`OR1200_ALUOP_DIV: begin
result = a[31] ^ b[31] ? ~mul_prod_r[31:0] + 32'd1 : mul_prod_r[31:0];
end
`OR1200_ALUOP_DIVU,
`endif
`OR1200_ALUOP_MUL: begin
result = mul_prod_r[31:0];
end
default:
//
// Select result of current ALU operation to be forwarded
// to next instruction and to WB stage
//
always @*
casez(alu_op) // synopsys parallel_case
`ifdef OR1200_DIV_IMPLEMENTED
`OR1200_ALUOP_DIV: begin
result = a[31] ^ b[31] ? ~div_quot_r[31:0] + 32'd1 : div_quot_r[31:0];
end
`OR1200_ALUOP_DIVU: begin
result = div_quot_r[31:0];
end
`endif
`ifdef OR1200_MULT_IMPLEMENTED
`OR1200_ALUOP_MUL: begin
result = a[31] ^ b[31] ? ~mul_prod_r[31:0] + 32'd1 : mul_prod_r[31:0];
end
`OR1200_ALUOP_MULU: begin
result = mul_prod_r[31:0];
end
`endif
default:
`ifdef OR1200_MAC_IMPLEMENTED
`ifdef OR1200_MAC_SHIFTBY
result = mac_r[`OR1200_MAC_SHIFTBY+31:`OR1200_MAC_SHIFTBY];
result = mac_r[`OR1200_MAC_SHIFTBY+31:`OR1200_MAC_SHIFTBY];
`else
result = mac_r[31:0];
result = mac_r[31:0];
`endif
endcase
`else
result = {width{1'b0}};
`endif
endcase
 
`ifdef OR1200_MULT_IMPLEMENTED
`ifdef OR1200_MULT_SERIAL
 
always @(`OR1200_RST_EVENT rst or posedge clk)
if (rst == `OR1200_RST_VALUE) begin
mul_prod_r <= 64'h0000_0000_0000_0000;
serial_mul_cnt <= 6'd0;
mul_free <= 1'b1;
end
else if (|serial_mul_cnt) begin
serial_mul_cnt <= serial_mul_cnt - 6'd1;
if (mul_prod_r[0])
mul_prod_r[(width*2)-1:width-1] <= mul_prod_r[(width*2)-1:width] + x;
else
mul_prod_r[(width*2)-1:width-1] <= {1'b0,mul_prod_r[(width*2)-1:
width]};
mul_prod_r[width-2:0] <= mul_prod_r[width-1:1];
end
else if (alu_op_mul && mul_free) begin
mul_prod_r <= {32'd0, y};
mul_free <= 0;
serial_mul_cnt <= 6'b10_0000;
end
else if (!ex_freeze | mul_free) begin
mul_free <= 1'b1;
end
 
assign mul_stall = (|serial_mul_cnt);
`else
//
// Instantiation of the multiplier
//
`ifdef OR1200_ASIC_MULTP2_32X32
or1200_amultp2_32x32 or1200_amultp2_32x32(
.X(x),
.Y(y),
.RST(rst),
.CLK(clk),
.P(mul_prod)
);
`else // OR1200_ASIC_MULTP2_32X32
or1200_gmultp2_32x32 or1200_gmultp2_32x32(
.X(x),
.Y(y),
.RST(rst),
.CLK(clk),
.P(mul_prod)
);
`endif // OR1200_ASIC_MULTP2_32X32
`ifdef OR1200_ASIC_MULTP2_32X32
or1200_amultp2_32x32 or1200_amultp2_32x32(
.X(x),
.Y(y),
.RST(rst),
.CLK(clk),
.P(mul_prod)
);
`else // OR1200_ASIC_MULTP2_32X32
or1200_gmultp2_32x32 or1200_gmultp2_32x32(
.X(x),
.Y(y),
.RST(rst),
.CLK(clk),
.P(mul_prod)
);
`endif // OR1200_ASIC_MULTP2_32X32
//
// Registered output from the multiplier
//
always @(`OR1200_RST_EVENT rst or posedge clk)
if (rst == `OR1200_RST_VALUE) begin
mul_prod_r <= 64'h0000_0000_0000_0000;
end
else begin
mul_prod_r <= mul_prod[63:0];
end
 
//
// Registered output from the multiplier and
// an optional divider
//
always @(`OR1200_RST_EVENT rst or posedge clk)
if (rst == `OR1200_RST_VALUE) begin
mul_prod_r <= 64'h0000_0000_0000_0000;
div_free <= 1'b1;
`ifdef OR1200_DIV_IMPLEMENTED
div_cntr <= 6'b00_0000;
`endif
end
`ifdef OR1200_DIV_IMPLEMENTED
else if (|div_cntr) begin
if (div_tmp[31])
mul_prod_r <= {mul_prod_r[62:0], 1'b0};
else
mul_prod_r <= {div_tmp[30:0], mul_prod_r[31:0], 1'b1};
div_cntr <= div_cntr - 6'd1;
end
else if (alu_op_div_divu && div_free) begin
mul_prod_r <= {31'b0, x[31:0], 1'b0};
div_cntr <= 6'b10_0000;
div_free <= 1'b0;
end
`endif // OR1200_DIV_IMPLEMENTED
else if (div_free | !ex_freeze) begin
mul_prod_r <= mul_prod[63:0];
div_free <= 1'b1;
end
 
assign mul_stall = 0;
`endif // !`ifdef OR1200_MULT_SERIAL
`else // OR1200_MULT_IMPLEMENTED
assign result = {width{1'b0}};
assign mul_prod = {2*width{1'b0}};
assign mul_prod_r = {2*width{1'b0}};
assign mul_prod = {2*width{1'b0}};
assign mul_prod_r = {2*width{1'b0}};
assign mul_stall = 0;
`endif // OR1200_MULT_IMPLEMENTED
 
`ifdef OR1200_MAC_IMPLEMENTED
// Signal to indicate when we should check for new MAC op
reg ex_freeze_r;
// Signal to indicate when we should check for new MAC op
reg ex_freeze_r;
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
ex_freeze_r <= 1'b1;
else
ex_freeze_r <= ex_freeze;
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
ex_freeze_r <= 1'b1;
else
ex_freeze_r <= ex_freeze;
//
// Propagation of l.mac opcode, only register it for one cycle
//
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
mac_op_r1 <= `OR1200_MACOP_WIDTH'b0;
else
mac_op_r1 <= !ex_freeze_r ? mac_op : `OR1200_MACOP_WIDTH'b0;
//
// Propagation of l.mac opcode, only register it for one cycle
//
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
mac_op_r1 <= `OR1200_MACOP_WIDTH'b0;
else
mac_op_r1 <= !ex_freeze_r ? mac_op : `OR1200_MACOP_WIDTH'b0;
 
//
// Propagation of l.mac opcode
//
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
mac_op_r2 <= `OR1200_MACOP_WIDTH'b0;
else
mac_op_r2 <= mac_op_r1;
//
// Propagation of l.mac opcode
//
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
mac_op_r2 <= `OR1200_MACOP_WIDTH'b0;
else
mac_op_r2 <= mac_op_r1;
 
//
// Propagation of l.mac opcode
//
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
mac_op_r3 <= `OR1200_MACOP_WIDTH'b0;
else
mac_op_r3 <= mac_op_r2;
//
// Propagation of l.mac opcode
//
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
mac_op_r3 <= `OR1200_MACOP_WIDTH'b0;
else
mac_op_r3 <= mac_op_r2;
 
//
// Implementation of MAC
//
always @(`OR1200_RST_EVENT rst or posedge clk)
if (rst == `OR1200_RST_VALUE)
mac_r <= 64'h0000_0000_0000_0000;
`ifdef OR1200_MAC_SPR_WE
else if (spr_maclo_we)
mac_r[31:0] <= spr_dat_i;
else if (spr_machi_we)
mac_r[63:32] <= spr_dat_i;
`endif
else if (mac_op_r3 == `OR1200_MACOP_MAC)
mac_r <= mac_r + mul_prod_r;
else if (mac_op_r3 == `OR1200_MACOP_MSB)
mac_r <= mac_r - mul_prod_r;
else if (macrc_op && !ex_freeze)
mac_r <= 64'h0000_0000_0000_0000;
//
// Implementation of MAC
//
always @(`OR1200_RST_EVENT rst or posedge clk)
if (rst == `OR1200_RST_VALUE)
mac_r <= 64'h0000_0000_0000_0000;
`ifdef OR1200_MAC_SPR_WE
else if (spr_maclo_we)
mac_r[31:0] <= spr_dat_i;
else if (spr_machi_we)
mac_r[63:32] <= spr_dat_i;
`endif
else if (mac_op_r3 == `OR1200_MACOP_MAC)
mac_r <= mac_r + mul_prod_r;
else if (mac_op_r3 == `OR1200_MACOP_MSB)
mac_r <= mac_r - mul_prod_r;
else if (macrc_op && !ex_freeze)
mac_r <= 64'h0000_0000_0000_0000;
 
//
// Stall CPU if l.macrc is in ID and MAC still has to process l.mac instructions
// in EX stage (e.g. inside multiplier)
// This stall signal is also used by the divider.
//
always @(`OR1200_RST_EVENT rst or posedge clk)
if (rst == `OR1200_RST_VALUE)
mac_stall_r <= 1'b0;
else
mac_stall_r <= (|mac_op | (|mac_op_r1) | (|mac_op_r2)) & (id_macrc_op | mac_stall_r)
`ifdef OR1200_DIV_IMPLEMENTED
| (|div_cntr)
`endif
;
//
// Stall CPU if l.macrc is in ID and MAC still has to process l.mac
// instructions in EX stage (e.g. inside multiplier)
// This stall signal is also used by the divider.
//
always @(`OR1200_RST_EVENT rst or posedge clk)
if (rst == `OR1200_RST_VALUE)
mac_stall_r <= 1'b0;
else
mac_stall_r <= (|mac_op | (|mac_op_r1) | (|mac_op_r2)) &
(id_macrc_op | mac_stall_r);
`else // OR1200_MAC_IMPLEMENTED
assign mac_stall_r = 1'b0;
assign mac_r = {2*width{1'b0}};
assign mac_op_r1 = `OR1200_MACOP_WIDTH'b0;
assign mac_op_r2 = `OR1200_MACOP_WIDTH'b0;
assign mac_op_r3 = `OR1200_MACOP_WIDTH'b0;
assign mac_stall_r = 1'b0;
assign mac_r = {2*width{1'b0}};
assign mac_op_r1 = `OR1200_MACOP_WIDTH'b0;
assign mac_op_r2 = `OR1200_MACOP_WIDTH'b0;
assign mac_op_r3 = `OR1200_MACOP_WIDTH'b0;
`endif // OR1200_MAC_IMPLEMENTED
 
`ifdef OR1200_DIV_IMPLEMENTED
//
// Serial division
//
`ifdef OR1200_DIV_SERIAL
assign div_tmp = div_quot_r[63:32] - y;
always @(`OR1200_RST_EVENT rst or posedge clk)
if (rst == `OR1200_RST_VALUE) begin
div_quot_r <= 64'h0000_0000_0000_0000;
div_free <= 1'b1;
div_cntr <= 6'b00_0000;
end
else if (|div_cntr) begin
if (div_tmp[31])
div_quot_r <= {div_quot_r[62:0], 1'b0};
else
div_quot_r <= {div_tmp[30:0], div_quot_r[31:0], 1'b1};
div_cntr <= div_cntr - 6'd1;
end
else if (alu_op_div && div_free) begin
div_quot_r <= {31'b0, x[31:0], 1'b0};
div_cntr <= 6'b10_0000;
div_free <= 1'b0;
end
else if (div_free | !ex_freeze) begin
//div_quot_r <= div_quot[63:0];
div_free <= 1'b1;
end
 
assign div_stall = (|div_cntr);
 
 
`else // !`ifdef OR1200_DIV_SERIAL
 
// Full divider
// TODO: Perhaps provide module that can be technology dependent.
always @(`OR1200_RST_EVENT rst or posedge clk) begin
if (rst == `OR1200_RST_VALUE) begin
div_quot_r <= 32'd0;
div_quot_generic <= 32'd0;
end
else begin
if (alu_op_udiv & !(|y)) // unsigned divide by 0 - force to MAX
div_quot_generic[31:0] <= 32'hffff_ffff;
else if (alu_op_div)
div_quot_generic[31:0] <= x / y;
end
 
// Add any additional statges of pipelining as required here. Ensure
// ends with div_quot_r.
// Then add logic to ensure div_stall stays high for as long as the
// division should take.
div_quot_r[31:0] <= div_quot_generic;
 
end
assign div_stall = 0;
`endif
 
`else // !`ifdef OR1200_DIV_IMPLEMENTED
 
assign div_stall = 0;
 
`endif // !`ifdef OR1200_DIV_IMPLEMENTED
//
// Stall output
//
assign mult_mac_stall = mac_stall_r | div_stall | mul_stall;
endmodule
/sim/bin/Makefile
392,6 → 392,15
# Now copy the file into the Verilated model build path
$(Q)cp $(SW_DIR)/lib/include/orpsoc-defines.h $(SIM_VLT_DIR)
 
# Create test software disassembly
 
sw-dis: $(TEST_SW_DIR)/$(TEST).dis
$(Q)cp -v $< .
 
$(TEST_SW_DIR)/$(TEST).dis:
$(Q)$(MAKE) -C $(TEST_SW_DIR) $(TEST).dis
 
 
#
# Cleaning rules
#
/sw/tests/ethmac/board/ethmac-ping.c
70,6 → 70,8
#define DEST_IP_BYTES 0xc0,0xa8,0x01,0x08 // 192 .168.1.8
//#define DEST_IP_BYTES 0xac,0x1e,0x0,0x01 // 172.30.0.1
 
#define BCAST_DEST_IP_BYTES 0xc0,0xa8,0x01,0xff // 192 .168.1.255
 
/* Functions in this file */
void ethmac_setup(void);
void oeth_printregs(void);
863,10 → 865,7
OETH_INT_MASK_BUSY |
OETH_INT_MASK_TXC |
OETH_INT_MASK_RXC;
#ifndef RTLSIM
printf("\nafter config\n\n");
oeth_printregs();
#endif
 
// Buffer setup stuff
volatile oeth_bd *tx_bd, *rx_bd;
int i,j,k;
1132,9 → 1131,9
0x00,
0x40,
0x01,
0xee,0xf5,
0xb5,0x8f,
OUR_IP_BYTES, /* Source IP */
0xc0,0xa8,0x64,0xff, /* Dest. IP */
BCAST_DEST_IP_BYTES, /* Dest. IP */
/* ICMP Message body */
0x08,0x00,0x7d,0x65,0xa7,0x20,0x00,0x01,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,
15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,
1900,13 → 1899,13
 
if (c == 's')
tx_packet((void*) ping_packet, 98);
if (c == 'S')
else if (c == 'S')
tx_packet((void*)big_ping_packet, 1514);
if (c == 'h')
else if (c == 'h')
scan_ethphys();
if (c == 'i')
else if (c == 'i')
ethphy_init();
if (c == 'P')
else if (c == 'P')
{
print_packet_contents = print_packet_contents ? 0 : 1;
if (print_packet_contents)
1914,38 → 1913,38
else
printf("Packet dumping disabled\n");
}
if (c == 'p')
else if (c == 'p')
oeth_printregs();
if (c == '0')
else if (c == '0')
scan_ethphy(0);
if (c == '1')
else if (c == '1')
scan_ethphy(1);
if (c == '7')
else if (c == '7')
{
//scan_ethphy(7);
//ethphy_print_status(7);
printf("ext_sr 0x%x\n",eth_mii_read(0x7, 0x1b));
}
if (c == 'r')
else if (c == 'r')
{
ethphy_reset(7);
printf("PHY reset\n");
}
if (c == 'R')
else if (c == 'R')
{
//oeth_reset_tx_bd_pointer();
ethmac_setup();
printf("MAC reset\n");
}
if (c == 'n')
else if (c == 'n')
ethphy_reneg(7);
if (c == 'N')
else if (c == 'N')
ethphy_set_autoneg(7);
if (c == 'm')
else if (c == 'm')
ethmac_togglehugen();
if (c == 't')
else if (c == 't')
ethphy_set_10mbit(0);
if (c == 'w')
else if (c == 'w')
{
// Play with HWCFG mode of Alaska 88e1111 Phy
c = uart_getc(DEFAULT_UART);
1968,12 → 1967,17
eth_mii_write(0x7, MII_M1111_PHY_EXT_SR, ext_sr);
printf("ext_sr updated to - 0x%x\n",eth_mii_read(0x7, MII_M1111_PHY_EXT_SR));
}
if ( c == 'b' )
else if ( c == 'b' )
{
printf("\n\t---\n");
oeth_dump_bds();
printf("\t---\n");
}
else if ( c == 'B' )
{
tx_packet((void*) broadcast_ping_packet, 298);
}
 
}
 
/sw/tests/or1200/sim/or1200-div.c
11,7 → 11,6
*/
 
#include "cpu-utils.h"
#include "uart.h"
#include "printf.h"
 
static int sdiv_errors, udiv_errors;
19,7 → 18,7
#define VERBOSE_TESTS 0
 
// Make this bigger when running on FPGA target. For simulation it's enough.
#define NUM_TESTS 200
#define NUM_TESTS 2000
 
int
or1k_div(int dividend, int divisor)
42,16 → 41,17
check_div(int dividend, int divisor, int expected_result)
{
#if VERBOSE_TESTS
printf("l.div 0x%.8x / 0x%.8x = 0x%.8x : ", dividend, divisor,
printf("l.div 0x%.8x / 0x%.8x = (SW) 0x%.8x : ", dividend, divisor,
expected_result);
#endif
int result = or1k_div(dividend, divisor);
report(result);
if ( result != expected_result)
{
printf("l.div 0x%.8x / 0x%.8x = 0x%.8x : ", dividend, divisor,
printf("l.div 0x%.8x / 0x%.8x = (SW) 0x%.8x : ", dividend, divisor,
expected_result);
printf("FAIL - 0x%.8x\n",result);
printf("(HW) 0x%.8x - MISMATCH\n",result);
sdiv_errors++;
}
#if VERBOSE_TESTS
66,17 → 66,18
unsigned int expected_result)
{
#if VERBOSE_TESTS
printf("l.divu 0x%.8x / 0x%.8x = 0x%.8x : ", dividend, divisor,
printf("l.divu 0x%.8x / 0x%.8x = (SW) 0x%.8x : ", dividend, divisor,
expected_result);
#endif
 
unsigned int result = or1k_div(dividend, divisor);
unsigned int result = or1k_divu(dividend, divisor);
report(result);
if ( result != expected_result)
{
printf("l.divu 0x%.8x / 0x%.8x = 0x%.8x : ", dividend, divisor,
printf("l.divu 0x%.8x / 0x%.8x = (SW) 0x%.8x : ", dividend, divisor,
expected_result);
printf("FAIL - 0x%.8x\n",result);
printf("(HW) 0x%.8x - MISMATCH\n",result);
udiv_errors++;
}
#if VERBOSE_TESTS
137,7 → 138,8
n = rand();
d = rand();
 
report(0x10101010);
 
while ( d >= n )
d >>= (rand() & 0xff);
 
146,9 → 148,11
// Calculate a value that's really smaller than the numerator
while ( d >= ~(n-1) )
d >>= (rand() & 0xff);
 
if (!d) d = 1;
// Processor thinks it's in 2's complement already, so we'll convert
// from the interpreted 2's complement to unsigned for our calculation
expected_result = div_soft(~(n-1), d);
expected_result = div_soft(~(n-1), d);
// Answer will be an unsigned +ve value, but of course it has to be
// negative so convert back to 2's complment negative
expected_result = ~expected_result + 1; // 2's complement
156,17 → 160,35
else
expected_result = div_soft(n, d);
 
/* Report things */
report(n);
report(d);
report(expected_result);
 
/* Signed divide */
check_div(n, d, expected_result);
 
/* Unsigned divide test */
/* Ensure numerator's bit 31 is clear */
n >>= 1;
 
/* If divisor is > numerator, shift it by a random amount */
while ( d >= n )
d >>= (rand() & 0xff);
if (!d) d = 1;
 
expected_result = div_soft(n, d);
 
/* Report things */
report(n);
report(d);
report(expected_result);
/* Unsigned divide */
check_divu(n, d, expected_result);
i++;
//printf("%d\n",i);
 
}
 
/sw/tests/or1200/sim/or1200-mul.c
0,0 → 1,205
/*
Test integer multiply
Use a software multiplication algorithm to compare against hardware
calculated results
 
Julius Baxter, julius@opencores.org
 
*/
 
#include "cpu-utils.h"
#include "printf.h"
 
static int smul_errors, umul_errors;
 
#define VERBOSE_TESTS 0
 
// Make this bigger when running on FPGA target. For simulation it's enough.
#define NUM_TESTS 2000
 
int
or1k_mul(int multiplicant, int multiplier)
{
int result;
asm ("l.mul\t%0,%1,%2" : "=r" (result) : "r" (multiplicant),
"r" (multiplier));
return result;
}
 
unsigned int
or1k_mulu(unsigned int mulidend, unsigned int mulisor)
{
int result;
asm ("l.mulu\t%0,%1,%2" : "=r" (result) : "r" (mulidend), "r" (mulisor));
return result;
}
 
 
void
check_mul(int multiplicand, int multiplier, int expected_result)
{
#if VERBOSE_TESTS
printf("l.mul 0x%.8x * 0x%.8x = (SW) 0x%.8x : ", multiplicand, multiplier,
expected_result);
#endif
int result = or1k_mul(multiplicand, multiplier);
report(result);
if ( result != expected_result)
{
printf("l.mul 0x%.8x * 0x%.8x = (SW) 0x%.8x : ", multiplicand, multiplier,
expected_result);
printf("(HW) 0x%.8x - MISMATCH\n",result);
smul_errors++;
}
#if VERBOSE_TESTS
else
printf("OK\n");
#endif
}
 
void
check_mulu(unsigned int multiplicand, unsigned int multiplier,
unsigned int expected_result)
{
#if VERBOSE_TESTS
printf("l.mulu 0x%.8x * 0x%.8x = (SW) 0x%.8x : ", multiplicand, multiplier,
expected_result);
#endif
 
unsigned int result = or1k_mulu(multiplicand, multiplier);
report(result);
if ( result != expected_result)
{
printf("l.mulu 0x%.8x * 0x%.8x = (SW) 0x%.8x : ", multiplicand, multiplier,
expected_result);
printf("(HW) 0x%.8x - MISMATCH\n",result);
umul_errors++;
}
#if VERBOSE_TESTS
else
printf("OK\n");
#endif
}
 
 
// Software implementation of multiply
unsigned int
mul_soft(unsigned int n, unsigned int d)
{
 
unsigned int m = 0;
//printf("sft: 0x%x 0x%xd\n",n,d);
int i;
for(i=0; i<32; i++)
{
//printf("bit %d: 0x%x\n",i, (((1<<i) & d)));
if ((1<<i) & d)
{
m += (unsigned int) (n << i);
}
}
 
return (unsigned int) m;
}
 
int
main(void)
{
#ifdef _UART_H_
uart_init(DEFAULT_UART);
#endif
umul_errors = 0;
smul_errors = 0;
 
int i;
 
unsigned int n, d;
unsigned int expected_result;
i=0;
n=0;d=0;
while(i < NUM_TESTS)
{
 
n = rand() >> 20;
d = (rand() >> 24);
 
report(0x10101010);
 
if (n&0x10) // Randomly select if we should negate n
{
// 2's complement of n
n = ~n + 1;
}
if (d&0x80) // Randomly select if we should negate d
{
// 2's complement of d
d = ~d + 1;
}
if ((n & 0x80000000) && (d & 0x80000000))
expected_result = mul_soft(~(n-1), ~(d-1));
else if ((n & 0x80000000) && !(d & 0x80000000))
{
expected_result = mul_soft(~(n-1), d);
expected_result = ~expected_result + 1; // 2's complement
}
else if (!(n & 0x80000000) && (d & 0x80000000))
{
expected_result = mul_soft(n, ~(d-1));
expected_result = ~expected_result + 1; // 2's complement
}
else if (!(n & 0x80000000) && !(d & 0x80000000))
expected_result = mul_soft(n, d);
 
 
/* Report things */
report(n);
report(d);
report(expected_result);
 
 
/* Signed mulide */
check_mul(n, d, expected_result);
 
/* Unsigned mulide test */
/* Ensure numerator's bit 31 is clear */
n >>= 1;
 
expected_result = mul_soft(n, d);
 
/* Report things */
report(n);
report(d);
report(expected_result);
/* Unsigned mulide */
check_mulu(n, d, expected_result);
report(i);
i++;
 
}
 
 
printf("Integer multiply check complete\n");
printf("Unsigned:\t%d tests\t %d errors\n",
NUM_TESTS, umul_errors);
printf("Signed:\t\t%d tests\t %d errors\n",
NUM_TESTS, smul_errors);
 
if ((umul_errors > 0) || (smul_errors > 0))
report(0xbaaaaaad);
else
report(0x8000000d);
 
return 0;
}
/boards/actel/ordb1a3pe1500/rtl/verilog/include/or1200_defines.v
360,32 → 360,31
// Implement multiply-and-accumulate
//
// By default MAC is implemented. To
// implement MAC, multiplier needs to be
// implement MAC, multiplier (non-serial) needs to be
// implemented.
//
`define OR1200_MAC_IMPLEMENTED
//`define OR1200_MAC_IMPLEMENTED
 
//
// Implement optional l.div/l.divu instructions
//
// By default divide instructions are not implemented
// to save area and increase clock frequency. or32 C/C++
// compiler can use soft library for division.
// to save area.
//
// To implement divide, both multiplier and MAC needs to be implemented.
//
`define OR1200_DIV_IMPLEMENTED
 
//
// Low power, slower multiplier
// Serial multiplier.
//
// Select between low-power (larger) multiplier
// and faster multiplier. The actual difference
// is only AND logic that prevents distribution
// of operands into the multiplier when instruction
// in execution is not multiply instruction
`define OR1200_MULT_SERIAL
 
//
//`define OR1200_LOWPWR_MULT
// Serial divider.
// Uncomment to use a serial divider, otherwise will
// be a generic parallel implementation.
//
`define OR1200_DIV_SERIAL
 
//
// Implement HW Single Precision FPU
464,8 → 463,8
`define OR1200_ALUOP_SHROT 4'd8
`define OR1200_ALUOP_DIV 4'd9
`define OR1200_ALUOP_DIVU 4'd10
/* Order not specifically defined. */
`define OR1200_ALUOP_IMM 4'd11
`define OR1200_ALUOP_MULU 4'd11
/* Values sent to ALU from decode unit - not strictly defined by ISA */
`define OR1200_ALUOP_MOVHI 4'd12
`define OR1200_ALUOP_COMP 4'd13
`define OR1200_ALUOP_MTSR 4'd14
/boards/xilinx/ml501/rtl/verilog/include/or1200_defines.v
349,6 → 349,7
//
`define OR1200_IMPL_ALU_FFL1
 
 
//
// Implement multiplier
//
360,7 → 361,7
// Implement multiply-and-accumulate
//
// By default MAC is implemented. To
// implement MAC, multiplier needs to be
// implement MAC, multiplier (non-serial) needs to be
// implemented.
//
`define OR1200_MAC_IMPLEMENTED
369,23 → 370,22
// Implement optional l.div/l.divu instructions
//
// By default divide instructions are not implemented
// to save area and increase clock frequency. or32 C/C++
// compiler can use soft library for division.
// to save area.
//
// To implement divide, both multiplier and MAC needs to be implemented.
//
`define OR1200_DIV_IMPLEMENTED
 
//
// Low power, slower multiplier
// Serial multiplier.
//
// Select between low-power (larger) multiplier
// and faster multiplier. The actual difference
// is only AND logic that prevents distribution
// of operands into the multiplier when instruction
// in execution is not multiply instruction
//`define OR1200_MULT_SERIAL
 
//
//`define OR1200_LOWPWR_MULT
// Serial divider.
// Uncomment to use a serial divider, otherwise will
// be a generic parallel implementation.
//
`define OR1200_DIV_SERIAL
 
//
// Implement HW Single Precision FPU
464,7 → 464,8
`define OR1200_ALUOP_SHROT 4'd8
`define OR1200_ALUOP_DIV 4'd9
`define OR1200_ALUOP_DIVU 4'd10
/* Order not specifically defined. */
`define OR1200_ALUOP_MULU 4'd11
/* Values sent to ALU from decode unit - not strictly defined by ISA */
`define OR1200_ALUOP_IMM 4'd11
`define OR1200_ALUOP_MOVHI 4'd12
`define OR1200_ALUOP_COMP 4'd13
/boards/xilinx/ml501/syn/xst/bin/Makefile
40,7 → 40,8
BOARD_DIR ?=$(CUR_DIR)/../../..
PROJECT_ROOT=$(BOARD_DIR)/../../..
 
DESIGN_NAME=orpsoc
DESIGN_NAME ?=orpsoc
RTL_TOP ?=$(DESIGN_NAME)_top
 
SYN_DIR=$(BOARD_DIR)/syn/xst
SYN_RUN_DIR=$(SYN_DIR)/run
220,7 → 221,7
$(Q)echo "run" >> $@
$(Q)echo "-ifn "$(PRJ_FILE) >> $@
$(Q)echo "-ifmt mixed" >> $@
$(Q)echo "-top "$(DESIGN_NAME)"_top" >> $@
$(Q)echo "-top "$(RTL_TOP) >> $@
$(Q)echo "-ofmt NGC" >> $@
$(Q)echo "-ofn "$(NGC_FILE) >> $@
$(Q)echo "-p "$(FPGA_PART) >> $@

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