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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/orpsocv2
    from Rev 435 to Rev 439
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  •

Rev 435 → Rev 439

/bench/sysc/include/OrpsocAccess.h
41,7 → 41,8
// Main memory access class - will change if main memory size or other
// parameters change
//Old ram_wbclass: class Vorpsoc_top_ram_wb_sc_sw__D20_A19_M800000;
class Vorpsoc_top_wb_ram_b3__D20_A17_M800000;
//class Vorpsoc_top_wb_ram_b3__D20_A17_M800000;
class Vorpsoc_top_ram_wb_b3__pi3;
// SoC Arbiter class - will also change if any modifications to bus architecture
//class Vorpsoc_top_wb_conbus_top__pi1;
 
109,7 → 110,8
Vorpsoc_top_or1200_except *or1200_except;
Vorpsoc_top_or1200_sprs *or1200_sprs;
Vorpsoc_top_or1200_dpram *rf_a;
/*Vorpsoc_top_ram_wb_sc_sw*//*Vorpsoc_top_ram_wb_sc_sw__D20_A19_M800000*/ Vorpsoc_top_wb_ram_b3__D20_A17_M800000 *ram_wb_sc_sw;
/*Vorpsoc_top_ram_wb_sc_sw*//*Vorpsoc_top_ram_wb_sc_sw__D20_A19_M800000*/ /*Vorpsoc_top_wb_ram_b3__D20_A17_M800000 *ram_wb_sc_sw;*/
Vorpsoc_top_ram_wb_b3__pi3 *wishbone_ram;
// Arbiter
//Vorpsoc_top_wb_conbus_top__pi1 *wb_arbiter;
 
/bench/sysc/src/OrpsocAccess.cpp
39,13 → 39,10
#include "Vorpsoc_top_or1200_rf.h"
#include "Vorpsoc_top_or1200_dpram.h"
// Need RAM instantiation has parameters after module name
// Includes for wb_ram
//#include "Vorpsoc_top_ram_wb__D20_A19_M800000.h"
//#include "Vorpsoc_top_ram_wb_sc_sw__D20_A19_M800000.h"
// Include for wb_ram_b3
#include "Vorpsoc_top_wb_ram_b3__D20_A17_M800000.h"
// Bus arbiter include - but is for old arbiter, no longer used
//#include "Vorpsoc_top_wb_conbus_top__pi1.h"
// Include for ram_wb
#include "Vorpsoc_top_ram_wb__A20_D20_M800000_MB17.h"
// Include for ram_wb_b3
#include "Vorpsoc_top_ram_wb_b3__pi3.h"
 
//! Constructor for the ORPSoC access class
 
63,7 → 60,8
rf_a = orpsoc_top->v->or1200_top0->or1200_cpu->or1200_rf->rf_a;
// Assign main memory accessor objects
// For old ram_wb: ram_wb_sc_sw = orpsoc_top->v->ram_wb0->ram0;
ram_wb_sc_sw = orpsoc_top->v->wb_ram_b3_0;
//ram_wb_sc_sw = orpsoc_top->v->wb_ram_b3_0;
wishbone_ram = orpsoc_top->v->ram_wb0->ram_wb_b3_0;
 
// Assign arbiter accessor object
//wb_arbiter = orpsoc_top->v->wb_conbus;
200,7 → 198,7
uint32_t
OrpsocAccess::get_mem32 (uint32_t addr)
{
return (ram_wb_sc_sw->get_mem) (addr/4);
return (wishbone_ram->get_mem) (addr/4);
 
} // get_mem32 ()
 
222,7 → 220,7
{
cached_word_addr = addr;
// Convert address to word number here
word = (ram_wb_sc_sw->get_mem) (addr);
word = (wishbone_ram->get_mem) (addr);
cached_word = word;
}
else
255,7 → 253,7
void
OrpsocAccess::set_mem32 (uint32_t addr, uint32_t data)
{
(ram_wb_sc_sw->set_mem) (addr/4, data);
(wishbone_ram->set_mem) (addr/4, data);
 
} // set_mem32 ()
 
264,7 → 262,7
void
OrpsocAccess::do_ram_readmemh (void)
{
(ram_wb_sc_sw->do_readmemh) ();
(wishbone_ram->do_readmemh) ();
 
} // do_ram_readmemh ()
 
/bench/verilog/or1200_monitor.v
455,12 → 455,12
 
 
`ifdef RAM_WB
`define RAM_WB_TOP `DUT_TOP.wb_ram_b3_0
`define RAM_WB_TOP `DUT_TOP.ram_wb0.ram_wb_b3_0
task get_insn_from_wb_ram;
input [31:0] addr;
output [31:0] insn;
begin
insn = `RAM_WB_TOP.mem[addr[31:2]];
insn = `RAM_WB_TOP.get_mem(addr);
end
endtask // get_insn_from_wb_ram
`endif
/rtl/verilog/include/ethmac_defines.v
191,23 → 191,23
`define ETH_TX_1KBYTE_FIFO // 1024 byte TX buffer - uncomment this
 
`ifdef ETH_TX_FULL_PACKET_FIFO
`define ETH_TX_FIFO_CNT_WIDTH 11
`define ETH_TX_FIFO_CNT_WIDTH 9
`define ETH_TX_FIFO_DEPTH 375
`else
`ifdef ETH_TX_1KBYTE_FIFO
`define ETH_TX_FIFO_CNT_WIDTH 9
`define ETH_TX_FIFO_CNT_WIDTH 8
`define ETH_TX_FIFO_DEPTH 256
`else
`ifdef ETH_TX_512BYTE_FIFO
`define ETH_TX_FIFO_CNT_WIDTH 8
`define ETH_TX_FIFO_CNT_WIDTH 7
`define ETH_TX_FIFO_DEPTH 128
`else
`ifdef ETH_TX_256BYTE_FIFO
`define ETH_TX_FIFO_CNT_WIDTH 7
`define ETH_TX_FIFO_CNT_WIDTH 6
`define ETH_TX_FIFO_DEPTH 64
`else
// Default is 64 bytes
`define ETH_TX_FIFO_CNT_WIDTH 5
`define ETH_TX_FIFO_CNT_WIDTH 4
`define ETH_TX_FIFO_DEPTH 16
`endif
`endif
217,15 → 217,15
 
 
// Settings for RX FIFO
`define ETH_RX_FIFO_CNT_WIDTH 9
`define ETH_RX_FIFO_CNT_WIDTH 8
`define ETH_RX_FIFO_DEPTH 256
//`define ETH_RX_FIFO_CNT_WIDTH 8
//`define ETH_RX_FIFO_CNT_WIDTH 7
//`define ETH_RX_FIFO_DEPTH 128
//`define ETH_RX_FIFO_CNT_WIDTH 7
//`define ETH_RX_FIFO_CNT_WIDTH 6
//`define ETH_RX_FIFO_DEPTH 64
//`define ETH_RX_FIFO_CNT_WIDTH 6
//`define ETH_RX_FIFO_CNT_WIDTH 5
//`define ETH_RX_FIFO_DEPTH 32
//`define ETH_RX_FIFO_CNT_WIDTH 5
//`define ETH_RX_FIFO_CNT_WIDTH 4
//`define ETH_RX_FIFO_DEPTH 16
 
`define ETH_RX_FIFO_DATA_WIDTH 32
/rtl/verilog/orpsoc_top/orpsoc_top.v
695,117 → 695,58
//
////////////////////////////////////////////////////////////////////////
 
parameter wb_ram_dat_width = 32;
parameter wb_ram_adr_width = 23;
//parameter ram_wb_mem_size = 2097152; // 8MB
parameter wb_ram_mem_size = 8388608; // 32MB -- for linux test
 
// Arbiter logic for sharing the RAM between 2 masters
// This should probably not be in the top-level module!
// Bus to WB B3 RAM
wire [wb_ram_adr_width-1:0] wb_ram_adr_i;
wire [1:0] wb_ram_bte_i;
wire [2:0] wb_ram_cti_i;
wire wb_ram_cyc_i;
wire [wb_ram_dat_width-1:0] wb_ram_dat_i;
wire [3:0] wb_ram_sel_i;
wire wb_ram_stb_i;
wire wb_ram_we_i;
wire wb_ram_ack_o;
wire wb_ram_err_o;
wire wb_ram_rty_o;
wire [wb_ram_dat_width-1:0] wb_ram_dat_o;
reg [1:0] wb_ram_mast_select;
reg [1:0] wb_ram_last_selected;
wire wb_ram_arb_for_dbus,
wb_ram_arb_for_ibus;
ram_wb ram_wb0
(
// Wishbone slave interface 0
.wbm0_dat_i (wbs_i_mc0_dat_i),
.wbm0_adr_i (wbs_i_mc0_adr_i),
.wbm0_sel_i (wbs_i_mc0_sel_i),
.wbm0_cti_i (wbs_i_mc0_cti_i),
.wbm0_bte_i (wbs_i_mc0_bte_i),
.wbm0_we_i (wbs_i_mc0_we_i ),
.wbm0_cyc_i (wbs_i_mc0_cyc_i),
.wbm0_stb_i (wbs_i_mc0_stb_i),
.wbm0_dat_o (wbs_i_mc0_dat_o),
.wbm0_ack_o (wbs_i_mc0_ack_o),
.wbm0_err_o (wbs_i_mc0_err_o),
.wbm0_rty_o (wbs_i_mc0_rty_o),
// Wishbone slave interface 1
.wbm1_dat_i (wbs_d_mc0_dat_i),
.wbm1_adr_i (wbs_d_mc0_adr_i),
.wbm1_sel_i (wbs_d_mc0_sel_i),
.wbm1_cti_i (wbs_d_mc0_cti_i),
.wbm1_bte_i (wbs_d_mc0_bte_i),
.wbm1_we_i (wbs_d_mc0_we_i ),
.wbm1_cyc_i (wbs_d_mc0_cyc_i),
.wbm1_stb_i (wbs_d_mc0_stb_i),
.wbm1_dat_o (wbs_d_mc0_dat_o),
.wbm1_ack_o (wbs_d_mc0_ack_o),
.wbm1_err_o (wbs_d_mc0_err_o),
.wbm1_rty_o (wbs_d_mc0_rty_o),
// Wishbone slave interface 2
.wbm2_dat_i (0),
.wbm2_adr_i (0),
.wbm2_sel_i (0),
.wbm2_cti_i (0),
.wbm2_bte_i (0),
.wbm2_we_i (0),
.wbm2_cyc_i (0),
.wbm2_stb_i (0),
.wbm2_dat_o (),
.wbm2_ack_o (),
.wbm2_err_o (),
.wbm2_rty_o (),
// Clock, reset
.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst));
 
// Wires allowing selection of new input
assign wb_ram_arb_for_dbus = (wb_ram_last_selected[1] | !wbs_i_mc0_cyc_i) &
!(|wb_ram_mast_select);
assign wb_ram_arb_for_ibus = (wb_ram_last_selected[0] | !wbs_d_mc0_cyc_i) &
!(|wb_ram_mast_select);
// Master select logic
always @(posedge wb_rst or posedge wb_clk)
if (wb_rst)
wb_ram_mast_select <= 0;
else if ((wb_ram_mast_select[0] & !wbs_d_mc0_cyc_i) |
(wb_ram_mast_select[1] & !wbs_i_mc0_cyc_i))
wb_ram_mast_select <= 0;
else if (!(&wb_ram_mast_select) & wbs_d_mc0_cyc_i & wb_ram_arb_for_dbus)
wb_ram_mast_select <= 2'b01;
else if (!(&wb_ram_mast_select) & wbs_i_mc0_cyc_i & wb_ram_arb_for_ibus)
wb_ram_mast_select <= 2'b10;
always @(posedge wb_rst or posedge wb_clk)
if (wb_rst)
wb_ram_last_selected <= 0;
else if (!(&wb_ram_mast_select) & wbs_d_mc0_cyc_i & wb_ram_arb_for_dbus)
wb_ram_last_selected <= 2'b01;
else if (!(&wb_ram_mast_select) & wbs_i_mc0_cyc_i & wb_ram_arb_for_ibus)
wb_ram_last_selected <= 2'b10;
// Mux input signals to RAM (default to wbs_d_mc0)
assign wb_ram_adr_i = (wb_ram_mast_select[1]) ?
wbs_i_mc0_adr_i[wb_ram_adr_width-1:0] :
(wb_ram_mast_select[0]) ?
wbs_d_mc0_adr_i[wb_ram_adr_width-1:0] : 0;
assign wb_ram_bte_i = (wb_ram_mast_select[1]) ? wbs_i_mc0_bte_i :
(wb_ram_mast_select[0]) ? wbs_d_mc0_bte_i : 0;
assign wb_ram_cti_i = (wb_ram_mast_select[1]) ? wbs_i_mc0_cti_i :
(wb_ram_mast_select[0]) ? wbs_d_mc0_cti_i : 0;
assign wb_ram_cyc_i = (wb_ram_mast_select[1]) ? wbs_i_mc0_cyc_i :
(wb_ram_mast_select[0]) ? wbs_d_mc0_cyc_i : 0;
assign wb_ram_dat_i = (wb_ram_mast_select[1]) ? wbs_i_mc0_dat_i :
(wb_ram_mast_select[0]) ? wbs_d_mc0_dat_i : 0;
assign wb_ram_sel_i = (wb_ram_mast_select[1]) ? wbs_i_mc0_sel_i :
(wb_ram_mast_select[0]) ? wbs_d_mc0_sel_i : 0;
assign wb_ram_stb_i = (wb_ram_mast_select[1]) ? wbs_i_mc0_stb_i :
(wb_ram_mast_select[0]) ? wbs_d_mc0_stb_i : 0;
assign wb_ram_we_i = (wb_ram_mast_select[1]) ? wbs_i_mc0_we_i :
(wb_ram_mast_select[0]) ? wbs_d_mc0_we_i : 0;
defparam ram_wb0.aw = wb_aw;
defparam ram_wb0.dw = wb_dw;
 
// Output from RAM, gate the ACK, ERR, RTY signals appropriately
assign wbs_d_mc0_dat_o = wb_ram_dat_o;
assign wbs_d_mc0_ack_o = wb_ram_ack_o & wb_ram_mast_select[0];
assign wbs_d_mc0_err_o = wb_ram_err_o & wb_ram_mast_select[0];
assign wbs_d_mc0_rty_o = wb_ram_rty_o & wb_ram_mast_select[0];
 
assign wbs_i_mc0_dat_o = wb_ram_dat_o;
assign wbs_i_mc0_ack_o = wb_ram_ack_o & wb_ram_mast_select[1];
assign wbs_i_mc0_err_o = wb_ram_err_o & wb_ram_mast_select[1];
assign wbs_i_mc0_rty_o = wb_ram_rty_o & wb_ram_mast_select[1];
 
defparam ram_wb0.mem_size_bytes = (8192*1024); // 8MB
defparam ram_wb0.mem_adr_width = 23; // log2(8192*1024)
// Wishbone B3 RAM
wb_ram_b3
#(
.dw(wb_ram_dat_width),
.aw(wb_ram_adr_width),
.mem_size(wb_ram_mem_size)
)
wb_ram_b3_0
(
// Outputs
.wb_ack_o (wb_ram_ack_o),
.wb_err_o (wb_ram_err_o),
.wb_rty_o (wb_ram_rty_o),
.wb_dat_o (wb_ram_dat_o),
// Inputs
.wb_adr_i (wb_ram_adr_i),
.wb_bte_i (wb_ram_bte_i),
.wb_cti_i (wb_ram_cti_i),
.wb_cyc_i (wb_ram_cyc_i),
.wb_dat_i (wb_ram_dat_i),
.wb_sel_i (wb_ram_sel_i),
.wb_stb_i (wb_ram_stb_i),
.wb_we_i (wb_ram_we_i),
.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst));
////////////////////////////////////////////////////////////////////////
`endif
/rtl/verilog/ethmac/eth_spram_256x32.v
76,7 → 76,7
 
module eth_spram_256x32(
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, do
clk, rst, ce, we, oe, addr, di, dato
 
`ifdef ETH_BIST
,
101,7 → 101,7
input oe; // Output enable input, active high
input [7:0] addr; // address bus inputs
input [31:0] di; // input data bus
output [31:0] do; // output data bus
output [31:0] dato; // output data bus
 
`ifdef ETH_BIST
136,7 → 136,7
 
RAMB4_S8 ram0
(
.DO (do[7:0]),
.DO (dato[7:0]),
.ADDR ({1'b0, addr}),
.DI (di[7:0]),
.EN (ce),
147,7 → 147,7
 
RAMB4_S8 ram1
(
.DO (do[15:8]),
.DO (dato[15:8]),
.ADDR ({1'b0, addr}),
.DI (di[15:8]),
.EN (ce),
158,7 → 158,7
 
RAMB4_S8 ram2
(
.DO (do[23:16]),
.DO (dato[23:16]),
.ADDR ({1'b0, addr}),
.DI (di[23:16]),
.EN (ce),
169,7 → 169,7
 
RAMB4_S8 ram3
(
.DO (do[31:24]),
.DO (dato[31:24]),
.ADDR ({1'b0, addr}),
.DI (di[31:24]),
.EN (ce),
194,7 → 194,7
.OEN (!oe),
.ADR (addr),
.DI (di),
.DOUT (do)
.DOUT (dato)
 
`ifdef ETH_BIST
,
222,7 → 222,7
.OEN (!oe),
.A (addr),
.D (di),
.Q (do)
.Q (dato)
 
`ifdef ETH_BIST
,
242,7 → 242,7
.wren (ce & we),
.clock (clk),
.data (di),
.q (do)
.q (dato)
); //exemplar attribute altera_spram_256x32_inst NOOPT TRUE
 
`else // !ETH_ALTERA_ALTSYNCRAM
268,7 → 268,7
// Data output drivers
//
//assign do = (oe & ce) ? q : {32{1'bz}};
assign do = (oe & ce) ? q : {32{1'bx}};
assign dato = (oe & ce) ? q : {32{1'bx}};
 
//
// RAM read and write
321,7 → 321,7
input [7:0] finish;
integer rnum;
begin
for (rnum=start;rnum<=finish;rnum=rnum+1)
for (rnum={24'd0,start};rnum<={24'd0,finish};rnum=rnum+1)
$display("Addr %h = %0h %0h %0h %0h",rnum,mem3[rnum],mem2[rnum],mem1[rnum],mem0[rnum]);
end
endtask
/rtl/verilog/ethmac/eth_shiftreg.v
118,12 → 118,14
begin
if(|ByteSelect)
begin
/* verilator lint_off CASEINCOMPLETE */
case (ByteSelect[3:0]) // synopsys parallel_case full_case
4'h1 : ShiftReg[7:0] <= {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};
4'h2 : ShiftReg[7:0] <= {Fiad[0], Rgad[4:0], 2'b10};
4'h4 : ShiftReg[7:0] <= CtrlData[15:8];
4'h8 : ShiftReg[7:0] <= CtrlData[7:0];
endcase
endcase // case (ByteSelect[3:0])
/* verilator lint_on CASEINCOMPLETE */
end
else
begin
/rtl/verilog/ethmac/eth_rxethmac.v
39,339 → 39,332
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.12 2004/04/26 15:26:23 igorm
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
// previous update of the core.
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
// register. (thanks to Mathias and Torbjorn)
// - Multicast reception was fixed. Thanks to Ulrich Gries
//
// Revision 1.11 2004/03/17 09:32:15 igorm
// Multicast detection fixed. Only the LSB of the first byte is checked.
//
// Revision 1.10 2002/11/22 01:57:06 mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
//
// Revision 1.9 2002/11/19 17:35:35 mohor
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
// that a frame was received because of the promiscous mode.
//
// Revision 1.8 2002/02/16 07:15:27 mohor
// Testbench fixed, code simplified, unused signals removed.
//
// Revision 1.7 2002/02/15 13:44:28 mohor
// RxAbort is an output. No need to have is declared as wire.
//
// Revision 1.6 2002/02/15 11:17:48 mohor
// File format changed.
//
// Revision 1.5 2002/02/14 20:48:43 billditt
// Addition of new module eth_addrcheck.v
//
// Revision 1.4 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.3 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.1 2001/06/27 21:26:19 mohor
// Initial release of the RxEthMAC module.
//
//
//
//
//
 
`include "timescale.v"
 
 
module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG, HugEn, DlyCrcEn,
RxData, RxValid, RxStartFrm, RxEndFrm, ByteCnt, ByteCntEq0, ByteCntGreat2,
ByteCntMaxFrame, CrcError, StateIdle, StatePreamble, StateSFD, StateData,
MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort, AddressMiss, PassAll, ControlFrmAddressOK
);
module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG,
HugEn, DlyCrcEn, RxData, RxValid, RxStartFrm, RxEndFrm,
ByteCnt, ByteCntEq0, ByteCntGreat2, ByteCntMaxFrame,
CrcError, StateIdle, StatePreamble, StateSFD, StateData,
MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort, AddressMiss,
PassAll, ControlFrmAddressOK
);
 
parameter Tp = 1;
input MRxClk;
input MRxDV;
input [3:0] MRxD;
input Transmitting;
input HugEn;
input DlyCrcEn;
input [15:0] MaxFL;
input r_IFG;
input Reset;
input [47:0] MAC; // Station Address
input r_Bro; // broadcast disable
input r_Pro; // promiscuous enable
input [31:0] r_HASH0; // lower 4 bytes Hash Table
input [31:0] r_HASH1; // upper 4 bytes Hash Table
input PassAll;
input ControlFrmAddressOK;
 
output [7:0] RxData;
output RxValid;
output RxStartFrm;
output RxEndFrm;
output [15:0] ByteCnt;
output ByteCntEq0;
output ByteCntGreat2;
output ByteCntMaxFrame;
output CrcError;
output StateIdle;
output StatePreamble;
output StateSFD;
output [1:0] StateData;
output RxAbort;
output AddressMiss;
 
reg [7:0] RxData;
reg RxValid;
reg RxStartFrm;
reg RxEndFrm;
reg Broadcast;
reg Multicast;
reg [5:0] CrcHash;
reg CrcHashGood;
reg DelayData;
reg [7:0] LatchedByte;
reg [7:0] RxData_d;
reg RxValid_d;
reg RxStartFrm_d;
reg RxEndFrm_d;
 
input MRxClk;
input MRxDV;
input [3:0] MRxD;
input Transmitting;
input HugEn;
input DlyCrcEn;
input [15:0] MaxFL;
input r_IFG;
input Reset;
input [47:0] MAC; // Station Address
input r_Bro; // broadcast disable
input r_Pro; // promiscuous enable
input [31:0] r_HASH0; // lower 4 bytes Hash Table
input [31:0] r_HASH1; // upper 4 bytes Hash Table
input PassAll;
input ControlFrmAddressOK;
wire MRxDEqD;
wire MRxDEq5;
wire StateDrop;
wire ByteCntEq1;
wire ByteCntEq2;
wire ByteCntEq3;
wire ByteCntEq4;
wire ByteCntEq5;
wire ByteCntEq6;
wire ByteCntEq7;
wire ByteCntSmall7;
wire [31:0] Crc;
wire Enable_Crc;
wire Initialize_Crc;
wire [3:0] Data_Crc;
wire GenerateRxValid;
wire GenerateRxStartFrm;
wire GenerateRxEndFrm;
wire DribbleRxEndFrm;
wire [3:0] DlyCrcCnt;
wire IFGCounterEq24;
 
output [7:0] RxData;
output RxValid;
output RxStartFrm;
output RxEndFrm;
output [15:0] ByteCnt;
output ByteCntEq0;
output ByteCntGreat2;
output ByteCntMaxFrame;
output CrcError;
output StateIdle;
output StatePreamble;
output StateSFD;
output [1:0] StateData;
output RxAbort;
output AddressMiss;
assign MRxDEqD = MRxD == 4'hd;
assign MRxDEq5 = MRxD == 4'h5;
 
reg [7:0] RxData;
reg RxValid;
reg RxStartFrm;
reg RxEndFrm;
reg Broadcast;
reg Multicast;
reg [5:0] CrcHash;
reg CrcHashGood;
reg DelayData;
reg [7:0] LatchedByte;
reg [7:0] RxData_d;
reg RxValid_d;
reg RxStartFrm_d;
reg RxEndFrm_d;
 
wire MRxDEqD;
wire MRxDEq5;
wire StateDrop;
wire ByteCntEq1;
wire ByteCntEq2;
wire ByteCntEq3;
wire ByteCntEq4;
wire ByteCntEq5;
wire ByteCntEq6;
wire ByteCntEq7;
wire ByteCntSmall7;
wire [31:0] Crc;
wire Enable_Crc;
wire Initialize_Crc;
wire [3:0] Data_Crc;
wire GenerateRxValid;
wire GenerateRxStartFrm;
wire GenerateRxEndFrm;
wire DribbleRxEndFrm;
wire [3:0] DlyCrcCnt;
wire IFGCounterEq24;
// Rx State Machine module
eth_rxstatem rxstatem1
(
.MRxClk(MRxClk),
.Reset(Reset),
.MRxDV(MRxDV),
.ByteCntEq0(ByteCntEq0),
.ByteCntGreat2(ByteCntGreat2),
.Transmitting(Transmitting),
.MRxDEq5(MRxDEq5),
.MRxDEqD(MRxDEqD),
.IFGCounterEq24(IFGCounterEq24),
.ByteCntMaxFrame(ByteCntMaxFrame),
.StateData(StateData),
.StateIdle(StateIdle),
.StatePreamble(StatePreamble),
.StateSFD(StateSFD),
.StateDrop(StateDrop)
);
 
assign MRxDEqD = MRxD == 4'hd;
assign MRxDEq5 = MRxD == 4'h5;
 
// Rx Counters module
eth_rxcounters rxcounters1
(.MRxClk(MRxClk),
.Reset(Reset),
.MRxDV(MRxDV),
.StateIdle(StateIdle),
.StateSFD(StateSFD),
.StateData(StateData),
.StateDrop(StateDrop),
.StatePreamble(StatePreamble),
.MRxDEqD(MRxDEqD),
.DlyCrcEn(DlyCrcEn),
.DlyCrcCnt(DlyCrcCnt),
.Transmitting(Transmitting),
.MaxFL(MaxFL),
.r_IFG(r_IFG),
.HugEn(HugEn),
.IFGCounterEq24(IFGCounterEq24),
.ByteCntEq0(ByteCntEq0),
.ByteCntEq1(ByteCntEq1),
.ByteCntEq2(ByteCntEq2),
.ByteCntEq3(ByteCntEq3),
.ByteCntEq4(ByteCntEq4),
.ByteCntEq5(ByteCntEq5),
.ByteCntEq6(ByteCntEq6),
.ByteCntEq7(ByteCntEq7),
.ByteCntGreat2(ByteCntGreat2),
.ByteCntSmall7(ByteCntSmall7),
.ByteCntMaxFrame(ByteCntMaxFrame),
.ByteCntOut(ByteCnt)
);
 
// Rx State Machine module
eth_rxstatem rxstatem1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .ByteCntEq0(ByteCntEq0),
.ByteCntGreat2(ByteCntGreat2), .Transmitting(Transmitting), .MRxDEq5(MRxDEq5),
.MRxDEqD(MRxDEqD), .IFGCounterEq24(IFGCounterEq24), .ByteCntMaxFrame(ByteCntMaxFrame),
.StateData(StateData), .StateIdle(StateIdle), .StatePreamble(StatePreamble),
.StateSFD(StateSFD), .StateDrop(StateDrop)
);
// Rx Address Check
 
eth_rxaddrcheck rxaddrcheck1
(.MRxClk(MRxClk),
.Reset( Reset),
.RxData(RxData),
.Broadcast (Broadcast),
.r_Bro (r_Bro),
.r_Pro(r_Pro),
.ByteCntEq6(ByteCntEq6),
.ByteCntEq7(ByteCntEq7),
.ByteCntEq2(ByteCntEq2),
.ByteCntEq3(ByteCntEq3),
.ByteCntEq4(ByteCntEq4),
.ByteCntEq5(ByteCntEq5),
.HASH0(r_HASH0),
.HASH1(r_HASH1),
.CrcHash(CrcHash),
.CrcHashGood(CrcHashGood),
.StateData(StateData),
.Multicast(Multicast),
.MAC(MAC),
.RxAbort(RxAbort),
.RxEndFrm(RxEndFrm),
.AddressMiss(AddressMiss),
.PassAll(PassAll),
.ControlFrmAddressOK(ControlFrmAddressOK)
);
 
// Rx Counters module
eth_rxcounters rxcounters1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .StateIdle(StateIdle),
.StateSFD(StateSFD), .StateData(StateData), .StateDrop(StateDrop),
.StatePreamble(StatePreamble), .MRxDEqD(MRxDEqD), .DlyCrcEn(DlyCrcEn),
.DlyCrcCnt(DlyCrcCnt), .Transmitting(Transmitting), .MaxFL(MaxFL), .r_IFG(r_IFG),
.HugEn(HugEn), .IFGCounterEq24(IFGCounterEq24), .ByteCntEq0(ByteCntEq0),
.ByteCntEq1(ByteCntEq1), .ByteCntEq2(ByteCntEq2), .ByteCntEq3(ByteCntEq3),
.ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5), .ByteCntEq6(ByteCntEq6),
.ByteCntEq7(ByteCntEq7), .ByteCntGreat2(ByteCntGreat2),
.ByteCntSmall7(ByteCntSmall7), .ByteCntMaxFrame(ByteCntMaxFrame),
.ByteCntOut(ByteCnt)
);
 
// Rx Address Check
assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame);
assign Initialize_Crc = StateSFD | DlyCrcEn & (|DlyCrcCnt[3:0]) &
DlyCrcCnt[3:0] < 4'h9;
 
eth_rxaddrcheck rxaddrcheck1
(.MRxClk(MRxClk), .Reset( Reset), .RxData(RxData),
.Broadcast (Broadcast), .r_Bro (r_Bro), .r_Pro(r_Pro),
.ByteCntEq6(ByteCntEq6), .ByteCntEq7(ByteCntEq7), .ByteCntEq2(ByteCntEq2),
.ByteCntEq3(ByteCntEq3), .ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5),
.HASH0(r_HASH0), .HASH1(r_HASH1),
.CrcHash(CrcHash), .CrcHashGood(CrcHashGood), .StateData(StateData),
.Multicast(Multicast), .MAC(MAC), .RxAbort(RxAbort),
.RxEndFrm(RxEndFrm), .AddressMiss(AddressMiss), .PassAll(PassAll),
.ControlFrmAddressOK(ControlFrmAddressOK)
);
assign Data_Crc[0] = MRxD[3];
assign Data_Crc[1] = MRxD[2];
assign Data_Crc[2] = MRxD[1];
assign Data_Crc[3] = MRxD[0];
 
 
assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame);
assign Initialize_Crc = StateSFD | DlyCrcEn & (|DlyCrcCnt[3:0]) & DlyCrcCnt[3:0] < 4'h9;
// Connecting module Crc
eth_crc crcrx
(.Clk(MRxClk),
.Reset(Reset),
.Data(Data_Crc),
.Enable(Enable_Crc),
.Initialize(Initialize_Crc),
.Crc(Crc), .CrcError(CrcError)
);
 
assign Data_Crc[0] = MRxD[3];
assign Data_Crc[1] = MRxD[2];
assign Data_Crc[2] = MRxD[1];
assign Data_Crc[3] = MRxD[0];
 
 
// Connecting module Crc
eth_crc crcrx (.Clk(MRxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
.Crc(Crc), .CrcError(CrcError)
);
// Latching CRC for use in the hash table
 
always @ (posedge MRxClk)
begin
CrcHashGood <= StateData[0] & ByteCntEq6;
end
 
always @ (posedge MRxClk)
begin
if(Reset | StateIdle)
CrcHash[5:0] <= 6'h0;
else
if(StateData[0] & ByteCntEq6)
CrcHash[5:0] <= Crc[31:26];
end
 
// Latching CRC for use in the hash table
 
always @ (posedge MRxClk)
begin
CrcHashGood <= StateData[0] & ByteCntEq6;
end
// Output byte stream
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxData_d[7:0] <= 8'h0;
DelayData <= 1'b0;
LatchedByte[7:0] <= 8'h0;
RxData[7:0] <= 8'h0;
end
else
begin
// Latched byte
LatchedByte[7:0] <= {MRxD[3:0], LatchedByte[7:4]};
DelayData <= StateData[0];
 
always @ (posedge MRxClk)
begin
if(Reset | StateIdle)
CrcHash[5:0] <= 6'h0;
else
if(StateData[0] & ByteCntEq6)
CrcHash[5:0] <= Crc[31:26];
end
if(GenerateRxValid)
// Data goes through only in data state
RxData_d[7:0] <= LatchedByte[7:0] & {8{|StateData}};
else
if(~DelayData)
// Delaying data to be valid for two cycles.
// Zero when not active.
RxData_d[7:0] <= 8'h0;
 
RxData[7:0] <= RxData_d[7:0]; // Output data byte
end
end
 
// Output byte stream
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxData_d[7:0] <= 8'h0;
DelayData <= 1'b0;
LatchedByte[7:0] <= 8'h0;
RxData[7:0] <= 8'h0;
end
else
begin
LatchedByte[7:0] <= {MRxD[3:0], LatchedByte[7:4]}; // Latched byte
DelayData <= StateData[0];
 
if(GenerateRxValid)
RxData_d[7:0] <= LatchedByte[7:0] & {8{|StateData}}; // Data goes through only in data state
else
if(~DelayData)
RxData_d[7:0] <= 8'h0; // Delaying data to be valid for two cycles. Zero when not active.
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
Broadcast <= 1'b0;
else
begin
if(StateData[0] & ~(&LatchedByte[7:0]) & ByteCntSmall7)
Broadcast <= 1'b0;
else
if(StateData[0] & (&LatchedByte[7:0]) & ByteCntEq1)
Broadcast <= 1'b1;
else
if(RxAbort | RxEndFrm)
Broadcast <= 1'b0;
end
end
 
RxData[7:0] <= RxData_d[7:0]; // Output data byte
end
end
 
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
Multicast <= 1'b0;
else
begin
if(StateData[0] & ByteCntEq1 & LatchedByte[0])
Multicast <= 1'b1;
else if(RxAbort | RxEndFrm)
Multicast <= 1'b0;
end
end
 
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
Broadcast <= 1'b0;
else
begin
if(StateData[0] & ~(&LatchedByte[7:0]) & ByteCntSmall7)
Broadcast <= 1'b0;
else
if(StateData[0] & (&LatchedByte[7:0]) & ByteCntEq1)
Broadcast <= 1'b1;
else
if(RxAbort | RxEndFrm)
Broadcast <= 1'b0;
end
end
 
assign GenerateRxValid = StateData[0] & (~ByteCntEq0 | DlyCrcCnt >= 4'h3);
 
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
Multicast <= 1'b0;
else
begin
if(StateData[0] & ByteCntEq1 & LatchedByte[0])
Multicast <= 1'b1;
else if(RxAbort | RxEndFrm)
Multicast <= 1'b0;
end
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxValid_d <= 1'b0;
RxValid <= 1'b0;
end
else
begin
RxValid_d <= GenerateRxValid;
RxValid <= RxValid_d;
end
end
 
 
assign GenerateRxValid = StateData[0] & (~ByteCntEq0 | DlyCrcCnt >= 4'h3);
assign GenerateRxStartFrm = StateData[0] &
((ByteCntEq1 & ~DlyCrcEn) |
((DlyCrcCnt == 4'h3) & DlyCrcEn));
 
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxValid_d <= 1'b0;
RxValid <= 1'b0;
end
else
begin
RxValid_d <= GenerateRxValid;
RxValid <= RxValid_d;
end
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxStartFrm_d <= 1'b0;
RxStartFrm <= 1'b0;
end
else
begin
RxStartFrm_d <= GenerateRxStartFrm;
RxStartFrm <= RxStartFrm_d;
end
end
 
 
assign GenerateRxStartFrm = StateData[0] & (ByteCntEq1 & ~DlyCrcEn | DlyCrcCnt == 4'h3 & DlyCrcEn);
assign GenerateRxEndFrm = StateData[0] &
(~MRxDV & ByteCntGreat2 | ByteCntMaxFrame);
assign DribbleRxEndFrm = StateData[1] & ~MRxDV & ByteCntGreat2;
 
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxStartFrm_d <= 1'b0;
RxStartFrm <= 1'b0;
end
else
begin
RxStartFrm_d <= GenerateRxStartFrm;
RxStartFrm <= RxStartFrm_d;
end
end
 
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxEndFrm_d <= 1'b0;
RxEndFrm <= 1'b0;
end
else
begin
RxEndFrm_d <= GenerateRxEndFrm;
RxEndFrm <= RxEndFrm_d | DribbleRxEndFrm;
end
end
 
assign GenerateRxEndFrm = StateData[0] & (~MRxDV & ByteCntGreat2 | ByteCntMaxFrame);
assign DribbleRxEndFrm = StateData[1] & ~MRxDV & ByteCntGreat2;
 
 
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxEndFrm_d <= 1'b0;
RxEndFrm <= 1'b0;
end
else
begin
RxEndFrm_d <= GenerateRxEndFrm;
RxEndFrm <= RxEndFrm_d | DribbleRxEndFrm;
end
end
 
 
endmodule
/rtl/verilog/ethmac/eth_rxcounters.v
39,58 → 39,18
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2002/02/15 11:13:29 mohor
// Format of the file changed a bit.
//
// Revision 1.4 2002/02/14 20:19:41 billditt
// Modified for Address Checking,
// addition of eth_addrcheck.v
//
// Revision 1.3 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.2 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.1 2001/06/27 21:26:19 mohor
// Initial release of the RxEthMAC module.
//
//
//
//
//
//
 
 
`include "timescale.v"
 
 
module eth_rxcounters (MRxClk, Reset, MRxDV, StateIdle, StateSFD, StateData, StateDrop, StatePreamble,
MRxDEqD, DlyCrcEn, DlyCrcCnt, Transmitting, MaxFL, r_IFG, HugEn, IFGCounterEq24,
ByteCntEq0, ByteCntEq1, ByteCntEq2,ByteCntEq3,ByteCntEq4,ByteCntEq5, ByteCntEq6,
ByteCntEq7, ByteCntGreat2, ByteCntSmall7, ByteCntMaxFrame, ByteCntOut
);
module eth_rxcounters
(
MRxClk, Reset, MRxDV, StateIdle, StateSFD, StateData, StateDrop, StatePreamble,
MRxDEqD, DlyCrcEn, DlyCrcCnt, Transmitting, MaxFL, r_IFG, HugEn, IFGCounterEq24,
ByteCntEq0, ByteCntEq1, ByteCntEq2,ByteCntEq3,ByteCntEq4,ByteCntEq5, ByteCntEq6,
ByteCntEq7, ByteCntGreat2, ByteCntSmall7, ByteCntMaxFrame, ByteCntOut
);
 
parameter Tp = 1;
 
input MRxClk;
input Reset;
input MRxDV;
146,30 → 106,30
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ByteCnt[15:0] <= 16'h0;
ByteCnt[15:0] <= 16'd0;
else
begin
if(ResetByteCounter)
ByteCnt[15:0] <= 16'h0;
ByteCnt[15:0] <= 16'd0;
else
if(IncrementByteCounter)
ByteCnt[15:0] <= ByteCnt[15:0] + 1'b1;
ByteCnt[15:0] <= ByteCnt[15:0] + 16'd1;
end
end
 
assign ByteCntDelayed = ByteCnt + 3'h4;
assign ByteCntOut = DlyCrcEn? ByteCntDelayed : ByteCnt;
assign ByteCntDelayed = ByteCnt + 16'd4;
assign ByteCntOut = DlyCrcEn ? ByteCntDelayed : ByteCnt;
 
assign ByteCntEq0 = ByteCnt == 16'h0;
assign ByteCntEq1 = ByteCnt == 16'h1;
assign ByteCntEq2 = ByteCnt == 16'h2;
assign ByteCntEq3 = ByteCnt == 16'h3;
assign ByteCntEq4 = ByteCnt == 16'h4;
assign ByteCntEq5 = ByteCnt == 16'h5;
assign ByteCntEq6 = ByteCnt == 16'h6;
assign ByteCntEq7 = ByteCnt == 16'h7;
assign ByteCntGreat2 = ByteCnt > 16'h2;
assign ByteCntSmall7 = ByteCnt < 16'h7;
assign ByteCntEq0 = ByteCnt == 16'd0;
assign ByteCntEq1 = ByteCnt == 16'd1;
assign ByteCntEq2 = ByteCnt == 16'd2;
assign ByteCntEq3 = ByteCnt == 16'd3;
assign ByteCntEq4 = ByteCnt == 16'd4;
assign ByteCntEq5 = ByteCnt == 16'd5;
assign ByteCntEq6 = ByteCnt == 16'd6;
assign ByteCntEq7 = ByteCnt == 16'd7;
assign ByteCntGreat2 = ByteCnt > 16'd2;
assign ByteCntSmall7 = ByteCnt < 16'd7;
assign ByteCntMax = ByteCnt == 16'hffff;
assign ByteCntMaxFrame = ByteCnt == MaxFL[15:0] & ~HugEn;
 
188,7 → 148,7
IFGCounter[4:0] <= 5'h0;
else
if(IncrementIFGCounter)
IFGCounter[4:0] <= IFGCounter[4:0] + 1'b1;
IFGCounter[4:0] <= IFGCounter[4:0] + 5'd1;
end
end
 
210,7 → 170,7
DlyCrcCnt[3:0] <= 4'h1;
else
if(DlyCrcEn & (|DlyCrcCnt[3:0]))
DlyCrcCnt[3:0] <= DlyCrcCnt[3:0] + 1'b1;
DlyCrcCnt[3:0] <= DlyCrcCnt[3:0] + 4'd1;
end
end
 
/rtl/verilog/ethmac/eth_txethmac.v
341,7 → 341,7
RetryCnt[3:0] <= 4'h0;
else
if(StateJam & NibCntEq7 & ColWindow & (RandomEq0 | NoBckof) | StateBackOff & RandomEqByteCnt)
RetryCnt[3:0] <= RetryCnt[3:0] + 1'b1;
RetryCnt[3:0] <= RetryCnt[3:0] + 1;
end
end
 
/rtl/verilog/ethmac/eth_wishbone.v
69,7 → 69,8
PerPacketPad,
 
//RX
MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort, RxStatusWriteLatched_sync2,
MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
RxStatusWriteLatched_sync2,
// Register
r_TxEn, r_RxEn, r_TxBDNum, r_RxFlow, r_PassAll,
79,11 → 80,13
// Rx Status
InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood, AddressMiss,
ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood,
AddressMiss,
ReceivedPauseFrm,
// Tx Status
RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, RstDeferLatched, CarrierSenseLost
RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, RstDeferLatched,
CarrierSenseLost
 
// Bist
`ifdef ETH_BIST
103,10 → 106,6
);
 
 
//parameter Tp = 1;
parameter Tp = 0;
 
 
// WISHBONE common
input WB_CLK_I; // WISHBONE clock
input [31:0] WB_DAT_I; // WISHBONE data input
261,10 → 260,10
reg TxAbortPacket;
reg TxAbortPacket_NotCleared;
reg RxBDReady;
reg RxBDOK;
reg RxBDOK/* synthesis syn_allow_retiming=0*/;
reg TxBDReady;
 
reg RxBDRead;
reg RxBDRead ;
 
reg [31:0] TxDataLatched;
reg [1:0] TxByteCnt;
340,8 → 339,8
reg [8:0] RxStatusInLatched;
 
reg WbEn, WbEn_q;
reg RxEn, RxEn_q;
reg TxEn, TxEn_q;
reg RxEn, RxEn_q /* synthesis syn_allow_retiming=0; syn_noprune=1; syn_keep=1 */;
reg TxEn, TxEn_q /* synthesis syn_allow_retiming=0; syn_noprune=1; syn_keep=1 */;
reg r_TxEn_q;
reg r_RxEn_q;
 
358,7 → 357,7
reg RxEn_needed;
 
wire StartRxPointerRead;
reg RxPointerRead;
reg RxPointerRead/* synthesis syn_allow_retiming=0*/;
 
// RX shift ending signals
reg ShiftEnded_rck;
376,11 → 375,68
reg rx_wb_last_writes;
 
`ifdef TXBD_POLL
reg [31:0] TxBDReadySamples; // -- jb
wire TxBDNotReady; // -- jb
`endif
reg StartOccured;
reg TxStartFrm_sync1;
reg TxStartFrm_sync2;
reg TxStartFrm_syncb1;
reg TxStartFrm_syncb2;
 
wire TxFifoClear;
wire TxBufferAlmostFull;
wire TxBufferFull;
wire TxBufferEmpty;
wire TxBufferAlmostEmpty;
wire SetReadTxDataFromMemory;
reg BlockReadTxDataFromMemory/* synthesis syn_allow_retiming=0*/;
 
reg tx_burst_en;
reg rx_burst_en;
reg [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt;
wire ReadTxDataFromMemory_2;
wire tx_burst;
 
wire [31:0] TxData_wb;
wire ReadTxDataFromFifo_wb;
 
wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
 
reg [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt;
 
wire rx_burst;
wire enough_data_in_rxfifo_for_burst;
wire enough_data_in_rxfifo_for_burst_plus1;
 
reg ReadTxDataFromMemory/* synthesis syn_allow_retiming=0*/;
wire WriteRxDataToMemory;
reg WriteRxDataToMemory_r ;
reg MasterWbTX;
reg MasterWbRX;
 
reg [29:0] m_wb_adr_o;
reg m_wb_cyc_o;
reg [3:0] m_wb_sel_o;
reg m_wb_we_o;
 
wire TxLengthEq0;
wire TxLengthLt4;
 
reg BlockingIncrementTxPointer;
reg [31:2] TxPointerMSB;
reg [1:0] TxPointerLSB;
reg [1:0] TxPointerLSB_rst;
reg [31:2] RxPointerMSB;
reg [1:0] RxPointerLSB_rst;
 
wire RxBurstAcc;
wire RxWordAcc;
wire RxHalfAcc;
wire RxByteAcc;
 
`ifdef ETH_WISHBONE_B3
`ifndef BURST_4BEAT
assign m_wb_bte_o = 2'b00; // Linear burst
408,7 → 464,7
.oe (ram_oe),
.addr (ram_addr),
.di (ram_di),
.do (ram_do)
.dato (ram_do)
`ifdef ETH_BIST
,
.mbist_si_i (mbist_si_i),
448,11 → 504,12
ram_addr <= 8'h0;
ram_di <= 32'h0;
BDRead <= 1'b0;
BDWrite <= 1'b0;
BDWrite <= 0;
end
else
begin
// Switching between three stages depends on enable signals
/* verilator lint_off CASEINCOMPLETE */ // JB
case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed}) // synopsys parallel_case
5'b100_10, 5'b100_11 :
begin
516,7 → 573,8
BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
BDRead <= (|BDCs) & ~WB_WE_I;
end
endcase
endcase //case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed})
/* verilator lint_on CASEINCOMPLETE */
end
end
 
573,30 → 631,6
TxBDReady <= 1'b0;
end
 
`ifdef TXBD_POLL
// Register TxBDReady 4 times, when all are low we know this one is not
// good to transmit
always @(posedge WB_CLK_I or posedge Reset) // -- jb
begin
if (Reset) TxBDReadySamples <= 32'hffffffff;
else begin
if (r_TxEn)
begin
if (TxBDNotReady)
TxBDReadySamples <= 32'hffffffff;
else
TxBDReadySamples[31:0] <= {TxBDReadySamples[30:0],TxBDReady};
end
else
TxBDReadySamples <= 32'hffffffff;
end // else: !if(Reset)
end // always @ (posedge WB_CLK_I or posedge Reset)
// When all low, this goes high -- jb
assign TxBDNotReady = ~(|TxBDReadySamples);
 
`endif
 
// Reading the Tx buffer descriptor
assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) &
~BlockingTxBDRead & ~TxBDReady;
711,9 → 745,6
TxStatus <= ram_do[14:11];
end
 
reg ReadTxDataFromMemory;
wire WriteRxDataToMemory;
reg WriteRxDataToMemory_r;
 
// Register WriteRxDataToMemory in Wishbone clock domain
// so it doesn't get out of sync with burst capability indication signals
722,30 → 753,8
WriteRxDataToMemory_r <= 0;
else
WriteRxDataToMemory_r <= WriteRxDataToMemory;
reg MasterWbTX;
reg MasterWbRX;
 
reg [29:0] m_wb_adr_o;
reg m_wb_cyc_o;
reg [3:0] m_wb_sel_o;
reg m_wb_we_o;
 
wire TxLengthEq0;
wire TxLengthLt4;
 
reg BlockingIncrementTxPointer;
reg [31:2] TxPointerMSB;
reg [1:0] TxPointerLSB;
reg [1:0] TxPointerLSB_rst;
reg [31:2] RxPointerMSB;
reg [1:0] RxPointerLSB_rst;
 
wire RxBurstAcc;
wire RxWordAcc;
wire RxHalfAcc;
wire RxByteAcc;
 
//Latching length from the buffer descriptor;
always @ (posedge WB_CLK_I or posedge Reset)
begin
761,19 → 770,19
TxLength <= 16'h0;
else
if(TxPointerLSB_rst==2'h0)
TxLength <= TxLength - 3'h4; // Length is subtracted at
TxLength <= TxLength - 16'd4; // Length is subtracted at
// the data request
else
if(TxPointerLSB_rst==2'h1)
TxLength <= TxLength - 3'h3; // Length is subtracted
TxLength <= TxLength - 16'd3; // Length is subtracted
// at the data request
else
if(TxPointerLSB_rst==2'h2)
TxLength <= TxLength - 3'h2; // Length is subtracted
TxLength <= TxLength - 16'd2; // Length is subtracted
// at the data request
else
if(TxPointerLSB_rst==2'h3)
TxLength <= TxLength - 3'h1; // Length is subtracted
TxLength <= TxLength - 16'd1; // Length is subtracted
// at the data request
end
end
809,7 → 818,7
else
if(IncrTxPointer & ~BlockingIncrementTxPointer)
// TxPointer is word-aligned
TxPointerMSB <= TxPointerMSB + 1'b1;
TxPointerMSB <= TxPointerMSB + 1;
end
 
 
862,14 → 871,6
end
 
 
wire TxBufferAlmostFull;
wire TxBufferFull;
wire TxBufferEmpty;
wire TxBufferAlmostEmpty;
wire SetReadTxDataFromMemory;
 
reg BlockReadTxDataFromMemory;
 
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
 
always @ (posedge WB_CLK_I or posedge Reset)
884,17 → 885,6
ReadTxDataFromMemory <= 1'b1;
end
 
reg tx_burst_en;
reg rx_burst_en;
reg [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt;
wire ReadTxDataFromMemory_2;
wire tx_burst;
 
wire [31:0] TxData_wb;
wire ReadTxDataFromFifo_wb;
 
assign ReadTxDataFromMemory_2 = ReadTxDataFromMemory &
~BlockReadTxDataFromMemory | (|tx_burst_cnt);
915,18 → 905,10
BlockReadTxDataFromMemory <= 1'b0;
end
 
`define TX_BURST_EN_CONDITION (txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4)))
`define TX_BURST_EN_CONDITION ({1'b0,txfifo_cnt}<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4)))
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
 
reg [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt;
 
wire rx_burst;
wire enough_data_in_rxfifo_for_burst;
wire enough_data_in_rxfifo_for_burst_plus1;
 
// Enabling master wishbone access to the memory for two devices TX and RX.
always @ (posedge WB_CLK_I or posedge Reset)
begin
954,7 → 936,7
else
begin
// Switching between two stages depends on enable signals
casex ({MasterWbTX,
casez ({MasterWbTX,
MasterWbRX,
ReadTxDataFromMemory_2,
WriteRxDataToMemory_r,
964,9 → 946,9
rx_burst}) // synopsys parallel_case
8'b00_10_00_10, // Idle and MRB needed
8'b10_1x_10_1x, // MRB continues
8'b10_1?_10_1?, // MRB continues
8'b10_10_01_10, // Clear (previously MR) and MRB needed
8'b01_1x_01_1x: // Clear (previously MW) and MRB needed
8'b01_1?_01_1?: // Clear (previously MW) and MRB needed
begin
MasterWbTX <= 1'b1; // tx burst
MasterWbRX <= 1'b0;
979,7 → 961,7
if(tx_burst_cnt==0)
m_wb_adr_o <= TxPointerMSB;
else
m_wb_adr_o <= m_wb_adr_o+1'b1;
m_wb_adr_o <= m_wb_adr_o + 1;
 
if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
begin
999,10 → 981,10
end
end // case: 8'b00_10_00_10,...
`ifdef ETH_RX_BURST_EN
8'b00_x1_00_x1, // Idle and MWB needed
8'b01_x1_10_x1, // MWB continues
8'b00_?1_00_?1, // Idle and MWB needed
8'b01_?1_10_?1, // MWB continues
8'b01_01_01_01, // Clear (previously MW) and MWB needed
8'b10_x1_01_x1 : // Clear (previously MR) and MWB needed
8'b10_?1_01_?1 : // Clear (previously MR) and MWB needed
begin
MasterWbTX <= 1'b0; // rx burst
MasterWbRX <= 1'b1;
1011,12 → 993,12
m_wb_sel_o <= RxByteSel;
IncrTxPointer<= 1'b0;
cyc_cleared<= 1'b0;
rx_burst_cnt <= rx_burst_cnt+3'h1;
rx_burst_cnt <= rx_burst_cnt+3'd1;
 
if(rx_burst_cnt==0)
m_wb_adr_o <= RxPointerMSB;
else
m_wb_adr_o <= m_wb_adr_o+1'b1;
m_wb_adr_o <= m_wb_adr_o + 1;
 
if(rx_burst_cnt==(`ETH_BURST_LENGTH-1))
begin
1036,8 → 1018,8
end
end // case: 8'b00_x1_00_x1,...
`endif // `ifdef ETH_RX_BURST_EN
8'b00_x1_00_x0 ,//idle and MW is needed (data write to rx buffer)
8'b01_x1_00_x0 :// Sometimes gets caught changing states - JB
8'b00_?1_00_?0 ,//idle and MW is needed (data write to rx buffer)
8'b01_?1_00_?0 :// Sometimes gets caught changing states - JB
begin
MasterWbTX <= 1'b0;
MasterWbRX <= !RxBufferEmpty;
1096,7 → 1078,7
`endif
end
8'b10_10_01_00,// MR and MR is needed (data read from tx buffer)
8'b01_1x_01_0x :// MW and MR is needed (data read from tx
8'b01_1?_01_0? :// MW and MR is needed (data read from tx
// buffer)
begin
MasterWbTX <= 1'b1; // Only switch to TX here
1132,7 → 1114,7
end
8'b01_01_01_00,// MW and MW needed (data write to rx buffer)
8'b10_x1_01_x0 ://MR and MW is needed (data write to rx buffer)
8'b10_?1_01_?0 ://MR and MW is needed (data write to rx buffer)
begin
MasterWbTX <= 1'b0;
MasterWbRX <= !RxBufferEmpty;
1163,11 → 1145,11
end
8'b01_01_10_00,// MW and MW needed (cycle is cleared between
// previous and next access)
8'b01_1x_10_x0,// MW and MW or MR or MRB needed (cycle is
8'b01_1?_10_?0,// MW and MW or MR or MRB needed (cycle is
// cleared between previous and next access)
8'b10_10_10_00,// MR and MR needed (cycle is cleared between
// previous and next access)
8'b10_x1_10_0x :// MR and MR or MW or MWB (cycle is cleared
8'b10_?1_10_0? :// MR and MR or MW or MWB (cycle is cleared
// between previous and next access)
begin
m_wb_cyc_o <= 1'b0;// whatever and master read or write is
1190,9 → 1172,9
m_wb_cti_o <= 3'b0;
`endif
end
8'bxx_00_10_00,// whatever and no master read or write is needed
8'b??_00_10_00,// whatever and no master read or write is needed
// (ack or err comes finishing previous access)
8'bxx_00_01_00 : // Between cyc_cleared request was cleared
8'b??_00_01_00 : // Between cyc_cleared request was cleared
begin
MasterWbTX <= 1'b0;
MasterWbRX <= 1'b0;
1244,9 → 1226,6
end
end
 
 
wire TxFifoClear;
 
assign TxFifoClear = (TxAbortPacket | TxRetryPacket | StartTxPointerRead);
eth_fifo
1271,16 → 1250,8
.cnt(txfifo_cnt)
);
 
 
reg StartOccured;
reg TxStartFrm_sync1;
reg TxStartFrm_sync2;
reg TxStartFrm_syncb1;
reg TxStartFrm_syncb2;
 
 
 
// Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
// Start: Generation of the TxStartFrm_wb which is then synchronized to the
// MTxClk
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
1421,13 → 1392,10
 
 
// Temporary Tx and Rx buffer descriptor address
`ifdef TXBD_POLL
assign TempTxBDAddress[7:1] = {7{ (TxStatusWrite|TxBDNotReady) & ~WrapTxStatusBit}} & (TxBDAddress + 1'b1) ; // Tx BD increment or wrap (last BD) -- jb
`else
assign TempTxBDAddress[7:1] = {7{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 1'b1) ; // Tx BD increment or wrap (last BD)
`endif
assign TempTxBDAddress[7:1] = {7{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 1) ; // Tx BD increment or wrap (last BD)
 
assign TempRxBDAddress[7:1] = {7{ WrapRxStatusBit}} & (r_TxBDNum[6:0]) | // Using first Rx BD
{7{~WrapRxStatusBit}} & (RxBDAddress + 1'b1) ; // Using next Rx BD (incremenrement address)
{7{~WrapRxStatusBit}} & (RxBDAddress + 1) ; // Using next Rx BD (incremenrement address)
 
 
// Latching Tx buffer descriptor address
1437,12 → 1405,8
TxBDAddress <= 7'h0;
else if (r_TxEn & (~r_TxEn_q))
TxBDAddress <= 7'h0;
`ifdef TXBD_POLL
else if (TxStatusWrite | TxBDNotReady) // -- jb
`else
else if (TxStatusWrite)
`endif
TxBDAddress <= TempTxBDAddress;
else if (TxStatusWrite)
TxBDAddress <= TempTxBDAddress;
end
 
 
1966,7 → 1930,7
rx_just_read_bd <= (RxEn & RxEn_q & RxBDRead);
 
// Signal to indicate we've checked and the RxBD we want to use is not free
reg rx_waiting_for_bd_to_become_free;
reg rx_waiting_for_bd_to_become_free/*syn_allow_retiming=0; syn_keep=1; syn_preserve=1*/;
always @ (posedge WB_CLK_I or posedge Reset)
if(Reset)
rx_waiting_for_bd_to_become_free <= 0;
2034,7 → 1998,7
if(MasterWbRX & m_wb_ack_i)
// Word access (always word access. m_wb_sel_o are used for
// selecting bytes)
RxPointerMSB <= RxPointerMSB + 1'b1;
RxPointerMSB <= RxPointerMSB + 1;
end
 
 
2131,7 → 2095,7
endcase
else
if(RxValid & RxEnableWindow /*& RxReady*/ | LastByteIn)
RxByteCnt <= RxByteCnt + 1'b1;
RxByteCnt <= RxByteCnt + 1;
end
 
 
2150,7 → 2114,7
endcase
else
if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
RxValidBytes <= RxValidBytes + 1'b1;
RxValidBytes <= RxValidBytes + 1;
end
 
 
2211,11 → 2175,11
 
 
// Indicating start of the reception process
assign SetWriteRxDataToFifo = (RxValid &/* RxReady &*/ ~RxStartFrm &
RxEnableWindow & (&RxByteCnt)) |
(RxValid &/* RxReady &*/ RxStartFrm &
(&RxPointerLSB_rst)) |
(ShiftWillEnd & LastByteIn & (&RxByteCnt));
assign SetWriteRxDataToFifo = (RxValid & ~RxStartFrm &
RxEnableWindow & (&RxByteCnt))
/*| (RxValid & RxStartFrm &
(&RxPointerLSB_rst)) */
|(ShiftWillEnd & LastByteIn & (&RxByteCnt));
 
always @ (posedge MRxClk or posedge Reset)
begin
2263,8 → 2227,8
~WriteRxDataToFifoSync3;
// Receive fifo selection register - JB
reg [3:0] rx_shift_ended_wb_shr;
reg rx_ethside_fifo_sel;
reg rx_wbside_fifo_sel;
reg rx_ethside_fifo_sel /* synthesis syn_allow_retiming=0; syn_noprune=1; syn_keep=1 */;
reg rx_wbside_fifo_sel /* synthesis syn_allow_retiming=0; syn_noprune=1; syn_keep=1 */;
 
// Shift in this - our detection of end of data RX
always @(posedge WB_CLK_I)
2454,10 → 2418,9
assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>(`ETH_BURST_LENGTH - 1);
// While receiving, don't flog the bus too hard, only write out when
// we can burst. But when finishing keep going until we've emptied the fifo
assign write_rx_data_to_memory_go =
RxEnableWindow & (rx_wbside_fifo_sel == rx_ethside_fifo_sel) ?
(rxfifo_cnt>(`ETH_BURST_LENGTH)+2) |
(|rx_burst_cnt) : ~RxBufferEmpty;
assign write_rx_data_to_memory_go
= RxEnableWindow & (rx_wbside_fifo_sel == rx_ethside_fifo_sel) ?
(rxfifo_cnt>(`ETH_BURST_LENGTH) + 2) | (|rx_burst_cnt) : ~RxBufferEmpty;
`else
assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=`ETH_BURST_LENGTH;
2465,7 → 2428,8
assign write_rx_data_to_memory_go = ~RxBufferEmpty;
`endif // !`ifdef ETH_RX_BURST_EN
assign WriteRxDataToMemory = write_rx_data_to_memory_go & !write_rx_data_to_memory_wait;
assign WriteRxDataToMemory = write_rx_data_to_memory_go &
!write_rx_data_to_memory_wait;
assign rx_burst = rx_burst_en & WriteRxDataToMemory;
 
2814,11 → 2778,9
`ifdef WISHBONE_DEBUG
// Top byte, burst progress counters
assign dbg_dat0[31] = 0;
assign dbg_dat0[30] = 0;
assign dbg_dat0[29:28] = rx_burst_cnt;
assign dbg_dat0[30:28] = rx_burst_cnt;
assign dbg_dat0[27] = 0;
assign dbg_dat0[26] = 0;
assign dbg_dat0[25:24] = tx_burst_cnt;
assign dbg_dat0[26:24] = tx_burst_cnt;
// Third byte
assign dbg_dat0[23] = 0;
/rtl/verilog/ethmac/eth_txcounters.v
159,7 → 159,7
NibCnt <= 16'h0;
else
if(IncrementNibCnt)
NibCnt <= NibCnt + 1'b1;
NibCnt <= NibCnt + 16'd1;
end
end
 
167,11 → 167,11
assign NibCntEq7 = &NibCnt[2:0];
assign NibCntEq15 = &NibCnt[3:0];
 
assign NibbleMinFl = NibCnt >= (((MinFL-3'h4)<<1) -1); // FCS should not be included in NibbleMinFl
assign NibbleMinFl = NibCnt >= (((MinFL-16'd4)<<1) -1); // FCS should not be included in NibbleMinFl
 
assign ExcessiveDeferCnt = NibCnt[13:0] == 16'h17b7;
assign ExcessiveDeferCnt = NibCnt[13:0] == 14'h17b7;
 
assign ExcessiveDefer = NibCnt[13:0] == 16'h17b7 & ~ExDfrEn; // 6071 nibbles
assign ExcessiveDefer = NibCnt[13:0] == 14'h17b7 & ~ExDfrEn; // 6071 nibbles
 
assign IncrementByteCnt = StateData[1] & ~ByteCntMax
| StateBackOff & (&NibCnt[6:0])
191,7 → 191,7
ByteCnt[15:0] <= 16'h0;
else
if(IncrementByteCnt)
ByteCnt[15:0] <= ByteCnt[15:0] + 1'b1;
ByteCnt[15:0] <= ByteCnt[15:0] + 16'd1;
end
end
 
212,7 → 212,7
DlyCrcCnt <= 3'h0;
else
if(DlyCrcEn & (StateSFD | StateData[1] & (|DlyCrcCnt[2:0])))
DlyCrcCnt <= DlyCrcCnt + 1'b1;
DlyCrcCnt <= DlyCrcCnt + 3'd1;
end
end
 
/rtl/verilog/ethmac/eth_fifo.v
3,10 → 3,11
//// eth_fifo.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/project,ethmac ////
//// http://www.opencores.org/project,ethmac ////
//// ////
//// Author(s): ////
//// - Igor Mohor (igorM@opencores.org) ////
//// - Julius Baxter (julius@opencores.org) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
37,33 → 38,16
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2002/04/22 13:45:52 mohor
// Generic ram or Xilinx ram can be used in fifo (selectable by setting
// ETH_FIFO_XILINX in ethmac_defines.v).
//
// Revision 1.2 2002/03/25 13:33:04 mohor
// When clear and read/write are active at the same time, cnt and pointers are
// set to 1.
//
// Revision 1.1 2002/02/05 16:44:39 mohor
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
// MHz. Statuses, overrun, control frame transmission and reception still need
// to be fixed.
//
//
 
`include "ethmac_defines.v"
`include "timescale.v"
 
module eth_fifo (data_in, data_out, clk, reset, write, read, clear, almost_full, full, almost_empty, empty, cnt);
module eth_fifo (data_in, data_out, clk, reset, write, read, clear,
almost_full, full, almost_empty, empty, cnt);
 
parameter DATA_WIDTH = 32;
parameter DEPTH = 8;
parameter CNT_WIDTH = 4;
parameter CNT_WIDTH = 3;
 
input clk;
input reset;
94,9 → 78,9
else
if(read ^ write)
if(read)
cnt <= cnt - 1'b1;
cnt <= cnt - 1;
else
cnt <= cnt + 1'b1;
cnt <= cnt + 1;
end
 
105,30 → 89,40
reg [DATA_WIDTH-1:0] fifo [0:DEPTH-1] /*synthesis syn_ramstyle = "no_rw_check"*/ ;
// This should make the synthesis tool infer RAMs
reg [CNT_WIDTH-2:0] waddr, raddr, raddr_reg;
reg clear_reg; // Register the clear pulse
// This should make the synthesis tool infer a RAM
reg [CNT_WIDTH-1:0] waddr, raddr, raddr_reg;
reg clear_reg; // Register the clear pulse
 
reg fallthrough_read;
reg [CNT_WIDTH-1:0] fallthrough_read_addr;
 
always @(posedge clk)
if (reset)
fallthrough_read <= 0;
else
fallthrough_read <= empty & write;
 
always @(posedge clk)
if (empty & write)
fallthrough_read_addr <= waddr;
always @(posedge clk)
if (reset)
waddr <= 0;
else if (write)
waddr <= waddr + 1;
 
wire raddr_reg_adv;
reg read_reg;
always @(posedge clk)
read_reg <= read;
 
// Advance the address after a read = first/next word fallthrough
assign raddr_reg_adv = (cnt > 2) & read_reg;
always @(posedge clk)
if (reset)
raddr <= 0;
else if (clear)
raddr <= waddr;
else if (read | clear_reg )
else if (read | clear_reg)
raddr <= raddr + 1;
always @ (posedge clk)
142,6 → 136,8
always @ (posedge clk)
if (read | clear_reg)
raddr_reg <= raddr;
else if (fallthrough_read) // To pulse RE for fall-through on Xilinx
raddr_reg <= fallthrough_read_addr;
assign data_out = fifo[raddr_reg];
 
154,16 → 150,15
else if ((cnt == 1) & read & !write)
final_read <= 1; // Indicate last read data has been output
assign empty = ~(|cnt);
assign almost_empty = cnt==1;
assign full = cnt == DEPTH;
assign almost_full = &cnt[CNT_WIDTH-2:0];
assign full = {{32-CNT_WIDTH{1'b0}},cnt} == (DEPTH-1);
assign almost_full = &cnt[CNT_WIDTH-1:0];
 
`else // !`ifdef ETH_FIFO_GENERIC
reg [CNT_WIDTH-2:0] read_pointer;
reg [CNT_WIDTH-2:0] write_pointer;
reg [CNT_WIDTH-1:0] read_pointer;
reg [CNT_WIDTH-1:0] write_pointer;
 
 
always @ (posedge clk or posedge reset)
172,8 → 167,8
read_pointer <= 0;
else
if(clear)
//read_pointer <= { {(CNT_WIDTH-2){1'b0}}, read};
read_pointer <= { {(CNT_WIDTH-2){1'b0}}, 1'b1};
//read_pointer <= { {(CNT_WIDTH-1){1'b0}}, read};
read_pointer <= { {(CNT_WIDTH-1){1'b0}}, 1'b1};
else
if(read & ~empty)
read_pointer <= read_pointer + 1'b1;
185,7 → 180,7
write_pointer <= 0;
else
if(clear)
write_pointer <= { {(CNT_WIDTH-2){1'b0}}, write};
write_pointer <= { {(CNT_WIDTH-1){1'b0}}, write};
else
if(write & ~full)
write_pointer <= write_pointer + 1'b1;
217,8 → 212,8
assign empty = ~(|cnt);
assign almost_empty = cnt == 1;
assign full = cnt == DEPTH;
assign almost_full = &cnt[CNT_WIDTH-2:0];
assign full = cnt == (DEPTH-1);
assign almost_full = &cnt[CNT_WIDTH-1:0];
`endif // !`ifdef ETH_FIFO_GENERIC
/rtl/verilog/ethmac/eth_receivecontrol.v
301,12 → 301,13
DlyCrcCnt <= 3'h0;
else
if(RxValid & ~RxEndFrm & ~DlyCrcCnt[2])
DlyCrcCnt <= DlyCrcCnt + 1'b1;
DlyCrcCnt <= DlyCrcCnt + 3'd1;
end
 
assign ResetByteCnt = RxEndFrm;
assign IncrementByteCnt = RxValid & DetectionWindow & ~ByteCntEq18 & (~DlyCrcEn | DlyCrcEn & DlyCrcCnt[2]);
assign IncrementByteCnt = RxValid & DetectionWindow & ~ByteCntEq18 &
(~DlyCrcEn | DlyCrcEn & DlyCrcCnt[2]);
 
 
// Byte counter
319,7 → 320,7
ByteCnt[4:0] <= 5'h0;
else
if(IncrementByteCnt)
ByteCnt[4:0] <= ByteCnt[4:0] + 1'b1;
ByteCnt[4:0] <= ByteCnt[4:0] + 5'd1;
end
 
 
352,7 → 353,7
PauseTimer[15:0] <= LatchedTimerValue[15:0];
else
if(DecrementPauseTimer)
PauseTimer[15:0] <= PauseTimer[15:0] - 1'b1;
PauseTimer[15:0] <= PauseTimer[15:0] - 16'd1;
end
 
assign PauseTimerEq0 = ~(|PauseTimer[15:0]);
413,7 → 414,7
SlotTimer[5:0] <= 6'h0;
else
if(IncrementSlotTimer)
SlotTimer[5:0] <= SlotTimer[5:0] + 1'b1;
SlotTimer[5:0] <= SlotTimer[5:0] + 6'd1;
end
 
 
/rtl/verilog/ethmac/eth_clockgen.v
89,7 → 89,7
 
 
assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
assign CounterPreset[7:0] = (TempDivider[7:0]>>1) - 1'b1; // We are counting half of period
assign CounterPreset[7:0] = (TempDivider[7:0]>>1) - 8'b1; // We are counting half of period
 
 
// Counter counts half period
/rtl/verilog/ethmac/eth_miim.v
406,7 → 406,7
if(NoPre & ( BitCounter == 7'h0 ))
BitCounter[6:0] <= 7'h21;
else
BitCounter[6:0] <= BitCounter[6:0] + 1'b1;
BitCounter[6:0] <= BitCounter[6:0] + 1;
end
else
BitCounter[6:0] <= 7'h0;
/rtl/verilog/ethmac/ethmac.v
3,7 → 3,7
//// eth.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/project,ethmac ////
//// http://www.opencores.org/project,ethmac ////
//// ////
//// Author(s): ////
//// - Igor Mohor (igorM@opencores.org) ////
45,741 → 45,1054
 
 
module ethmac // renamed jb
(
// WISHBONE common
wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
(
// WISHBONE common
wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
 
// WISHBONE slave
wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
// WISHBONE slave
wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
 
// WISHBONE master
m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
// WISHBONE master
m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
 
`ifdef ETH_WISHBONE_B3
m_wb_cti_o, m_wb_bte_o,
m_wb_cti_o, m_wb_bte_o,
`endif
 
//TX
mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
//TX
mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
 
//RX
mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i,
//RX
mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i,
mcrs_pad_i,
// MIIM
mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o,
// MIIM
mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o,
 
int_o
int_o
 
// Bist
// Bist
`ifdef ETH_BIST
,
// debug chain signals
mbist_si_i, // bist scan serial in
mbist_so_o, // bist scan serial out
mbist_ctrl_i // bist chain shift control
,
// debug chain signals
mbist_si_i, // bist scan serial in
mbist_so_o, // bist scan serial out
mbist_ctrl_i // bist chain shift control
`endif
 
);
);
 
 
parameter Tp = 1;
 
// WISHBONE common
input wb_clk_i; // WISHBONE clock
input wb_rst_i; // WISHBONE reset
input [31:0] wb_dat_i; // WISHBONE data input
output [31:0] wb_dat_o; // WISHBONE data output
output wb_err_o; // WISHBONE error output
 
// WISHBONE common
input wb_clk_i; // WISHBONE clock
input wb_rst_i; // WISHBONE reset
input [31:0] wb_dat_i; // WISHBONE data input
output [31:0] wb_dat_o; // WISHBONE data output
output wb_err_o; // WISHBONE error output
// WISHBONE slave
input [11:2] wb_adr_i; // WISHBONE address input
input [3:0] wb_sel_i; // WISHBONE byte select input
input wb_we_i; // WISHBONE write enable input
input wb_cyc_i; // WISHBONE cycle input
input wb_stb_i; // WISHBONE strobe input
output wb_ack_o; // WISHBONE acknowledge output
 
// WISHBONE slave
input [11:2] wb_adr_i; // WISHBONE address input
input [3:0] wb_sel_i; // WISHBONE byte select input
input wb_we_i; // WISHBONE write enable input
input wb_cyc_i; // WISHBONE cycle input
input wb_stb_i; // WISHBONE strobe input
output wb_ack_o; // WISHBONE acknowledge output
// WISHBONE master
output [31:0] m_wb_adr_o;
output [3:0] m_wb_sel_o;
output m_wb_we_o;
input [31:0] m_wb_dat_i;
output [31:0] m_wb_dat_o;
output m_wb_cyc_o;
output m_wb_stb_o;
input m_wb_ack_i;
input m_wb_err_i;
 
// WISHBONE master
output [31:0] m_wb_adr_o;
output [3:0] m_wb_sel_o;
output m_wb_we_o;
input [31:0] m_wb_dat_i;
output [31:0] m_wb_dat_o;
output m_wb_cyc_o;
output m_wb_stb_o;
input m_wb_ack_i;
input m_wb_err_i;
wire [29:0] m_wb_adr_tmp;
 
wire [29:0] m_wb_adr_tmp;
 
`ifdef ETH_WISHBONE_B3
output [2:0] m_wb_cti_o; // Cycle Type Identifier
output [1:0] m_wb_bte_o; // Burst Type Extension
output [2:0] m_wb_cti_o; // Cycle Type Identifier
output [1:0] m_wb_bte_o; // Burst Type Extension
`endif
 
// Tx
input mtx_clk_pad_i; // Transmit clock (from PHY)
output [3:0] mtxd_pad_o; // Transmit nibble (to PHY)
output mtxen_pad_o; // Transmit enable (to PHY)
output mtxerr_pad_o; // Transmit error (to PHY)
// Tx
input mtx_clk_pad_i; // Transmit clock (from PHY)
output [3:0] mtxd_pad_o; // Transmit nibble (to PHY)
output mtxen_pad_o; // Transmit enable (to PHY)
output mtxerr_pad_o; // Transmit error (to PHY)
 
// Rx
input mrx_clk_pad_i; // Receive clock (from PHY)
input [3:0] mrxd_pad_i; // Receive nibble (from PHY)
input mrxdv_pad_i; // Receive data valid (from PHY)
input mrxerr_pad_i; // Receive data error (from PHY)
// Rx
input mrx_clk_pad_i; // Receive clock (from PHY)
input [3:0] mrxd_pad_i; // Receive nibble (from PHY)
input mrxdv_pad_i; // Receive data valid (from PHY)
input mrxerr_pad_i; // Receive data error (from PHY)
 
// Common Tx and Rx
input mcoll_pad_i; // Collision (from PHY)
input mcrs_pad_i; // Carrier sense (from PHY)
// Common Tx and Rx
input mcoll_pad_i; // Collision (from PHY)
input mcrs_pad_i; // Carrier sense (from PHY)
 
// MII Management interface
input md_pad_i; // MII data input (from I/O cell)
output mdc_pad_o; // MII Management data clock (to PHY)
output md_pad_o; // MII data output (to I/O cell)
output md_padoe_o; // MII data output enable (to I/O cell)
// MII Management interface
input md_pad_i; // MII data input (from I/O cell)
output mdc_pad_o; // MII Management data clock (to PHY)
output md_pad_o; // MII data output (to I/O cell)
output md_padoe_o; // MII data output enable (to I/O cell)
 
output int_o; // Interrupt output
output int_o; // Interrupt output
 
// Bist
// Bist
`ifdef ETH_BIST
input mbist_si_i; // bist scan serial in
output mbist_so_o; // bist scan serial out
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
input mbist_si_i; // bist scan serial in
output mbist_so_o; // bist scan serial out
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
`endif
 
`ifdef WISHBONE_DEBUG
wire [31:0] wb_dbg_dat0;
wire [31:0] wb_dbg_dat0;
`endif
 
wire [7:0] r_ClkDiv;
wire r_MiiNoPre;
wire [15:0] r_CtrlData;
wire [4:0] r_FIAD;
wire [4:0] r_RGAD;
wire r_WCtrlData;
wire r_RStat;
wire r_ScanStat;
wire NValid_stat;
wire Busy_stat;
wire LinkFail;
wire [15:0] Prsd; // Read Status Data (data read from the PHY)
wire WCtrlDataStart;
wire RStatStart;
wire UpdateMIIRX_DATAReg;
wire [7:0] r_ClkDiv;
wire r_MiiNoPre;
wire [15:0] r_CtrlData;
wire [4:0] r_FIAD;
wire [4:0] r_RGAD;
wire r_WCtrlData;
wire r_RStat;
wire r_ScanStat;
wire NValid_stat;
wire Busy_stat;
wire LinkFail;
wire [15:0] Prsd; // Read Status Data (data read
// from the PHY)
wire WCtrlDataStart;
wire RStatStart;
wire UpdateMIIRX_DATAReg;
 
wire TxStartFrm;
wire TxEndFrm;
wire TxUsedData;
wire [7:0] TxData;
wire TxRetry;
wire TxAbort;
wire TxUnderRun;
wire TxDone;
wire TxStartFrm;
wire TxEndFrm;
wire TxUsedData;
wire [7:0] TxData;
wire TxRetry;
wire TxAbort;
wire TxUnderRun;
wire TxDone;
 
 
reg WillSendControlFrame_sync1;
reg WillSendControlFrame_sync2;
reg WillSendControlFrame_sync3;
reg RstTxPauseRq;
reg WillSendControlFrame_sync1;
reg WillSendControlFrame_sync2;
reg WillSendControlFrame_sync3;
reg RstTxPauseRq;
 
reg TxPauseRq_sync1;
reg TxPauseRq_sync2;
reg TxPauseRq_sync3;
reg TPauseRq;
reg TxPauseRq_sync1;
reg TxPauseRq_sync2;
reg TxPauseRq_sync3;
reg TPauseRq;
 
 
// Connecting Miim module
eth_miim miim1
(
.Clk(wb_clk_i), .Reset(wb_rst_i), .Divider(r_ClkDiv),
.NoPre(r_MiiNoPre), .CtrlData(r_CtrlData), .Rgad(r_RGAD),
.Fiad(r_FIAD), .WCtrlData(r_WCtrlData), .RStat(r_RStat),
.ScanStat(r_ScanStat), .Mdi(md_pad_i), .Mdo(md_pad_o),
.MdoEn(md_padoe_o), .Mdc(mdc_pad_o), .Busy(Busy_stat),
.Prsd(Prsd), .LinkFail(LinkFail), .Nvalid(NValid_stat),
.WCtrlDataStart(WCtrlDataStart), .RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg)
);
// Connecting Miim module
eth_miim miim1
(
.Clk(wb_clk_i),
.Reset(wb_rst_i),
.Divider(r_ClkDiv),
.NoPre(r_MiiNoPre),
.CtrlData(r_CtrlData),
.Rgad(r_RGAD),
.Fiad(r_FIAD),
.WCtrlData(r_WCtrlData),
.RStat(r_RStat),
.ScanStat(r_ScanStat),
.Mdi(md_pad_i),
.Mdo(md_pad_o),
.MdoEn(md_padoe_o),
.Mdc(mdc_pad_o),
.Busy(Busy_stat),
.Prsd(Prsd),
.LinkFail(LinkFail),
.Nvalid(NValid_stat),
.WCtrlDataStart(WCtrlDataStart),
.RStatStart(RStatStart),
.UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg)
);
 
 
 
 
wire [3:0] RegCs; // Connected to registers
wire [31:0] RegDataOut; // Multiplexed to wb_dat_o
wire r_RecSmall; // Receive small frames
wire r_LoopBck; // Loopback
wire r_TxEn; // Tx Enable
wire r_RxEn; // Rx Enable
wire [3:0] RegCs; // Connected to registers
wire [31:0] RegDataOut; // Multiplexed to wb_dat_o
wire r_RecSmall; // Receive small frames
wire r_LoopBck; // Loopback
wire r_TxEn; // Tx Enable
wire r_RxEn; // Rx Enable
 
wire MRxDV_Lb; // Muxed MII receive data valid
wire MRxErr_Lb; // Muxed MII Receive Error
wire [3:0] MRxD_Lb; // Muxed MII Receive Data
wire Transmitting; // Indication that TxEthMAC is transmitting
wire r_HugEn; // Huge packet enable
wire r_DlyCrcEn; // Delayed CRC enabled
wire [15:0] r_MaxFL; // Maximum frame length
wire MRxDV_Lb; // Muxed MII receive data valid
wire MRxErr_Lb; // Muxed MII Receive Error
wire [3:0] MRxD_Lb; // Muxed MII Receive Data
wire Transmitting; // Indication that TxEthMAC is transmitting
wire r_HugEn; // Huge packet enable
wire r_DlyCrcEn; // Delayed CRC enabled
wire [15:0] r_MaxFL; // Maximum frame length
 
wire [15:0] r_MinFL; // Minimum frame length
wire ShortFrame;
wire DribbleNibble; // Extra nibble received
wire ReceivedPacketTooBig; // Received packet is too big
wire [47:0] r_MAC; // MAC address
wire LoadRxStatus; // Rx status was loaded
wire [31:0] r_HASH0; // HASH table, lower 4 bytes
wire [31:0] r_HASH1; // HASH table, upper 4 bytes
wire [7:0] r_TxBDNum; // Receive buffer descriptor number
wire [6:0] r_IPGT; //
wire [6:0] r_IPGR1; //
wire [6:0] r_IPGR2; //
wire [5:0] r_CollValid; //
wire [15:0] r_TxPauseTV; // Transmit PAUSE value
wire r_TxPauseRq; // Transmit PAUSE request
wire [15:0] r_MinFL; // Minimum frame length
wire ShortFrame;
wire DribbleNibble; // Extra nibble received
wire ReceivedPacketTooBig; // Received packet is too big
wire [47:0] r_MAC; // MAC address
wire LoadRxStatus; // Rx status was loaded
wire [31:0] r_HASH0; // HASH table, lower 4 bytes
wire [31:0] r_HASH1; // HASH table, upper 4 bytes
wire [7:0] r_TxBDNum; // Receive buffer descriptor number
wire [6:0] r_IPGT; //
wire [6:0] r_IPGR1; //
wire [6:0] r_IPGR2; //
wire [5:0] r_CollValid; //
wire [15:0] r_TxPauseTV; // Transmit PAUSE value
wire r_TxPauseRq; // Transmit PAUSE request
 
wire [3:0] r_MaxRet; //
wire r_NoBckof; //
wire r_ExDfrEn; //
wire r_TxFlow; // Tx flow control enable
wire r_IFG; // Minimum interframe gap for incoming packets
wire [3:0] r_MaxRet; //
wire r_NoBckof; //
wire r_ExDfrEn; //
wire r_TxFlow; // Tx flow control enable
wire r_IFG; // Minimum interframe gap for incoming packets
 
wire TxB_IRQ; // Interrupt Tx Buffer
wire TxE_IRQ; // Interrupt Tx Error
wire RxB_IRQ; // Interrupt Rx Buffer
wire RxE_IRQ; // Interrupt Rx Error
wire Busy_IRQ; // Interrupt Busy (lack of buffers)
wire TxB_IRQ; // Interrupt Tx Buffer
wire TxE_IRQ; // Interrupt Tx Error
wire RxB_IRQ; // Interrupt Rx Buffer
wire RxE_IRQ; // Interrupt Rx Error
wire Busy_IRQ; // Interrupt Busy (lack of buffers)
 
//wire DWord;
wire ByteSelected;
wire BDAck;
wire [31:0] BD_WB_DAT_O; // wb_dat_o that comes from the Wishbone module (for buffer descriptors read/write)
wire [3:0] BDCs; // Buffer descriptor CS
wire CsMiss; // When access to the address between 0x800 and 0xfff occurs, acknowledge is set
// but data is not valid.
wire r_Pad;
wire r_CrcEn;
wire r_FullD;
wire r_Pro;
wire r_Bro;
wire r_NoPre;
wire r_RxFlow;
wire r_PassAll;
wire TxCtrlEndFrm;
wire StartTxDone;
wire SetPauseTimer;
wire TxUsedDataIn;
wire TxDoneIn;
wire TxAbortIn;
wire PerPacketPad;
wire PadOut;
wire PerPacketCrcEn;
wire CrcEnOut;
wire TxStartFrmOut;
wire TxEndFrmOut;
wire ReceivedPauseFrm;
wire ControlFrmAddressOK;
wire RxStatusWriteLatched_sync2;
wire LateCollision;
wire DeferIndication;
wire LateCollLatched;
wire DeferLatched;
wire RstDeferLatched;
wire CarrierSenseLost;
//wire DWord;
wire ByteSelected;
wire BDAck;
wire [31:0] BD_WB_DAT_O; // wb_dat_o that comes from the Wishbone module (for buffer descriptors read/write)
wire [3:0] BDCs; // Buffer descriptor CS
wire CsMiss; // When access to the address between 0x800 and 0xfff occurs, acknowledge is set
// but data is not valid.
wire r_Pad;
wire r_CrcEn;
wire r_FullD;
wire r_Pro;
wire r_Bro;
wire r_NoPre;
wire r_RxFlow;
wire r_PassAll;
wire TxCtrlEndFrm;
wire StartTxDone;
wire SetPauseTimer;
wire TxUsedDataIn;
wire TxDoneIn;
wire TxAbortIn;
wire PerPacketPad;
wire PadOut;
wire PerPacketCrcEn;
wire CrcEnOut;
wire TxStartFrmOut;
wire TxEndFrmOut;
wire ReceivedPauseFrm;
wire ControlFrmAddressOK;
wire RxStatusWriteLatched_sync2;
wire LateCollision;
wire DeferIndication;
wire LateCollLatched;
wire DeferLatched;
wire RstDeferLatched;
wire CarrierSenseLost;
 
wire temp_wb_ack_o;
wire [31:0] temp_wb_dat_o;
wire temp_wb_err_o;
wire temp_wb_ack_o;
wire [31:0] temp_wb_dat_o;
wire temp_wb_err_o;
 
`ifdef ETH_REGISTERED_OUTPUTS
reg temp_wb_ack_o_reg;
reg [31:0] temp_wb_dat_o_reg;
reg temp_wb_err_o_reg;
reg temp_wb_ack_o_reg;
reg [31:0] temp_wb_dat_o_reg;
reg temp_wb_err_o_reg;
`endif
 
//assign DWord = &wb_sel_i;
assign ByteSelected = |wb_sel_i;
assign RegCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[3]; // 0x0 - 0x3FF
assign RegCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[2]; // 0x0 - 0x3FF
assign RegCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[1]; // 0x0 - 0x3FF
assign RegCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[0]; // 0x0 - 0x3FF
assign BDCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[3]; // 0x400 - 0x7FF
assign BDCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[2]; // 0x400 - 0x7FF
assign BDCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[1]; // 0x400 - 0x7FF
assign BDCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[0]; // 0x400 - 0x7FF
assign CsMiss = wb_stb_i & wb_cyc_i & ByteSelected & wb_adr_i[11]; // 0x800 - 0xfFF
assign temp_wb_dat_o = ((|RegCs) & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~ByteSelected | CsMiss);
//assign DWord = &wb_sel_i;
assign ByteSelected = |wb_sel_i;
assign RegCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[3]; // 0x0 - 0x3FF
assign RegCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[2]; // 0x0 - 0x3FF
assign RegCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[1]; // 0x0 - 0x3FF
assign RegCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[0]; // 0x0 - 0x3FF
assign BDCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[3]; // 0x400 - 0x7FF
assign BDCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[2]; // 0x400 - 0x7FF
assign BDCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[1]; // 0x400 - 0x7FF
assign BDCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[0]; // 0x400 - 0x7FF
assign CsMiss = wb_stb_i & wb_cyc_i & ByteSelected & wb_adr_i[11]; // 0x800 - 0xfFF
assign temp_wb_dat_o = ((|RegCs) & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~ByteSelected | CsMiss);
 
`ifdef ETH_REGISTERED_OUTPUTS
assign wb_ack_o = temp_wb_ack_o_reg;
assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
assign wb_err_o = temp_wb_err_o_reg;
assign wb_ack_o = temp_wb_ack_o_reg;
assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
assign wb_err_o = temp_wb_err_o_reg;
`else
assign wb_ack_o = temp_wb_ack_o;
assign wb_dat_o[31:0] = temp_wb_dat_o;
assign wb_err_o = temp_wb_err_o;
assign wb_ack_o = temp_wb_ack_o;
assign wb_dat_o[31:0] = temp_wb_dat_o;
assign wb_err_o = temp_wb_err_o;
`endif
 
`ifdef ETH_AVALON_BUS
// As Avalon has no corresponding "error" signal, I (erroneously) will
// send an ack to Avalon, even when accessing undefined memory. This
// is a grey area in Avalon vs. Wishbone specs: My understanding
// is that Avalon expects all memory addressable by the addr bus feeding
// a slave to be, at the very minimum, readable.
assign temp_wb_ack_o = (|RegCs) | BDAck | CsMiss;
// As Avalon has no corresponding "error" signal, I (erroneously) will
// send an ack to Avalon, even when accessing undefined memory. This
// is a grey area in Avalon vs. Wishbone specs: My understanding
// is that Avalon expects all memory addressable by the addr bus feeding
// a slave to be, at the very minimum, readable.
assign temp_wb_ack_o = (|RegCs) | BDAck | CsMiss;
`else // WISHBONE
assign temp_wb_ack_o = (|RegCs) | BDAck;
assign temp_wb_ack_o = (|RegCs) | BDAck;
`endif
 
`ifdef ETH_REGISTERED_OUTPUTS
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
temp_wb_ack_o_reg <= 1'b0;
temp_wb_dat_o_reg <= 32'h0;
temp_wb_err_o_reg <= 1'b0;
end
else
begin
temp_wb_ack_o_reg <= temp_wb_ack_o & ~temp_wb_ack_o_reg;
temp_wb_dat_o_reg <= temp_wb_dat_o;
temp_wb_err_o_reg <= temp_wb_err_o & ~temp_wb_err_o_reg;
end
end
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
temp_wb_ack_o_reg <= 1'b0;
temp_wb_dat_o_reg <= 32'h0;
temp_wb_err_o_reg <= 1'b0;
end
else
begin
temp_wb_ack_o_reg <= temp_wb_ack_o & ~temp_wb_ack_o_reg;
temp_wb_dat_o_reg <= temp_wb_dat_o;
temp_wb_err_o_reg <= temp_wb_err_o & ~temp_wb_err_o_reg;
end
end
`endif
 
 
// Connecting Ethernet registers
eth_registers ethreg1
(
.DataIn(wb_dat_i), .Address(wb_adr_i[9:2]), .Rw(wb_we_i),
.Cs(RegCs), .Clk(wb_clk_i), .Reset(wb_rst_i),
.DataOut(RegDataOut), .r_RecSmall(r_RecSmall),
.r_Pad(r_Pad), .r_HugEn(r_HugEn), .r_CrcEn(r_CrcEn),
.r_DlyCrcEn(r_DlyCrcEn), .r_FullD(r_FullD),
.r_ExDfrEn(r_ExDfrEn), .r_NoBckof(r_NoBckof), .r_LoopBck(r_LoopBck),
.r_IFG(r_IFG), .r_Pro(r_Pro), .r_Iam(),
.r_Bro(r_Bro), .r_NoPre(r_NoPre), .r_TxEn(r_TxEn),
.r_RxEn(r_RxEn), .Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ),
.RxB_IRQ(RxB_IRQ), .TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
.r_IPGT(r_IPGT),
.r_IPGR1(r_IPGR1), .r_IPGR2(r_IPGR2), .r_MinFL(r_MinFL),
.r_MaxFL(r_MaxFL), .r_MaxRet(r_MaxRet), .r_CollValid(r_CollValid),
.r_TxFlow(r_TxFlow), .r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll),
.r_MiiNoPre(r_MiiNoPre), .r_ClkDiv(r_ClkDiv),
.r_WCtrlData(r_WCtrlData), .r_RStat(r_RStat), .r_ScanStat(r_ScanStat),
.r_RGAD(r_RGAD), .r_FIAD(r_FIAD), .r_CtrlData(r_CtrlData),
.NValid_stat(NValid_stat), .Busy_stat(Busy_stat),
.LinkFail(LinkFail), .r_MAC(r_MAC), .WCtrlDataStart(WCtrlDataStart),
.RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg), .Prsd(Prsd),
.r_TxBDNum(r_TxBDNum), .int_o(int_o),
.r_HASH0(r_HASH0), .r_HASH1(r_HASH1), .r_TxPauseRq(r_TxPauseRq),
.r_TxPauseTV(r_TxPauseTV), .RstTxPauseRq(RstTxPauseRq), .TxCtrlEndFrm(TxCtrlEndFrm),
.StartTxDone(StartTxDone), .TxClk(mtx_clk_pad_i), .RxClk(mrx_clk_pad_i),
.dbg_dat(wb_dbg_dat0),
.SetPauseTimer(SetPauseTimer)
);
// Connecting Ethernet registers
eth_registers ethreg1
(
.DataIn(wb_dat_i),
.Address(wb_adr_i[9:2]),
.Rw(wb_we_i),
.Cs(RegCs),
.Clk(wb_clk_i),
.Reset(wb_rst_i),
.DataOut(RegDataOut),
.r_RecSmall(r_RecSmall),
.r_Pad(r_Pad),
.r_HugEn(r_HugEn),
.r_CrcEn(r_CrcEn),
.r_DlyCrcEn(r_DlyCrcEn),
.r_FullD(r_FullD),
.r_ExDfrEn(r_ExDfrEn),
.r_NoBckof(r_NoBckof),
.r_LoopBck(r_LoopBck),
.r_IFG(r_IFG),
.r_Pro(r_Pro),
.r_Iam(),
.r_Bro(r_Bro),
.r_NoPre(r_NoPre),
.r_TxEn(r_TxEn),
.r_RxEn(r_RxEn),
.Busy_IRQ(Busy_IRQ),
.RxE_IRQ(RxE_IRQ),
.RxB_IRQ(RxB_IRQ),
.TxE_IRQ(TxE_IRQ),
.TxB_IRQ(TxB_IRQ),
.r_IPGT(r_IPGT),
.r_IPGR1(r_IPGR1),
.r_IPGR2(r_IPGR2),
.r_MinFL(r_MinFL),
.r_MaxFL(r_MaxFL),
.r_MaxRet(r_MaxRet),
.r_CollValid(r_CollValid),
.r_TxFlow(r_TxFlow),
.r_RxFlow(r_RxFlow),
.r_PassAll(r_PassAll),
.r_MiiNoPre(r_MiiNoPre),
.r_ClkDiv(r_ClkDiv),
.r_WCtrlData(r_WCtrlData),
.r_RStat(r_RStat),
.r_ScanStat(r_ScanStat),
.r_RGAD(r_RGAD),
.r_FIAD(r_FIAD),
.r_CtrlData(r_CtrlData),
.NValid_stat(NValid_stat),
.Busy_stat(Busy_stat),
.LinkFail(LinkFail),
.r_MAC(r_MAC),
.WCtrlDataStart(WCtrlDataStart),
.RStatStart(RStatStart),
.UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg),
.Prsd(Prsd),
.r_TxBDNum(r_TxBDNum),
.int_o(int_o),
.r_HASH0(r_HASH0),
.r_HASH1(r_HASH1),
.r_TxPauseRq(r_TxPauseRq),
.r_TxPauseTV(r_TxPauseTV),
.RstTxPauseRq(RstTxPauseRq),
.TxCtrlEndFrm(TxCtrlEndFrm),
.StartTxDone(StartTxDone),
.TxClk(mtx_clk_pad_i),
.RxClk(mrx_clk_pad_i),
.dbg_dat(wb_dbg_dat0),
.SetPauseTimer(SetPauseTimer)
);
 
 
 
wire [7:0] RxData;
wire RxValid;
wire RxStartFrm;
wire RxEndFrm;
wire RxAbort;
wire [7:0] RxData;
wire RxValid;
wire RxStartFrm;
wire RxEndFrm;
wire RxAbort;
 
wire WillTransmit; // Will transmit (to RxEthMAC)
wire ResetCollision; // Reset Collision (for synchronizing collision)
wire [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC)
wire WillSendControlFrame;
wire ReceiveEnd;
wire ReceivedPacketGood;
wire ReceivedLengthOK;
wire InvalidSymbol;
wire LatchedCrcError;
wire RxLateCollision;
wire [3:0] RetryCntLatched;
wire [3:0] RetryCnt;
wire StartTxAbort;
wire MaxCollisionOccured;
wire RetryLimit;
wire StatePreamble;
wire [1:0] StateData;
wire WillTransmit; // Will transmit (to RxEthMAC)
wire ResetCollision; // Reset Collision (for synchronizing
// collision)
wire [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC)
wire WillSendControlFrame;
wire ReceiveEnd;
wire ReceivedPacketGood;
wire ReceivedLengthOK;
wire InvalidSymbol;
wire LatchedCrcError;
wire RxLateCollision;
wire [3:0] RetryCntLatched;
wire [3:0] RetryCnt;
wire StartTxAbort;
wire MaxCollisionOccured;
wire RetryLimit;
wire StatePreamble;
wire [1:0] StateData;
 
// Connecting MACControl
eth_maccontrol maccontrol1
(
.MTxClk(mtx_clk_pad_i), .TPauseRq(TPauseRq),
.TxPauseTV(r_TxPauseTV), .TxDataIn(TxData),
.TxStartFrmIn(TxStartFrm), .TxEndFrmIn(TxEndFrm),
.TxUsedDataIn(TxUsedDataIn), .TxDoneIn(TxDoneIn),
.TxAbortIn(TxAbortIn), .MRxClk(mrx_clk_pad_i),
.RxData(RxData), .RxValid(RxValid),
.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood),
.TxFlow(r_TxFlow),
.RxFlow(r_RxFlow), .DlyCrcEn(r_DlyCrcEn),
.MAC(r_MAC), .PadIn(r_Pad | PerPacketPad),
.PadOut(PadOut), .CrcEnIn(r_CrcEn | PerPacketCrcEn),
.CrcEnOut(CrcEnOut), .TxReset(wb_rst_i),
.RxReset(wb_rst_i), .ReceivedLengthOK(ReceivedLengthOK),
.TxDataOut(TxDataOut), .TxStartFrmOut(TxStartFrmOut),
.TxEndFrmOut(TxEndFrmOut), .TxUsedDataOut(TxUsedData),
.TxDoneOut(TxDone), .TxAbortOut(TxAbort),
.WillSendControlFrame(WillSendControlFrame), .TxCtrlEndFrm(TxCtrlEndFrm),
.ReceivedPauseFrm(ReceivedPauseFrm), .ControlFrmAddressOK(ControlFrmAddressOK),
.SetPauseTimer(SetPauseTimer),
.RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2), .r_PassAll(r_PassAll)
);
// Connecting MACControl
eth_maccontrol maccontrol1
(
.MTxClk(mtx_clk_pad_i),
.TPauseRq(TPauseRq),
.TxPauseTV(r_TxPauseTV),
.TxDataIn(TxData),
.TxStartFrmIn(TxStartFrm),
.TxEndFrmIn(TxEndFrm),
.TxUsedDataIn(TxUsedDataIn),
.TxDoneIn(TxDoneIn),
.TxAbortIn(TxAbortIn),
.MRxClk(mrx_clk_pad_i),
.RxData(RxData),
.RxValid(RxValid),
.RxStartFrm(RxStartFrm),
.RxEndFrm(RxEndFrm),
.ReceiveEnd(ReceiveEnd),
.ReceivedPacketGood(ReceivedPacketGood),
.TxFlow(r_TxFlow),
.RxFlow(r_RxFlow),
.DlyCrcEn(r_DlyCrcEn),
.MAC(r_MAC),
.PadIn(r_Pad | PerPacketPad),
.PadOut(PadOut),
.CrcEnIn(r_CrcEn | PerPacketCrcEn),
.CrcEnOut(CrcEnOut),
.TxReset(wb_rst_i),
.RxReset(wb_rst_i),
.ReceivedLengthOK(ReceivedLengthOK),
.TxDataOut(TxDataOut),
.TxStartFrmOut(TxStartFrmOut),
.TxEndFrmOut(TxEndFrmOut),
.TxUsedDataOut(TxUsedData),
.TxDoneOut(TxDone),
.TxAbortOut(TxAbort),
.WillSendControlFrame(WillSendControlFrame),
.TxCtrlEndFrm(TxCtrlEndFrm),
.ReceivedPauseFrm(ReceivedPauseFrm),
.ControlFrmAddressOK(ControlFrmAddressOK),
.SetPauseTimer(SetPauseTimer),
.RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2),
.r_PassAll(r_PassAll)
);
 
 
 
wire TxCarrierSense; // Synchronized CarrierSense (to Tx clock)
wire Collision; // Synchronized Collision
wire TxCarrierSense; // Synchronized CarrierSense (to Tx
// clock)
wire Collision; // Synchronized Collision
 
reg CarrierSense_Tx1;
reg CarrierSense_Tx2;
reg Collision_Tx1;
reg Collision_Tx2;
reg CarrierSense_Tx1;
reg CarrierSense_Tx2;
reg Collision_Tx1;
reg Collision_Tx2;
 
reg RxEnSync; // Synchronized Receive Enable
reg WillTransmit_q;
reg WillTransmit_q2;
reg RxEnSync; // Synchronized Receive Enable
reg WillTransmit_q;
reg WillTransmit_q2;
 
 
 
// Muxed MII receive data valid
assign MRxDV_Lb = r_LoopBck? mtxen_pad_o : mrxdv_pad_i & RxEnSync;
// Muxed MII receive data valid
assign MRxDV_Lb = r_LoopBck? mtxen_pad_o : mrxdv_pad_i & RxEnSync;
 
// Muxed MII Receive Error
assign MRxErr_Lb = r_LoopBck? mtxerr_pad_o : mrxerr_pad_i & RxEnSync;
// Muxed MII Receive Error
assign MRxErr_Lb = r_LoopBck? mtxerr_pad_o : mrxerr_pad_i & RxEnSync;
 
// Muxed MII Receive Data
assign MRxD_Lb[3:0] = r_LoopBck? mtxd_pad_o[3:0] : mrxd_pad_i[3:0];
// Muxed MII Receive Data
assign MRxD_Lb[3:0] = r_LoopBck? mtxd_pad_o[3:0] : mrxd_pad_i[3:0];
 
 
 
// Connecting TxEthMAC
eth_txethmac txethmac1
(
.MTxClk(mtx_clk_pad_i), .Reset(wb_rst_i), .CarrierSense(TxCarrierSense),
.Collision(Collision), .TxData(TxDataOut), .TxStartFrm(TxStartFrmOut),
.TxUnderRun(TxUnderRun), .TxEndFrm(TxEndFrmOut), .Pad(PadOut),
.MinFL(r_MinFL), .CrcEn(CrcEnOut), .FullD(r_FullD),
.HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn), .IPGT(r_IPGT),
.IPGR1(r_IPGR1), .IPGR2(r_IPGR2), .CollValid(r_CollValid),
.MaxRet(r_MaxRet), .NoBckof(r_NoBckof), .ExDfrEn(r_ExDfrEn),
.MaxFL(r_MaxFL), .MTxEn(mtxen_pad_o), .MTxD(mtxd_pad_o),
.MTxErr(mtxerr_pad_o), .TxUsedData(TxUsedDataIn), .TxDone(TxDoneIn),
.TxRetry(TxRetry), .TxAbort(TxAbortIn), .WillTransmit(WillTransmit),
.ResetCollision(ResetCollision), .RetryCnt(RetryCnt), .StartTxDone(StartTxDone),
.StartTxAbort(StartTxAbort), .MaxCollisionOccured(MaxCollisionOccured), .LateCollision(LateCollision),
.DeferIndication(DeferIndication), .StatePreamble(StatePreamble), .StateData(StateData)
);
// Connecting TxEthMAC
eth_txethmac txethmac1
(
.MTxClk(mtx_clk_pad_i),
.Reset(wb_rst_i),
.CarrierSense(TxCarrierSense),
.Collision(Collision),
.TxData(TxDataOut),
.TxStartFrm(TxStartFrmOut),
.TxUnderRun(TxUnderRun),
.TxEndFrm(TxEndFrmOut),
.Pad(PadOut),
.MinFL(r_MinFL),
.CrcEn(CrcEnOut),
.FullD(r_FullD),
.HugEn(r_HugEn),
.DlyCrcEn(r_DlyCrcEn),
.IPGT(r_IPGT),
.IPGR1(r_IPGR1),
.IPGR2(r_IPGR2),
.CollValid(r_CollValid),
.MaxRet(r_MaxRet),
.NoBckof(r_NoBckof),
.ExDfrEn(r_ExDfrEn),
.MaxFL(r_MaxFL),
.MTxEn(mtxen_pad_o),
.MTxD(mtxd_pad_o),
.MTxErr(mtxerr_pad_o),
.TxUsedData(TxUsedDataIn),
.TxDone(TxDoneIn),
.TxRetry(TxRetry),
.TxAbort(TxAbortIn),
.WillTransmit(WillTransmit),
.ResetCollision(ResetCollision),
.RetryCnt(RetryCnt),
.StartTxDone(StartTxDone),
.StartTxAbort(StartTxAbort),
.MaxCollisionOccured(MaxCollisionOccured),
.LateCollision(LateCollision),
.DeferIndication(DeferIndication),
.StatePreamble(StatePreamble),
.StateData(StateData)
);
 
 
 
 
wire [15:0] RxByteCnt;
wire RxByteCntEq0;
wire RxByteCntGreat2;
wire RxByteCntMaxFrame;
wire RxCrcError;
wire RxStateIdle;
wire RxStatePreamble;
wire RxStateSFD;
wire [1:0] RxStateData;
wire AddressMiss;
wire [15:0] RxByteCnt;
wire RxByteCntEq0;
wire RxByteCntGreat2;
wire RxByteCntMaxFrame;
wire RxCrcError;
wire RxStateIdle;
wire RxStatePreamble;
wire RxStateSFD;
wire [1:0] RxStateData;
wire AddressMiss;
 
 
 
// Connecting RxEthMAC
eth_rxethmac rxethmac1
(
.MRxClk(mrx_clk_pad_i), .MRxDV(MRxDV_Lb), .MRxD(MRxD_Lb),
.Transmitting(Transmitting), .HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn),
.MaxFL(r_MaxFL), .r_IFG(r_IFG), .Reset(wb_rst_i),
.RxData(RxData), .RxValid(RxValid), .RxStartFrm(RxStartFrm),
.RxEndFrm(RxEndFrm), .ByteCnt(RxByteCnt),
.ByteCntEq0(RxByteCntEq0), .ByteCntGreat2(RxByteCntGreat2), .ByteCntMaxFrame(RxByteCntMaxFrame),
.CrcError(RxCrcError), .StateIdle(RxStateIdle), .StatePreamble(RxStatePreamble),
.StateSFD(RxStateSFD), .StateData(RxStateData),
.MAC(r_MAC), .r_Pro(r_Pro), .r_Bro(r_Bro),
.r_HASH0(r_HASH0), .r_HASH1(r_HASH1), .RxAbort(RxAbort),
.AddressMiss(AddressMiss), .PassAll(r_PassAll), .ControlFrmAddressOK(ControlFrmAddressOK)
);
// Connecting RxEthMAC
eth_rxethmac rxethmac1
(
.MRxClk(mrx_clk_pad_i),
.MRxDV(MRxDV_Lb),
.MRxD(MRxD_Lb),
.Transmitting(Transmitting),
.HugEn(r_HugEn),
.DlyCrcEn(r_DlyCrcEn),
.MaxFL(r_MaxFL),
.r_IFG(r_IFG),
.Reset(wb_rst_i),
.RxData(RxData),
.RxValid(RxValid),
.RxStartFrm(RxStartFrm),
.RxEndFrm(RxEndFrm),
.ByteCnt(RxByteCnt),
.ByteCntEq0(RxByteCntEq0),
.ByteCntGreat2(RxByteCntGreat2),
.ByteCntMaxFrame(RxByteCntMaxFrame),
.CrcError(RxCrcError),
.StateIdle(RxStateIdle),
.StatePreamble(RxStatePreamble),
.StateSFD(RxStateSFD),
.StateData(RxStateData),
.MAC(r_MAC),
.r_Pro(r_Pro),
.r_Bro(r_Bro),
.r_HASH0(r_HASH0),
.r_HASH1(r_HASH1),
.RxAbort(RxAbort),
.AddressMiss(AddressMiss),
.PassAll(r_PassAll),
.ControlFrmAddressOK(ControlFrmAddressOK)
);
 
 
// MII Carrier Sense Synchronization
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
CarrierSense_Tx1 <= 1'b0;
CarrierSense_Tx2 <= 1'b0;
end
else
begin
CarrierSense_Tx1 <= mcrs_pad_i;
CarrierSense_Tx2 <= CarrierSense_Tx1;
end
end
// MII Carrier Sense Synchronization
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
CarrierSense_Tx1 <= 1'b0;
CarrierSense_Tx2 <= 1'b0;
end
else
begin
CarrierSense_Tx1 <= mcrs_pad_i;
CarrierSense_Tx2 <= CarrierSense_Tx1;
end
end
 
assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2;
assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2;
 
 
// MII Collision Synchronization
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
Collision_Tx1 <= 1'b0;
Collision_Tx2 <= 1'b0;
end
else
begin
Collision_Tx1 <= mcoll_pad_i;
if(ResetCollision)
Collision_Tx2 <= 1'b0;
else
if(Collision_Tx1)
Collision_Tx2 <= 1'b1;
end
end
// MII Collision Synchronization
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
Collision_Tx1 <= 1'b0;
Collision_Tx2 <= 1'b0;
end
else
begin
Collision_Tx1 <= mcoll_pad_i;
if(ResetCollision)
Collision_Tx2 <= 1'b0;
else
if(Collision_Tx1)
Collision_Tx2 <= 1'b1;
end
end
 
 
// Synchronized Collision
assign Collision = ~r_FullD & Collision_Tx2;
// Synchronized Collision
assign Collision = ~r_FullD & Collision_Tx2;
 
 
 
// Delayed WillTransmit
always @ (posedge mrx_clk_pad_i)
begin
WillTransmit_q <= WillTransmit;
WillTransmit_q2 <= WillTransmit_q;
end
// Delayed WillTransmit
always @ (posedge mrx_clk_pad_i)
begin
WillTransmit_q <= WillTransmit;
WillTransmit_q2 <= WillTransmit_q;
end
 
 
assign Transmitting = ~r_FullD & WillTransmit_q2;
assign Transmitting = ~r_FullD & WillTransmit_q2;
 
 
 
// Synchronized Receive Enable
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
RxEnSync <= 1'b0;
else
if(~mrxdv_pad_i)
RxEnSync <= r_RxEn;
end
// Synchronized Receive Enable
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
RxEnSync <= 1'b0;
else
if(~mrxdv_pad_i)
RxEnSync <= r_RxEn;
end
 
 
 
// Synchronizing WillSendControlFrame to WB_CLK;
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
WillSendControlFrame_sync1 <= 1'b0;
else
WillSendControlFrame_sync1 <= WillSendControlFrame;
end
// Synchronizing WillSendControlFrame to WB_CLK;
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
WillSendControlFrame_sync1 <= 1'b0;
else
WillSendControlFrame_sync1 <= WillSendControlFrame;
end
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
WillSendControlFrame_sync2 <= 1'b0;
else
WillSendControlFrame_sync2 <= WillSendControlFrame_sync1;
end
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
WillSendControlFrame_sync2 <= 1'b0;
else
WillSendControlFrame_sync2 <= WillSendControlFrame_sync1;
end
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
WillSendControlFrame_sync3 <= 1'b0;
else
WillSendControlFrame_sync3 <= WillSendControlFrame_sync2;
end
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
WillSendControlFrame_sync3 <= 1'b0;
else
WillSendControlFrame_sync3 <= WillSendControlFrame_sync2;
end
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
RstTxPauseRq <= 1'b0;
else
RstTxPauseRq <= WillSendControlFrame_sync2 & ~WillSendControlFrame_sync3;
end
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
RstTxPauseRq <= 1'b0;
else
RstTxPauseRq <= WillSendControlFrame_sync2 &
~WillSendControlFrame_sync3;
end
 
 
 
 
// TX Pause request Synchronization
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
TxPauseRq_sync1 <= 1'b0;
TxPauseRq_sync2 <= 1'b0;
TxPauseRq_sync3 <= 1'b0;
end
else
begin
TxPauseRq_sync1 <= (r_TxPauseRq & r_TxFlow);
TxPauseRq_sync2 <= TxPauseRq_sync1;
TxPauseRq_sync3 <= TxPauseRq_sync2;
end
end
// TX Pause request Synchronization
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
TxPauseRq_sync1 <= 1'b0;
TxPauseRq_sync2 <= 1'b0;
TxPauseRq_sync3 <= 1'b0;
end
else
begin
TxPauseRq_sync1 <= (r_TxPauseRq & r_TxFlow);
TxPauseRq_sync2 <= TxPauseRq_sync1;
TxPauseRq_sync3 <= TxPauseRq_sync2;
end
end
 
 
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
TPauseRq <= 1'b0;
else
TPauseRq <= TxPauseRq_sync2 & (~TxPauseRq_sync3);
end
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
TPauseRq <= 1'b0;
else
TPauseRq <= TxPauseRq_sync2 & (~TxPauseRq_sync3);
end
 
 
wire LatchedMRxErr;
reg RxAbort_latch;
reg RxAbort_sync1;
reg RxAbort_wb;
reg RxAbortRst_sync1;
reg RxAbortRst;
wire LatchedMRxErr;
reg RxAbort_latch;
reg RxAbort_sync1;
reg RxAbort_wb;
reg RxAbortRst_sync1;
reg RxAbortRst;
 
// Synchronizing RxAbort to the WISHBONE clock
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
RxAbort_latch <= 1'b0;
else if(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr & ~InvalidSymbol | (ReceivedPauseFrm & (~r_PassAll)))
RxAbort_latch <= 1'b1;
else if(RxAbortRst)
RxAbort_latch <= 1'b0;
end
// Synchronizing RxAbort to the WISHBONE clock
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
RxAbort_latch <= 1'b0;
else if(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr &
~InvalidSymbol | (ReceivedPauseFrm & (~r_PassAll)))
RxAbort_latch <= 1'b1;
else if(RxAbortRst)
RxAbort_latch <= 1'b0;
end
 
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
RxAbort_sync1 <= 1'b0;
RxAbort_wb <= 1'b0;
RxAbort_wb <= 1'b0;
end
else
begin
RxAbort_sync1 <= RxAbort_latch;
RxAbort_wb <= RxAbort_sync1;
end
end
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
RxAbort_sync1 <= 1'b0;
RxAbort_wb <= 1'b0;
RxAbort_wb <= 1'b0;
end
else
begin
RxAbort_sync1 <= RxAbort_latch;
RxAbort_wb <= RxAbort_sync1;
end
end
 
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
RxAbortRst_sync1 <= 1'b0;
RxAbortRst <= 1'b0;
end
else
begin
RxAbortRst_sync1 <= RxAbort_wb;
RxAbortRst <= RxAbortRst_sync1;
end
end
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
begin
if(wb_rst_i)
begin
RxAbortRst_sync1 <= 1'b0;
RxAbortRst <= 1'b0;
end
else
begin
RxAbortRst_sync1 <= RxAbort_wb;
RxAbortRst <= RxAbortRst_sync1;
end
end
 
 
 
// Connecting Wishbone module
eth_wishbone wishbone
(
.WB_CLK_I(wb_clk_i), .WB_DAT_I(wb_dat_i),
.WB_DAT_O(BD_WB_DAT_O),
// Connecting Wishbone module
eth_wishbone wishbone
(
.WB_CLK_I(wb_clk_i),
.WB_DAT_I(wb_dat_i),
.WB_DAT_O(BD_WB_DAT_O),
 
// WISHBONE slave
.WB_ADR_I(wb_adr_i[9:2]), .WB_WE_I(wb_we_i),
.BDCs(BDCs), .WB_ACK_O(BDAck),
// WISHBONE slave
.WB_ADR_I(wb_adr_i[9:2]),
.WB_WE_I(wb_we_i),
.BDCs(BDCs),
.WB_ACK_O(BDAck),
 
.Reset(wb_rst_i),
.Reset(wb_rst_i),
 
// WISHBONE master
.m_wb_adr_o(m_wb_adr_tmp), .m_wb_sel_o(m_wb_sel_o), .m_wb_we_o(m_wb_we_o),
.m_wb_dat_i(m_wb_dat_i), .m_wb_dat_o(m_wb_dat_o), .m_wb_cyc_o(m_wb_cyc_o),
.m_wb_stb_o(m_wb_stb_o), .m_wb_ack_i(m_wb_ack_i), .m_wb_err_i(m_wb_err_i),
// WISHBONE master
.m_wb_adr_o(m_wb_adr_tmp),
.m_wb_sel_o(m_wb_sel_o),
.m_wb_we_o(m_wb_we_o),
.m_wb_dat_i(m_wb_dat_i),
.m_wb_dat_o(m_wb_dat_o),
.m_wb_cyc_o(m_wb_cyc_o),
.m_wb_stb_o(m_wb_stb_o),
.m_wb_ack_i(m_wb_ack_i),
.m_wb_err_i(m_wb_err_i),
`ifdef ETH_WISHBONE_B3
.m_wb_cti_o(m_wb_cti_o), .m_wb_bte_o(m_wb_bte_o),
.m_wb_cti_o(m_wb_cti_o),
.m_wb_bte_o(m_wb_bte_o),
`endif
 
//TX
.MTxClk(mtx_clk_pad_i), .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm),
.TxUsedData(TxUsedData), .TxData(TxData),
.TxRetry(TxRetry), .TxAbort(TxAbort), .TxUnderRun(TxUnderRun),
.TxDone(TxDone),
.PerPacketCrcEn(PerPacketCrcEn), .PerPacketPad(PerPacketPad),
//TX
.MTxClk(mtx_clk_pad_i),
.TxStartFrm(TxStartFrm),
.TxEndFrm(TxEndFrm),
.TxUsedData(TxUsedData),
.TxData(TxData),
.TxRetry(TxRetry),
.TxAbort(TxAbort),
.TxUnderRun(TxUnderRun),
.TxDone(TxDone),
.PerPacketCrcEn(PerPacketCrcEn),
.PerPacketPad(PerPacketPad),
 
// Register
.r_TxEn(r_TxEn), .r_RxEn(r_RxEn), .r_TxBDNum(r_TxBDNum),
.r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll),
// Register
.r_TxEn(r_TxEn),
.r_RxEn(r_RxEn),
.r_TxBDNum(r_TxBDNum),
.r_RxFlow(r_RxFlow),
.r_PassAll(r_PassAll),
 
//RX
.MRxClk(mrx_clk_pad_i), .RxData(RxData), .RxValid(RxValid),
.RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
.Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ), .RxB_IRQ(RxB_IRQ),
.TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
//RX
.MRxClk(mrx_clk_pad_i),
.RxData(RxData),
.RxValid(RxValid),
.RxStartFrm(RxStartFrm),
.RxEndFrm(RxEndFrm),
.Busy_IRQ(Busy_IRQ),
.RxE_IRQ(RxE_IRQ),
.RxB_IRQ(RxB_IRQ),
.TxE_IRQ(TxE_IRQ),
.TxB_IRQ(TxB_IRQ),
 
.RxAbort(RxAbort_wb), .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2),
.RxAbort(RxAbort_wb),
.RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2),
 
.InvalidSymbol(InvalidSymbol), .LatchedCrcError(LatchedCrcError), .RxLength(RxByteCnt),
.RxLateCollision(RxLateCollision), .ShortFrame(ShortFrame), .DribbleNibble(DribbleNibble),
.ReceivedPacketTooBig(ReceivedPacketTooBig), .LoadRxStatus(LoadRxStatus), .RetryCntLatched(RetryCntLatched),
.RetryLimit(RetryLimit), .LateCollLatched(LateCollLatched), .DeferLatched(DeferLatched),
.RstDeferLatched(RstDeferLatched),
.CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood), .AddressMiss(AddressMiss),
.ReceivedPauseFrm(ReceivedPauseFrm)
.InvalidSymbol(InvalidSymbol),
.LatchedCrcError(LatchedCrcError),
.RxLength(RxByteCnt),
.RxLateCollision(RxLateCollision),
.ShortFrame(ShortFrame),
.DribbleNibble(DribbleNibble),
.ReceivedPacketTooBig(ReceivedPacketTooBig),
.LoadRxStatus(LoadRxStatus),
.RetryCntLatched(RetryCntLatched),
.RetryLimit(RetryLimit),
.LateCollLatched(LateCollLatched),
.DeferLatched(DeferLatched),
.RstDeferLatched(RstDeferLatched),
.CarrierSenseLost(CarrierSenseLost),
.ReceivedPacketGood(ReceivedPacketGood),
.AddressMiss(AddressMiss),
.ReceivedPauseFrm(ReceivedPauseFrm)
`ifdef ETH_BIST
,
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
,
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
`ifdef WISHBONE_DEBUG
,
.dbg_dat0(wb_dbg_dat0)
`ifdef WISHBONE_DEBUG
,
.dbg_dat0(wb_dbg_dat0)
`endif
 
);
);
 
assign m_wb_adr_o = {m_wb_adr_tmp, 2'h0};
assign m_wb_adr_o = {m_wb_adr_tmp, 2'h0};
 
// Connecting MacStatus module
eth_macstatus macstatus1
(
.MRxClk(mrx_clk_pad_i), .Reset(wb_rst_i),
.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood), .ReceivedLengthOK(ReceivedLengthOK),
.RxCrcError(RxCrcError), .MRxErr(MRxErr_Lb), .MRxDV(MRxDV_Lb),
.RxStateSFD(RxStateSFD), .RxStateData(RxStateData), .RxStatePreamble(RxStatePreamble),
.RxStateIdle(RxStateIdle), .Transmitting(Transmitting), .RxByteCnt(RxByteCnt),
.RxByteCntEq0(RxByteCntEq0), .RxByteCntGreat2(RxByteCntGreat2), .RxByteCntMaxFrame(RxByteCntMaxFrame),
.InvalidSymbol(InvalidSymbol),
.MRxD(MRxD_Lb), .LatchedCrcError(LatchedCrcError), .Collision(mcoll_pad_i),
.CollValid(r_CollValid), .RxLateCollision(RxLateCollision), .r_RecSmall(r_RecSmall),
.r_MinFL(r_MinFL), .r_MaxFL(r_MaxFL), .ShortFrame(ShortFrame),
.DribbleNibble(DribbleNibble), .ReceivedPacketTooBig(ReceivedPacketTooBig), .r_HugEn(r_HugEn),
.LoadRxStatus(LoadRxStatus), .RetryCnt(RetryCnt), .StartTxDone(StartTxDone),
.StartTxAbort(StartTxAbort), .RetryCntLatched(RetryCntLatched), .MTxClk(mtx_clk_pad_i),
.MaxCollisionOccured(MaxCollisionOccured), .RetryLimit(RetryLimit), .LateCollision(LateCollision),
.LateCollLatched(LateCollLatched), .DeferIndication(DeferIndication), .DeferLatched(DeferLatched),
.RstDeferLatched(RstDeferLatched),
.TxStartFrm(TxStartFrmOut), .StatePreamble(StatePreamble), .StateData(StateData),
.CarrierSense(CarrierSense_Tx2), .CarrierSenseLost(CarrierSenseLost), .TxUsedData(TxUsedDataIn),
.LatchedMRxErr(LatchedMRxErr), .Loopback(r_LoopBck), .r_FullD(r_FullD)
);
// Connecting MacStatus module
eth_macstatus macstatus1
(
.MRxClk(mrx_clk_pad_i),
.Reset(wb_rst_i),
.ReceiveEnd(ReceiveEnd),
.ReceivedPacketGood(ReceivedPacketGood),
.ReceivedLengthOK(ReceivedLengthOK),
.RxCrcError(RxCrcError),
.MRxErr(MRxErr_Lb),
.MRxDV(MRxDV_Lb),
.RxStateSFD(RxStateSFD),
.RxStateData(RxStateData),
.RxStatePreamble(RxStatePreamble),
.RxStateIdle(RxStateIdle),
.Transmitting(Transmitting),
.RxByteCnt(RxByteCnt),
.RxByteCntEq0(RxByteCntEq0),
.RxByteCntGreat2(RxByteCntGreat2),
.RxByteCntMaxFrame(RxByteCntMaxFrame),
.InvalidSymbol(InvalidSymbol),
.MRxD(MRxD_Lb),
.LatchedCrcError(LatchedCrcError),
.Collision(mcoll_pad_i),
.CollValid(r_CollValid),
.RxLateCollision(RxLateCollision),
.r_RecSmall(r_RecSmall),
.r_MinFL(r_MinFL),
.r_MaxFL(r_MaxFL),
.ShortFrame(ShortFrame),
.DribbleNibble(DribbleNibble),
.ReceivedPacketTooBig(ReceivedPacketTooBig),
.r_HugEn(r_HugEn),
.LoadRxStatus(LoadRxStatus),
.RetryCnt(RetryCnt),
.StartTxDone(StartTxDone),
.StartTxAbort(StartTxAbort),
.RetryCntLatched(RetryCntLatched),
.MTxClk(mtx_clk_pad_i),
.MaxCollisionOccured(MaxCollisionOccured),
.RetryLimit(RetryLimit),
.LateCollision(LateCollision),
.LateCollLatched(LateCollLatched),
.DeferIndication(DeferIndication),
.DeferLatched(DeferLatched),
.RstDeferLatched(RstDeferLatched),
.TxStartFrm(TxStartFrmOut),
.StatePreamble(StatePreamble),
.StateData(StateData),
.CarrierSense(CarrierSense_Tx2),
.CarrierSenseLost(CarrierSenseLost),
.TxUsedData(TxUsedDataIn),
.LatchedMRxErr(LatchedMRxErr),
.Loopback(r_LoopBck),
.r_FullD(r_FullD)
);
 
 
endmodule
/rtl/verilog/ethmac/eth_transmitcontrol.v
252,7 → 252,7
DlyCrcCnt <= 4'h0;
else
if(IncrementDlyCrcCnt)
DlyCrcCnt <= DlyCrcCnt + 1'b1;
DlyCrcCnt <= DlyCrcCnt + 4'd1;
end
 
271,10 → 271,10
ByteCnt <= 6'h0;
else
if(IncrementByteCntBy2 & EnableCnt)
ByteCnt <= (ByteCnt[5:0] ) + 2'h2;
ByteCnt <= (ByteCnt[5:0] ) + 6'd2;
else
if(IncrementByteCnt & EnableCnt)
ByteCnt <= (ByteCnt[5:0] ) + 1'b1;
ByteCnt <= (ByteCnt[5:0] ) + 6'd1;
end
 
 
/rtl/verilog/ethmac/eth_rxstatem.v
135,9 → 135,8
 
assign StartData1 = MRxDV & StateData0 & (~ByteCntMaxFrame);
 
assign StartDrop = MRxDV & (StateIdle & Transmitting | StateSFD & ~IFGCounterEq24 & MRxDEqD
| StateData0 & ByteCntMaxFrame
);
assign StartDrop = MRxDV & (StateIdle & Transmitting | StateSFD & ~IFGCounterEq24 &
MRxDEqD | StateData0 & ByteCntMaxFrame);
 
// Rx State Machine
always @ (posedge MRxClk or posedge Reset)
/rtl/verilog/ethmac/eth_registers.v
859,33 → 859,33
if(Read) // read
begin
case(Address)
`ETH_MODER_ADR : DataOut<=MODEROut;
`ETH_INT_SOURCE_ADR : DataOut<=INT_SOURCEOut;
`ETH_INT_MASK_ADR : DataOut<=INT_MASKOut;
`ETH_IPGT_ADR : DataOut<=IPGTOut;
`ETH_IPGR1_ADR : DataOut<=IPGR1Out;
`ETH_IPGR2_ADR : DataOut<=IPGR2Out;
`ETH_PACKETLEN_ADR : DataOut<=PACKETLENOut;
`ETH_COLLCONF_ADR : DataOut<=COLLCONFOut;
`ETH_CTRLMODER_ADR : DataOut<=CTRLMODEROut;
`ETH_MIIMODER_ADR : DataOut<=MIIMODEROut;
`ETH_MIICOMMAND_ADR : DataOut<=MIICOMMANDOut;
`ETH_MIIADDRESS_ADR : DataOut<=MIIADDRESSOut;
`ETH_MIITX_DATA_ADR : DataOut<=MIITX_DATAOut;
`ETH_MIIRX_DATA_ADR : DataOut<=MIIRX_DATAOut;
`ETH_MIISTATUS_ADR : DataOut<=MIISTATUSOut;
`ETH_MAC_ADDR0_ADR : DataOut<=MAC_ADDR0Out;
`ETH_MAC_ADDR1_ADR : DataOut<=MAC_ADDR1Out;
`ETH_TX_BD_NUM_ADR : DataOut<=TX_BD_NUMOut;
`ETH_HASH0_ADR : DataOut<=HASH0Out;
`ETH_HASH1_ADR : DataOut<=HASH1Out;
`ETH_TX_CTRL_ADR : DataOut<=TXCTRLOut;
`ETH_DBG_ADR : DataOut<=dbg_dat; // debug data out -- JB
default: DataOut<=32'h0;
`ETH_MODER_ADR : DataOut=MODEROut;
`ETH_INT_SOURCE_ADR : DataOut=INT_SOURCEOut;
`ETH_INT_MASK_ADR : DataOut=INT_MASKOut;
`ETH_IPGT_ADR : DataOut=IPGTOut;
`ETH_IPGR1_ADR : DataOut=IPGR1Out;
`ETH_IPGR2_ADR : DataOut=IPGR2Out;
`ETH_PACKETLEN_ADR : DataOut=PACKETLENOut;
`ETH_COLLCONF_ADR : DataOut=COLLCONFOut;
`ETH_CTRLMODER_ADR : DataOut=CTRLMODEROut;
`ETH_MIIMODER_ADR : DataOut=MIIMODEROut;
`ETH_MIICOMMAND_ADR : DataOut=MIICOMMANDOut;
`ETH_MIIADDRESS_ADR : DataOut=MIIADDRESSOut;
`ETH_MIITX_DATA_ADR : DataOut=MIITX_DATAOut;
`ETH_MIIRX_DATA_ADR : DataOut=MIIRX_DATAOut;
`ETH_MIISTATUS_ADR : DataOut=MIISTATUSOut;
`ETH_MAC_ADDR0_ADR : DataOut=MAC_ADDR0Out;
`ETH_MAC_ADDR1_ADR : DataOut=MAC_ADDR1Out;
`ETH_TX_BD_NUM_ADR : DataOut=TX_BD_NUMOut;
`ETH_HASH0_ADR : DataOut=HASH0Out;
`ETH_HASH1_ADR : DataOut=HASH1Out;
`ETH_TX_CTRL_ADR : DataOut=TXCTRLOut;
`ETH_DBG_ADR : DataOut=dbg_dat; // debug data out -- JB
default: DataOut=32'h0;
endcase
end
else
DataOut<=32'h0;
DataOut=32'h0;
end
 
 
893,7 → 893,7
assign r_Pad = MODEROut[15];
assign r_HugEn = MODEROut[14];
assign r_CrcEn = MODEROut[13];
assign r_DlyCrcEn = MODEROut[12];
assign r_DlyCrcEn = /*MODEROut[12]*/1'b0; // Synthesis bugfix JB
// assign r_Rst = MODEROut[11]; This signal is not used any more
assign r_FullD = MODEROut[10];
assign r_ExDfrEn = MODEROut[9];
/rtl/verilog/ram_wb/ram_wb_b3.v
1,6 → 1,3
//`define NONBLOCK_ASSIGN <= #1
`define NONBLOCK_ASSIGN <=
 
module ram_wb_b3(
wb_adr_i, wb_bte_i, wb_cti_i, wb_cyc_i, wb_dat_i, wb_sel_i,
wb_stb_i, wb_we_i,
30,19 → 27,19
input wb_rst_i;
 
// Memory parameters
//parameter mem_span = 32'h0000_0400;
parameter mem_span = 32'h0000_5000;
// parameter adr_width_for_span = 11; //(log2(mem_span));
parameter adr_width_for_span = 15; //(log2(mem_span));
parameter mem_size_bytes = 32'h0000_5000; // 20KBytes
parameter mem_adr_width = 15; //(log2(mem_size_bytes));
parameter bytes_per_dw = (dw/8);
parameter adr_width_for_num_word_bytes = 2; //(log2(bytes_per_dw))
parameter mem_words = (mem_span/bytes_per_dw);
parameter mem_words = (mem_size_bytes/bytes_per_dw);
 
// synthesis attribute ram_style of mem is block
reg [dw-1:0] mem [ 0 : mem_words-1 ] /* synthesis ram_style = no_rw_check */;
 
// Register to address internal memory array
reg [(mem_adr_width-adr_width_for_num_word_bytes)-1:0] adr;
reg [(adr_width_for_span-2)-1:0] adr;
wire [31:0] wr_data;
 
// Register to indicate if the cycle is a Wishbone B3-registered feedback
51,11 → 48,14
wire wb_b3_trans_start, wb_b3_trans_stop;
// Register to use for counting the addresses when doing burst accesses
reg [adr_width_for_span-1-2:0] burst_adr_counter;
reg [mem_adr_width-adr_width_for_num_word_bytes-1:0] burst_adr_counter;
reg [2:0] wb_cti_i_r;
reg [1:0] wb_bte_i_r;
wire using_burst_adr;
wire burst_access_wrong_wb_adr;
 
// Wire to indicate addressing error
wire addr_err;
// Logic to detect if there's a burst access going on
67,11 → 67,11
always @(posedge wb_clk_i)
if (wb_rst_i)
wb_b3_trans `NONBLOCK_ASSIGN 0;
wb_b3_trans <= 0;
else if (wb_b3_trans_start)
wb_b3_trans `NONBLOCK_ASSIGN 1;
wb_b3_trans <= 1;
else if (wb_b3_trans_stop)
wb_b3_trans `NONBLOCK_ASSIGN 0;
wb_b3_trans <= 0;
 
// Burst address generation logic
always @(/*AUTOSENSE*/wb_ack_o or wb_b3_trans or wb_b3_trans_start
80,40 → 80,40
// Kick off burst_adr_counter, this assumes 4-byte words when getting
// address off incoming Wishbone bus address!
// So if dw is no longer 4 bytes, change this!
burst_adr_counter <= wb_adr_i[adr_width_for_span-1:2];
burst_adr_counter = wb_adr_i[mem_adr_width-1:2];
else if ((wb_cti_i_r == 3'b010) & wb_ack_o & wb_b3_trans)
// Incrementing burst
begin
if (wb_bte_i_r == 2'b00) // Linear burst
burst_adr_counter <= adr + 1;
burst_adr_counter = adr + 1;
if (wb_bte_i_r == 2'b01) // 4-beat wrap burst
burst_adr_counter[1:0] <= adr[1:0] + 1;
burst_adr_counter[1:0] = adr[1:0] + 1;
if (wb_bte_i_r == 2'b10) // 8-beat wrap burst
burst_adr_counter[2:0] <= adr[2:0] + 1;
burst_adr_counter[2:0] = adr[2:0] + 1;
if (wb_bte_i_r == 2'b11) // 16-beat wrap burst
burst_adr_counter[3:0] <= adr[3:0] + 1;
burst_adr_counter[3:0] = adr[3:0] + 1;
end // if ((wb_cti_i_r == 3'b010) & wb_ack_o_r)
 
 
always @(posedge wb_clk_i)
wb_bte_i_r `NONBLOCK_ASSIGN wb_bte_i;
wb_bte_i_r <= wb_bte_i;
 
// Register it locally
always @(posedge wb_clk_i)
wb_cti_i_r `NONBLOCK_ASSIGN wb_cti_i;
wb_cti_i_r <= wb_cti_i;
 
assign using_burst_adr = wb_b3_trans;
assign burst_access_wrong_wb_adr = (using_burst_adr & (adr != wb_adr_i[adr_width_for_span-1:2]));
assign burst_access_wrong_wb_adr = (using_burst_adr &
(adr != wb_adr_i[mem_adr_width-1:2]));
 
// Address registering logic
always@(posedge wb_clk_i)
if(wb_rst_i)
adr `NONBLOCK_ASSIGN 0;
adr <= 0;
else if (using_burst_adr)
adr `NONBLOCK_ASSIGN burst_adr_counter;
adr <= burst_adr_counter;
else if (wb_cyc_i & wb_stb_i)
adr `NONBLOCK_ASSIGN wb_adr_i[adr_width_for_span-1:2];
adr <= wb_adr_i[mem_adr_width-1:2];
parameter memory_file = "sram.vmem";
 
139,7 → 139,7
always @ (posedge wb_clk_i)
begin
if (ram_we)
mem[adr] `NONBLOCK_ASSIGN wr_data;
mem[adr] <= wr_data;
end
// Ack Logic
149,18 → 149,22
always @ (posedge wb_clk_i)
if (wb_rst_i)
wb_ack_o_r `NONBLOCK_ASSIGN 1'b0;
wb_ack_o_r <= 1'b0;
else if (wb_cyc_i) // We have bus
begin
if (wb_cti_i == 3'b000)
if (addr_err & wb_stb_i)
begin
wb_ack_o_r <= 1;
end
else if (wb_cti_i == 3'b000)
begin
// Classic cycle acks
if (wb_stb_i)
begin
if (!wb_ack_o_r)
wb_ack_o_r `NONBLOCK_ASSIGN 1;
wb_ack_o_r <= 1;
else
wb_ack_o_r `NONBLOCK_ASSIGN 0;
wb_ack_o_r <= 0;
end
end // if (wb_cti_i == 3'b000)
else if ((wb_cti_i == 3'b001) | (wb_cti_i == 3'b010))
167,23 → 171,84
begin
// Increment/constant address bursts
if (wb_stb_i)
wb_ack_o_r `NONBLOCK_ASSIGN 1;
wb_ack_o_r <= 1;
else
wb_ack_o_r `NONBLOCK_ASSIGN 0;
wb_ack_o_r <= 0;
end
else if (wb_cti_i == 3'b111)
begin
// End of cycle
if (!wb_ack_o_r)
wb_ack_o_r `NONBLOCK_ASSIGN wb_stb_i;
wb_ack_o_r <= wb_stb_i;
else
wb_ack_o_r `NONBLOCK_ASSIGN 0;
wb_ack_o_r <= 0;
end
end // if (wb_cyc_i)
else
wb_ack_o_r `NONBLOCK_ASSIGN 0;
wb_ack_o_r <= 0;
 
 
//
// Error signal generation
//
assign wb_err_o = wb_ack_o & (burst_access_wrong_wb_adr); // OR in other errors here
// Error when out of bounds of memory - skip top byte of address in case
// this is mapped somewhere other than 0x00.
assign addr_err = wb_cyc_i & wb_stb_i & (|wb_adr_i[aw-1-8:mem_adr_width]);
// OR in other errors here...
assign wb_err_o = wb_ack_o & (burst_access_wrong_wb_adr | addr_err);
 
`ifdef verilator
task do_readmemh;
// verilator public
$readmemh(memory_file, mem);
endtask // do_readmemh
`else
initial
begin
$readmemh(memory_file, mem);
end
`endif // !`ifdef verilator
 
//
// Access functions
//
// Function to access RAM (for use by Verilator).
function [31:0] get_mem;
// verilator public
input [aw-1:0] addr;
get_mem = mem[addr[mem_adr_width-1:adr_width_for_num_word_bytes]];
endfunction // get_mem
 
// Function to access RAM (for use by Verilator).
function [7:0] get_byte;
// verilator public
input [aw-1:0] addr;
reg [31:0] temp_word;
begin
temp_word = mem[addr[mem_adr_width-1:adr_width_for_num_word_bytes]];
// Big endian mapping.
get_byte = (addr[1:0]==2'b00) ? temp_word[31:24] :
(addr[1:0]==2'b01) ? temp_word[23:16] :
(addr[1:0]==2'b10) ? temp_word[15:8] : temp_word[7:0];
end
endfunction // get_mem
 
// Function to write RAM (for use by Verilator).
function set_mem;
// verilator public
input [aw-1:0] addr;
input [dw-1:0] data;
mem[addr[mem_adr_width-1:adr_width_for_num_word_bytes]] = data;
endfunction // set_mem
endmodule // ram_wb_b3
 
/rtl/verilog/ram_wb/ram_wb.v
12,6 → 12,12
// Outputs
wbm1_ack_o, wbm1_err_o, wbm1_rty_o, wbm1_dat_o,
 
// Inputs
wbm2_adr_i, wbm2_bte_i, wbm2_cti_i, wbm2_cyc_i, wbm2_dat_i, wbm2_sel_i,
wbm2_stb_i, wbm2_we_i,
// Outputs
wbm2_ack_o, wbm2_err_o, wbm2_rty_o, wbm2_dat_o,
 
// Clock, reset
wb_clk_i, wb_rst_i
);
19,10 → 25,9
parameter dw = 32;
parameter aw = 32;
// Memory parameters
parameter mem_span = 32'h0000_0400;
parameter adr_width_for_span = 11; //(log2(mem_span));
parameter mem_size_bytes = 32'h0000_0400; // 1KBytes
parameter mem_adr_width = 10; //(log2(mem_span));
 
 
input [aw-1:0] wbm0_adr_i;
input [1:0] wbm0_bte_i;
input [2:0] wbm0_cti_i;
50,103 → 55,139
output wbm1_err_o;
output wbm1_rty_o;
output [dw-1:0] wbm1_dat_o;
 
input [aw-1:0] wbm2_adr_i;
input [1:0] wbm2_bte_i;
input [2:0] wbm2_cti_i;
input wbm2_cyc_i;
input [dw-1:0] wbm2_dat_i;
input [3:0] wbm2_sel_i;
input wbm2_stb_i;
input wbm2_we_i;
output wbm2_ack_o;
output wbm2_err_o;
output wbm2_rty_o;
output [dw-1:0] wbm2_dat_o;
 
input wb_clk_i;
input wb_rst_i;
 
// Internal wires to actual RAM
wire [aw-1:0] wb_ram_adr_i;
wire [1:0] wb_ram_bte_i;
wire [2:0] wb_ram_cti_i;
wire wb_ram_cyc_i;
wire [dw-1:0] wb_ram_dat_i;
wire [3:0] wb_ram_sel_i;
wire wb_ram_stb_i;
wire wb_ram_we_i;
wire [aw-1:0] wbs_ram_adr_i;
wire [1:0] wbs_ram_bte_i;
wire [2:0] wbs_ram_cti_i;
wire wbs_ram_cyc_i;
wire [dw-1:0] wbs_ram_dat_i;
wire [3:0] wbs_ram_sel_i;
wire wbs_ram_stb_i;
wire wbs_ram_we_i;
wire wb_ram_ack_o;
wire wb_ram_err_o;
wire wb_ram_rty_o;
wire [dw-1:0] wb_ram_dat_o;
wire wbs_ram_ack_o;
wire wbs_ram_err_o;
wire wbs_ram_rty_o;
wire [dw-1:0] wbs_ram_dat_o;
 
reg [1:0] input_select, last_selected;
wire arb_for_wbm0, arb_for_wbm1;
reg [2:0] input_select, last_selected;
wire arb_for_wbm0, arb_for_wbm1, arb_for_wbm2;
// Wires allowing selection of new input
assign arb_for_wbm0 = (last_selected[1] | !wbm1_cyc_i) & !(|input_select);
assign arb_for_wbm1 = (last_selected[0] | !wbm0_cyc_i) & !(|input_select);
assign arb_for_wbm0 = (last_selected[1] | last_selected[2] |
!wbm1_cyc_i | !wbm2_cyc_i) & !(|input_select);
assign arb_for_wbm1 = (last_selected[0] | last_selected[2] |
!wbm0_cyc_i | !wbm2_cyc_i) & !(|input_select);
assign arb_for_wbm2 = (last_selected[0] | last_selected[1] |
!wbm0_cyc_i | !wbm1_cyc_i) & !(|input_select);
// Master select logic
always @(posedge wb_clk_i)
if (wb_rst_i)
input_select <= 0;
else if ((input_select[0] & !wbm0_cyc_i) | (input_select[1] & !wbm1_cyc_i))
else if ((input_select[0] & !wbm0_cyc_i) | (input_select[1] & !wbm1_cyc_i)
| (input_select[2] & !wbm2_cyc_i))
input_select <= 0;
else if (!(&input_select) & wbm0_cyc_i & arb_for_wbm0)
input_select <= 2'b01;
input_select <= 3'b001;
else if (!(&input_select) & wbm1_cyc_i & arb_for_wbm1)
input_select <= 2'b10;
input_select <= 3'b010;
else if (!(&input_select) & wbm2_cyc_i & arb_for_wbm2)
input_select <= 3'b100;
always @(posedge wb_clk_i)
if (wb_rst_i)
last_selected <= 0;
else if (!(&input_select) & wbm0_cyc_i & arb_for_wbm0)
last_selected <= 2'b01;
last_selected <= 3'b001;
else if (!(&input_select) & wbm1_cyc_i & arb_for_wbm1)
last_selected <= 2'b10;
last_selected <= 3'b010;
else if (!(&input_select) & wbm2_cyc_i & arb_for_wbm2)
last_selected <= 3'b100;
 
// Mux input signals to RAM (default to wbm0)
assign wb_ram_adr_i = (input_select[1]) ? wbm1_adr_i :
(input_select[0]) ? wbm0_adr_i : 0;
assign wb_ram_bte_i = (input_select[1]) ? wbm1_bte_i :
(input_select[0]) ? wbm0_bte_i : 0;
assign wb_ram_cti_i = (input_select[1]) ? wbm1_cti_i :
(input_select[0]) ? wbm0_cti_i : 0;
assign wb_ram_cyc_i = (input_select[1]) ? wbm1_cyc_i :
(input_select[0]) ? wbm0_cyc_i : 0;
assign wb_ram_dat_i = (input_select[1]) ? wbm1_dat_i :
(input_select[0]) ? wbm0_dat_i : 0;
assign wb_ram_sel_i = (input_select[1]) ? wbm1_sel_i :
(input_select[0]) ? wbm0_sel_i : 0;
assign wb_ram_stb_i = (input_select[1]) ? wbm1_stb_i :
(input_select[0]) ? wbm0_stb_i : 0;
assign wb_ram_we_i = (input_select[1]) ? wbm1_we_i :
(input_select[0]) ? wbm0_we_i : 0;
// Mux input signals to RAM (default to wbm0)
assign wbs_ram_adr_i = (input_select[2]) ? wbm2_adr_i :
(input_select[1]) ? wbm1_adr_i :
(input_select[0]) ? wbm0_adr_i : 0;
assign wbs_ram_bte_i = (input_select[2]) ? wbm2_bte_i :
(input_select[1]) ? wbm1_bte_i :
(input_select[0]) ? wbm0_bte_i : 0;
assign wbs_ram_cti_i = (input_select[2]) ? wbm2_cti_i :
(input_select[1]) ? wbm1_cti_i :
(input_select[0]) ? wbm0_cti_i : 0;
assign wbs_ram_cyc_i = (input_select[2]) ? wbm2_cyc_i :
(input_select[1]) ? wbm1_cyc_i :
(input_select[0]) ? wbm0_cyc_i : 0;
assign wbs_ram_dat_i = (input_select[2]) ? wbm2_dat_i :
(input_select[1]) ? wbm1_dat_i :
(input_select[0]) ? wbm0_dat_i : 0;
assign wbs_ram_sel_i = (input_select[2]) ? wbm2_sel_i :
(input_select[1]) ? wbm1_sel_i :
(input_select[0]) ? wbm0_sel_i : 0;
assign wbs_ram_stb_i = (input_select[2]) ? wbm2_stb_i :
(input_select[1]) ? wbm1_stb_i :
(input_select[0]) ? wbm0_stb_i : 0;
assign wbs_ram_we_i = (input_select[2]) ? wbm2_we_i :
(input_select[1]) ? wbm1_we_i :
(input_select[0]) ? wbm0_we_i : 0;
 
// Output from RAM, gate the ACK, ERR, RTY signals appropriately
assign wbm0_dat_o = wb_ram_dat_o;
assign wbm0_ack_o = wb_ram_ack_o & input_select[0];
assign wbm0_err_o = wb_ram_err_o & input_select[0];
assign wbm0_rty_o = wb_ram_rty_o & input_select[0];
assign wbm0_dat_o = wbs_ram_dat_o;
assign wbm0_ack_o = wbs_ram_ack_o & input_select[0];
assign wbm0_err_o = wbs_ram_err_o & input_select[0];
assign wbm0_rty_o = 0;
 
assign wbm1_dat_o = wb_ram_dat_o;
assign wbm1_ack_o = wb_ram_ack_o & input_select[1];
assign wbm1_err_o = wb_ram_err_o & input_select[1];
assign wbm1_rty_o = wb_ram_rty_o & input_select[1];
assign wbm1_dat_o = wbs_ram_dat_o;
assign wbm1_ack_o = wbs_ram_ack_o & input_select[1];
assign wbm1_err_o = wbs_ram_err_o & input_select[1];
assign wbm1_rty_o = 0;
 
assign wbm2_dat_o = wbs_ram_dat_o;
assign wbm2_ack_o = wbs_ram_ack_o & input_select[2];
assign wbm2_err_o = wbs_ram_err_o & input_select[2];
assign wbm2_rty_o = 0;
ram_wb_b3 ram_wb_b3_0
(
// Outputs
.wb_ack_o (wb_ram_ack_o),
.wb_err_o (wb_ram_err_o),
.wb_rty_o (wb_ram_rty_o),
.wb_dat_o (wb_ram_dat_o),
.wb_ack_o (wbs_ram_ack_o),
.wb_err_o (wbs_ram_err_o),
.wb_rty_o (wbs_ram_rty_o),
.wb_dat_o (wbs_ram_dat_o),
// Inputs
.wb_adr_i (wb_ram_adr_i),
.wb_bte_i (wb_ram_bte_i),
.wb_cti_i (wb_ram_cti_i),
.wb_cyc_i (wb_ram_cyc_i),
.wb_dat_i (wb_ram_dat_i),
.wb_sel_i (wb_ram_sel_i),
.wb_stb_i (wb_ram_stb_i),
.wb_we_i (wb_ram_we_i),
.wb_adr_i (wbs_ram_adr_i),
.wb_bte_i (wbs_ram_bte_i),
.wb_cti_i (wbs_ram_cti_i),
.wb_cyc_i (wbs_ram_cyc_i),
.wb_dat_i (wbs_ram_dat_i),
.wb_sel_i (wbs_ram_sel_i),
.wb_stb_i (wbs_ram_stb_i),
.wb_we_i (wbs_ram_we_i),
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i));
 
defparam ram_wb_b3_0.aw = aw;
defparam ram_wb_b3_0.dw = dw;
defparam ram_wb_b3_0.mem_span = mem_span;
defparam ram_wb_b3_0.adr_width_for_span = adr_width_for_span;
defparam ram_wb_b3_0.mem_size_bytes = mem_size_bytes;
defparam ram_wb_b3_0.mem_adr_width = mem_adr_width;
 
endmodule // ram_wb
 
/doc/orpsoc.texi
607,7 → 607,7
Backend: Actel Designer (included in Actel Libero Suite)
Programming: Actel FlashPRO (included in Actel Libero Suite)
 
This has been developed with Libero v8.6 for Linux.
This has been tested with with Libero v8.6 and v9.0sp1 under Ubuntu Linux.
 
@node ORDB1A3PE1500 Debug Tools
@subsubsection Debug Tools
737,12 → 737,12
 
This will create a @code{.adb} file in the same path.
 
All steps, up to programming file generation are done here. This is mainly a licensing thing (free licenses for Libero under Linux @emph{do not} allow programming file generation - they do, however, under Windows.)
All steps, up to and including programming file generation are done here. FPGA device programming must be done using the programming FlashPro tool under Windows if using a free license.
 
@node ORDB1A3PE1500 Place and route options
@subsubsection Options
 
Most of the design's parameters are determined by processing the @code{orpsoc-defines.v} file and determining, for example, the frequency of the clocks entering the design.
Most of the design's parameters are determined by processing the @code{orpsoc-defines.v} file and extracting, for example, the frequency of the clocks entering the design.
 
The following can be passed as environment variables when running @kbd{make all}.
 
1001,7 → 1001,7
Backend: ngdbuild/map/par/bitgen/promgen, etc. (from Xilinx ISE)
Programming: iMPACT (from Xilinx ISE)
 
This has been developed with Xilinx ISE 11.1 under Linux.
This has been tested with Xilinx ISE 11.1 under Ubuntu Linux.
 
 
@node ML501 Debug Tools
/sw/tests/ethmac/sim/ethmac-rxtx.c
59,7 → 59,7
static void oeth_tx(void);
 
/* Let the ethernet packets use a space beginning here for buffering */
#define ETH_BUFF_BASE 0x01000000
#define ETH_BUFF_BASE 0x200000;
 
 
#define RXBUFF_PREALLOC 1
/sw/tests/ethmac/sim/ethmac-rx.c
58,7 → 58,7
unsigned short calculate_checksum(char* dats, unsigned int len) ;
 
/* Let the ethernet packets use a space beginning here for buffering */
#define ETH_BUFF_BASE 0x01000000
#define ETH_BUFF_BASE 0x200000;
 
#define RXBUFF_PREALLOC 1
#define TXBUFF_PREALLOC 1
443,6 → 443,7
rx_done = 0;
ethmac_setup(); /* Configure MAC, TX/RX BDs and enable RX in MODER */
 
#define NUM_PRIMES_TO_CHECK 1000
/sw/tests/ethmac/sim/ethmac-tx.c
58,7 → 58,7
static void oeth_tx(void);
 
/* Let the ethernet packets use a space beginning here for buffering */
#define ETH_BUFF_BASE 0x01000000
#define ETH_BUFF_BASE 0x200000;
 
#define RXBUFF_PREALLOC 1
#define TXBUFF_PREALLOC 1
330,18 → 330,6
else
tx_bd->len_status &= ~OETH_TX_BD_PAD;
#ifdef _ETH_RXTX_DATA_H_
// Set the address pointer to the place
// in memory where the data is and transmit from there
tx_bd->addr = (char*) &tx_data_array[tx_data_pointer&~(0x3)];
 
tx_data_pointer += length;
if (tx_data_pointer > (255*1024))
tx_data_pointer = 0;
 
#else
if (data){
//Copy the data into the transmit buffer, byte at a time
char* data_p = (char*) data;
351,7 → 339,6
data_b[i] = data_p[i];
}
}
#endif
 
/* Set the length of the packet's data in the buffer descriptor */
tx_bd->len_status = (tx_bd->len_status & 0x0000ffff) |
534,8 → 521,6
// If it's in use - wait
while ((tx_bd->len_status & OETH_TX_BD_IRQ));
 
#ifndef _ETH_RXTX_DATA_H_
// Use rand() function to generate data for transmission
// Assumption: ethernet buffer descriptors are 4byte aligned
char* data_b = (char*) tx_bd->addr;
555,7 → 540,6
{
data_b[i] = rand()&0xff;
}
#endif
 
tx_packet((void*)0, size);
}
565,10 → 549,6
{
int i;
 
#ifdef _ETH_RXTX_DATA_H_
tx_data_pointer = 0;
#endif
 
/* Initialise handler vector */
int_init();
 
/sw/tests/or1200/board/or1200-mul.c
0,0 → 1,225
/*
Test integer multiply
Use a software multiplication algorithm to compare against hardware
calculated results
 
Julius Baxter, julius@opencores.org
 
*/
 
#include "cpu-utils.h"
#include "uart.h"
#include "printf.h"
#include "board.h"
 
static int smul_errors, umul_errors;
 
#define VERBOSE_TESTS 0
 
// Make this bigger when running on FPGA target. For simulation it's enough.
#define NUM_TESTS 2000000
 
int
or1k_mul(int multiplicant, int multiplier)
{
int result;
asm ("l.mul\t%0,%1,%2" : "=r" (result) : "r" (multiplicant),
"r" (multiplier));
return result;
}
 
unsigned int
or1k_mulu(unsigned int mulidend, unsigned int mulisor)
{
int result;
asm ("l.mulu\t%0,%1,%2" : "=r" (result) : "r" (mulidend), "r" (mulisor));
return result;
}
 
 
void
check_mul(int multiplicand, int multiplier, int expected_result)
{
#if VERBOSE_TESTS
printf("l.mul 0x%.8x * 0x%.8x = (SW) 0x%.8x : ", multiplicand, multiplier,
expected_result);
#endif
int result = or1k_mul(multiplicand, multiplier);
report(result);
if ( result != expected_result)
{
printf("l.mul 0x%.8x * 0x%.8x = (SW) 0x%.8x : ", multiplicand, multiplier,
expected_result);
printf("(HW) 0x%.8x - MISMATCH\n",result);
smul_errors++;
}
#if VERBOSE_TESTS
else
printf("OK\n");
#endif
}
 
void
check_mulu(unsigned int multiplicand, unsigned int multiplier,
unsigned int expected_result)
{
#if VERBOSE_TESTS
printf("l.mulu 0x%.8x * 0x%.8x = (SW) 0x%.8x : ", multiplicand, multiplier,
expected_result);
#endif
 
unsigned int result = or1k_mulu(multiplicand, multiplier);
report(result);
if ( result != expected_result)
{
printf("l.mulu 0x%.8x * 0x%.8x = (SW) 0x%.8x : ", multiplicand, multiplier,
expected_result);
printf("(HW) 0x%.8x - MISMATCH\n",result);
umul_errors++;
}
#if VERBOSE_TESTS
else
printf("OK\n");
#endif
}
 
 
// Software implementation of multiply
unsigned int
mul_soft(unsigned int n, unsigned int d)
{
 
unsigned int m = 0;
//printf("sft: 0x%x 0x%xd\n",n,d);
int i;
for(i=0; i<32; i++)
{
//printf("bit %d: 0x%x\n",i, (((1<<i) & d)));
if ((1<<i) & d)
{
m += (unsigned int) (n << i);
}
}
 
return (unsigned int) m;
}
 
int
main(void)
{
#ifdef _UART_H_
uart_init(DEFAULT_UART);
#endif
 
unsigned int seconds = 0;
cpu_reset_timer_ticks();
cpu_enable_timer();
 
printf("\n\n\tOR1200 Multiplication Instruction Tests\n");
printf("\tRunning %d tests\n", NUM_TESTS);
printf("\tElapsed time: 000");
 
// Variables for tracking errors
umul_errors = 0;
smul_errors = 0;
 
int i;
 
unsigned int n, d;
unsigned int expected_result;
i=0;
n=0;d=0;
while(i < NUM_TESTS)
{
 
n = rand() >> 20;
d = (rand() >> 24);
 
report(0x10101010);
 
if (n&0x10) // Randomly select if we should negate n
{
// 2's complement of n
n = ~n + 1;
}
if (d&0x80) // Randomly select if we should negate d
{
// 2's complement of d
d = ~d + 1;
}
if ((n & 0x80000000) && (d & 0x80000000))
expected_result = mul_soft(~(n-1), ~(d-1));
else if ((n & 0x80000000) && !(d & 0x80000000))
{
expected_result = mul_soft(~(n-1), d);
expected_result = ~expected_result + 1; // 2's complement
}
else if (!(n & 0x80000000) && (d & 0x80000000))
{
expected_result = mul_soft(n, ~(d-1));
expected_result = ~expected_result + 1; // 2's complement
}
else if (!(n & 0x80000000) && !(d & 0x80000000))
expected_result = mul_soft(n, d);
 
 
/* Report things */
report(n);
report(d);
report(expected_result);
 
 
/* Signed mulide */
check_mul(n, d, expected_result);
 
/* Unsigned mulide test */
/* Ensure numerator's bit 31 is clear */
n >>= 1;
 
expected_result = mul_soft(n, d);
 
/* Report things */
report(n);
report(d);
report(expected_result);
/* Unsigned mulide */
check_mulu(n, d, expected_result);
report(i);
i++;
 
if (cpu_get_timer_ticks() >= TICKS_PER_SEC)
{
cpu_reset_timer_ticks();
seconds++;
printf("\b\b\b%.3d",seconds);
}
 
}
 
printf("\n");
printf("Integer multiply check complete\n");
printf("Unsigned:\t%d tests\t %d errors\n",
NUM_TESTS, umul_errors);
printf("Signed:\t\t%d tests\t %d errors\n",
NUM_TESTS, smul_errors);
 
if ((umul_errors > 0) || (smul_errors > 0))
report(0xbaaaaaad);
else
report(0x8000000d);
 
return 0;
}
/sw/tests/or1200/board/or1200-div.c
0,0 → 1,229
/*
Test integer division
Use a software division algorithm to perform division and compare against
the hardware calculated results
 
TODO: Check the signed division software calculation stuff is 100% correct!
 
Julius Baxter, julius@opencores.org
 
*/
 
#include "cpu-utils.h"
#include "uart.h"
#include "printf.h"
#include "board.h"
 
static int sdiv_errors, udiv_errors;
 
#define VERBOSE_TESTS 0
 
// Make this bigger when running on FPGA target. For simulation it's enough.
#define NUM_TESTS 2000000
 
int
or1k_div(int dividend, int divisor)
{
int result;
asm ("l.div\t%0,%1,%2" : "=r" (result) : "r" (dividend), "r" (divisor));
return result;
}
 
unsigned int
or1k_divu(unsigned int dividend, unsigned int divisor)
{
int result;
asm ("l.divu\t%0,%1,%2" : "=r" (result) : "r" (dividend), "r" (divisor));
return result;
}
 
 
void
check_div(int dividend, int divisor, int expected_result)
{
#if VERBOSE_TESTS
printf("l.div 0x%.8x / 0x%.8x = (SW) 0x%.8x : ", dividend, divisor,
expected_result);
#endif
int result = or1k_div(dividend, divisor);
report(result);
if ( result != expected_result)
{
printf("l.div 0x%.8x / 0x%.8x = (SW) 0x%.8x : ", dividend, divisor,
expected_result);
printf("(HW) 0x%.8x - MISMATCH\n",result);
sdiv_errors++;
}
#if VERBOSE_TESTS
else
printf("OK\n");
#endif
}
 
void
check_divu(unsigned int dividend, unsigned int divisor,
unsigned int expected_result)
{
#if VERBOSE_TESTS
printf("l.divu 0x%.8x / 0x%.8x = (SW) 0x%.8x : ", dividend, divisor,
expected_result);
#endif
 
unsigned int result = or1k_divu(dividend, divisor);
report(result);
if ( result != expected_result)
{
printf("l.divu 0x%.8x / 0x%.8x = (SW) 0x%.8x : ", dividend, divisor,
expected_result);
printf("(HW) 0x%.8x - MISMATCH\n",result);
udiv_errors++;
}
#if VERBOSE_TESTS
else
printf("OK\n");
#endif
}
 
 
// Software implementation of division
unsigned int
div_soft(unsigned int n, unsigned int d)
{
 
// unsigned 32-bit restoring divide algo:
unsigned long long p, dd;
long long p_signed;
unsigned int q = 0;
 
p = (unsigned long long) n;
dd = (unsigned long long) d << 32;
 
int i;
for(i=31; i>-1; i--){
p_signed = (2*p) - dd;
if (p_signed>=0)
{
p = (2*p) - dd;
q |= 1 << i;
}
else
{
p = p_signed + dd;
}
}
return q;
 
}
 
int
main(void)
{
#ifdef _UART_H_
uart_init(DEFAULT_UART);
#endif
 
unsigned int seconds = 0;
cpu_reset_timer_ticks();
cpu_enable_timer();
 
printf("\n\n\tOR1200 Division Instruction Tests\n");
printf("\tRunning %d tests\n", NUM_TESTS);
#if VERBOSE_TESTS==0
printf("\tElapsed time: 000");
#endif
udiv_errors = 0;
sdiv_errors = 0;
 
int i;
 
unsigned long n, d;
unsigned long expected_result;
i=0;
while(i < NUM_TESTS)
{
n = rand();
d = rand();
 
report(0x10101010);
 
while ( d >= n )
d >>= (rand() & 0xff);
 
if (n&0x80000000) // numerator is negative
{
// Calculate a value that's really smaller than the numerator
while ( d >= ~(n-1) )
d >>= (rand() & 0xff);
 
if (!d) d = 1;
// Processor thinks it's in 2's complement already, so we'll convert
// from the interpreted 2's complement to unsigned for our calculation
expected_result = div_soft(~(n-1), d);
// Answer will be an unsigned +ve value, but of course it has to be
// negative so convert back to 2's complment negative
expected_result = ~expected_result + 1; // 2's complement
}
else
expected_result = div_soft(n, d);
 
/* Report things */
report(n);
report(d);
report(expected_result);
 
/* Signed divide */
check_div(n, d, expected_result);
 
/* Unsigned divide test */
/* Ensure numerator's bit 31 is clear */
n >>= 1;
 
/* If divisor is > numerator, shift it by a random amount */
while ( d >= n )
d >>= (rand() & 0xff);
if (!d) d = 1;
 
expected_result = div_soft(n, d);
 
/* Report things */
report(n);
report(d);
report(expected_result);
/* Unsigned divide */
check_divu(n, d, expected_result);
i++;
#if VERBOSE_TESTS==0
if (cpu_get_timer_ticks() >= TICKS_PER_SEC)
{
cpu_reset_timer_ticks();
seconds++;
printf("\b\b\b%.3d",seconds);
}
#endif
}
 
printf("\n");
 
printf("Division check complete\n");
printf("Unsigned:\t%d tests\t %d errors\n",
NUM_TESTS, udiv_errors);
printf("Signed:\t\t%d tests\t %d errors\n",
NUM_TESTS, sdiv_errors);
 
if ((udiv_errors > 0) || (sdiv_errors > 0))
report(0xbaaaaaad);
else
report(0x8000000d);
 
return 0;
}
/sw/tests/or1200/sim/or1200-dctest.c
14,8 → 14,9
#define LOOPS 64
#define WORD_STRIDE 8
 
// Memory area to test at
#define TEST_BASE 0x600000 /* 6MB */
 
 
unsigned long int my_lfsr;
 
unsigned long int next_rand()
36,7 → 37,7
return 0;
}
 
volatile char* ptr = (volatile char*) 0xe00000;
volatile char* ptr = (volatile char*) TEST_BASE;
int i;
 
ptr[0] = 0xab;
98,7 → 99,7
 
// init LFSR
my_lfsr = RAND_LFSR_SEED;
volatile unsigned long int *lptr = (volatile unsigned long int*) 0xa00000;
volatile unsigned long int *lptr = (volatile unsigned long int*) TEST_BASE;
for(i=0;i<LOOPS;i++)
{
lptr[(i*WORD_STRIDE)-1] = next_rand();
/sw/tests/or1200/sim/or1200-mmu.c
1427,8 → 1427,8
start_text_addr = (unsigned long*)&_stext;
end_text_addr = (unsigned long*)&_endtext;
end_data_addr = (unsigned long*)&_stack;
end_data_addr += 4;
 
 
#ifndef TLB_BOTTOM_TEST_PAGE_HARDSET
TLB_TEXT_SET_NB = TLB_DATA_SET_NB = (end_data_addr+PAGE_SIZE) / PAGE_SIZE;
#endif
/sw/tests/uart/sim/uart-interruptloopback.c
0,0 → 1,146
/*
* UART loopback interrupt test
*
* Tests UART and interrupt routines servicing them.
*
* Relies on testbench having uart0's lines in loopback (rx = tx)
*
* Julius Baxter, julius.baxter@orsoc.se
*
*/
 
 
#include "cpu-utils.h"
#include "spr-defs.h"
#include "board.h"
#include "uart.h"
#include "int.h"
#include "orpsoc-defines.h"
 
#ifndef UART0
# error
# error UART0 missing and is required for UART interrupt (loopback) test
# error
#endif
 
struct uart_tx_ctrl
{
char *bufptr;
int busy;
};
 
volatile struct uart_tx_ctrl uart0_tx_ctrl;
 
void uart_int_handler(void* corenum);
 
void uart_int_handler(void* corenum)
{
 
int core = *((int*)corenum);
 
if (core)report(core);
char iir = uart_get_iir(core);
 
if ( (iir & UART_IIR_RLSI) == UART_IIR_RLSI)
uart_get_lsr(core); // Should clear this interrupt
else if ( (iir & UART_IIR_RDI) == UART_IIR_RDI )
{
// Was potentially also a timeout. Do we care?
// Data received. Pull all from the FIFO buffer, here we just report it
// and throw it away
char rxchar;
while (uart_check_for_char(core))
{
rxchar = uart_getc(core);
report(0xff & rxchar);
if (rxchar == 0x2a) // Exit simulation when RX char is '*'
{
report(0x8000000d);
exit(0);
}
}
}
else if ( (iir & UART_IIR_THRI) == UART_IIR_THRI)
{
// Only trigered if we've set something to be transmitted
// and enabled the interrupt.
// Put next thing to be transmitted into buffer, check if it's
// the last, if so, disable interrupts.
if (uart0_tx_ctrl.bufptr[0] == 0) // EOL, disable interrupt after this char
{
uart_txint_disable(core);
uart0_tx_ctrl.busy = 0;
}
else // Transmit this byte
{
uart_putc_noblock(core, uart0_tx_ctrl.bufptr[0]);
uart0_tx_ctrl.bufptr++;
}
}
else if ( (iir & UART_IIR_MSI) == UART_IIR_MSI )
{
// Just read the modem status register to clear this
uart_get_msr(core);
}
}
 
 
void uart0_tx_buffer(char* buf)
{
while (uart0_tx_ctrl.busy); // Wait until we can transmit more
uart0_tx_ctrl.bufptr = buf;
uart0_tx_ctrl.busy = 1;
uart_txint_enable(0);
}
 
int main()
{
int uart0_core = 0;
int uart1_core = 1;
uart0_tx_ctrl.busy = 0;
/* Set up interrupt handler */
int_init();
 
/* Install UART core 0 interrupt handler */
int_add(UART0_IRQ, uart_int_handler,(void*) &uart0_core);
/* Install UART core 1 interrupt handler */
//int_add(UART1_IRQ, uart_int_handler,(void*) &uart1_core);
 
/* Enable interrupts in supervisor register */
mtspr (SPR_SR, mfspr (SPR_SR) | SPR_SR_IEE);
uart_init(uart0_core);
//uart_init(uart1_core);
//uart_rxint_enable(uart1_core);
uart_rxint_enable(uart0_core);
char* teststring = "\n\tHello world from UART 0\n\0";
 
uart0_tx_buffer(teststring);
 
// Do other things while we transmit
float f1, f2, f3; int i;
f1 = 0.2382; f2 = 4342.65; f3=0;
for(i=0;i<32;i++) f3 += f1*f3 + f2;
 
report(f3);
report(0x4aaaaa1f);
char* done_calculating = "\tDone with the number crunching!\n\0";
 
uart0_tx_buffer(done_calculating);
// Character '*', which will be received in the interrupt handler and cause
// the simulation to exit.
char* finish = "*\n\0";
uart0_tx_buffer(finish);
while(1); // will exit in the rx interrupt routine
 
}
/sw/drivers/or1200/link.ld
9,13 → 9,10
}
 
 
/*
* Allocate the stack to be at the top of memory, since the stack
* grows down.
*/
PROVIDE (stack = 128K - 4);
PROVIDE (_stack = 128K - 4);
/* Stack information variables */
_min_stack = 0x2000; /* 8K - minimum stack space to reserve */
 
 
SECTIONS
{
.vectors :
77,8 → 74,21
__end = ALIGN(0x8);
ebss = .;
_ebss = .;
}
} > ram
/* ensure there is enough room for stack */
.stack (NOLOAD): {
. = ALIGN(4);
sstack = . ;
_sstack = . ;
. = . + _min_stack ;
. = ALIGN(4);
stack = . ;
_stack = . ;
estack = . ;
_estack = . ;
} > ram
.stab 0 (NOLOAD) :
{
[ .stab ]
/boards/actel/ordb1a3pe1500/bench/verilog/include/eth_stim.v
464,10 → 464,10
reg [24:0] txpnt_sdram; // Index in array of shorts for data in SDRAM
// part
reg [21:0] buffer;
reg [7:0] sdram_byte;
reg [7:0] destram_byte;
reg [31:0] tx_len_bd;
integer i;
integer i,j;
integer failure;
begin
failure = 0;
496,20 → 496,46
// Variable we'll use for index in the PHY's TX buffer
buffer = 0; // Start of TX data
`ifdef VERSATILE_SDRAM
`ifdef RAM_WB
for (i=0;i<tx_len_bd;i=i+1)
begin
//$display("Checking address in tx bd 0x%0h",txpnt_sdram);
sdram0.get_byte(txpnt_sdram,sdram_byte);
destram_byte = dut.ram_wb0.ram_wb_b3_0.get_byte(txpnt_sdram);
phy_byte = eth_phy0.tx_mem[buffer];
// Debugging output
//$display("txpnt_sdram = 0x%h, destram_byte = 0x%h, buffer = 0x%h,
//phy_byte = 0x%h", txpnt_sdram, destram_byte, buffer, phy_byte);
if (phy_byte !== destram_byte)
begin
`TIME;
$display("*E Wrong byte (%d) of TX packet! ram = %h, phy = %h",buffer, destram_byte, phy_byte);
failure = 1;
end
buffer = buffer + 1;
txpnt_sdram = txpnt_sdram+1;
end // for (i=0;i<tx_len_bd;i=i+1)
`else
`ifdef VERSATILE_SDRAM
for (i=0;i<tx_len_bd;i=i+1)
begin
//$display("Checking address in tx bd 0x%0h",txpnt_sdram);
sdram0.get_byte(txpnt_sdram,destram_byte);
 
phy_byte = eth_phy0.tx_mem[buffer];
// Debugging output
//$display("txpnt_sdram = 0x%h, sdram_byte = 0x%h, buffer = 0x%h, phy_byte = 0x%h", txpnt_sdram, sdram_byte, buffer, phy_byte);
if (phy_byte !== sdram_byte)
//$display("txpnt_sdram = 0x%h, destram_byte = 0x%h, buffer = 0x%h, phy_byte = 0x%h", txpnt_sdram, destram_byte, buffer, phy_byte);
if (phy_byte !== destram_byte)
begin
`TIME;
$display("*E Wrong byte (%d) of TX packet! ram = %h, phy = %h",buffer, sdram_byte, phy_byte);
$display("*E Wrong byte (%d) of TX packet! ram = %h, phy = %h",buffer, destram_byte, phy_byte);
failure = 1;
end
519,12 → 545,15
end // for (i=0;i<tx_len_bd;i=i+1)
`else
$display("SET ME UP TO LOOK IN ANOTHER MEMORY!");
`else // !`ifdef VERSATILE_SDRAM
 
$display("eth_stim.v: CANNOT INSPECT RAM. PLEASE CONFIGURE CORRECTLY");
$display("RAM pointer for BD is 0x%h, bank offset we'll use is 0x%h",
tx_bd_addr, txpnt_wb);
$finish;
`endif // !`ifdef VERSATILE_SDRAM
`endif // !`ifdef VERSATILE_SDRAM
`endif // !`ifdef RAM_WB
if (failure)
begin
#100
963,8 → 992,7
reg [31:0] rxpnt_wb; // Pointer in array to where data should be
reg [24:0] rxpnt_sdram; // byte address from CPU in RAM
reg [15:0] sdram_short;
reg [7:0] sdram_byte;
//reg [7:0] phy_rx_mem [0:2000];
reg [7:0] destram_byte;
integer i;
integer failure;
1002,8 → 1030,31
rxpnt_wb = {14'd0,rx_bd_addr[17:0]};
rxpnt_sdram = rx_bd_addr[24:0];
`ifdef VERSATILE_SDRAM
`ifdef RAM_WB
for (i=0;i<len;i=i+1)
begin
 
destram_byte = dut.ram_wb0.ram_wb_b3_0.get_byte(rxpnt_sdram);
 
phy_byte = eth_rx_sent_circbuf[eth_rx_sent_circbuf_read_ptr];
 
if (phy_byte !== destram_byte)
begin
$display("*E Wrong byte (%5d) of RX packet %5d! phy = %h, ram = %h",
i, eth_rx_num_packets_checked, phy_byte, destram_byte);
failure = 1;
end
 
eth_rx_sent_circbuf_read_ptr = (eth_rx_sent_circbuf_read_ptr+1)&
eth_rx_sent_circbuf_size_mask;
 
rxpnt_sdram = rxpnt_sdram+1;
end
`else
`ifdef VERSATILE_SDRAM
// We'll look inside the SDRAM array
// Hard coded for the SDRAM buffer area to be from the halfway mark in
// memory (so starting in Bank2)
1016,15 → 1067,15
for (i=0;i<len;i=i+1)
begin
 
sdram0.get_byte(rxpnt_sdram,sdram_byte);
sdram0.get_byte(rxpnt_sdram,destram_byte);
 
phy_byte = eth_rx_sent_circbuf[eth_rx_sent_circbuf_read_ptr];//phy_rx_mem[buffer]; //eth_phy0.rx_mem[buffer];
 
if (phy_byte !== sdram_byte)
if (phy_byte !== destram_byte)
begin
// `TIME;
$display("*E Wrong byte (%5d) of RX packet %5d! phy = %h, ram = %h",
i, eth_rx_num_packets_checked, phy_byte, sdram_byte);
i, eth_rx_num_packets_checked, phy_byte, destram_byte);
failure = 1;
end
 
1034,15 → 1085,17
rxpnt_sdram = rxpnt_sdram+1;
end // for (i=0;i<len;i=i+2)
`else
`else
 
$display("SET ME UP TO LOOK IN ANOTHER MEMORY!");
$display("eth_stim.v: CANNOT INSPECT RAM. PLEASE CONFIGURE CORRECTLY");
$display("RAM pointer for BD is 0x%h, bank offset we'll use is 0x%h",
rx_bd_addr, rxpnt_wb);
$finish;
`endif // !`ifdef VERSATILE_SDRAM
`endif // !`ifdef VERSATILE_SDRAM
`endif // !`ifdef RAM_WB
 
if (failure)
begin
/boards/actel/ordb1a3pe1500/rtl/verilog/include/orpsoc-params.v
122,15 → 122,6
parameter wbs_i_mc0_data_width = 32;
parameter wbs_d_mc0_data_width = 32;
 
// Memory sizing for synthesis (small)
parameter sdram_ba_width = 2;
// For 8MB part, mt16lc4m16a2
parameter sdram_row_width = 12;
parameter sdram_col_width = 8;
// For 32MB part, mt16lc4m16a2
//parameter sdram_row_width = 13;
//parameter sdram_col_width = 9;
 
// ETH0 defines
parameter eth0_wb_adr = 8'h92;
parameter wbs_d_eth0_data_width = 32;
138,9 → 129,9
parameter wbm_eth0_data_width = 32;
parameter wbm_eth0_addr_width = 32;
 
// Memory sizing for synthesis (small)
parameter internal_sram_mem_span = 32'h0080_0000;
parameter internal_sram_adr_width_for_span = 23;
// Memory sizing for wb_ram (simulation only)
parameter internal_sram_mem_span = 32'h0080_0000; // 8MB
parameter internal_sram_adr_width_for_span = 23; // log2(8192*1024)
 
//////////////////////////////////////////////////////
// //
/boards/actel/ordb1a3pe1500/rtl/verilog/include/ethmac_defines.v
191,23 → 191,23
`define ETH_TX_1KBYTE_FIFO // 1024 byte TX buffer - uncomment this
 
`ifdef ETH_TX_FULL_PACKET_FIFO
`define ETH_TX_FIFO_CNT_WIDTH 11
`define ETH_TX_FIFO_CNT_WIDTH 9
`define ETH_TX_FIFO_DEPTH 375
`else
`ifdef ETH_TX_1KBYTE_FIFO
`define ETH_TX_FIFO_CNT_WIDTH 9
`define ETH_TX_FIFO_CNT_WIDTH 8
`define ETH_TX_FIFO_DEPTH 256
`else
`ifdef ETH_TX_512BYTE_FIFO
`define ETH_TX_FIFO_CNT_WIDTH 8
`define ETH_TX_FIFO_CNT_WIDTH 7
`define ETH_TX_FIFO_DEPTH 128
`else
`ifdef ETH_TX_256BYTE_FIFO
`define ETH_TX_FIFO_CNT_WIDTH 7
`define ETH_TX_FIFO_CNT_WIDTH 6
`define ETH_TX_FIFO_DEPTH 64
`else
// Default is 64 bytes
`define ETH_TX_FIFO_CNT_WIDTH 5
`define ETH_TX_FIFO_CNT_WIDTH 4
`define ETH_TX_FIFO_DEPTH 16
`endif
`endif
217,16 → 217,16
 
 
// Settings for RX FIFO
`define ETH_RX_FIFO_CNT_WIDTH 9
`define ETH_RX_FIFO_CNT_WIDTH 8
`define ETH_RX_FIFO_DEPTH 256
//`define ETH_RX_FIFO_CNT_WIDTH 8
//`define ETH_RX_FIFO_CNT_WIDTH 7
//`define ETH_RX_FIFO_DEPTH 128
//`define ETH_RX_FIFO_CNT_WIDTH 7
//`define ETH_RX_FIFO_CNT_WIDTH 6
//`define ETH_RX_FIFO_DEPTH 64
//`define ETH_RX_FIFO_CNT_WIDTH 6
//`define ETH_RX_FIFO_CNT_WIDTH 5
//`define ETH_RX_FIFO_DEPTH 32
//`define ETH_RX_FIFO_CNT_WIDTH 5
//`define ETH_RX_FIFO_DEPTH 16
//`define ETH_RX_FIFO_CNT_WIDTH 4
//`define ETH_RX_FIFO_DEPTH 1
 
`define ETH_RX_FIFO_DATA_WIDTH 32
 
/boards/actel/ordb1a3pe1500/rtl/verilog/orpsoc_top/orpsoc_top.v
109,7 → 109,7
 
rst_n_pad_i
 
) /* synthesis syn_global_buffers = 8; syn_hier = "flatten" */;
)/* synthesis syn_global_buffers = 8; */;
 
`include "orpsoc-params.v"
 
1351,8 → 1351,8
.wbm0_stb_i (wbs_i_mc0_stb_i),
.wbm0_dat_o (wbs_i_mc0_dat_o),
.wbm0_ack_o (wbs_i_mc0_ack_o),
.wbm0_err_o (),
.wbm0_rty_o (),
.wbm0_err_o (wbs_i_mc0_err_o),
.wbm0_rty_o (wbs_i_mc0_rty_o),
// Wishbone slave interface 1
.wbm1_dat_i (wbs_d_mc0_dat_i),
.wbm1_adr_i (wbs_d_mc0_adr_i),
1364,22 → 1364,29
.wbm1_stb_i (wbs_d_mc0_stb_i),
.wbm1_dat_o (wbs_d_mc0_dat_o),
.wbm1_ack_o (wbs_d_mc0_ack_o),
.wbm1_err_o (),
.wbm1_rty_o (),
.wbm1_err_o (wbs_d_mc0_err_o),
.wbm1_rty_o (wbs_d_mc0_rty_o),
// Wishbone slave interface 2
.wbm2_dat_i (wbm_eth0_dat_o),
.wbm2_adr_i (wbm_eth0_adr_o),
.wbm2_sel_i (wbm_eth0_sel_o),
.wbm2_cti_i (wbm_eth0_cti_o),
.wbm2_bte_i (wbm_eth0_bte_o),
.wbm2_we_i (wbm_eth0_we_o ),
.wbm2_cyc_i (wbm_eth0_cyc_o),
.wbm2_stb_i (wbm_eth0_stb_o),
.wbm2_dat_o (wbm_eth0_dat_i),
.wbm2_ack_o (wbm_eth0_ack_i),
.wbm2_err_o (wbm_eth0_err_i),
.wbm2_rty_o (wbm_eth0_rty_i),
// Clock, reset
.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst));
 
assign wbs_i_mc0_err_o = 0;
assign wbs_i_mc0_rty_o = 0;
 
assign wbs_d_mc0_err_o = 0;
assign wbs_d_mc0_rty_o = 0;
defparam ram_wb0.aw = wb_aw;
defparam ram_wb0.dw = wb_dw;
defparam ram_wb0.mem_span = internal_sram_mem_span;
defparam ram_wb0.adr_width_for_span = internal_sram_adr_width_for_span;
defparam ram_wb0.mem_size_bytes = internal_sram_mem_span;
defparam ram_wb0.mem_adr_width = internal_sram_adr_width_for_span;
////////////////////////////////////////////////////////////////////////
`endif // `ifdef RAM_WB
 
/boards/actel/ordb1a3pe1500/backend/par/bin/Makefile
53,6 → 53,7
TCL_SCRIPT_COMPILE=compile.tcl
TCL_SCRIPT_PAR=par.tcl
TCL_SCRIPT_CREATE_COMPILE_PAR=create-compile-par.tcl
TCL_SCRIPT_CREATE_COMPILE_PAR_BITGEN=create-compile-par-bitgen.tcl
TCL_SCRIPT_REPORT=report.tcl
TCL_SCRIPT_BITGEN=bitgen.tcl
# Generate these every time
120,7 → 121,7
TIME_CMD=time -p
 
# Rule for everything from, potentially, synthesis up to PAR
all: print-config print-defines create-compile-par
all: print-config print-defines create-compile-par-bitgen
 
# Not possible to do programming file generation under Linux
# not with the free tools
131,6 → 132,9
create-compile-par: sdc-file pdc-file $(PROJ_EDF_FILE) $(TCL_SCRIPT_CREATE_COMPILE_PAR)
$(TIME_CMD) $(VENDOR_TCL_SHELL) $(TCL_SCRIPT_CREATE_COMPILE_PAR)
 
create-compile-par-bitgen: sdc-file pdc-file $(PROJ_EDF_FILE) $(TCL_SCRIPT_CREATE_COMPILE_PAR_BITGEN)
$(TIME_CMD) $(VENDOR_TCL_SHELL) $(TCL_SCRIPT_CREATE_COMPILE_PAR_BITGEN)
 
par: $(TCL_SCRIPT_PAR)
$(TIME_CMD) $(VENDOR_TCL_SHELL) $<
 
223,6 → 227,17
$(Q)echo "\"">> $@
$(Q)echo >> $@
 
# Do project creation, compile and PAR in one single run of the tool
$(TCL_SCRIPT_CREATE_COMPILE_PAR_BITGEN):
TCL_FILE=$@ $(MAKE) tcl-common
$(Q)echo "run_designer \"Create compile and PAR and generate programming file\" \" " >> $@
TCL_FILE=$@ $(MAKE) dump-actel-create-project-tcl
TCL_FILE=$@ $(MAKE) dump-actel-compile-project-tcl
TCL_FILE=$@ $(MAKE) dump-actel-par-project-tcl
TCL_FILE=$@ $(MAKE) dump-actel-bitgen-project-tcl
$(Q)echo "\"">> $@
$(Q)echo >> $@
 
# The different texts that we dump out for the different sets of command files
 
# This is the common header, setting variables in the TCL file
/boards/actel/ordb1a3pe1500/syn/synplify/bin/Makefile
112,7 → 112,7
SYN_LOG ?=syn.log
SYN_TOOL ?=synplify_pro # Name of the executable to call
# Options passed after the executable.
SYN_LICENSE_OPTS ?=-licensetype synplifypro_acteloem
SYN_LICENSE_OPTS ?=-licensetype synplifypro_actel
SYN_TOOL_OPTS ?=$(SYN_SCRIPT) $(SYN_LICENSE_OPTS) -batch -log $(SYN_LOG)
 
 
/boards/xilinx/ml501/bench/verilog/include/eth_stim.v
76,7 → 76,7
parameter eth_stim_num_rx_only_packet_size = 512;
parameter eth_stim_num_rx_only_packet_size_change = 2'b01; // 2'b01: Increment
parameter eth_stim_num_rx_only_packet_size_change_amount = 1;
parameter eth_stim_num_rx_only_IPG = 800000; // ns
parameter eth_stim_num_rx_only_IPG = 800000000; // ns
 
// Do call/response test
reg eth_stim_do_rx_reponse_to_tx;
632,7 → 632,9
begin
//$display("Checking address in tx bd 0x%0h",txpnt_sdram);
sdram_byte = 8'hx;
`ifdef RAM_WB
sdram_byte = dut.ram_wb0.ram_wb_b3_0.get_byte(txpnt_sdram);
`endif
`ifdef VERSATILE_SDRAM
sdram0.get_byte(txpnt_sdram,sdram_byte);
`endif
1152,9 → 1154,12
begin
 
sdram_byte = 8'hx;
`ifdef RAM_WB
sdram_byte = dut.ram_wb0.ram_wb_b3_0.get_byte(rxpnt_sdram);
`endif
`ifdef VERSATILE_SDRAM
sdram0.get_byte(rxpnt_sdram,sdram_byte);
`endif
`endif
`ifdef XILINX_DDR2
get_byte_from_xilinx_ddr2(rxpnt_sdram, sdram_byte);
`endif
/boards/xilinx/ml501/rtl/verilog/include/ethmac_defines.v
191,23 → 191,23
`define ETH_TX_1KBYTE_FIFO // 1024 byte TX buffer - uncomment this
 
`ifdef ETH_TX_FULL_PACKET_FIFO
`define ETH_TX_FIFO_CNT_WIDTH 11
`define ETH_TX_FIFO_CNT_WIDTH 9
`define ETH_TX_FIFO_DEPTH 375
`else
`ifdef ETH_TX_1KBYTE_FIFO
`define ETH_TX_FIFO_CNT_WIDTH 9
`define ETH_TX_FIFO_CNT_WIDTH 8
`define ETH_TX_FIFO_DEPTH 256
`else
`ifdef ETH_TX_512BYTE_FIFO
`define ETH_TX_FIFO_CNT_WIDTH 8
`define ETH_TX_FIFO_CNT_WIDTH 7
`define ETH_TX_FIFO_DEPTH 128
`else
`ifdef ETH_TX_256BYTE_FIFO
`define ETH_TX_FIFO_CNT_WIDTH 7
`define ETH_TX_FIFO_CNT_WIDTH 6
`define ETH_TX_FIFO_DEPTH 64
`else
// Default is 64 bytes
`define ETH_TX_FIFO_CNT_WIDTH 5
`define ETH_TX_FIFO_CNT_WIDTH 4
`define ETH_TX_FIFO_DEPTH 16
`endif
`endif
217,15 → 217,15
 
 
// Settings for RX FIFO
`define ETH_RX_FIFO_CNT_WIDTH 9
`define ETH_RX_FIFO_CNT_WIDTH 8
`define ETH_RX_FIFO_DEPTH 256
//`define ETH_RX_FIFO_CNT_WIDTH 8
//`define ETH_RX_FIFO_CNT_WIDTH 7
//`define ETH_RX_FIFO_DEPTH 128
//`define ETH_RX_FIFO_CNT_WIDTH 7
//`define ETH_RX_FIFO_CNT_WIDTH 6
//`define ETH_RX_FIFO_DEPTH 64
//`define ETH_RX_FIFO_CNT_WIDTH 6
//`define ETH_RX_FIFO_CNT_WIDTH 5
//`define ETH_RX_FIFO_DEPTH 32
//`define ETH_RX_FIFO_CNT_WIDTH 5
//`define ETH_RX_FIFO_CNT_WIDTH 4
//`define ETH_RX_FIFO_DEPTH 16
 
`define ETH_RX_FIFO_DATA_WIDTH 32
/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/xilinx_ddr2.v
181,6 → 181,8
.wb_ack_o (wbs_ram_ack_o),
.wb_adr_i (wbs_ram_adr_i[31:0]),
.wb_stb_i (wbs_ram_stb_i),
.wb_cti_i (wbs_ram_cti_i),
.wb_bte_i (wbs_ram_bte_i),
.wb_cyc_i (wbs_ram_cyc_i),
.wb_we_i (wbs_ram_we_i),
.wb_sel_i (wbs_ram_sel_i[3:0]),
/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/xilinx_ddr2_if.v
104,6 → 104,8
input [31:0] wb_adr_i,
input wb_stb_i,
input wb_cyc_i,
input [2:0] wb_cti_i,
input [1:0] wb_bte_i,
input wb_we_i,
input [3:0] wb_sel_i,
input [31:0] wb_dat_i,
199,7 → 201,6
wire [(APPDATA_WIDTH)-1:0] rd_data_fifo_out;
wire phy_init_done;
assign cache_hit = (cached_addr == wb_adr_i[31:6]) & cached_addr_valid;
// Wishbone request detection
366,7 → 367,8
always @(posedge ddr2_clk)
if (ddr2_rst)
ddr2_read_done <= 0;
else if (!rd_data_valid & rd_data_valid_r) // Detect read data valid falling edge
// Detect read data valid falling edge
else if (!rd_data_valid & rd_data_valid_r)
ddr2_read_done <= 1;
else if (!(|ddr2_clk_phase) & !do_readfrom) // Read WB domain
ddr2_read_done <= 0;
/boards/xilinx/ml501/rtl/verilog/orpsoc_top/orpsoc_top.v
1037,8 → 1037,8
.wbm0_stb_i (wbs_i_mc0_stb_i),
.wbm0_dat_o (wbs_i_mc0_dat_o),
.wbm0_ack_o (wbs_i_mc0_ack_o),
.wbm0_err_o (),
.wbm0_rty_o (),
.wbm0_err_o (wbs_i_mc0_err_o),
.wbm0_rty_o (wbs_i_mc0_rty_o),
// Wishbone slave interface 1
.wbm1_dat_i (wbs_d_mc0_dat_i),
.wbm1_adr_i (wbs_d_mc0_adr_i),
1050,22 → 1050,30
.wbm1_stb_i (wbs_d_mc0_stb_i),
.wbm1_dat_o (wbs_d_mc0_dat_o),
.wbm1_ack_o (wbs_d_mc0_ack_o),
.wbm1_err_o (),
.wbm1_rty_o (),
.wbm1_err_o (wbs_d_mc0_err_o),
.wbm1_rty_o (wbs_d_mc0_rty_o),
// Wishbone slave interface 2
.wbm2_dat_i (wbm_eth0_dat_o),
.wbm2_adr_i (wbm_eth0_adr_o),
.wbm2_sel_i (wbm_eth0_sel_o),
.wbm2_cti_i (wbm_eth0_cti_o),
.wbm2_bte_i (wbm_eth0_bte_o),
.wbm2_we_i (wbm_eth0_we_o ),
.wbm2_cyc_i (wbm_eth0_cyc_o),
.wbm2_stb_i (wbm_eth0_stb_o),
.wbm2_dat_o (wbm_eth0_dat_i),
.wbm2_ack_o (wbm_eth0_ack_i),
.wbm2_err_o (wbm_eth0_err_i),
.wbm2_rty_o (wbm_eth0_rty_i),
// Clock, reset
.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst));
 
assign wbs_i_mc0_err_o = 0;
assign wbs_i_mc0_rty_o = 0;
 
assign wbs_d_mc0_err_o = 0;
assign wbs_d_mc0_rty_o = 0;
defparam ram_wb0.aw = wb_aw;
defparam ram_wb0.dw = wb_dw;
defparam ram_wb0.mem_span = internal_sram_mem_span;
defparam ram_wb0.adr_width_for_span = internal_sram_adr_width_for_span;
defparam ram_wb0.mem_size_bytes = (8192*1024); // 8MB
defparam ram_wb0.mem_adr_width = 23; // log2(8192*1024)
////////////////////////////////////////////////////////////////////////
`endif // `ifdef RAM_WB
 
/boards/xilinx/ml501/sw/board/include/board.h
10,8 → 10,8
// file, which is compiled and converted into Verilog for inclusion at
// synthesis time. See bootloader/bootloader.S for details on each option.
 
#define BOOTROM_SPI_FLASH
//#define BOOTROM_GOTO_RESET
//#define BOOTROM_SPI_FLASH
#define BOOTROM_GOTO_RESET
//#define BOOTROM_LOOP_AT_ZERO
//#define BOOTROM_LOOP_IN_ROM
 
/boards/xilinx/ml501/syn/xst/bin/Makefile
198,6 → 198,7
NGC_FILE=$(DESIGN_NAME).ngc
NETLIST_FILE=$(DESIGN_NAME).v
 
 
XST_PRJ_FILE_SRC_DECLARE=verilog work
 
print-config:
283,6 → 284,8
$(Q)(. $(XILINX_SETTINGS_SCRIPT) ; xst -ifn $(XST_FILE) $(XILINX_FLAGS) $(XST_FLAGS) )
$(Q)echo
 
netlist: $(NETLIST_FILE)
 
# Netlist generation command
$(NETLIST_FILE): $(NGC_FILE)
$(Q)echo; echo "\t#### Generating verilog netlist ####"; echo;

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