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    /openrisc/trunk/orpsocv2
    from Rev 479 to Rev 480
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Rev 479 → Rev 480

/boards/actel/ordb1a3pe1500/sw/Makefile.inc
15,8 → 15,6
RTL_VERILOG_INCLUDE_DIR=$(shell pwd)/$(BOARD_SW_ROOT)/../rtl/verilog/include
 
# Set the processor capability flags
# This doesn't work! :-( Need to figure out way to set these and have them
# carry through to things like the liborpsoc driver modules etc.
#MARCH_FLAGS =-mhard-mul -mhard-div -msoft-float
MARCH_FLAGS =-mhard-mul -msoft-div -msoft-float
export MARCH_FLAGS
/boards/xilinx/ml501/bench/verilog/include/eth_stim.v
72,11 → 72,11
integer lfsr_last_byte;
 
// Is number of ethernet packets to send if doing the eth-rx test.
parameter eth_stim_num_rx_only_num_packets = 500; // Set to 0 for continuous RX
parameter eth_stim_num_rx_only_packet_size = 512;
parameter eth_stim_num_rx_only_num_packets = 12; // Set to 0 for continuous RX
parameter eth_stim_num_rx_only_packet_size = 60;
parameter eth_stim_num_rx_only_packet_size_change = 2'b01; // 2'b01: Increment
parameter eth_stim_num_rx_only_packet_size_change_amount = 1;
parameter eth_stim_num_rx_only_IPG = 800000000; // ns
parameter eth_stim_num_rx_only_packet_size_change_amount = 127;
parameter eth_stim_num_rx_only_IPG = 180_000_000; // ps
 
// Do call/response test
reg eth_stim_do_rx_reponse_to_tx;
95,10 → 95,10
 
// Use the smallest possible IPG
parameter eth_stim_use_min_IPG = 0;
parameter eth_stim_IPG_delay_max = 500_000; // Maximum 500uS ga
parameter eth_stim_IPG_delay_max = 500_000_000; // Maximum 500uS ga
//parameter eth_stim_IPG_delay_max = 100_000_000; // Maximum 100mS between packets
parameter eth_stim_IPG_min_10mb = 9600; // 9.6 uS
parameter eth_stim_IPG_min_100mb = 800; // 860+~100 = 960 nS 100MBit min IPG
parameter eth_stim_IPG_min_10mb = 9600_000; // 9.6 uS
parameter eth_stim_IPG_min_100mb = 800_000; // 860+~100 = 960 nS 100MBit min IPG
parameter eth_stim_check_rx_packet_contents = 1;
parameter eth_stim_check_tx_packet_contents = 1;
 
115,8 → 115,6
// For 64MHz sdram controller, use following:
parameter Td_rx_packet_check = (`BOARD_CLOCK_PERIOD * 500);
 
 
 
integer expected_rxbd;// init to 0
integer expected_txbd;
 
581,7 → 579,25
 
`endif
 
`ifdef XILINX_DDR2
task sync_controller_cache_xilinx_ddr;
begin
// Sync cache (writeback dirty lines) with external memory
dut.xilinx_ddr2_0.xilinx_ddr2_if0.do_sync;
// Wait for it to occur.
while (dut.xilinx_ddr2_0.xilinx_ddr2_if0.sync)
#100;
 
// Wait just incase writeback of all data hasn't fully occurred.
// 4uS, in case RAM needs to refresh while writing back.
#4_000_000;
end
endtask // sync_controller_cache_xilinx_ddr
`endif
 
//
// Check packet TX'd by MAC was good
//
602,7 → 618,7
integer failure;
begin
failure = 0;
get_bd_lenstat(tx_bd_num, tx_len_bd);
tx_len_bd = {15'd0,tx_len_bd[31:16]};
616,6 → 632,10
#100;
$finish;
end
 
`ifdef XILINX_DDR2
sync_controller_cache_xilinx_ddr;
`endif
get_bd_addr(tx_bd_num, tx_bd_addr);
634,27 → 654,26
sdram_byte = 8'hx;
`ifdef RAM_WB
sdram_byte = dut.ram_wb0.ram_wb_b3_0.get_byte(txpnt_sdram);
`endif
`ifdef VERSATILE_SDRAM
sdram0.get_byte(txpnt_sdram,sdram_byte);
`else
`ifdef VERSATILE_SDRAM
sdram0.get_byte(txpnt_sdram,sdram_byte);
`else
`ifdef XILINX_DDR2
get_byte_from_xilinx_ddr2(txpnt_sdram, sdram_byte);
`else
$display(" * Error: sdram_byte was %x", sdram_byte);
$display(" * eth_stim needs to be able to access the main memory to check packet rx/tx");
$finish;
`endif
`endif
`endif
`ifdef XILINX_DDR2
get_byte_from_xilinx_ddr2(txpnt_sdram, sdram_byte);
`endif
if (sdram_byte === 8'hx)
begin
$display(" * Error: sdram_byte was %x", sdram_byte);
$display(" * eth_stim needs to be able to access the main memory to check packet rx/tx");
$display(" * RAM pointer for BD is 0x%h, bank offset we'll use is 0x%h",
tx_bd_addr, txpnt_wb);
$finish;
end
 
 
phy_byte = eth_phy0.tx_mem[buffer];
// Debugging output
//$display("txpnt_sdram = 0x%h, sdram_byte = 0x%h, buffer = 0x%h, phy_byte = 0x%h", txpnt_sdram, sdram_byte, buffer, phy_byte);
if (phy_byte !== sdram_byte)
begin
`TIME;
1107,7 → 1126,6
reg [24:0] rxpnt_sdram; // byte address from CPU in RAM
reg [15:0] sdram_short;
reg [7:0] sdram_byte;
//reg [7:0] phy_rx_mem [0:2000];
integer i;
integer failure;
1131,6 → 1149,10
// Delay some time - takes a bit for the Wishbone FSM to pipe out the
// packet over Wishbone and into whatever memory it's going into
#Td_rx_packet_check;
 
`ifdef XILINX_DDR2
sync_controller_cache_xilinx_ddr;
`endif
// Ok, buffer filled, let's get its offset in memory
get_bd_addr(rx_bd_num, rx_bd_addr);
1154,31 → 1176,21
begin
 
sdram_byte = 8'hx;
`ifdef RAM_WB
sdram_byte = dut.ram_wb0.ram_wb_b3_0.get_byte(rxpnt_sdram);
`endif
`ifdef VERSATILE_SDRAM
sdram0.get_byte(rxpnt_sdram,sdram_byte);
`endif
`ifdef XILINX_DDR2
get_byte_from_xilinx_ddr2(rxpnt_sdram, sdram_byte);
`endif
if (sdram_byte === 8'hx)
begin
$display(" * Error:");
$display(" * eth_stim needs to be able to access the main memory to check packet rx/tx");
$display("RAM pointer for BD is 0x%h, bank offset we'll use is 0x%h",
rx_bd_addr, rxpnt_wb);
$finish;
end
`else
$display(" * Error:");
$display(" * eth_stim needs to be able to access the main memory to check packet rx/tx");
$finish;
`endif
phy_byte = eth_rx_sent_circbuf[eth_rx_sent_circbuf_read_ptr];
 
phy_byte = eth_rx_sent_circbuf[eth_rx_sent_circbuf_read_ptr];//phy_rx_mem[buffer]; //eth_phy0.rx_mem[buffer];
 
if (phy_byte !== sdram_byte)
begin
// `TIME;
$display("*E Wrong byte (%5d) of RX packet %5d! phy = %h, ram = %h",
$display("*E Wrong byte (%5d) of RX packet %5d. phy mem = %h, ram = %h",
i, eth_rx_num_packets_checked, phy_byte, sdram_byte);
failure = 1;
end
/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/ddr2_ctrl.v
347,10 → 347,14
// for simulation purposes - to force CTRL_AF_RDEN low during reset
if (rst_r1)
rd_af_flag_r <= 1'd0;
else if (rd_af_flag_r) // jb - probably should find a way to stop this toggling all the time
rd_af_flag_r <= 0; // jb
else if (rd_af_flag_r) // jb - probably should find a way
// to stop this toggling all the time
rd_af_flag_r <= 0; // jb
else if((ctrl_af_rden_r) ||
(/*rd_af_flag_r &&*/ (af_valid_r || af_valid_r1))) // Fixed bug where third addresses would get lost (pulled off fifo and then clobbered by other value later, thus ignored/skipped) - just make sure we don't get too excited and pull too many off at once - jb
(/*rd_af_flag_r &&*/ (af_valid_r || af_valid_r1)))
// Fixed bug where third addresses would get lost (pulled off fifo and
// then clobbered by other value later, thus ignored/skipped) - just
// make sure we don't get too excited and pull too many off at once - jb
rd_af_flag_r <= 1'd0;
else if (~af_valid_r1 || ~af_valid_r)
rd_af_flag_r <= 1'd1;
/boards/xilinx/ml501/rtl/verilog/xilinx_ddr2/xilinx_ddr2_if.v
95,7 → 95,7
* wb_clk:do_readfrom -> ddr2_clk:ddr2_read_done
*
*/
module xilinx_ddr2_if2 (
module xilinx_ddr2_if (
input [31:0] wb_adr_i,
input wb_stb_i,
input wb_cyc_i,
250,8 → 250,12
wire ack_err;
reg ack_err_r;
 
 
// Synchronisation signals
reg sync, sync_r;
wire sync_start;
wire sync_done;
 
// Decoded select line
wire [`DDR2_CACHE_NUM_LINES-1:0] selected_cache_line;
wire [`DDR2_CACHE_NUM_LINES_ENC_WIDTH-1:0] selected_cache_line_enc;
283,6 → 287,7
.cache_line_invalidate (cache_line_addr_invalidate),
.selected_cache_line (selected_cache_line),
.selected_cache_line_enc (selected_cache_line_enc),
.sync_done (sync_done),
// Inputs
.cache_line_addr_valid (cache_line_addr_valid),
.cache_line_addr_hit (cache_line_hit),
290,6 → 295,7
.cache_write (cache_write),
.writeback_done (do_writeback_finished),
.fill_done (do_readfrom_finished),
.sync_start (sync_start),
.wb_clk (wb_clk),
.wb_rst (wb_rst));
 
310,7 → 316,7
assign wb_req_addr_hit = (wb_req & cache_hit & cached_addr_valid);
// Wishbone request detection
assign wb_req = wb_stb_i & wb_cyc_i & phy_init_done;
assign wb_req = wb_stb_i & wb_cyc_i & phy_init_done & !sync;
always @(posedge wb_clk)
wb_req_r <= wb_req;
407,6 → 413,28
always @(posedge wb_clk)
wb_ack_o_r <= wb_ack_o;
// Logic controling synchronisation
always @(posedge wb_clk)
if (wb_rst)
sync <= 0;
else if (sync_done) // Sync. done indicator from cache controller
sync <= 0;
 
always @(posedge wb_clk)
sync_r <= sync;
 
assign sync_start = sync & !sync_r;
task do_sync;
begin
// Wait for us to not be doing a transaction.
while(wb_req)
@wb_clk;
// Cache not busy, initiate sync.
sync = 1;
end
endtask // do_sync
 
// Writeback/readfrom lower address generation
always @(posedge wb_clk)
if (wb_rst)
717,10 → 745,11
endmodule // xilinx_ddr2_wb_if_cache_adr_reg
 
module xilinx_ddr2_wb_if_cache_control
( cache_line_addr_valid, cache_line_addr_hit,
( cache_line_addr_valid, cache_line_addr_hit,
wb_req,
cache_write,
writeback_done, fill_done,
writeback_done, fill_done,
sync_start, sync_done,
start_writeback, start_fill,
cache_line_validate, cache_line_invalidate,
selected_cache_line, selected_cache_line_enc,
735,33 → 764,44
input wb_req;
input cache_write;
input writeback_done, fill_done;
 
input sync_start;
output sync_done;
output reg start_writeback;
output reg start_fill;
output reg [num_lines-1:0] cache_line_validate;
output reg [num_lines-1:0] cache_line_invalidate;
output [num_lines-1:0] selected_cache_line;
output [num_lines-1:0] selected_cache_line;
output reg [num_lines_log2-1:0] selected_cache_line_enc;
input wb_clk, wb_rst;
input wb_clk, wb_rst;
reg [num_lines-1:0] dirty;
reg [num_lines-1:0] lines_dirty;
reg [num_lines-1:0] selected_cache_line_from_miss;
 
reg selected_cache_line_new;
reg [num_lines-1:0] selected_cache_line_from_miss;
reg invalidate_clean_line;
reg selected_cache_line_new;
reg [num_lines-1:0] selected_cache_line_r;
reg [num_lines-1:0] selected_cache_line_r2;
reg invalidate_clean_line;
reg [num_lines-1:0] selected_cache_line_r;
reg [num_lines-1:0] selected_cache_line_r2;
reg wb_req_r;
wire wb_req_new;
reg wb_req_new_r;
parameter sync_line_check_wait = 4;
reg [num_lines-1:0] sync_line_counter;
reg sync_doing;
reg [sync_line_check_wait-1:0] sync_line_select_wait_counter_shr;
reg sync_line_done;
wire sync_writeback_line;
 
reg wb_req_r;
 
wire wb_req_new;
reg wb_req_new_r;
 
always @(posedge wb_clk)
wb_req_r <= wb_req;
789,6 → 829,8
selected_cache_line_r <= cache_line_addr_valid & cache_line_addr_hit;
else if (wb_req_new_r & !(|selected_cache_line_r))
selected_cache_line_r <= selected_cache_line_from_miss;
else if (sync_doing)
selected_cache_line_r <= sync_line_counter;
 
always @(posedge wb_clk)
selected_cache_line_r2 <= selected_cache_line_r;
811,11 → 853,11
 
always @(posedge wb_clk)
if (wb_rst)
dirty <= 0;
lines_dirty <= 0;
else if (cache_write)
dirty <= dirty | selected_cache_line_r;
lines_dirty <= lines_dirty | selected_cache_line_r;
else if (writeback_done)
dirty <= dirty & ~(selected_cache_line_r);
lines_dirty <= lines_dirty & ~(selected_cache_line_r);
// Validate the cache line address in the register when line filled
always @(posedge wb_clk)
830,7 → 872,7
always @(posedge wb_clk)
if (wb_rst)
cache_line_invalidate <= 0;
else if (writeback_done | invalidate_clean_line)
else if ((writeback_done & !sync_doing) | invalidate_clean_line)
cache_line_invalidate <= selected_cache_line_r;
else if (|cache_line_invalidate)
cache_line_invalidate <= 0;
839,12 → 881,15
always @(posedge wb_clk)
if (wb_rst)
start_writeback <= 0;
else if (selected_cache_line_new & (|(dirty & selected_cache_line_r)) &
else if (start_writeback)
start_writeback <= 0;
else if (selected_cache_line_new &
(|(lines_dirty & selected_cache_line_r)) &
(|(selected_cache_line_r & cache_line_addr_valid)) &
!(|(cache_line_addr_hit & selected_cache_line_r)))
start_writeback <= 1;
else if (start_writeback)
start_writeback <= 0;
else if (sync_writeback_line)
start_writeback <= 1;
 
// Invalidate lines which we haven't written to so we can fill them
always @(posedge wb_clk)
853,7 → 898,7
else if (invalidate_clean_line)
invalidate_clean_line <= 0;
else if ((selected_cache_line_new) & // New line selected
!(|(dirty & selected_cache_line_r)) & // It's not dirty
!(|(lines_dirty & selected_cache_line_r)) & // It's not dirty
// It's valid, but we've selected it so we're trashing it
(|(selected_cache_line_r & cache_line_addr_valid)) &
!(|(cache_line_addr_hit & selected_cache_line_r))) // Not a hit
871,13 → 916,13
else if (((selected_cache_line_new) & // New line selected
// not valid
!(|(cache_line_addr_valid & selected_cache_line_r))) |
writeback_done | invalidate_clean_line_r
(writeback_done & !sync_doing) | invalidate_clean_line_r
)
start_fill <= 1;
else if (start_fill)
start_fill <= 0;
 
// Relies on there only being 4 lines
// Hardcoded to 4 lines currently.
always @(posedge wb_clk)
if (selected_cache_line_r[0])
selected_cache_line_enc <= 0;
889,4 → 934,55
selected_cache_line_enc <= 3;
 
 
// Synchronisation control
 
always @(posedge wb_clk)
if (wb_rst)
sync_doing <= 0;
else if (sync_start)
sync_doing <= 1;
else if (sync_done)
sync_doing <= 0;
 
always @(posedge wb_clk)
if (wb_rst)
sync_line_counter <= 0;
else if (sync_start)
// Set first line to check
sync_line_counter[0] <= 1'b1;
else if (sync_line_done)
// Shift along, check next line
sync_line_counter <= {sync_line_counter[num_lines-2:0], 1'b0};
 
// Pulse this on finishing of checking lines
assign sync_done = sync_line_counter[num_lines-1] & sync_line_done;
// Pulses when a dirty line is detected and should be written back.
assign sync_writeback_line = sync_doing &
sync_line_select_wait_counter_shr[0] &
cache_line_addr_valid &
|(sync_line_counter & lines_dirty);
always @(posedge wb_clk)
if (wb_rst)
sync_line_select_wait_counter_shr <= 0;
else if (|sync_line_select_wait_counter_shr)
sync_line_select_wait_counter_shr
<= {1'b0,sync_line_select_wait_counter_shr[sync_line_check_wait-1:1]};
else if (sync_start | (sync_line_done & !sync_done))
sync_line_select_wait_counter_shr[sync_line_check_wait-1] <= 1'b1;
 
always @(posedge wb_clk)
if (wb_rst)
sync_line_done <= 1'b0;
else if (sync_line_done)
sync_line_done <= 1'b0;
// Either line doesn't need writeback
else if (sync_line_select_wait_counter_shr[0] & !sync_writeback_line)
sync_line_done <= 1'b1;
// Or writeback finished
else if (writeback_done & sync_doing)
sync_line_done <= 1'b1;
 
endmodule // xilinx_ddr2_wb_if_cache_control
/boards/xilinx/ml501/sw/eth/eth_reset.S File deleted
/boards/xilinx/ml501/sw/eth/mii.h File deleted
/boards/xilinx/ml501/sw/eth/open_eth.h File deleted
/boards/xilinx/ml501/sw/eth/except.S File deleted
/boards/xilinx/ml501/sw/eth/Makefile File deleted
/boards/xilinx/ml501/sw/eth/eth.ld File deleted
/boards/xilinx/ml501/sw/eth/eth.c File deleted
/boards/xilinx/ml501/sw/gpio/gpio.c File deleted
/boards/xilinx/ml501/sw/gpio/gpio_reset.S File deleted
/boards/xilinx/ml501/sw/gpio/gpio.ld File deleted
/boards/xilinx/ml501/sw/gpio/Makefile File deleted \ No newline at end of file
/boards/xilinx/ml501/sw/memtest/Makefile File deleted \ No newline at end of file
/boards/xilinx/ml501/sw/memtest/memtest.c File deleted
/boards/xilinx/ml501/sw/memtest/memtest_reset.S File deleted
/boards/xilinx/ml501/sw/memtest/memtest.ld File deleted
/boards/xilinx/ml501/sw/Makefile.inc
15,11 → 15,9
RTL_VERILOG_INCLUDE_DIR=$(shell pwd)/$(BOARD_SW_ROOT)/../rtl/verilog/include
 
# Set the processor capability flags
# This doesn't work! :-( Need to figure out way to set these and have them
# carry through to things like the liborpsoc driver modules etc.
#MARCH_FLAGS =-mhard-mul -mhard-div -msoft-float
MARCH_FLAGS =-mhard-mul -mhard-div -mhard-float
#MARCH_FLAGS =-mhard-mul -msoft-div -msoft-float
#export MARCH_FLAGS
export MARCH_FLAGS
 
# Finally include the main software include file
 

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