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rtl/verilog/intercon.vm Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: rtl/verilog/components/wb_conbus/wb_conbus_top.v =================================================================== --- rtl/verilog/components/wb_conbus/wb_conbus_top.v (nonexistent) +++ rtl/verilog/components/wb_conbus/wb_conbus_top.v (revision 54) @@ -0,0 +1,765 @@ +////////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE Connection Bus Top Level //// +//// //// +//// //// +//// Author: Johny Chi //// +//// chisuhua@yahoo.com.cn //// +//// Modified to include or1200 boot instructions (jb@orsoc.se) //// +//// //// +//// Downloaded from: http://opencores.org/project,wb_conbus //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000 Authors and OPENCORES.ORG //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// Description +// 1. Up to 8 masters and 8 slaves share bus Wishbone connection +// 2. no priorty arbitor , 8 masters are processed in a round +// robin way, +// 3. if WB_USE_TRISTATE was defined, the share bus is a tristate +// bus, and use less logic resource. +// 4. wb_conbus was synthesis to XC2S100-5-PQ208 using synplify, +// Max speed >60M , and 374 SLICE if using Multiplexor bus +// or 150 SLICE if using tri-state bus. +// +`define dw 32 // Data bus Width +`define aw 32 // Address bus Width +`define sw `dw / 8 // Number of Select Lines +`define mbusw `aw + `sw + `dw +4 //address width + byte select width + dat width + cyc + we + stb +cab , input from master interface +`define sbusw 3 // ack + err + rty, input from slave interface +`define mselectw 8 // number of masters +`define sselectw 8 // number of slavers + +//`define WB_USE_TRISTATE + +// Define the following to enable logic to generate the first few instructions at reset +`define OR1200_BOOT_LOGIC + +module wb_conbus_top( + clk_i, rst_i, + + // Master 0 Interface + m0_dat_i, m0_dat_o, m0_adr_i, m0_sel_i, m0_we_i, m0_cyc_i, + m0_stb_i, m0_ack_o, m0_err_o, m0_rty_o, m0_cab_i, + + // Master 1 Interface + m1_dat_i, m1_dat_o, m1_adr_i, m1_sel_i, m1_we_i, m1_cyc_i, + m1_stb_i, m1_ack_o, m1_err_o, m1_rty_o, m1_cab_i, + + // Master 2 Interface + m2_dat_i, m2_dat_o, m2_adr_i, m2_sel_i, m2_we_i, m2_cyc_i, + m2_stb_i, m2_ack_o, m2_err_o, m2_rty_o, m2_cab_i, + + // Master 3 Interface + m3_dat_i, m3_dat_o, m3_adr_i, m3_sel_i, m3_we_i, m3_cyc_i, + m3_stb_i, m3_ack_o, m3_err_o, m3_rty_o, m3_cab_i, + + // Master 4 Interface + m4_dat_i, m4_dat_o, m4_adr_i, m4_sel_i, m4_we_i, m4_cyc_i, + m4_stb_i, m4_ack_o, m4_err_o, m4_rty_o, m4_cab_i, + + // Master 5 Interface + m5_dat_i, m5_dat_o, m5_adr_i, m5_sel_i, m5_we_i, m5_cyc_i, + m5_stb_i, m5_ack_o, m5_err_o, m5_rty_o, m5_cab_i, + + // Master 6 Interface + m6_dat_i, m6_dat_o, m6_adr_i, m6_sel_i, m6_we_i, m6_cyc_i, + m6_stb_i, m6_ack_o, m6_err_o, m6_rty_o, m6_cab_i, + + // Master 7 Interface + m7_dat_i, m7_dat_o, m7_adr_i, m7_sel_i, m7_we_i, m7_cyc_i, + m7_stb_i, m7_ack_o, m7_err_o, m7_rty_o, m7_cab_i, + + // Slave 0 Interface + s0_dat_i, s0_dat_o, s0_adr_o, s0_sel_o, s0_we_o, s0_cyc_o, + s0_stb_o, s0_ack_i, s0_err_i, s0_rty_i, s0_cab_o, + + // Slave 1 Interface + s1_dat_i, s1_dat_o, s1_adr_o, s1_sel_o, s1_we_o, s1_cyc_o, + s1_stb_o, s1_ack_i, s1_err_i, s1_rty_i, s1_cab_o, + + // Slave 2 Interface + s2_dat_i, s2_dat_o, s2_adr_o, s2_sel_o, s2_we_o, s2_cyc_o, + s2_stb_o, s2_ack_i, s2_err_i, s2_rty_i, s2_cab_o, + + // Slave 3 Interface + s3_dat_i, s3_dat_o, s3_adr_o, s3_sel_o, s3_we_o, s3_cyc_o, + s3_stb_o, s3_ack_i, s3_err_i, s3_rty_i, s3_cab_o, + + // Slave 4 Interface + s4_dat_i, s4_dat_o, s4_adr_o, s4_sel_o, s4_we_o, s4_cyc_o, + s4_stb_o, s4_ack_i, s4_err_i, s4_rty_i, s4_cab_o, + + // Slave 5 Interface + s5_dat_i, s5_dat_o, s5_adr_o, s5_sel_o, s5_we_o, s5_cyc_o, + s5_stb_o, s5_ack_i, s5_err_i, s5_rty_i, s5_cab_o, + + // Slave 6 Interface + s6_dat_i, s6_dat_o, s6_adr_o, s6_sel_o, s6_we_o, s6_cyc_o, + s6_stb_o, s6_ack_i, s6_err_i, s6_rty_i, s6_cab_o, + + // Slave 7 Interface + s7_dat_i, s7_dat_o, s7_adr_o, s7_sel_o, s7_we_o, s7_cyc_o, + s7_stb_o, s7_ack_i, s7_err_i, s7_rty_i, s7_cab_o + + ); + + //////////////////////////////////////////////////////////////////// + // + // Module Parameters + // + + + parameter s0_addr_w = 4 ; // slave 0 address decode width + parameter s0_addr = 4'h0; // slave 0 address + parameter s1_addr_w = 4 ; // slave 1 address decode width + parameter s1_addr = 4'h1; // slave 1 address + parameter s27_addr_w = 8 ; // slave 2 to slave 7 address decode width + parameter s2_addr = 8'h92; // slave 2 address + parameter s3_addr = 8'h93; // slave 3 address + parameter s4_addr = 8'h94; // slave 4 address + parameter s5_addr = 8'h95; // slave 5 address + parameter s6_addr = 8'h96; // slave 6 address + parameter s7_addr = 8'h97; // slave 7 address + + + //////////////////////////////////////////////////////////////////// + // + // Module IOs + // + + input clk_i, rst_i; + + // Master 0 Interface + input [`dw-1:0] m0_dat_i; + output [`dw-1:0] m0_dat_o; + input [`aw-1:0] m0_adr_i; + input [`sw-1:0] m0_sel_i; + input m0_we_i; + input m0_cyc_i; + input m0_stb_i; + input m0_cab_i; + output m0_ack_o; + output m0_err_o; + output m0_rty_o; + + // Master 1 Interface + input [`dw-1:0] m1_dat_i; + output [`dw-1:0] m1_dat_o; + input [`aw-1:0] m1_adr_i; + input [`sw-1:0] m1_sel_i; + input m1_we_i; + input m1_cyc_i; + input m1_stb_i; + input m1_cab_i; + output m1_ack_o; + output m1_err_o; + output m1_rty_o; + + // Master 2 Interface + input [`dw-1:0] m2_dat_i; + output [`dw-1:0] m2_dat_o; + input [`aw-1:0] m2_adr_i; + input [`sw-1:0] m2_sel_i; + input m2_we_i; + input m2_cyc_i; + input m2_stb_i; + input m2_cab_i; + output m2_ack_o; + output m2_err_o; + output m2_rty_o; + + // Master 3 Interface + input [`dw-1:0] m3_dat_i; + output [`dw-1:0] m3_dat_o; + input [`aw-1:0] m3_adr_i; + input [`sw-1:0] m3_sel_i; + input m3_we_i; + input m3_cyc_i; + input m3_stb_i; + input m3_cab_i; + output m3_ack_o; + output m3_err_o; + output m3_rty_o; + + // Master 4 Interface + input [`dw-1:0] m4_dat_i; + output [`dw-1:0] m4_dat_o; + input [`aw-1:0] m4_adr_i; + input [`sw-1:0] m4_sel_i; + input m4_we_i; + input m4_cyc_i; + input m4_stb_i; + input m4_cab_i; + output m4_ack_o; + output m4_err_o; + output m4_rty_o; + + // Master 5 Interface + input [`dw-1:0] m5_dat_i; + output [`dw-1:0] m5_dat_o; + input [`aw-1:0] m5_adr_i; + input [`sw-1:0] m5_sel_i; + input m5_we_i; + input m5_cyc_i; + input m5_stb_i; + input m5_cab_i; + output m5_ack_o; + output m5_err_o; + output m5_rty_o; + + // Master 6 Interface + input [`dw-1:0] m6_dat_i; + output [`dw-1:0] m6_dat_o; + input [`aw-1:0] m6_adr_i; + input [`sw-1:0] m6_sel_i; + input m6_we_i; + input m6_cyc_i; + input m6_stb_i; + input m6_cab_i; + output m6_ack_o; + output m6_err_o; + output m6_rty_o; + + // Master 7 Interface + input [`dw-1:0] m7_dat_i; + output [`dw-1:0] m7_dat_o; + input [`aw-1:0] m7_adr_i; + input [`sw-1:0] m7_sel_i; + input m7_we_i; + input m7_cyc_i; + input m7_stb_i; + input m7_cab_i; + output m7_ack_o; + output m7_err_o; + output m7_rty_o; + + // Slave 0 Interface + input [`dw-1:0] s0_dat_i; + output [`dw-1:0] s0_dat_o; + output [`aw-1:0] s0_adr_o; + output [`sw-1:0] s0_sel_o; + output s0_we_o; + output s0_cyc_o; + output s0_stb_o; + output s0_cab_o; + input s0_ack_i; + input s0_err_i; + input s0_rty_i; + + // Slave 1 Interface + input [`dw-1:0] s1_dat_i; + output [`dw-1:0] s1_dat_o; + output [`aw-1:0] s1_adr_o; + output [`sw-1:0] s1_sel_o; + output s1_we_o; + output s1_cyc_o; + output s1_stb_o; + output s1_cab_o; + input s1_ack_i; + input s1_err_i; + input s1_rty_i; + + // Slave 2 Interface + input [`dw-1:0] s2_dat_i; + output [`dw-1:0] s2_dat_o; + output [`aw-1:0] s2_adr_o; + output [`sw-1:0] s2_sel_o; + output s2_we_o; + output s2_cyc_o; + output s2_stb_o; + output s2_cab_o; + input s2_ack_i; + input s2_err_i; + input s2_rty_i; + + // Slave 3 Interface + input [`dw-1:0] s3_dat_i; + output [`dw-1:0] s3_dat_o; + output [`aw-1:0] s3_adr_o; + output [`sw-1:0] s3_sel_o; + output s3_we_o; + output s3_cyc_o; + output s3_stb_o; + output s3_cab_o; + input s3_ack_i; + input s3_err_i; + input s3_rty_i; + + // Slave 4 Interface + input [`dw-1:0] s4_dat_i; + output [`dw-1:0] s4_dat_o; + output [`aw-1:0] s4_adr_o; + output [`sw-1:0] s4_sel_o; + output s4_we_o; + output s4_cyc_o; + output s4_stb_o; + output s4_cab_o; + input s4_ack_i; + input s4_err_i; + input s4_rty_i; + + // Slave 5 Interface + input [`dw-1:0] s5_dat_i; + output [`dw-1:0] s5_dat_o; + output [`aw-1:0] s5_adr_o; + output [`sw-1:0] s5_sel_o; + output s5_we_o; + output s5_cyc_o; + output s5_stb_o; + output s5_cab_o; + input s5_ack_i; + input s5_err_i; + input s5_rty_i; + + // Slave 6 Interface + input [`dw-1:0] s6_dat_i; + output [`dw-1:0] s6_dat_o; + output [`aw-1:0] s6_adr_o; + output [`sw-1:0] s6_sel_o; + output s6_we_o; + output s6_cyc_o; + output s6_stb_o; + output s6_cab_o; + input s6_ack_i; + input s6_err_i; + input s6_rty_i; + + // Slave 7 Interface + input [`dw-1:0] s7_dat_i; + output [`dw-1:0] s7_dat_o; + output [`aw-1:0] s7_adr_o; + output [`sw-1:0] s7_sel_o; + output s7_we_o; + output s7_cyc_o; + output s7_stb_o; + output s7_cab_o; + input s7_ack_i; + input s7_err_i; + input s7_rty_i; + + + //////////////////////////////////////////////////////////////////// + // + // Local wires + // + + wire [`mselectw -1:0] i_gnt_arb; + wire [2:0] gnt; + reg [`sselectw -1:0] i_ssel_dec; +`ifdef WB_USE_TRISTATE + wire [`mbusw -1:0] i_bus_m; +`else + reg [`mbusw -1:0] i_bus_m; // internal share bus, master data and control to slave +`endif + wire [`dw -1:0] i_dat_s; // internal share bus , slave data to master + wire [`sbusw -1:0] i_bus_s; // internal share bus , slave control to master + + wire [7:0] addr_err; // Generate an error signal when no slave is selected + reg addr_err_r; + wire addr_err_out; + + //////////////////////////////////////////////////////////////////// + // + // OR1200 reset boot instruction generation + // +`ifdef OR1200_BOOT_LOGIC + // Presumes OR1200 instruction bus is master 0 + reg [2:0] count; + reg proc_init; + reg proc_init_ack_o; + reg [31:0] proc_init_dat_o; + `define OR1200_BOOT_LOGIC_NUM_INSNS 4 + + always @(posedge clk_i or posedge rst_i) + begin + if (rst_i) + begin + proc_init <= 1'b1; + count <= 0; + proc_init_ack_o <= 1'b0; + end + else + begin + if (proc_init) + begin + // Advance counter when de asserting ack + if (m0_cyc_i & m0_stb_i & proc_init_ack_o) + begin + proc_init_ack_o <= 1'b0; + + if (count < `OR1200_BOOT_LOGIC_NUM_INSNS) + count <= count + 1; + end + + // Assert ack + if (m0_cyc_i & m0_stb_i & ~proc_init_ack_o) + proc_init_ack_o <= 1'b1; + + // Finish this init logic when we've output all insns + if (count == `OR1200_BOOT_LOGIC_NUM_INSNS) + proc_init <= 1'b0; + end // if (proc_init) + end // else: !if(rst_i) + end // always @ (posedge clk_i or posedge rst_i) + //`define ARB_BOOT_TOP_WORD f000 + //`define ARB_BOOT_BTM_WORD 0100 + + always @(count) + begin + case (count) + // 0: proc_init_dat_o <= 32'h1820_`ARB_BOOT_TOP_WORD; //l.movhi r1,0xf000 + // 1: proc_init_dat_o <= 32'ha821_`ARB_BOOT_BTM_WORD; //l.ori r1,r1,0x100 + 0: proc_init_dat_o = 32'h1820_f000; //l.movhi r1,0xf000 + 1: proc_init_dat_o = 32'ha821_0100; //l.ori r1,r1,0x100 + + 2: proc_init_dat_o = 32'h44000800; //l.jr r1 + 3: proc_init_dat_o = 32'h15000000; //l.nop 0x0 + 4: proc_init_dat_o = 32'h15000000; //l.nop 0x0 + endcase // case (count) + end + + + + //////////////////////////////////////////////////////////////////// + // + // Master output Interfaces + // + + // master0 + assign m0_dat_o = proc_init ? proc_init_dat_o : i_dat_s; + assign {m0_ack_o, m0_err_o, m0_rty_o} = proc_init ? {proc_init_ack_o, 2'b00} : + i_bus_s & {3{i_gnt_arb[0]}}; + +`else // !`ifdef OR1200_BOOT_LOGIC + + // master0 + assign m0_dat_o = i_dat_s; + assign {m0_ack_o, m0_err_o, m0_rty_o} = i_bus_s & {3{i_gnt_arb[0]}}; +`endif // !`ifdef OR1200_BOOT_LOGIC + + // master1 + assign m1_dat_o = i_dat_s; + assign {m1_ack_o, m1_err_o, m1_rty_o} = i_bus_s & {3{i_gnt_arb[1]}}; + + // master2 + + assign m2_dat_o = i_dat_s; + assign {m2_ack_o, m2_err_o, m2_rty_o} = i_bus_s & {3{i_gnt_arb[2]}}; + + // master3 + + assign m3_dat_o = i_dat_s; + assign {m3_ack_o, m3_err_o, m3_rty_o} = i_bus_s & {3{i_gnt_arb[3]}}; + + // master4 + + assign m4_dat_o = i_dat_s; + assign {m4_ack_o, m4_err_o, m4_rty_o} = i_bus_s & {3{i_gnt_arb[4]}}; + + // master5 + + assign m5_dat_o = i_dat_s; + assign {m5_ack_o, m5_err_o, m5_rty_o} = i_bus_s & {3{i_gnt_arb[5]}}; + + // master6 + + assign m6_dat_o = i_dat_s; + assign {m6_ack_o, m6_err_o, m6_rty_o} = i_bus_s & {3{i_gnt_arb[6]}}; + + // master7 + + assign m7_dat_o = i_dat_s; + assign {m7_ack_o, m7_err_o, m7_rty_o} = i_bus_s & {3{i_gnt_arb[7]}}; + + // Now containing additional no-existing slave select err bit -- jb 090905 + assign i_bus_s = {s0_ack_i | s1_ack_i | s2_ack_i | s3_ack_i | s4_ack_i | s5_ack_i | s6_ack_i | s7_ack_i , + s0_err_i | s1_err_i | s2_err_i | s3_err_i | s4_err_i | s5_err_i | s6_err_i | s7_err_i | addr_err_out, + s0_rty_i | s1_rty_i | s2_rty_i | s3_rty_i | s4_rty_i | s5_rty_i | s6_rty_i | s7_rty_i }; + + //////////////////////////////// + // Slave output interface + // + // slave0 + assign {s0_adr_o, s0_sel_o, s0_dat_o, s0_we_o, s0_cab_o,s0_cyc_o} = i_bus_m[`mbusw -1:1]; +`ifdef OR1200_BOOT_LOGIC + assign s0_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[0] & ~proc_init; // stb_o = cyc_i & stb_i & i_ssel_dec +`else + assign s0_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[0]; // stb_o = cyc_i & stb_i & i_ssel_dec +`endif + + // slave1 + + assign {s1_adr_o, s1_sel_o, s1_dat_o, s1_we_o, s1_cab_o, s1_cyc_o} = i_bus_m[`mbusw -1:1]; + assign s1_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[1]; + + // slave2 + + assign {s2_adr_o, s2_sel_o, s2_dat_o, s2_we_o, s2_cab_o, s2_cyc_o} = i_bus_m[`mbusw -1:1]; + assign s2_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[2]; + + // slave3 + + assign {s3_adr_o, s3_sel_o, s3_dat_o, s3_we_o, s3_cab_o, s3_cyc_o} = i_bus_m[`mbusw -1:1]; + assign s3_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[3]; + + // slave4 + + assign {s4_adr_o, s4_sel_o, s4_dat_o, s4_we_o, s4_cab_o, s4_cyc_o} = i_bus_m[`mbusw -1:1]; + assign s4_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[4]; + + // slave5 + + assign {s5_adr_o, s5_sel_o, s5_dat_o, s5_we_o, s5_cab_o, s5_cyc_o} = i_bus_m[`mbusw -1:1]; + assign s5_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[5]; + + // slave6 + + assign {s6_adr_o, s6_sel_o, s6_dat_o, s6_we_o, s6_cab_o, s6_cyc_o} = i_bus_m[`mbusw -1:1]; + assign s6_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[6]; + + // slave7 + + assign {s7_adr_o, s7_sel_o, s7_dat_o, s7_we_o, s7_cab_o, s7_cyc_o} = i_bus_m[`mbusw -1:1]; + assign s7_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[7]; + + /////////////////////////////////////// + // Master and Slave input interface + // + +`ifdef WB_USE_TRISTATE + // input from master interface + assign i_bus_m = i_gnt_arb[0] ? {m0_adr_i, m0_sel_i, m0_dat_i, m0_we_i, m0_cab_i, m0_cyc_i, m0_stb_i} : 72'bz ; + assign i_bus_m = i_gnt_arb[1] ? {m1_adr_i, m1_sel_i, m1_dat_i, m1_we_i, m1_cab_i,m1_cyc_i, m1_stb_i} : 72'bz ; + assign i_bus_m = i_gnt_arb[2] ? {m2_adr_i, m2_sel_i, m2_dat_i, m2_we_i, m2_cab_i, m2_cyc_i, m2_stb_i} : 72'bz ; + assign i_bus_m = i_gnt_arb[3] ? {m3_adr_i, m3_sel_i, m3_dat_i, m3_we_i, m3_cab_i, m3_cyc_i, m3_stb_i} : 72'bz ; + assign i_bus_m = i_gnt_arb[4] ? {m4_adr_i, m4_sel_i, m4_dat_i, m4_we_i, m4_cab_i, m4_cyc_i, m4_stb_i} : 72'bz ; + assign i_bus_m = i_gnt_arb[5] ? {m5_adr_i, m5_sel_i, m5_dat_i, m5_we_i, m5_cab_i, m5_cyc_i, m5_stb_i} : 72'bz ; + assign i_bus_m = i_gnt_arb[6] ? {m6_adr_i, m6_sel_i, m6_dat_i, m6_we_i, m6_cab_i, m6_cyc_i, m6_stb_i} : 72'bz ; + assign i_bus_m = i_gnt_arb[7] ? {m7_adr_i, m7_sel_i, m7_dat_i, m7_we_i, m7_cab_i, m7_cyc_i,m7_stb_i} : 72'bz ; + // input from slave interface + assign i_dat_s = i_ssel_dec[0] ? s0_dat_i: 32'bz; + assign i_dat_s = i_ssel_dec[1] ? s1_dat_i: 32'bz; + assign i_dat_s = i_ssel_dec[2] ? s2_dat_i: 32'bz; + assign i_dat_s = i_ssel_dec[3] ? s3_dat_i: 32'bz; + assign i_dat_s = i_ssel_dec[4] ? s4_dat_i: 32'bz; + assign i_dat_s = i_ssel_dec[5] ? s5_dat_i: 32'bz; + assign i_dat_s = i_ssel_dec[6] ? s6_dat_i: 32'bz; + assign i_dat_s = i_ssel_dec[7] ? s7_dat_i: 32'bz; + +`else + + always @(gnt , m0_adr_i, m0_sel_i, m0_dat_i, m0_we_i, m0_cab_i, m0_cyc_i,m0_stb_i, + m1_adr_i, m1_sel_i, m1_dat_i, m1_we_i, m1_cab_i, m1_cyc_i,m1_stb_i, + m2_adr_i, m2_sel_i, m2_dat_i, m2_we_i, m2_cab_i, m2_cyc_i,m2_stb_i, + m3_adr_i, m3_sel_i, m3_dat_i, m3_we_i, m3_cab_i, m3_cyc_i,m3_stb_i, + m4_adr_i, m4_sel_i, m4_dat_i, m4_we_i, m4_cab_i, m4_cyc_i,m4_stb_i, + m5_adr_i, m5_sel_i, m5_dat_i, m5_we_i, m5_cab_i, m5_cyc_i,m5_stb_i, + m6_adr_i, m6_sel_i, m6_dat_i, m6_we_i, m6_cab_i, m6_cyc_i,m6_stb_i, + m7_adr_i, m7_sel_i, m7_dat_i, m7_we_i, m7_cab_i, m7_cyc_i,m7_stb_i) + case(gnt) + /* verilator lint_off WIDTHCONCAT */ + 3'h0: i_bus_m = {m0_adr_i, m0_sel_i, m0_dat_i, m0_we_i, m0_cab_i, m0_cyc_i,m0_stb_i}; + 3'h1: i_bus_m = {m1_adr_i, m1_sel_i, m1_dat_i, m1_we_i, m1_cab_i, m1_cyc_i,m1_stb_i}; + 3'h2: i_bus_m = {m2_adr_i, m2_sel_i, m2_dat_i, m2_we_i, m2_cab_i, m2_cyc_i,m2_stb_i}; + 3'h3: i_bus_m = {m3_adr_i, m3_sel_i, m3_dat_i, m3_we_i, m3_cab_i, m3_cyc_i,m3_stb_i}; + 3'h4: i_bus_m = {m4_adr_i, m4_sel_i, m4_dat_i, m4_we_i, m4_cab_i, m4_cyc_i,m4_stb_i}; + 3'h5: i_bus_m = {m5_adr_i, m5_sel_i, m5_dat_i, m5_we_i, m5_cab_i, m5_cyc_i,m5_stb_i}; + 3'h6: i_bus_m = {m6_adr_i, m6_sel_i, m6_dat_i, m6_we_i, m6_cab_i, m6_cyc_i,m6_stb_i}; + 3'h7: i_bus_m = {m7_adr_i, m7_sel_i, m7_dat_i, m7_we_i, m7_cab_i, m7_cyc_i,m7_stb_i}; + default:i_bus_m = 72'b0;//{m0_adr_i, m0_sel_i, m0_dat_i, m0_we_i, m0_cab_i, m0_cyc_i,m0_stb_i}; + /* verilator lint_on WIDTHCONCAT */ + endcase + + assign i_dat_s = i_ssel_dec[0] ? s0_dat_i : + i_ssel_dec[1] ? s1_dat_i : + i_ssel_dec[2] ? s2_dat_i : + i_ssel_dec[3] ? s3_dat_i : + i_ssel_dec[4] ? s4_dat_i : + i_ssel_dec[5] ? s5_dat_i : + i_ssel_dec[6] ? s6_dat_i : + i_ssel_dec[7] ? s7_dat_i : {`dw{1'b0}}; +`endif + // + // arbitor + // + assign i_gnt_arb[0] = (gnt == 3'd0); + assign i_gnt_arb[1] = (gnt == 3'd1); + assign i_gnt_arb[2] = (gnt == 3'd2); + assign i_gnt_arb[3] = (gnt == 3'd3); + assign i_gnt_arb[4] = (gnt == 3'd4); + assign i_gnt_arb[5] = (gnt == 3'd5); + assign i_gnt_arb[6] = (gnt == 3'd6); + assign i_gnt_arb[7] = (gnt == 3'd7); + + wire arb_rst; +`ifdef OR1200_BOOT_LOGIC + assign arb_rst = rst_i | proc_init; +`else + assign arb_rst = rst_i; +`endif + wb_conbus_arb wb_conbus_arb( + .clk(clk_i), + .rst(arb_rst), + .req({ m7_cyc_i, + m6_cyc_i, + m5_cyc_i, + m4_cyc_i, + m3_cyc_i, + m2_cyc_i, + m1_cyc_i, + m0_cyc_i}), + .gnt(gnt) + ); + + ////////////////////////////////// + // address decode logic + // + wire [7:0] m0_ssel_dec, m1_ssel_dec, m2_ssel_dec, m3_ssel_dec, m4_ssel_dec, m5_ssel_dec, m6_ssel_dec, m7_ssel_dec; + always @(gnt, m0_ssel_dec, m1_ssel_dec, m2_ssel_dec, m3_ssel_dec, m4_ssel_dec, m5_ssel_dec, m6_ssel_dec, m7_ssel_dec) + case(gnt) + 3'h0: i_ssel_dec = m0_ssel_dec; + 3'h1: i_ssel_dec = m1_ssel_dec; + 3'h2: i_ssel_dec = m2_ssel_dec; + 3'h3: i_ssel_dec = m3_ssel_dec; + 3'h4: i_ssel_dec = m4_ssel_dec; + 3'h5: i_ssel_dec = m5_ssel_dec; + 3'h6: i_ssel_dec = m6_ssel_dec; + 3'h7: i_ssel_dec = m7_ssel_dec; + default: i_ssel_dec = 7'b0; + endcase // case (gnt) + + // Generate error signals if address requested does not exist + //wire [7:0] addr_err; + // This goes high when we've granted bus to this master, but its addresss does not select + // any valid master, and it's requesting the bus. + assign addr_err[0] = ((gnt == 3'h0) & !(|m0_ssel_dec) & m0_cyc_i); + assign addr_err[1] = ((gnt == 3'h1) & !(|m1_ssel_dec) & m1_cyc_i); + assign addr_err[2] = ((gnt == 3'h2) & !(|m2_ssel_dec) & m2_cyc_i); + assign addr_err[3] = ((gnt == 3'h3) & !(|m3_ssel_dec) & m3_cyc_i); + assign addr_err[4] = ((gnt == 3'h4) & !(|m4_ssel_dec) & m4_cyc_i); + assign addr_err[5] = ((gnt == 3'h5) & !(|m5_ssel_dec) & m5_cyc_i); + assign addr_err[6] = ((gnt == 3'h6) & !(|m6_ssel_dec) & m6_cyc_i); + assign addr_err[7] = ((gnt == 3'h7) & !(|m7_ssel_dec) & m7_cyc_i); + + always @(posedge clk_i) + begin + addr_err_r <= addr_err[gnt]; + end + + assign addr_err_out = addr_err_r & i_bus_m[1]; // AND it with the CYC input of the master also + + + + + + // + // decode all master address before arbitor for running faster + // + assign m0_ssel_dec[0] = (m0_adr_i[`aw -1 : `aw - s0_addr_w ] == s0_addr); + assign m0_ssel_dec[1] = (m0_adr_i[`aw -1 : `aw - s1_addr_w ] == s1_addr); + assign m0_ssel_dec[2] = (m0_adr_i[`aw -1 : `aw - s27_addr_w ] == s2_addr); + assign m0_ssel_dec[3] = (m0_adr_i[`aw -1 : `aw - s27_addr_w ] == s3_addr); + assign m0_ssel_dec[4] = (m0_adr_i[`aw -1 : `aw - s27_addr_w ] == s4_addr); + assign m0_ssel_dec[5] = (m0_adr_i[`aw -1 : `aw - s27_addr_w ] == s5_addr); + assign m0_ssel_dec[6] = (m0_adr_i[`aw -1 : `aw - s27_addr_w ] == s6_addr); + assign m0_ssel_dec[7] = (m0_adr_i[`aw -1 : `aw - s27_addr_w ] == s7_addr); + + assign m1_ssel_dec[0] = (m1_adr_i[`aw -1 : `aw - s0_addr_w ] == s0_addr); + assign m1_ssel_dec[1] = (m1_adr_i[`aw -1 : `aw - s1_addr_w ] == s1_addr); + assign m1_ssel_dec[2] = (m1_adr_i[`aw -1 : `aw - s27_addr_w ] == s2_addr); + assign m1_ssel_dec[3] = (m1_adr_i[`aw -1 : `aw - s27_addr_w ] == s3_addr); + assign m1_ssel_dec[4] = (m1_adr_i[`aw -1 : `aw - s27_addr_w ] == s4_addr); + assign m1_ssel_dec[5] = (m1_adr_i[`aw -1 : `aw - s27_addr_w ] == s5_addr); + assign m1_ssel_dec[6] = (m1_adr_i[`aw -1 : `aw - s27_addr_w ] == s6_addr); + assign m1_ssel_dec[7] = (m1_adr_i[`aw -1 : `aw - s27_addr_w ] == s7_addr); + + assign m2_ssel_dec[0] = (m2_adr_i[`aw -1 : `aw - s0_addr_w ] == s0_addr); + assign m2_ssel_dec[1] = (m2_adr_i[`aw -1 : `aw - s1_addr_w ] == s1_addr); + assign m2_ssel_dec[2] = (m2_adr_i[`aw -1 : `aw - s27_addr_w ] == s2_addr); + assign m2_ssel_dec[3] = (m2_adr_i[`aw -1 : `aw - s27_addr_w ] == s3_addr); + assign m2_ssel_dec[4] = (m2_adr_i[`aw -1 : `aw - s27_addr_w ] == s4_addr); + assign m2_ssel_dec[5] = (m2_adr_i[`aw -1 : `aw - s27_addr_w ] == s5_addr); + assign m2_ssel_dec[6] = (m2_adr_i[`aw -1 : `aw - s27_addr_w ] == s6_addr); + assign m2_ssel_dec[7] = (m2_adr_i[`aw -1 : `aw - s27_addr_w ] == s7_addr); + + assign m3_ssel_dec[0] = (m3_adr_i[`aw -1 : `aw - s0_addr_w ] == s0_addr); + assign m3_ssel_dec[1] = (m3_adr_i[`aw -1 : `aw - s1_addr_w ] == s1_addr); + assign m3_ssel_dec[2] = (m3_adr_i[`aw -1 : `aw - s27_addr_w ] == s2_addr); + assign m3_ssel_dec[3] = (m3_adr_i[`aw -1 : `aw - s27_addr_w ] == s3_addr); + assign m3_ssel_dec[4] = (m3_adr_i[`aw -1 : `aw - s27_addr_w ] == s4_addr); + assign m3_ssel_dec[5] = (m3_adr_i[`aw -1 : `aw - s27_addr_w ] == s5_addr); + assign m3_ssel_dec[6] = (m3_adr_i[`aw -1 : `aw - s27_addr_w ] == s6_addr); + assign m3_ssel_dec[7] = (m3_adr_i[`aw -1 : `aw - s27_addr_w ] == s7_addr); + + assign m4_ssel_dec[0] = (m4_adr_i[`aw -1 : `aw - s0_addr_w ] == s0_addr); + assign m4_ssel_dec[1] = (m4_adr_i[`aw -1 : `aw - s1_addr_w ] == s1_addr); + assign m4_ssel_dec[2] = (m4_adr_i[`aw -1 : `aw - s27_addr_w ] == s2_addr); + assign m4_ssel_dec[3] = (m4_adr_i[`aw -1 : `aw - s27_addr_w ] == s3_addr); + assign m4_ssel_dec[4] = (m4_adr_i[`aw -1 : `aw - s27_addr_w ] == s4_addr); + assign m4_ssel_dec[5] = (m4_adr_i[`aw -1 : `aw - s27_addr_w ] == s5_addr); + assign m4_ssel_dec[6] = (m4_adr_i[`aw -1 : `aw - s27_addr_w ] == s6_addr); + assign m4_ssel_dec[7] = (m4_adr_i[`aw -1 : `aw - s27_addr_w ] == s7_addr); + + assign m5_ssel_dec[0] = (m5_adr_i[`aw -1 : `aw - s0_addr_w ] == s0_addr); + assign m5_ssel_dec[1] = (m5_adr_i[`aw -1 : `aw - s1_addr_w ] == s1_addr); + assign m5_ssel_dec[2] = (m5_adr_i[`aw -1 : `aw - s27_addr_w ] == s2_addr); + assign m5_ssel_dec[3] = (m5_adr_i[`aw -1 : `aw - s27_addr_w ] == s3_addr); + assign m5_ssel_dec[4] = (m5_adr_i[`aw -1 : `aw - s27_addr_w ] == s4_addr); + assign m5_ssel_dec[5] = (m5_adr_i[`aw -1 : `aw - s27_addr_w ] == s5_addr); + assign m5_ssel_dec[6] = (m5_adr_i[`aw -1 : `aw - s27_addr_w ] == s6_addr); + assign m5_ssel_dec[7] = (m5_adr_i[`aw -1 : `aw - s27_addr_w ] == s7_addr); + + assign m6_ssel_dec[0] = (m6_adr_i[`aw -1 : `aw - s0_addr_w ] == s0_addr); + assign m6_ssel_dec[1] = (m6_adr_i[`aw -1 : `aw - s1_addr_w ] == s1_addr); + assign m6_ssel_dec[2] = (m6_adr_i[`aw -1 : `aw - s27_addr_w ] == s2_addr); + assign m6_ssel_dec[3] = (m6_adr_i[`aw -1 : `aw - s27_addr_w ] == s3_addr); + assign m6_ssel_dec[4] = (m6_adr_i[`aw -1 : `aw - s27_addr_w ] == s4_addr); + assign m6_ssel_dec[5] = (m6_adr_i[`aw -1 : `aw - s27_addr_w ] == s5_addr); + assign m6_ssel_dec[6] = (m6_adr_i[`aw -1 : `aw - s27_addr_w ] == s6_addr); + assign m6_ssel_dec[7] = (m6_adr_i[`aw -1 : `aw - s27_addr_w ] == s7_addr); + + assign m7_ssel_dec[0] = (m7_adr_i[`aw -1 : `aw - s0_addr_w ] == s0_addr); + assign m7_ssel_dec[1] = (m7_adr_i[`aw -1 : `aw - s1_addr_w ] == s1_addr); + assign m7_ssel_dec[2] = (m7_adr_i[`aw -1 : `aw - s27_addr_w ] == s2_addr); + assign m7_ssel_dec[3] = (m7_adr_i[`aw -1 : `aw - s27_addr_w ] == s3_addr); + assign m7_ssel_dec[4] = (m7_adr_i[`aw -1 : `aw - s27_addr_w ] == s4_addr); + assign m7_ssel_dec[5] = (m7_adr_i[`aw -1 : `aw - s27_addr_w ] == s5_addr); + assign m7_ssel_dec[6] = (m7_adr_i[`aw -1 : `aw - s27_addr_w ] == s6_addr); + assign m7_ssel_dec[7] = (m7_adr_i[`aw -1 : `aw - s27_addr_w ] == s7_addr); + + //assign i_ssel_dec[0] = (i_bus_m[`mbusw -1 : `mbusw - s0_addr_w ] == s0_addr); + //assign i_ssel_dec[1] = (i_bus_m[`mbusw -1 : `mbusw - s1_addr_w ] == s1_addr); + //assign i_ssel_dec[2] = (i_bus_m[`mbusw -1 : `mbusw - s27_addr_w ] == s2_addr); + //assign i_ssel_dec[3] = (i_bus_m[`mbusw -1 : `mbusw - s27_addr_w ] == s3_addr); + //assign i_ssel_dec[4] = (i_bus_m[`mbusw -1 : `mbusw - s27_addr_w ] == s4_addr); + //assign i_ssel_dec[5] = (i_bus_m[`mbusw -1 : `mbusw - s27_addr_w ] == s5_addr); + //assign i_ssel_dec[6] = (i_bus_m[`mbusw -1 : `mbusw - s27_addr_w ] == s6_addr); + //assign i_ssel_dec[7] = (i_bus_m[`mbusw -1 : `mbusw - s27_addr_w ] == s7_addr); + + +endmodule Index: rtl/verilog/components/wb_conbus/wb_conbus_arb.v =================================================================== --- rtl/verilog/components/wb_conbus/wb_conbus_arb.v (nonexistent) +++ rtl/verilog/components/wb_conbus/wb_conbus_arb.v (revision 54) @@ -0,0 +1,249 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// General Round Robin Arbiter //// +//// //// +//// //// +//// Author: Rudolf Usselmann //// +//// rudi@asics.ws //// +//// //// +//// //// +//// Downloaded from: http://opencores.org/project,wb_conbus //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000-2002 Rudolf Usselmann //// +//// www.asics.ws //// +//// rudi@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + + +// +// copy from wb_conmax +// +// +// +// +// + +module wb_conbus_arb(clk, rst, req, gnt); + + input clk; + input rst; + input [7:0] req; // Req input + output [2:0] gnt; // Grant output + //input next; // Next Target + + /////////////////////////////////////////////////////////////////////// + // + // Parameters + // + + + parameter [2:0] + grant0 = 3'h0, + grant1 = 3'h1, + grant2 = 3'h2, + grant3 = 3'h3, + grant4 = 3'h4, + grant5 = 3'h5, + grant6 = 3'h6, + grant7 = 3'h7; + + /////////////////////////////////////////////////////////////////////// + // + // Local Registers and Wires + // + + reg [2:0] state, next_state; + + /////////////////////////////////////////////////////////////////////// + // + // Misc Logic + // + + assign gnt = state; + + always@(posedge clk or posedge rst) + if(rst) state <= #1 grant0; + else state <= #1 next_state; + + /////////////////////////////////////////////////////////////////////// + // + // Next State Logic + // - implements round robin arbitration algorithm + // - switches grant if current req is dropped or next is asserted + // - parks at last grant + // + + always@(state or req ) + begin + next_state = state; // Default Keep State + case(state) // synopsys parallel_case full_case + grant0: + // if this req is dropped or next is asserted, check for other req's + if(!req[0] ) + begin + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + end + grant1: + // if this req is dropped or next is asserted, check for other req's + if(!req[1] ) + begin + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[0]) next_state = grant0; + end + grant2: + // if this req is dropped or next is asserted, check for other req's + if(!req[2] ) + begin + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + end + grant3: + // if this req is dropped or next is asserted, check for other req's + if(!req[3] ) + begin + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + end + grant4: + // if this req is dropped or next is asserted, check for other req's + if(!req[4] ) + begin + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + end + grant5: + // if this req is dropped or next is asserted, check for other req's + if(!req[5] ) + begin + if(req[6]) next_state = grant6; + else + if(req[7]) next_state = grant7; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + end + grant6: + // if this req is dropped or next is asserted, check for other req's + if(!req[6] ) + begin + if(req[7]) next_state = grant7; + else + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + end + grant7: + // if this req is dropped or next is asserted, check for other req's + if(!req[7] ) + begin + if(req[0]) next_state = grant0; + else + if(req[1]) next_state = grant1; + else + if(req[2]) next_state = grant2; + else + if(req[3]) next_state = grant3; + else + if(req[4]) next_state = grant4; + else + if(req[5]) next_state = grant5; + else + if(req[6]) next_state = grant6; + end + endcase + end + +endmodule // wb_conbus_arb Index: rtl/verilog/orpsoc_top.v =================================================================== --- rtl/verilog/orpsoc_top.v (revision 53) +++ rtl/verilog/orpsoc_top.v (revision 54) @@ -43,329 +43,483 @@ module orpsoc_top ( - output spi_sd_sclk_pad_o , - output spi_sd_ss_pad_o , - input spi_sd_miso_pad_i , - output spi_sd_mosi_pad_o , + output spi_sd_sclk_pad_o , + output spi_sd_ss_pad_o , + input spi_sd_miso_pad_i , + output spi_sd_mosi_pad_o , `ifdef USE_SDRAM // SDRAM bus signals - inout [15:0] mem_dat_pad_io, - output [12:0] mem_adr_pad_o , - output [1:0] mem_dqm_pad_o , - output [1:0] mem_ba_pad_o , - output mem_cs_pad_o , - output mem_ras_pad_o , - output mem_cas_pad_o , - output mem_we_pad_o , - output mem_cke_pad_o , + inout [15:0] mem_dat_pad_io, + output [12:0] mem_adr_pad_o , + output [1:0] mem_dqm_pad_o , + output [1:0] mem_ba_pad_o , + output mem_cs_pad_o , + output mem_ras_pad_o , + output mem_cas_pad_o , + output mem_we_pad_o , + output mem_cke_pad_o , // SPI bus signals for flash memory - output spi_flash_sclk_pad_o , - output spi_flash_ss_pad_o , - input spi_flash_miso_pad_i , - output spi_flash_mosi_pad_o , - output spi_flash_w_n_pad_o , - output spi_flash_hold_n_pad_o, + output spi_flash_sclk_pad_o , + output spi_flash_ss_pad_o , + input spi_flash_miso_pad_i , + output spi_flash_mosi_pad_o , + output spi_flash_w_n_pad_o , + output spi_flash_hold_n_pad_o, `endif // `ifdef USE_SDRAM `ifdef USE_ETHERNET_IO - output [1:1] eth_sync_pad_o, - output [1:1] eth_tx_pad_o, - input [1:1] eth_rx_pad_i, - input eth_clk_pad_i, - inout [1:1] eth_md_pad_io, - output [1:1] eth_mdc_pad_o, + output [1:1] eth_sync_pad_o, + output [1:1] eth_tx_pad_o, + input [1:1] eth_rx_pad_i, + input eth_clk_pad_i, + inout [1:1] eth_md_pad_io, + output [1:1] eth_mdc_pad_o, `endif // `ifdef USE_ETHERNET_IO - output spi1_mosi_pad_o, - input spi1_miso_pad_i, - output spi1_ss_pad_o , - output spi1_sclk_pad_o, + output spi1_mosi_pad_o, + input spi1_miso_pad_i, + output spi1_ss_pad_o , + output spi1_sclk_pad_o, `ifdef DISABLE_IOS_FOR_VERILATOR - output [8-1:0] gpio_a_pad_io, + output [8-1:0] gpio_a_pad_io, `else - inout [8-1:0] gpio_a_pad_io, + inout [8-1:0] gpio_a_pad_io, `endif - input uart0_srx_pad_i , - output uart0_stx_pad_o , - input dbg_tdi_pad_i, - input dbg_tck_pad_i, - input dbg_tms_pad_i, - output dbg_tdo_pad_o, - input rst_pad_i, - output rst_pad_o, - input clk_pad_i + input uart0_srx_pad_i , + output uart0_stx_pad_o , + input dbg_tdi_pad_i, + input dbg_tck_pad_i, + input dbg_tms_pad_i, + output dbg_tdo_pad_o, + input rst_pad_i, + output rst_pad_o, + input clk_pad_i ) -; - wire wb_rst; - wire wb_clk, clk50, clk100, usbClk, dbg_tck; - wire pll_lock; - wire mem_io_req, mem_io_gnt, mem_io_busy; - wire [15:0] mem_dat_pad_i, mem_dat_pad_o; - wire [30:0] pic_ints; - wire spi3_irq, spi2_irq, spi1_irq, spi0_irq, uart0_irq; - wire eth0_int_o; -parameter [31:0] wbm_or12_i_dat_o = 32'h0; -wire [31:0] wbm_or12_i_adr_o; -wire [3:0] wbm_or12_i_sel_o; -wire wbm_or12_i_we_o; -wire [1:0] wbm_or12_i_bte_o; -wire [2:0] wbm_or12_i_cti_o; -wire wbm_or12_i_stb_o; -wire wbm_or12_i_cyc_o; -wire [31:0] wbm_or12_i_dat_i; -wire wbm_or12_i_ack_i; -wire wbm_or12_i_err_i; -wire wbm_or12_i_rty_i; -wire [31:0] wbm_or12_debug_dat_o; -wire [31:0] wbm_or12_debug_adr_o; -wire [3:0] wbm_or12_debug_sel_o; -wire wbm_or12_debug_we_o; -wire [1:0] wbm_or12_debug_bte_o; -wire [2:0] wbm_or12_debug_cti_o; -wire wbm_or12_debug_stb_o; -wire wbm_or12_debug_cyc_o; -wire [31:0] wbm_or12_debug_dat_i; -wire wbm_or12_debug_ack_i; -wire wbm_or12_debug_err_i; -wire wbm_or12_debug_rty_i; -wire [31:0] wbm_or12_d_dat_o; -wire [31:0] wbm_or12_d_adr_o; -wire [3:0] wbm_or12_d_sel_o; -wire wbm_or12_d_we_o; -wire [1:0] wbm_or12_d_bte_o; -wire [2:0] wbm_or12_d_cti_o; -wire wbm_or12_d_stb_o; -wire wbm_or12_d_cyc_o; -wire [31:0] wbm_or12_d_dat_i; -wire wbm_or12_d_ack_i; -wire wbm_or12_d_err_i; -wire wbm_or12_d_rty_i; -wire [31:0] wbm_eth1_dat_o; -wire [31:0] wbm_eth1_adr_o; -wire [3:0] wbm_eth1_sel_o; -wire wbm_eth1_we_o; -wire [1:0] wbm_eth1_bte_o; -wire [2:0] wbm_eth1_cti_o; -wire wbm_eth1_stb_o; -wire wbm_eth1_cyc_o; -wire [31:0] wbm_eth1_dat_i; -wire wbm_eth1_ack_i; -wire wbm_eth1_err_i; -wire wbm_eth1_rty_i; -wire [31:0] wbs_eth1_cfg_dat_o; -wire [31:0] wbs_eth1_cfg_dat_i; -wire [31:0] wbs_eth1_cfg_adr_i; -wire [3:0] wbs_eth1_cfg_sel_i; -wire [1:0] wbs_eth1_cfg_bte_i; -wire [2:0] wbs_eth1_cfg_cti_i; -wire wbs_eth1_cfg_stb_i; -wire wbs_eth1_cfg_cyc_i; -wire wbs_eth1_cfg_ack_o; -wire wbs_eth1_cfg_err_o; -parameter wbs_eth1_cfg_rty_o = 1'b0; -wire [31:0] wbs_rom_dat_o; -wire [31:0] wbs_rom_dat_i; -wire [31:0] wbs_rom_adr_i; -wire [3:0] wbs_rom_sel_i; -wire [1:0] wbs_rom_bte_i; -wire [2:0] wbs_rom_cti_i; -wire wbs_rom_stb_i; -wire wbs_rom_cyc_i; -wire wbs_rom_ack_o; -parameter wbs_rom_err_o = 1'b0; -parameter wbs_rom_rty_o = 1'b0; -wire [31:0] wbs_mc_m_dat_o; -wire [31:0] wbs_mc_m_dat_i; -wire [31:0] wbs_mc_m_adr_i; -wire [3:0] wbs_mc_m_sel_i; -wire [1:0] wbs_mc_m_bte_i; -wire [2:0] wbs_mc_m_cti_i; -wire wbs_mc_m_stb_i; -wire wbs_mc_m_cyc_i; -wire wbs_mc_m_ack_o; -wire wbs_mc_m_err_o; -parameter wbs_mc_m_rty_o = 1'b0; -wire [31:0] wbs_spi_flash_dat_o; -wire [31:0] wbs_spi_flash_dat_i; -wire [31:0] wbs_spi_flash_adr_i; -wire [3:0] wbs_spi_flash_sel_i; -wire [1:0] wbs_spi_flash_bte_i; -wire [2:0] wbs_spi_flash_cti_i; -wire wbs_spi_flash_stb_i; -wire wbs_spi_flash_cyc_i; -wire wbs_spi_flash_ack_o; -parameter wbs_spi_flash_err_o = 1'b0; -parameter wbs_spi_flash_rty_o = 1'b0; -wire [31:0] wbs_uart0_dat_o; -wire [31:0] wbs_uart0_dat_i; -wire [31:0] wbs_uart0_adr_i; -wire [3:0] wbs_uart0_sel_i; -wire [1:0] wbs_uart0_bte_i; -wire [2:0] wbs_uart0_cti_i; -wire wbs_uart0_stb_i; -wire wbs_uart0_cyc_i; -wire wbs_uart0_ack_o; -parameter wbs_uart0_err_o = 1'b0; -parameter wbs_uart0_rty_o = 1'b0; -wire [31:0] wbs_ds1_dat_o; -wire [31:0] wbs_ds1_dat_i; -wire [31:0] wbs_ds1_adr_i; -wire [3:0] wbs_ds1_sel_i; -wire [1:0] wbs_ds1_bte_i; -wire [2:0] wbs_ds1_cti_i; -wire wbs_ds1_stb_i; -wire wbs_ds1_cyc_i; -wire wbs_ds1_ack_o; -parameter wbs_ds1_err_o = 1'b0; -parameter wbs_ds1_rty_o = 1'b0; -wire [31:0] wbs_ds2_dat_o; -wire [31:0] wbs_ds2_dat_i; -wire [31:0] wbs_ds2_adr_i; -wire [3:0] wbs_ds2_sel_i; -wire [1:0] wbs_ds2_bte_i; -wire [2:0] wbs_ds2_cti_i; -wire wbs_ds2_stb_i; -wire wbs_ds2_cyc_i; -wire wbs_ds2_ack_o; -parameter wbs_ds2_err_o = 1'b0; -parameter wbs_ds2_rty_o = 1'b0; - wire eth_clk; - wire [1:1] eth_int; -intercon intercon1 ( - .wbm_or12_isaw_dat_o(wbm_or12_i_dat_o), - .wbm_or12_isaw_adr_o(wbm_or12_i_adr_o), - .wbm_or12_isaw_sel_o(wbm_or12_i_sel_o), - .wbm_or12_isaw_we_o(wbm_or12_i_we_o), - .wbm_or12_isaw_bte_o(wbm_or12_i_bte_o), - .wbm_or12_isaw_cti_o(wbm_or12_i_cti_o), - .wbm_or12_isaw_stb_o(wbm_or12_i_stb_o), - .wbm_or12_isaw_cyc_o(wbm_or12_i_cyc_o), - .wbm_or12_isaw_dat_i(wbm_or12_i_dat_i), - .wbm_or12_isaw_ack_i(wbm_or12_i_ack_i), - .wbm_or12_isaw_err_i(wbm_or12_i_err_i), - .wbm_or12_isaw_rty_i(wbm_or12_i_rty_i), - .wbm_or12_debug_dat_o(wbm_or12_debug_dat_o), - .wbm_or12_debug_adr_o(wbm_or12_debug_adr_o), - .wbm_or12_debug_sel_o(wbm_or12_debug_sel_o), - .wbm_or12_debug_we_o(wbm_or12_debug_we_o), - .wbm_or12_debug_bte_o(wbm_or12_debug_bte_o), - .wbm_or12_debug_cti_o(wbm_or12_debug_cti_o), - .wbm_or12_debug_stb_o(wbm_or12_debug_stb_o), - .wbm_or12_debug_cyc_o(wbm_or12_debug_cyc_o), - .wbm_or12_debug_dat_i(wbm_or12_debug_dat_i), - .wbm_or12_debug_ack_i(wbm_or12_debug_ack_i), - .wbm_or12_debug_err_i(wbm_or12_debug_err_i), - .wbm_or12_debug_rty_i(wbm_or12_debug_rty_i), - .wbm_or12_d_dat_o(wbm_or12_d_dat_o), - .wbm_or12_d_adr_o(wbm_or12_d_adr_o), - .wbm_or12_d_sel_o(wbm_or12_d_sel_o), - .wbm_or12_d_we_o(wbm_or12_d_we_o), - .wbm_or12_d_bte_o(wbm_or12_d_bte_o), - .wbm_or12_d_cti_o(wbm_or12_d_cti_o), - .wbm_or12_d_stb_o(wbm_or12_d_stb_o), - .wbm_or12_d_cyc_o(wbm_or12_d_cyc_o), - .wbm_or12_d_dat_i(wbm_or12_d_dat_i), - .wbm_or12_d_ack_i(wbm_or12_d_ack_i), - .wbm_or12_d_err_i(wbm_or12_d_err_i), - .wbm_or12_d_rty_i(wbm_or12_d_rty_i), - .wbm_eth1_dat_o(wbm_eth1_dat_o), - .wbm_eth1_adr_o(wbm_eth1_adr_o), - .wbm_eth1_sel_o(wbm_eth1_sel_o), - .wbm_eth1_we_o(wbm_eth1_we_o), - .wbm_eth1_bte_o(wbm_eth1_bte_o), - .wbm_eth1_cti_o(wbm_eth1_cti_o), - .wbm_eth1_stb_o(wbm_eth1_stb_o), - .wbm_eth1_cyc_o(wbm_eth1_cyc_o), - .wbm_eth1_dat_i(wbm_eth1_dat_i), - .wbm_eth1_ack_i(wbm_eth1_ack_i), - .wbm_eth1_err_i(wbm_eth1_err_i), - .wbm_eth1_rty_i(wbm_eth1_rty_i), - .wbs_eth1_cfg_dat_i(wbs_eth1_cfg_dat_i), - .wbs_eth1_cfg_adr_i(wbs_eth1_cfg_adr_i), - .wbs_eth1_cfg_sel_i(wbs_eth1_cfg_sel_i), - .wbs_eth1_cfg_we_i(wbs_eth1_cfg_we_i), - .wbs_eth1_cfg_bte_i(wbs_eth1_cfg_bte_i), - .wbs_eth1_cfg_cti_i(wbs_eth1_cfg_cti_i), - .wbs_eth1_cfg_stb_i(wbs_eth1_cfg_stb_i), - .wbs_eth1_cfg_cyc_i(wbs_eth1_cfg_cyc_i), - .wbs_eth1_cfg_dat_o(wbs_eth1_cfg_dat_o), - .wbs_eth1_cfg_ack_o(wbs_eth1_cfg_ack_o), - .wbs_eth1_cfg_err_o(wbs_eth1_cfg_err_o), - .wbs_eth1_cfg_rty_o(wbs_eth1_cfg_rty_o), - .wbs_rom_dat_i(wbs_rom_dat_i), - .wbs_rom_adr_i(wbs_rom_adr_i), - .wbs_rom_sel_i(wbs_rom_sel_i), - .wbs_rom_we_i(wbs_rom_we_i), - .wbs_rom_bte_i(wbs_rom_bte_i), - .wbs_rom_cti_i(wbs_rom_cti_i), - .wbs_rom_stb_i(wbs_rom_stb_i), - .wbs_rom_cyc_i(wbs_rom_cyc_i), - .wbs_rom_dat_o(wbs_rom_dat_o), - .wbs_rom_ack_o(wbs_rom_ack_o), - .wbs_rom_err_o(wbs_rom_err_o), - .wbs_rom_rty_o(wbs_rom_rty_o), - .wbs_mc_m_dat_i(wbs_mc_m_dat_i), - .wbs_mc_m_adr_i(wbs_mc_m_adr_i), - .wbs_mc_m_sel_i(wbs_mc_m_sel_i), - .wbs_mc_m_we_i(wbs_mc_m_we_i), - .wbs_mc_m_bte_i(wbs_mc_m_bte_i), - .wbs_mc_m_cti_i(wbs_mc_m_cti_i), - .wbs_mc_m_stb_i(wbs_mc_m_stb_i), - .wbs_mc_m_cyc_i(wbs_mc_m_cyc_i), - .wbs_mc_m_dat_o(wbs_mc_m_dat_o), - .wbs_mc_m_ack_o(wbs_mc_m_ack_o), - .wbs_mc_m_err_o(wbs_mc_m_err_o), - .wbs_mc_m_rty_o(wbs_mc_m_rty_o), - .wbs_spi_flash_dat_i(wbs_spi_flash_dat_i), - .wbs_spi_flash_adr_i(wbs_spi_flash_adr_i), - .wbs_spi_flash_sel_i(wbs_spi_flash_sel_i), - .wbs_spi_flash_we_i(wbs_spi_flash_we_i), - .wbs_spi_flash_bte_i(wbs_spi_flash_bte_i), - .wbs_spi_flash_cti_i(wbs_spi_flash_cti_i), - .wbs_spi_flash_stb_i(wbs_spi_flash_stb_i), - .wbs_spi_flash_cyc_i(wbs_spi_flash_cyc_i), - .wbs_spi_flash_dat_o(wbs_spi_flash_dat_o), - .wbs_spi_flash_ack_o(wbs_spi_flash_ack_o), - .wbs_spi_flash_err_o(wbs_spi_flash_err_o), - .wbs_spi_flash_rty_o(wbs_spi_flash_rty_o), - .wbs_uart0_dat_i(wbs_uart0_dat_i), - .wbs_uart0_adr_i(wbs_uart0_adr_i), - .wbs_uart0_sel_i(wbs_uart0_sel_i), - .wbs_uart0_we_i(wbs_uart0_we_i), - .wbs_uart0_bte_i(wbs_uart0_bte_i), - .wbs_uart0_cti_i(wbs_uart0_cti_i), - .wbs_uart0_stb_i(wbs_uart0_stb_i), - .wbs_uart0_cyc_i(wbs_uart0_cyc_i), - .wbs_uart0_dat_o(wbs_uart0_dat_o), - .wbs_uart0_ack_o(wbs_uart0_ack_o), - .wbs_uart0_err_o(wbs_uart0_err_o), - .wbs_uart0_rty_o(wbs_uart0_rty_o), - .wbs_ds1_dat_i(wbs_ds1_dat_i), - .wbs_ds1_adr_i(wbs_ds1_adr_i), - .wbs_ds1_sel_i(wbs_ds1_sel_i), - .wbs_ds1_we_i(wbs_ds1_we_i), - .wbs_ds1_bte_i(wbs_ds1_bte_i), - .wbs_ds1_cti_i(wbs_ds1_cti_i), - .wbs_ds1_stb_i(wbs_ds1_stb_i), - .wbs_ds1_cyc_i(wbs_ds1_cyc_i), - .wbs_ds1_dat_o(wbs_ds1_dat_o), - .wbs_ds1_ack_o(wbs_ds1_ack_o), - .wbs_ds1_err_o(wbs_ds1_err_o), - .wbs_ds1_rty_o(wbs_ds1_rty_o), - .wbs_ds2_dat_i(wbs_ds2_dat_i), - .wbs_ds2_adr_i(wbs_ds2_adr_i), - .wbs_ds2_sel_i(wbs_ds2_sel_i), - .wbs_ds2_we_i(wbs_ds2_we_i), - .wbs_ds2_bte_i(wbs_ds2_bte_i), - .wbs_ds2_cti_i(wbs_ds2_cti_i), - .wbs_ds2_stb_i(wbs_ds2_stb_i), - .wbs_ds2_cyc_i(wbs_ds2_cyc_i), - .wbs_ds2_dat_o(wbs_ds2_dat_o), - .wbs_ds2_ack_o(wbs_ds2_ack_o), - .wbs_ds2_err_o(wbs_ds2_err_o), - .wbs_ds2_rty_o(wbs_ds2_rty_o), - .wb_clk_i(wb_clk), - .wb_rst_i(wb_rst) -); - assign pic_ints[30] = 1'b0; + ; + wire wb_rst; + wire wb_clk, clk50, clk100, usbClk, dbg_tck; + wire pll_lock; + wire mem_io_req, mem_io_gnt, mem_io_busy; + wire [15:0] mem_dat_pad_i, mem_dat_pad_o; + wire [30:0] pic_ints; + wire spi3_irq, spi2_irq, spi1_irq, spi0_irq, uart0_irq; + wire eth0_int_o; + parameter [31:0] wbm_or12_i_dat_o = 32'h0; + wire [31:0] wbm_or12_i_adr_o; + wire [3:0] wbm_or12_i_sel_o; + wire wbm_or12_i_we_o; + wire [1:0] wbm_or12_i_bte_o; + wire [2:0] wbm_or12_i_cti_o; + wire wbm_or12_i_stb_o; + wire wbm_or12_i_cyc_o; + wire [31:0] wbm_or12_i_dat_i; + wire wbm_or12_i_ack_i; + wire wbm_or12_i_err_i; + wire wbm_or12_i_rty_i; + wire [31:0] wbm_or12_debug_dat_o; + wire [31:0] wbm_or12_debug_adr_o; + wire [3:0] wbm_or12_debug_sel_o; + wire wbm_or12_debug_we_o; + wire [1:0] wbm_or12_debug_bte_o; + wire [2:0] wbm_or12_debug_cti_o; + wire wbm_or12_debug_stb_o; + wire wbm_or12_debug_cyc_o; + wire [31:0] wbm_or12_debug_dat_i; + wire wbm_or12_debug_ack_i; + wire wbm_or12_debug_err_i; + wire wbm_or12_debug_rty_i; + wire [31:0] wbm_or12_d_dat_o; + wire [31:0] wbm_or12_d_adr_o; + wire [3:0] wbm_or12_d_sel_o; + wire wbm_or12_d_we_o; + wire [1:0] wbm_or12_d_bte_o; + wire [2:0] wbm_or12_d_cti_o; + wire wbm_or12_d_stb_o; + wire wbm_or12_d_cyc_o; + wire [31:0] wbm_or12_d_dat_i; + wire wbm_or12_d_ack_i; + wire wbm_or12_d_err_i; + wire wbm_or12_d_rty_i; + wire [31:0] wbm_eth1_dat_o; + wire [31:0] wbm_eth1_adr_o; + wire [3:0] wbm_eth1_sel_o; + wire wbm_eth1_we_o; + wire [1:0] wbm_eth1_bte_o; + wire [2:0] wbm_eth1_cti_o; + wire wbm_eth1_stb_o; + wire wbm_eth1_cyc_o; + wire [31:0] wbm_eth1_dat_i; + wire wbm_eth1_ack_i; + wire wbm_eth1_err_i; + wire wbm_eth1_rty_i; + wire [31:0] wbs_eth1_cfg_dat_o; + wire [31:0] wbs_eth1_cfg_dat_i; + wire [31:0] wbs_eth1_cfg_adr_i; + wire [3:0] wbs_eth1_cfg_sel_i; + wire [1:0] wbs_eth1_cfg_bte_i; + wire [2:0] wbs_eth1_cfg_cti_i; + wire wbs_eth1_cfg_stb_i; + wire wbs_eth1_cfg_cyc_i; + wire wbs_eth1_cfg_ack_o; + wire wbs_eth1_cfg_err_o; + parameter wbs_eth1_cfg_rty_o = 1'b0; + wire [31:0] wbs_rom_dat_o; + wire [31:0] wbs_rom_dat_i; + wire [31:0] wbs_rom_adr_i; + wire [3:0] wbs_rom_sel_i; + wire [1:0] wbs_rom_bte_i; + wire [2:0] wbs_rom_cti_i; + wire wbs_rom_stb_i; + wire wbs_rom_cyc_i; + wire wbs_rom_ack_o; + parameter wbs_rom_err_o = 1'b0; + parameter wbs_rom_rty_o = 1'b0; + wire [31:0] wbs_mc_m_dat_o; + wire [31:0] wbs_mc_m_dat_i; + wire [31:0] wbs_mc_m_adr_i; + wire [3:0] wbs_mc_m_sel_i; + wire [1:0] wbs_mc_m_bte_i; + wire [2:0] wbs_mc_m_cti_i; + wire wbs_mc_m_stb_i; + wire wbs_mc_m_cyc_i; + wire wbs_mc_m_ack_o; + wire wbs_mc_m_err_o; + parameter wbs_mc_m_rty_o = 1'b0; + wire [31:0] wbs_spi_flash_dat_o; + wire [31:0] wbs_spi_flash_dat_i; + wire [31:0] wbs_spi_flash_adr_i; + wire [3:0] wbs_spi_flash_sel_i; + wire [1:0] wbs_spi_flash_bte_i; + wire [2:0] wbs_spi_flash_cti_i; + wire wbs_spi_flash_stb_i; + wire wbs_spi_flash_cyc_i; + wire wbs_spi_flash_ack_o; + parameter wbs_spi_flash_err_o = 1'b0; + parameter wbs_spi_flash_rty_o = 1'b0; + wire [31:0] wbs_uart0_dat_o; + wire [31:0] wbs_uart0_dat_i; + wire [31:0] wbs_uart0_adr_i; + wire [3:0] wbs_uart0_sel_i; + wire [1:0] wbs_uart0_bte_i; + wire [2:0] wbs_uart0_cti_i; + wire wbs_uart0_stb_i; + wire wbs_uart0_cyc_i; + wire wbs_uart0_ack_o; + parameter wbs_uart0_err_o = 1'b0; + parameter wbs_uart0_rty_o = 1'b0; + wire [31:0] wbs_ds1_dat_o; + wire [31:0] wbs_ds1_dat_i; + wire [31:0] wbs_ds1_adr_i; + wire [3:0] wbs_ds1_sel_i; + wire [1:0] wbs_ds1_bte_i; + wire [2:0] wbs_ds1_cti_i; + wire wbs_ds1_stb_i; + wire wbs_ds1_cyc_i; + wire wbs_ds1_ack_o; + parameter wbs_ds1_err_o = 1'b0; + parameter wbs_ds1_rty_o = 1'b0; + wire [31:0] wbs_ds2_dat_o; + wire [31:0] wbs_ds2_dat_i; + wire [31:0] wbs_ds2_adr_i; + wire [3:0] wbs_ds2_sel_i; + wire [1:0] wbs_ds2_bte_i; + wire [2:0] wbs_ds2_cti_i; + wire wbs_ds2_stb_i; + wire wbs_ds2_cyc_i; + wire wbs_ds2_ack_o; + parameter wbs_ds2_err_o = 1'b0; + parameter wbs_ds2_rty_o = 1'b0; + wire [31:0] wbs_ds3_dat_o; + wire [31:0] wbs_ds3_dat_i; + wire [31:0] wbs_ds3_adr_i; + wire [3:0] wbs_ds3_sel_i; + wire [1:0] wbs_ds3_bte_i; + wire [2:0] wbs_ds3_cti_i; + wire wbs_ds3_stb_i; + wire wbs_ds3_cyc_i; + wire wbs_ds3_ack_o; + parameter wbs_ds3_err_o = 1'b0; + parameter wbs_ds3_rty_o = 1'b0; + + wire eth_clk; + wire [1:1] eth_int; + + wb_conbus_top + #(.s0_addr_w(4), .s0_addr(4'h0), // MC + .s1_addr_w(4), .s1_addr(4'hf), // ROM + .s27_addr_w(8), + .s2_addr(8'h92), // ETH Slave + .s3_addr(8'hb0), // SPI + .s4_addr(8'h90), // UART + .s5_addr(8'hc0), // DS1 + .s6_addr(8'hd0), // DS2 + .s7_addr(8'he0)) // DS3 + wb_conbus + ( + // Master 0 + // Inputs + .m0_dat_i (wbm_or12_i_dat_o), + .m0_adr_i (wbm_or12_i_adr_o), + .m0_sel_i (wbm_or12_i_sel_o), + .m0_we_i (wbm_or12_i_we_o), + .m0_cyc_i (wbm_or12_i_cyc_o), + .m0_stb_i (wbm_or12_i_stb_o), + .m0_cab_i (1'b0), + // Outputs + .m0_dat_o (wbm_or12_i_dat_i), + .m0_ack_o (wbm_or12_i_ack_i), + .m0_err_o (wbm_or12_i_err_i), + .m0_rty_o (wbm_or12_i_rty_i), + + // Master 1 + // Inputs + .m1_dat_i (wbm_or12_debug_dat_o), + .m1_adr_i (wbm_or12_debug_adr_o), + .m1_sel_i (wbm_or12_debug_sel_o), + .m1_we_i (wbm_or12_debug_we_o), + .m1_cyc_i (wbm_or12_debug_cyc_o), + .m1_stb_i (wbm_or12_debug_stb_o), + .m1_cab_i (1'b0), + // Outputs + .m1_dat_o (wbm_or12_debug_dat_i), + .m1_ack_o (wbm_or12_debug_ack_i), + .m1_err_o (wbm_or12_debug_err_i), + .m1_rty_o (wbm_or12_debug_rty_i), + + // Master 2 + // Inputs + .m2_dat_i (wbm_or12_d_dat_o), + .m2_adr_i (wbm_or12_d_adr_o), + .m2_sel_i (wbm_or12_d_sel_o), + .m2_we_i (wbm_or12_d_we_o), + .m2_cyc_i (wbm_or12_d_cyc_o), + .m2_stb_i (wbm_or12_d_stb_o), + .m2_cab_i (1'b0), + // Outputs + .m2_dat_o (wbm_or12_d_dat_i), + .m2_ack_o (wbm_or12_d_ack_i), + .m2_err_o (wbm_or12_d_err_i), + .m2_rty_o (wbm_or12_d_rty_i), + + // Master 3 + // Inputs + .m3_dat_i (wbm_eth1_dat_o), + .m3_adr_i (wbm_eth1_adr_o), + .m3_sel_i (wbm_eth1_sel_o), + .m3_we_i (wbm_eth1_we_o), + .m3_cyc_i (wbm_eth1_cyc_o), + .m3_stb_i (wbm_eth1_stb_o), + .m3_cab_i (1'b0), + // Outputs + .m3_dat_o (wbm_eth1_dat_i), + .m3_ack_o (wbm_eth1_ack_i), + .m3_err_o (wbm_eth1_err_i), + .m3_rty_o (wbm_eth1_rty_i), + + // Master 4 + // Inputs + .m4_dat_i (0), + .m4_adr_i (0), + .m4_sel_i (0), + .m4_we_i (0), + .m4_cyc_i (0), + .m4_stb_i (0), + .m4_cab_i (0), + // Outputs + //.m4_dat_o (), + //.m4_ack_o (), + //.m4_err_o (), + //.m4_rty_o (), + + // Master 5 + // Inputs + .m5_dat_i (0), + .m5_adr_i (0), + .m5_sel_i (0), + .m5_we_i (0), + .m5_cyc_i (0), + .m5_stb_i (0), + .m5_cab_i (0), + // Outputs + //.m5_dat_o (), + //.m5_ack_o (), + //.m5_err_o (), + //.m5_rty_o (), + + // Master 6 + // Inputs + .m6_dat_i (0), + .m6_adr_i (0), + .m6_sel_i (0), + .m6_we_i (0), + .m6_cyc_i (0), + .m6_stb_i (0), + .m6_cab_i (0), + // Outputs + //.m6_dat_o (), + //.m6_ack_o (), + //.m6_err_o (), + //.m6_rty_o (), + + // Master 7 + // Inputs + .m7_dat_i (0), + .m7_adr_i (0), + .m7_sel_i (0), + .m7_we_i (0), + .m7_cyc_i (0), + .m7_stb_i (0), + .m7_cab_i (0), + // Outputs + //.m7_dat_o (), + //.m7_ack_o (), + //.m7_err_o (), + //.m7_rty_o (), + + + // Slave 0 + // Inputs + .s0_dat_i (wbs_mc_m_dat_o), + .s0_ack_i (wbs_mc_m_ack_o), + .s0_err_i (wbs_mc_m_err_o), + .s0_rty_i (wbs_mc_m_rty_o), + // Outputs + .s0_dat_o (wbs_mc_m_dat_i), + .s0_adr_o (wbs_mc_m_adr_i), + .s0_sel_o (wbs_mc_m_sel_i), + .s0_we_o (wbs_mc_m_we_i), + .s0_cyc_o (wbs_mc_m_cyc_i), + .s0_stb_o (wbs_mc_m_stb_i), + //.s0_cab_o (), + + // Slave 1 + // Inputs + .s1_dat_i (wbs_rom_dat_o), + .s1_ack_i (wbs_rom_ack_o), + .s1_err_i (wbs_rom_err_o), + .s1_rty_i (wbs_rom_rty_o), + // Outputs + .s1_dat_o (wbs_rom_dat_i), + .s1_adr_o (wbs_rom_adr_i), + .s1_sel_o (wbs_rom_sel_i), + .s1_we_o (wbs_rom_we_i), + .s1_cyc_o (wbs_rom_cyc_i), + .s1_stb_o (wbs_rom_stb_i), + //.s1_cab_o (), + + // Slave 2 + // Inputs + .s2_dat_i (wbs_eth1_cfg_dat_o), + .s2_ack_i (wbs_eth1_cfg_ack_o), + .s2_err_i (wbs_eth1_cfg_err_o), + .s2_rty_i (wbs_eth1_cfg_rty_o), + // Outputs + .s2_dat_o (wbs_eth1_cfg_dat_i), + .s2_adr_o (wbs_eth1_cfg_adr_i), + .s2_sel_o (wbs_eth1_cfg_sel_i), + .s2_we_o (wbs_eth1_cfg_we_i), + .s2_cyc_o (wbs_eth1_cfg_cyc_i), + .s2_stb_o (wbs_eth1_cfg_stb_i), + //.s2_cab_o (), + + // Slave 3 + // Inputs + .s3_dat_i (wbs_spi_flash_dat_o), + .s3_ack_i (wbs_spi_flash_ack_o), + .s3_err_i (wbs_spi_flash_err_o), + .s3_rty_i (wbs_spi_flash_rty_o), + // Outputs + .s3_dat_o (wbs_spi_flash_dat_i), + .s3_adr_o (wbs_spi_flash_adr_i), + .s3_sel_o (wbs_spi_flash_sel_i), + .s3_we_o (wbs_spi_flash_we_i), + .s3_cyc_o (wbs_spi_flash_cyc_i), + .s3_stb_o (wbs_spi_flash_stb_i), + //.s3_cab_o (), + + // Slave 4 + // Inputs + .s4_dat_i (wbs_uart0_dat_o), + .s4_ack_i (wbs_uart0_ack_o), + .s4_err_i (wbs_uart0_err_o), + .s4_rty_i (wbs_uart0_rty_o), + // Outputs + .s4_dat_o (wbs_uart0_dat_i), + .s4_adr_o (wbs_uart0_adr_i), + .s4_sel_o (wbs_uart0_sel_i), + .s4_we_o (wbs_uart0_we_i), + .s4_cyc_o (wbs_uart0_cyc_i), + .s4_stb_o (wbs_uart0_stb_i), + //.s4_cab_o (), + + // Slave 5 + // Inputs + .s5_dat_i (wbs_ds1_dat_o), + .s5_ack_i (wbs_ds1_ack_o), + .s5_err_i (0), + .s5_rty_i (0), + // Outputs + .s5_dat_o (wbs_ds1_dat_i), + .s5_adr_o (wbs_ds1_adr_i), + .s5_sel_o (wbs_ds1_sel_i), + .s5_we_o (wbs_ds1_we_i), + .s5_cyc_o (wbs_ds1_cyc_i), + .s5_stb_o (wbs_ds1_stb_i), + .s5_cab_o (), + + // Slave 6 + // Inputs + .s6_dat_i (wbs_ds2_dat_o), + .s6_ack_i (wbs_ds2_ack_o), + .s6_err_i (0), + .s6_rty_i (0), + // Outputs + .s6_dat_o (wbs_ds2_dat_i), + .s6_adr_o (wbs_ds2_adr_i), + .s6_sel_o (wbs_ds2_sel_i), + .s6_we_o (wbs_ds2_we_i), + .s6_cyc_o (wbs_ds2_cyc_i), + .s6_stb_o (wbs_ds2_stb_i), + .s6_cab_o (), + + // Slave 7 + // Inputs + .s7_dat_i (wbs_ds3_dat_o), + .s7_ack_i (wbs_ds3_ack_o), + .s7_err_i (0), + .s7_rty_i (0), + // Outputs + .s7_dat_o (wbs_ds3_dat_i), + .s7_adr_o (wbs_ds3_adr_i), + .s7_sel_o (wbs_ds3_sel_i), + .s7_we_o (wbs_ds3_we_i), + .s7_cyc_o (wbs_ds3_cyc_i), + .s7_stb_o (wbs_ds3_stb_i), + .s7_cab_o (), + + // Inputs + .clk_i (wb_clk), + .rst_i (wb_rst)); + + // Tie all cycle type identifiers (CTI) and burst type extension (BTE) signals low + // Not supported by this arbiter. + assign wbs_eth1_cfg_bte_i = 0; + assign wbs_eth1_cfg_cti_i = 0; + assign wbs_rom_bte_i = 0; + assign wbs_rom_cti_i = 0; + assign wbs_spi_flash_bte_i = 0; + assign wbs_spi_flash_cti_i = 0; + assign wbs_mc_m_bte_i = 0; + assign wbs_mc_m_cti_i = 0; + assign wbs_uart0_bte_i = 0; + assign wbs_uart0_cti_i = 0; + assign wbs_ds1_bte_i = 0; + assign wbs_ds1_cti_i = 0; + assign wbs_ds2_bte_i = 0; + assign wbs_ds2_cti_i = 0; + assign wbs_ds3_bte_i = 0; + assign wbs_ds3_cti_i = 0; + + // Programmable interrupt controller lines (aka. IRQ lines) + assign pic_ints[30] = 1'b0; assign pic_ints[29] = 1'b0; assign pic_ints[28] = 1'b0; assign pic_ints[27] = 1'b0; @@ -396,7 +550,7 @@ assign pic_ints[2] = uart0_irq; assign pic_ints[1] = 1'b0; assign pic_ints[0] = 1'b0; - or1k_top i_or1k + or1k_top i_or1k ( .clk_i (wb_clk), .rst_i (wb_rst), @@ -447,67 +601,67 @@ .tdo_pad_o (dbg_tdo_pad_o), .tdo_padoe_o ( ) ); - OR1K_startup OR1K_startup0 - ( - .wb_adr_i(wbs_rom_adr_i[6:2]), - .wb_stb_i(wbs_rom_stb_i), - .wb_cyc_i(wbs_rom_cyc_i), - .wb_dat_o(wbs_rom_dat_o), - .wb_ack_o(wbs_rom_ack_o), - .wb_clk(wb_clk), - .wb_rst(wb_rst) - ); -wire spi_flash_mosi, spi_flash_miso, spi_flash_sclk; -wire [1:0] spi_flash_ss; -spi_flash_top # - ( - .divider(0), - .divider_len(2) - ) -spi_flash_top0 - ( - .wb_clk_i(wb_clk), - .wb_rst_i(wb_rst), - .wb_adr_i(wbs_spi_flash_adr_i[4:2]), - .wb_dat_i(wbs_spi_flash_dat_i), - .wb_dat_o(wbs_spi_flash_dat_o), - .wb_sel_i(wbs_spi_flash_sel_i), - .wb_we_i(wbs_spi_flash_we_i), - .wb_stb_i(wbs_spi_flash_stb_i), - .wb_cyc_i(wbs_spi_flash_cyc_i), - .wb_ack_o(wbs_spi_flash_ack_o), - .mosi_pad_o(spi_flash_mosi), - .miso_pad_i(spi_flash_miso), - .sclk_pad_o(spi_flash_sclk), - .ss_pad_o(spi_flash_ss) - ); + OR1K_startup OR1K_startup0 + ( + .wb_adr_i(wbs_rom_adr_i[6:2]), + .wb_stb_i(wbs_rom_stb_i), + .wb_cyc_i(wbs_rom_cyc_i), + .wb_dat_o(wbs_rom_dat_o), + .wb_ack_o(wbs_rom_ack_o), + .wb_clk(wb_clk), + .wb_rst(wb_rst) + ); + wire spi_flash_mosi, spi_flash_miso, spi_flash_sclk; + wire [1:0] spi_flash_ss; + spi_flash_top # + ( + .divider(0), + .divider_len(2) + ) + spi_flash_top0 + ( + .wb_clk_i(wb_clk), + .wb_rst_i(wb_rst), + .wb_adr_i(wbs_spi_flash_adr_i[4:2]), + .wb_dat_i(wbs_spi_flash_dat_i), + .wb_dat_o(wbs_spi_flash_dat_o), + .wb_sel_i(wbs_spi_flash_sel_i), + .wb_we_i(wbs_spi_flash_we_i), + .wb_stb_i(wbs_spi_flash_stb_i), + .wb_cyc_i(wbs_spi_flash_cyc_i), + .wb_ack_o(wbs_spi_flash_ack_o), + .mosi_pad_o(spi_flash_mosi), + .miso_pad_i(spi_flash_miso), + .sclk_pad_o(spi_flash_sclk), + .ss_pad_o(spi_flash_ss) + ); `ifdef USE_SDRAM - wb_sdram_ctrl wb_sdram_ctrl0 - ( - .wb_dat_i(wbs_mc_m_dat_i), - .wb_dat_o(wbs_mc_m_dat_o), - .wb_sel_i(wbs_mc_m_sel_i), - .wb_adr_i(wbs_mc_m_adr_i[24:2]), - .wb_we_i (wbs_mc_m_we_i), - .wb_cti_i(wbs_mc_m_cti_i), - .wb_stb_i(wbs_mc_m_stb_i), - .wb_cyc_i(wbs_mc_m_cyc_i), - .wb_ack_o(wbs_mc_m_ack_o), - .sdr_cke_o(mem_cke_pad_o), - .sdr_cs_n_o(mem_cs_pad_o), - .sdr_ras_n_o(mem_ras_pad_o), - .sdr_cas_n_o(mem_cas_pad_o), - .sdr_we_n_o(mem_we_pad_o), - .sdr_a_o(mem_adr_pad_o), - .sdr_ba_o(mem_ba_pad_o), - .sdr_dq_io(mem_dat_pad_io), - .sdr_dqm_o(mem_dqm_pad_o), - .sdram_clk(wb_clk), - .wb_clk(wb_clk), - .wb_rst(wb_rst) - ); + wb_sdram_ctrl wb_sdram_ctrl0 + ( + .wb_dat_i(wbs_mc_m_dat_i), + .wb_dat_o(wbs_mc_m_dat_o), + .wb_sel_i(wbs_mc_m_sel_i), + .wb_adr_i(wbs_mc_m_adr_i[24:2]), + .wb_we_i (wbs_mc_m_we_i), + .wb_cti_i(wbs_mc_m_cti_i), + .wb_stb_i(wbs_mc_m_stb_i), + .wb_cyc_i(wbs_mc_m_cyc_i), + .wb_ack_o(wbs_mc_m_ack_o), + .sdr_cke_o(mem_cke_pad_o), + .sdr_cs_n_o(mem_cs_pad_o), + .sdr_ras_n_o(mem_ras_pad_o), + .sdr_cas_n_o(mem_cas_pad_o), + .sdr_we_n_o(mem_we_pad_o), + .sdr_a_o(mem_adr_pad_o), + .sdr_ba_o(mem_ba_pad_o), + .sdr_dq_io(mem_dat_pad_io), + .sdr_dqm_o(mem_dqm_pad_o), + .sdram_clk(wb_clk), + .wb_clk(wb_clk), + .wb_rst(wb_rst) + ); // SPI flash memory signals assign spi_flash_mosi_pad_o = !spi_flash_ss[0] ? spi_flash_mosi : 1'b1; @@ -519,8 +673,8 @@ assign spi_sd_sclk_pad_o = !spi_flash_ss[1] ? spi_flash_sclk : 1'b1; assign spi_sd_ss_pad_o = spi_flash_ss[1]; assign spi_flash_miso = !spi_flash_ss[0] ? spi_flash_miso_pad_i : - !spi_flash_ss[1] ? spi_sd_miso_pad_i : - 1'b0; + !spi_flash_ss[1] ? spi_sd_miso_pad_i : + 1'b0; `else // !`ifdef USE_SDRAM @@ -529,33 +683,33 @@ //parameter ram_wb_mem_size = 2097152; // 8MB parameter ram_wb_mem_size = 8388608; // 32MB -- for linux test - ram_wb - # - ( - .dat_width(ram_wb_dat_width), - .adr_width(ram_wb_adr_width), - .mem_size(ram_wb_mem_size) - ) + ram_wb + # + ( + .dat_width(ram_wb_dat_width), + .adr_width(ram_wb_adr_width), + .mem_size(ram_wb_mem_size) + ) ram_wb0 - ( - .dat_i(wbs_mc_m_dat_i), - .dat_o(wbs_mc_m_dat_o), - .sel_i(wbs_mc_m_sel_i), - .adr_i(wbs_mc_m_adr_i[ram_wb_adr_width-1:2]), - .we_i (wbs_mc_m_we_i), - .cti_i(wbs_mc_m_cti_i), - .stb_i(wbs_mc_m_stb_i), - .cyc_i(wbs_mc_m_cyc_i), - .ack_o(wbs_mc_m_ack_o), - .clk_i(wb_clk), - .rst_i(wb_rst) - ); + ( + .dat_i(wbs_mc_m_dat_i), + .dat_o(wbs_mc_m_dat_o), + .sel_i(wbs_mc_m_sel_i), + .adr_i(wbs_mc_m_adr_i[ram_wb_adr_width-1:2]), + .we_i (wbs_mc_m_we_i), + .cti_i(wbs_mc_m_cti_i), + .stb_i(wbs_mc_m_stb_i), + .cyc_i(wbs_mc_m_cyc_i), + .ack_o(wbs_mc_m_ack_o), + .clk_i(wb_clk), + .rst_i(wb_rst) + ); `endif // !`ifdef USE_SDRAM -assign wbs_mc_m_err_o = 1'b0; + assign wbs_mc_m_err_o = 1'b0; - uart_top + uart_top #( 32, 5) i_uart_0_top ( @@ -582,128 +736,128 @@ assign gpio_a_pad_io[7:0] = 8'hfe; `ifdef USE_ETHERNET - wire m1tx_clk; -wire [3:0] m1txd; -wire m1txen; -wire m1txerr; -wire m1rx_clk; -wire [3:0] m1rxd; -wire m1rxdv; -wire m1rxerr; -wire m1coll; -wire m1crs; -wire [10:1] state; -wire sync; -wire [1:1] rx, tx; -wire [1:1] mdc_o, md_i, md_o, md_oe; -smii_sync smii_sync1 - ( - .sync(sync), - .state(state), - .clk(eth_clk), - .rst(wb_rst) - ); -eth_top eth_top1 - ( - .wb_clk_i(wb_clk), - .wb_rst_i(wb_rst), - .wb_dat_i(wbs_eth1_cfg_dat_i), - .wb_dat_o(wbs_eth1_cfg_dat_o), - .wb_adr_i(wbs_eth1_cfg_adr_i[11:2]), - .wb_sel_i(wbs_eth1_cfg_sel_i), - .wb_we_i(wbs_eth1_cfg_we_i), - .wb_cyc_i(wbs_eth1_cfg_cyc_i), - .wb_stb_i(wbs_eth1_cfg_stb_i), - .wb_ack_o(wbs_eth1_cfg_ack_o), - .wb_err_o(wbs_eth1_cfg_err_o), - .m_wb_adr_o(wbm_eth1_adr_o), - .m_wb_sel_o(wbm_eth1_sel_o), - .m_wb_we_o(wbm_eth1_we_o), - .m_wb_dat_o(wbm_eth1_dat_o), - .m_wb_dat_i(wbm_eth1_dat_i), - .m_wb_cyc_o(wbm_eth1_cyc_o), - .m_wb_stb_o(wbm_eth1_stb_o), - .m_wb_ack_i(wbm_eth1_ack_i), - .m_wb_err_i(wbm_eth1_err_i), - .m_wb_cti_o(wbm_eth1_cti_o), - .m_wb_bte_o(wbm_eth1_bte_o), - .mtx_clk_pad_i(m1tx_clk), - .mtxd_pad_o(m1txd), - .mtxen_pad_o(m1txen), - .mtxerr_pad_o(m1txerr), - .mrx_clk_pad_i(m1rx_clk), - .mrxd_pad_i(m1rxd), - .mrxdv_pad_i(m1rxdv), - .mrxerr_pad_i(m1rxerr), - .mcoll_pad_i(m1coll), - .mcrs_pad_i(m1crs), - .mdc_pad_o(mdc_o[1]), - .md_pad_i(md_i[1]), - .md_pad_o(md_o[1]), - .md_padoe_o(md_oe[1]), - .int_o(eth_int[1]) - ); + wire m1tx_clk; + wire [3:0] m1txd; + wire m1txen; + wire m1txerr; + wire m1rx_clk; + wire [3:0] m1rxd; + wire m1rxdv; + wire m1rxerr; + wire m1coll; + wire m1crs; + wire [10:1] state; + wire sync; + wire [1:1] rx, tx; + wire [1:1] mdc_o, md_i, md_o, md_oe; + smii_sync smii_sync1 + ( + .sync(sync), + .state(state), + .clk(eth_clk), + .rst(wb_rst) + ); + eth_top eth_top1 + ( + .wb_clk_i(wb_clk), + .wb_rst_i(wb_rst), + .wb_dat_i(wbs_eth1_cfg_dat_i), + .wb_dat_o(wbs_eth1_cfg_dat_o), + .wb_adr_i(wbs_eth1_cfg_adr_i[11:2]), + .wb_sel_i(wbs_eth1_cfg_sel_i), + .wb_we_i(wbs_eth1_cfg_we_i), + .wb_cyc_i(wbs_eth1_cfg_cyc_i), + .wb_stb_i(wbs_eth1_cfg_stb_i), + .wb_ack_o(wbs_eth1_cfg_ack_o), + .wb_err_o(wbs_eth1_cfg_err_o), + .m_wb_adr_o(wbm_eth1_adr_o), + .m_wb_sel_o(wbm_eth1_sel_o), + .m_wb_we_o(wbm_eth1_we_o), + .m_wb_dat_o(wbm_eth1_dat_o), + .m_wb_dat_i(wbm_eth1_dat_i), + .m_wb_cyc_o(wbm_eth1_cyc_o), + .m_wb_stb_o(wbm_eth1_stb_o), + .m_wb_ack_i(wbm_eth1_ack_i), + .m_wb_err_i(wbm_eth1_err_i), + .m_wb_cti_o(wbm_eth1_cti_o), + .m_wb_bte_o(wbm_eth1_bte_o), + .mtx_clk_pad_i(m1tx_clk), + .mtxd_pad_o(m1txd), + .mtxen_pad_o(m1txen), + .mtxerr_pad_o(m1txerr), + .mrx_clk_pad_i(m1rx_clk), + .mrxd_pad_i(m1rxd), + .mrxdv_pad_i(m1rxdv), + .mrxerr_pad_i(m1rxerr), + .mcoll_pad_i(m1coll), + .mcrs_pad_i(m1crs), + .mdc_pad_o(mdc_o[1]), + .md_pad_i(md_i[1]), + .md_pad_o(md_o[1]), + .md_padoe_o(md_oe[1]), + .int_o(eth_int[1]) + ); -`ifdef USE_ETHERNET_IO -iobuftri iobuftri1 - ( - .i(md_o[1]), - .oe(md_oe[1]), - .o(md_i[1]), - .pad(eth_md_pad_io[1]) - ); -obuf obuf1 - ( - .i(mdc_o[1]), - .pad(eth_mdc_pad_o[1]) - ); -smii_txrx smii_txrx1 - ( - .tx(tx[1]), - .rx(rx[1]), - .mtx_clk(m1tx_clk), - .mtxd(m1txd), - .mtxen(m1txen), - .mtxerr(m1txerr), - .mrx_clk(m1rx_clk), - .mrxd(m1rxd), - .mrxdv(m1rxdv), - .mrxerr(m1rxerr), - .mcoll(m1coll), - .mcrs(m1crs), - .state(state), - .clk(eth_clk), - .rst(wb_rst) - ); + `ifdef USE_ETHERNET_IO + iobuftri iobuftri1 + ( + .i(md_o[1]), + .oe(md_oe[1]), + .o(md_i[1]), + .pad(eth_md_pad_io[1]) + ); + obuf obuf1 + ( + .i(mdc_o[1]), + .pad(eth_mdc_pad_o[1]) + ); + smii_txrx smii_txrx1 + ( + .tx(tx[1]), + .rx(rx[1]), + .mtx_clk(m1tx_clk), + .mtxd(m1txd), + .mtxen(m1txen), + .mtxerr(m1txerr), + .mrx_clk(m1rx_clk), + .mrxd(m1rxd), + .mrxdv(m1rxdv), + .mrxerr(m1rxerr), + .mcoll(m1coll), + .mcrs(m1crs), + .state(state), + .clk(eth_clk), + .rst(wb_rst) + ); -obufdff obufdff_sync1 - ( - .d(sync), - .pad(eth_sync_pad_o[1]), - .clk(eth_clk), - .rst(wb_rst) - ); -obufdff obufdff_tx1 - ( - .d(tx[1]), - .pad(eth_tx_pad_o[1]), - .clk(eth_clk), - .rst(wb_rst) - ); -ibufdff ibufdff_rx1 - ( - .pad(eth_rx_pad_i[1]), - .q(rx[1]), - .clk(eth_clk), - .rst(wb_rst) - ); -`endif // `ifdef USE_ETHERNET_IO + obufdff obufdff_sync1 + ( + .d(sync), + .pad(eth_sync_pad_o[1]), + .clk(eth_clk), + .rst(wb_rst) + ); + obufdff obufdff_tx1 + ( + .d(tx[1]), + .pad(eth_tx_pad_o[1]), + .clk(eth_clk), + .rst(wb_rst) + ); + ibufdff ibufdff_rx1 + ( + .pad(eth_rx_pad_i[1]), + .q(rx[1]), + .clk(eth_clk), + .rst(wb_rst) + ); + `endif // `ifdef USE_ETHERNET_IO `else // !`ifdef USE_ETHERNET // If ethernet core is disabled, still ack anyone who tries // to access its config port. This allows linux to boot in // the verilated ORPSoC. - reg wbs_eth1_cfg_ack_r; + reg wbs_eth1_cfg_ack_r; always @(posedge wb_clk) wbs_eth1_cfg_ack_r <= (wbs_eth1_cfg_cyc_i & wbs_eth1_cfg_stb_i); @@ -734,8 +888,8 @@ .rst(wb_rst) ); dummy_slave - # ( .value(32'hf0000000)) - ds2 + # ( .value(32'hd0000000)) + ds2 ( .dat_o(wbs_ds2_dat_o), .stb_i(wbs_ds2_stb_i), @@ -744,6 +898,18 @@ .clk(wb_clk), .rst(wb_rst) ); + dummy_slave + # ( .value(32'he0000000)) + ds3 + ( + .dat_o(wbs_ds3_dat_o), + .stb_i(wbs_ds3_stb_i), + .cyc_i(wbs_ds3_cyc_i), + .ack_o(wbs_ds3_ack_o), + .clk(wb_clk), + .rst(wb_rst) + ); + clk_gen iclk_gen ( .POWERDOWN (1'b1),

/sim/bin/icarus.scr

/sim/bin/Makefile

/sim/bin/verilator.scr