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https://opencores.org/ocsvn/openrisc/openrisc/trunk
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- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2
- from Rev 563 to Rev 564
- ↔ Reverse comparison
Rev 563 → Rev 564
/doc/orpsoc.texi
164,7 → 164,7
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Typically, a board-targeted design will wish to reuse common components (processor, debug interface, Wishbone arbiters, UART etc.) |
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The project has been configured so a board build will use modules in the ``common'' RTL path (@code{rtl/verilog/}) @emph{unless} there is a copy in the board's ``local'' RTL path ( @code{boards/vendor/boardname/rtl/verilog}). |
The project has been configured so a board build will use modules in the ``common'' RTL path (@code{rtl/verilog/}) @emph{unless} there is a copy in the board's ``local'' RTL path ( @code{boards/vendor/boardname/rtl/verilog}) or the board includes an external module in @code{boards/vendor/boardname/modules}. |
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For example, in the event that modification to a module in the common RTL set is required for it to function correctly in a board build, it's advisable to copy that module to the board's @emph{local} RTL path and modify it there. Simulation and backend scripts should then use this board-specific version instead of the one in the common RTL path. |
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288,6 → 288,8
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The directory structure consists of an @code{rtl} directory in the root, and a @code{verilog} path under that. Within the @code{rtl/verilog} path, each module has its own directory. |
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External modules using the OpenCores structure can be put under each boards @code{modules} directory. The scripts will the look for verilog files under @code{modules/<module_name>/rtl/verilog}. |
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A common Verilog include path, @code{rtl/verilog/include} directory is used. The Verilog HDL include files for each module should be moved here. This allows each @value{ORPSOC} implementation (board design) to maintain their own include path, and thus configure the modules for their specific implementation. |
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@node Reference Design Software |
883,8 → 885,10
@itemize @bullet |
@item RTL Files |
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Create a directory under the board's @code{rtl/verilog} directory, and name it the same as the top level of the module. |
Create a directory under the board's @code{rtl/verilog} directory, and name it the same as the top level of the module. |
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Ensure the module's top level file and actual name of the module when it will be instantiated are @emph{all the same}. |
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Place any include files into the board's @code{rtl/verilog/include} path. |
1310,12 → 1314,17
@itemize @bullet |
@item RTL Files |
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Create a directory under the board's @code{rtl/verilog} directory, and name it the same as the top level of the module. |
@itemize @bullet |
@item Create a directory under the board's @code{rtl/verilog} directory, and name it the same as the top level of the module. |
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Ensure the module's top level file and actual name of the module when it will be instantiated are @emph{all the same}. |
@emph{or} |
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Place any include files into the board's @code{rtl/verilog/include} path. |
Create a directory under the board's @code{modules} directory, containing a @code{rtl/verilog} directory, and name it the same as the top level of the module |
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@item Ensure the module's top level file and actual name of the module when it will be instantiated are @emph{all the same}. |
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@item Place any include files into the board's @code{rtl/verilog/include} path. |
@end itemize |
@item Instantiate in ORPSoC Top Level File |
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Instantiate the module in the ORPSoC top level file, @code{rtl/verilog/orpsoc_top/orpsoc_top.v}, and be sure to take care of the following. |