URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
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- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2
- from Rev 64 to Rev 65
- ↔ Reverse comparison
Rev 64 → Rev 65
/bench/verilog/uart_decoder.v
75,8 → 75,11
reg [7:0] tx_byte; |
begin |
|
while (`UART_TX_LINE !== 1'b1) |
@(`UART_TX_LINE); |
// Wait for start bit |
while (`UART_TX_LINE == 1'b1) |
//while (`UART_TX_LINE == 1'b1) |
while (`UART_TX_LINE !== 1'b0) |
@(`UART_TX_LINE); |
#(UART_TX_WAIT+(UART_TX_WAIT/2)); |
tx_byte[0] = `UART_TX_LINE; |
96,11 → 99,13
tx_byte[7] = `UART_TX_LINE; |
#UART_TX_WAIT; |
//Check for stop bit |
if (`UART_TX_LINE == 1'b0) |
//if (`UART_TX_LINE == 1'b0) |
if (`UART_TX_LINE !== 1'b1) |
begin |
//$display("* WARNING: user stop bit not received when expected at time %d__", $time); |
// Wait for return to idle |
while (`UART_TX_LINE == 1'b0) |
//while (`UART_TX_LINE == 1'b0) |
while (`UART_TX_LINE !== 1'b1) |
@(`UART_TX_LINE); |
//$display("* USER UART returned to idle at time %d",$time); |
end |
/rtl/verilog/or1200_defines.v
1060,8 → 1060,8
// |
`define OR1200_DU_HWBKPTS |
|
// Number of DVR/DCR pairs if HW breakpoints enabled |
`define OR1200_DU_DVRDCR_PAIRS 8 |
// Number of DVR/DCR pairs, minus one, if HW breakpoints enabled |
`define OR1200_DU_DVRDCR_PAIRS 7 |
|
// Define if you want trace buffer |
//`define OR1200_DU_TB_IMPLEMENTED |