URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/openrisc/trunk/orpsocv2
- from Rev 656 to Rev 660
- ↔ Reverse comparison
Rev 656 → Rev 660
/scripts/make/Makefile-board-modelsim.inc
15,7 → 15,7
ifeq ($(FPGA_VENDOR), xilinx) |
MGC_VSIM_TGT=orpsoc_testbench glbl |
else |
MGC_VSIM_TGT=orpsoc_testbench -L $(BACKEND_LIB) |
MGC_VSIM_TGT=orpsoc_testbench |
endif |
|
else |
35,7 → 35,16
# Suppressed warnings - 3009: Failed to open $readmemh() file |
# Suppressed warnings - 3009: Module 'blah' does not have a `timescale directive in effect, but previous modules do. |
# Suppressed warnings - 8598: Non-positive replication multiplier inside concat. Replication will be ignored |
|
# - set GUI=1 if you want to invoke Modelsim GUI to debug |
# - Propably you would like to switch off optimization |
# also which will allow you to see all nets ... |
# |
ifeq ($(GUI), 1) |
VSIM_ARGS+= -suppress 7 -suppress 3009 -suppress 8598 -novopt -do "set StdArithNoWarnings 1" |
else |
VSIM_ARGS+= -suppress 7 -suppress 3009 -suppress 8598 -c $(QUIET) -do "set StdArithNoWarnings 1; run -all; exit" |
endif |
|
# VPI debugging interface set up |
VPI_SRC_C_DIR=$(COMMON_BENCH_VERILOG_DIR)/vpi/c |
61,9 → 70,11
# Backend script generation - make these rules sensitive to source and includes |
modelsim_backend.scr: $(BOARD_BACKEND_VERILOG_SRC) |
$(Q)echo "+incdir+"$(TECHNOLOGY_BACKEND_VERILOG_DIR) > $@; |
$(Q)echo "-y " $(BOARD_BACKEND_VERILOG_DIR) >> $@; |
$(Q)echo "+incdir+"$(BOARD_BACKEND_VERILOG_SRC) >> $@; |
$(Q)echo "+incdir+"$(BOARD_BENCH_VERILOG_DIR) > $@; |
$(Q)for vsrc in $(BACKEND_TECHNOLOGY_VERILOG_SRC); do echo $$vsrc >> $@; done |
$(Q)echo "-y " $(TECHNOLOGY_LIBRARY_VERILOG_DIR) >> $@; |
$(Q)for vsrc in $(BOARD_BACKEND_VERILOG_SRC); do echo $$vsrc >> $@; done |
$(Q)echo "+libext+.v" >> $@; |
$(Q)echo >> $@; |
|
84,10 → 95,14
$(Q)echo "-y "$(TECHNOLOGY_LIBRARY_VERILOG_DIR)"/src/unisims" >> $@; |
$(Q)echo "-y "$(TECHNOLOGY_LIBRARY_VERILOG_DIR)"/src/XilinxCoreLib" >> $@; |
endif |
$(Q)echo >> $@ |
ifeq ($(BOARD_NAME), ordb2a-ep4ce22) |
$(Q)echo "../../rtl/verilog/versatile_library/versatile_library_ordbcycloneiv.v" >> $@; |
endif |
$(Q)echo >> $@; |
|
modelsim_bench.scr: $(BOARD_BENCH_VERILOG_SRC) $(COMMON_BENCH_VERILOG_SRC) |
$(Q)echo "+incdir+"$(BOARD_BENCH_VERILOG_INCLUDE_DIR) > $@; |
$(Q)echo "+incdir+"$(BOARD_RTL_VERILOG_INCLUDE_DIR) > $@; |
$(Q)echo "+incdir+"$(BOARD_BENCH_VERILOG_INCLUDE_DIR) >> $@; |
$(Q)echo "+incdir+"$(COMMON_BENCH_VERILOG_INCLUDE_DIR) >> $@; |
$(Q)for path in $(BENCH_VERILOG_SUBDIRS); do echo "+incdir+"$$path >> $@; done |
$(Q)for path in $(BENCH_VERILOG_SUBDIRS); do echo "-y "$$path >> $@; done |
115,7 → 130,7
work: modelsim_dut.scr |
$(Q)if [ ! -e $@ ]; then vlib $@; fi |
$(Q)echo; echo "\t### Compiling Verilog design library ###"; echo |
$(Q)vlog $(QUIET) -f $< $(DUT_TOP_FILE) |
$(Q)vlog $(QUIET) -f $< $(DUT_TOP_FILE) |
$(Q)if [ "$(RTL_VHDL_SRC)" != "" ]; then \ |
echo; echo "\t### Compiling VHDL design library ###"; \ |
echo; \ |
152,7 → 167,10
$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(BACKEND_LIB) $(VPI_LIBS) work |
$(Q)echo; echo "\t### Compiling testbench ###"; echo |
$(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP_FILE) -f $< |
ifneq ($(MGC_NO_VOPT), 1) |
$(Q)echo; echo "\t### Optimizing testbench ###"; echo |
$(Q)$(MGC_VOPT_EXE) $(QUIET) $(RTL_TESTBENCH_TOP_NAME) $(VOPT_ARGS) -L $(BACKEND_LIB) -o tb |
endif |
$(Q)echo; echo "\t### Launching simulation ###"; echo |
$(Q)vsim $(VSIM_ARGS) $(MGC_VSIM_TGT) |
endif |
$(Q)vsim $(QUIET) $(VSIM_ARGS) $(MGC_VSIM_TGT) -L $(BACKEND_LIB) |
endif |