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    /openrisc/trunk/rtos/ecos-2.0/packages/hal/arm/at91
    from Rev 27 to Rev 174
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Rev 27 → Rev 174

/v2_0/cdl/hal_arm_at91.cdl
0,0 → 1,293
# ====================================================================
#
# hal_arm_at91.cdl
#
# Atmel evaluation board (EB40) HAL package configuration data
#
# ====================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
# ====================================================================
######DESCRIPTIONBEGIN####
#
# Author(s): gthomas
# Contributors: gthomas
# Date: 2001-07-12
#
#####DESCRIPTIONEND####
#
# ====================================================================
 
cdl_package CYGPKG_HAL_ARM_AT91 {
display "Atmel evaluation board (EB40)"
parent CYGPKG_HAL_ARM
define_header hal_arm_at91.h
include_dir cyg/hal
hardware
description "
The AT91 HAL package provides the support needed to run
eCos on an Atmel AT91/EB40 eval board."
 
compile hal_diag.c at91_misc.c
 
implements CYGINT_HAL_DEBUG_GDB_STUBS
implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
implements CYGINT_HAL_ARM_ARCH_ARM7
implements CYGINT_HAL_ARM_THUMB_ARCH
 
define_proc {
puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_arm.h>"
puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_at91.h>"
puts $::cdl_header "#define HAL_PLATFORM_CPU \"ARM7TDMI\""
puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Atmel AT91/EB40\""
puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\""
}
 
cdl_component CYG_HAL_STARTUP {
display "Startup type"
flavor data
default_value {"RAM"}
legal_values {"RAM" "ROM" "ROMRAM"}
no_define
define -file system.h CYG_HAL_STARTUP
description "
When targetting the AT91 eval board it is possible to build
the system for either RAM bootstrap or ROM bootstrap(s). Select
'ram' when building programs to load into RAM using onboard
debug software such as Angel or eCos GDB stubs. Select 'rom'
when building a stand-alone application which will be put
into ROM. Using ROMRAM will allow the program to exist in
ROM, but be copied to RAM during startup."
}
 
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
display "Number of communication channels on the board"
flavor data
calculated 2
}
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
display "Debug serial port"
active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
flavor data
legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
default_value 0
description "
The AT91 board has two serial ports. This option
chooses which port will be used to connect to a host
running GDB."
}
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
display "Diagnostic serial port"
active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
flavor data
legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
default_value 0
description "
The AT91 board has two serial ports. This option
chooses which port will be used for diagnostic output."
}
 
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CHANNELS_DEFAULT_BAUD {
display "Console/GDB serial port baud rate"
flavor data
legal_values 9600 19200 38400 57600 115200
default_value 38400
description "
This option controls the default baud rate used for the
Console/GDB connection."
}
 
# Real-time clock/counter specifics
cdl_option CYGNUM_HAL_ARM_AT91_CLOCK_SPEED {
display "CPU clock speed"
flavor data
calculated 32768000
}
 
cdl_component CYGNUM_HAL_RTC_CONSTANTS {
display "Real-time clock constants"
flavor none
cdl_option CYGNUM_HAL_RTC_NUMERATOR {
display "Real-time clock numerator"
flavor data
calculated 1000000000
}
cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
display "Real-time clock denominator"
flavor data
calculated 100
}
cdl_option CYGNUM_HAL_RTC_PERIOD {
display "Real-time clock period"
flavor data
calculated ((CYGNUM_HAL_ARM_AT91_CLOCK_SPEED/32) / CYGNUM_HAL_RTC_DENOMINATOR)
}
}
 
cdl_component CYGBLD_GLOBAL_OPTIONS {
display "Global build options"
flavor none
parent CYGPKG_NONE
description "
Global build options including control over
compiler flags, linker flags and choice of toolchain."
 
 
cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
display "Global command prefix"
flavor data
no_define
default_value { "arm-elf" }
description "
This option specifies the command prefix used when
invoking the build tools."
}
 
cdl_option CYGBLD_GLOBAL_CFLAGS {
display "Global compiler flags"
flavor data
no_define
default_value { "-mcpu=arm7tdmi -mno-short-load-words -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
description "
This option controls the global compiler flags which are used to
compile all packages by default. Individual packages may define
options which override these global flags."
}
 
cdl_option CYGBLD_GLOBAL_LDFLAGS {
display "Global linker flags"
flavor data
no_define
default_value { "-mcpu=arm7tdmi -mno-short-load-words -Wl,--gc-sections -Wl,-static -g -nostdlib" }
description "
This option controls the global linker flags. Individual
packages may define options which override these global flags."
}
}
 
cdl_component CYGHWR_MEMORY_LAYOUT {
display "Memory layout"
flavor data
no_define
calculated { (CYG_HAL_STARTUP == "RAM") ? "arm_at91_eb40_ram" :
(CYG_HAL_STARTUP == "ROMRAM") ? "arm_at91_eb40_romram" :
"arm_at91_eb40_rom" }
 
cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
display "Memory layout linker script fragment"
flavor data
no_define
define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_arm_at91_eb40_ram.ldi>" :
(CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_at91_eb40_romram.ldi>" :
"<pkgconf/mlt_arm_at91_eb40_rom.ldi>" }
}
 
cdl_option CYGHWR_MEMORY_LAYOUT_H {
display "Memory layout header file"
flavor data
no_define
define -file system.h CYGHWR_MEMORY_LAYOUT_H
calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_arm_at91_eb40_ram.h>" :
(CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_at91_eb40_romram.h>" :
"<pkgconf/mlt_arm_at91_eb40_rom.h>" }
}
}
 
cdl_option CYGSEM_HAL_ROM_MONITOR {
display "Behave as a ROM monitor"
flavor bool
default_value 0
parent CYGPKG_HAL_ROM_MONITOR
requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM" }
description "
Enable this option if this program is to be used as a ROM monitor,
i.e. applications will be loaded into RAM on the board, and this
ROM monitor may process exceptions or interrupts generated from the
application. This enables features such as utilizing a separate
interrupt stack when exceptions are generated."
}
 
cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
display "Work with a ROM monitor"
flavor booldata
legal_values { "Generic" "GDB_stubs" }
default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
parent CYGPKG_HAL_ROM_MONITOR
requires { CYG_HAL_STARTUP == "RAM" }
description "
Support can be enabled for different varieties of ROM monitor.
This support changes various eCos semantics such as the encoding
of diagnostic output, or the overriding of hardware interrupt
vectors.
Firstly there is \"Generic\" support which prevents the HAL
from overriding the hardware vectors that it does not use, to
instead allow an installed ROM monitor to handle them. This is
the most basic support which is likely to be common to most
implementations of ROM monitor.
\"GDB_stubs\" provides support when GDB stubs are included in
the ROM monitor or boot ROM."
}
 
cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
display "Redboot HAL options"
flavor none
no_define
parent CYGPKG_REDBOOT
active_if CYGPKG_REDBOOT
description "
This option lists the target's requirements for a valid Redboot
configuration."
 
cdl_option CYGBLD_BUILD_REDBOOT_BIN {
display "Build Redboot ROM binary image"
active_if CYGBLD_BUILD_REDBOOT
default_value 1
no_define
description "This option enables the conversion of the Redboot ELF
image to a binary image suitable for ROM programming."
make -priority 325 {
<PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
$(OBJCOPY) --strip-debug $< $(@:.bin=.img)
$(OBJCOPY) -O srec $< $(@:.bin=.srec)
$(OBJCOPY) -O binary $< $@
}
 
}
}
}
/v2_0/include/plf_stub.h
0,0 → 1,86
#ifndef CYGONCE_HAL_PLF_STUB_H
#define CYGONCE_HAL_PLF_STUB_H
 
//=============================================================================
//
// plf_stub.h
//
// Platform header for GDB stub support.
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
// Contributors:jskov, gthomas
// Date: 2001-07-12
// Purpose: Platform HAL stub support for AT91/EB40 boards.
// Usage: #include <cyg/hal/plf_stub.h>
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
#include CYGBLD_HAL_PLATFORM_H
 
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 
#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM
 
#include <cyg/hal/arm_stub.h> // architecture stub support
 
//----------------------------------------------------------------------------
// Define some platform specific communication details. This is mostly
// handled by hal_if now, but we need to make sure the comms tables are
// properly initialized.
 
externC void cyg_hal_plf_comms_init(void);
 
#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init()
 
#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud))
#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0
#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT
 
//----------------------------------------------------------------------------
// Stub initializer.
#define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT
 
#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 
//-----------------------------------------------------------------------------
#endif // CYGONCE_HAL_PLF_STUB_H
// End of plf_stub.h
/v2_0/include/pkgconf/mlt_arm_at91_eb40_rom.h
0,0 → 1,25
// eCos memory layout - Wed Apr 11 13:49:55 2001
 
// This is a generated file - do not edit
 
#ifndef __ASSEMBLER__
#include <cyg/infra/cyg_type.h>
#include <stddef.h>
 
#endif
#define CYGMEM_REGION_ram (0x02000000)
#define CYGMEM_REGION_ram_SIZE (0x80000)
#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
#define CYGMEM_REGION_rom (0x01000000)
#define CYGMEM_REGION_rom_SIZE (0x20000)
#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__reserved_bootmon) [];
#endif
#define CYGMEM_SECTION_reserved_bootmon (CYG_LABEL_NAME (__reserved_bootmon))
#define CYGMEM_SECTION_reserved_bootmon_SIZE (0x10000)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__heap1) [];
#endif
#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
#define CYGMEM_SECTION_heap1_SIZE (0x02080000 - (size_t) CYG_LABEL_NAME (__heap1))
/v2_0/include/pkgconf/mlt_arm_at91_eb40_romram.h
0,0 → 1,20
// eCos memory layout - Mon Jul 23 11:49:04 2001
 
// This is a generated file - do not edit
 
#ifndef __ASSEMBLER__
#include <cyg/infra/cyg_type.h>
#include <stddef.h>
 
#endif
#define CYGMEM_REGION_sram (0)
#define CYGMEM_REGION_sram_SIZE (0x1000)
#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
#define CYGMEM_REGION_ram (0x2000000)
#define CYGMEM_REGION_ram_SIZE (0x80000)
#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__heap1) [];
#endif
#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
#define CYGMEM_SECTION_heap1_SIZE (0x2080000 - (size_t) CYG_LABEL_NAME (__heap1))
/v2_0/include/pkgconf/mlt_arm_at91_eb40_rom.ldi
0,0 → 1,30
// eCos memory layout - Wed Apr 11 13:49:55 2001
 
// This is a generated file - do not edit
 
#include <cyg/infra/cyg_type.inc>
 
MEMORY
{
sram : ORIGIN = 0x00000000, LENGTH = 0x2000
ram : ORIGIN = 0x02000000, LENGTH = 0x80000
rom : ORIGIN = 0x01000000, LENGTH = 0x20000
}
 
SECTIONS
{
SECTIONS_BEGIN
CYG_LABEL_DEFN(__reserved_bootmon) = 0x01000000; . = CYG_LABEL_DEFN(__reserved_bootmon) + 0x10000;
SECTION_rom_vectors (rom, ALIGN (0x8), LMA_EQ_VMA)
SECTION_text (rom, ALIGN (0x1), LMA_EQ_VMA)
SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fixed_vectors (sram, 0x20, LMA_EQ_VMA)
SECTION_data (ram, 0x02000000, FOLLOWING (.gcc_except_table))
SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
SECTIONS_END
}
/v2_0/include/pkgconf/mlt_arm_at91_eb40_romram.ldi
0,0 → 1,28
// eCos memory layout - Mon Jul 23 11:49:04 2001
 
// This is a generated file - do not edit
 
#include <cyg/infra/cyg_type.inc>
 
MEMORY
{
sram : ORIGIN = 0, LENGTH = 0x1000
ram : ORIGIN = 0x2000000, LENGTH = 0x80000
}
 
SECTIONS
{
SECTIONS_BEGIN
SECTION_fixed_vectors (sram, 0x20, LMA_EQ_VMA)
SECTION_rom_vectors (ram, 0x2000000, LMA_EQ_VMA)
SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata1 (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_data (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
SECTIONS_END
}
/v2_0/include/pkgconf/mlt_arm_at91_eb40_ram.h
0,0 → 1,20
// eCos memory layout - Mon Jul 23 11:49:04 2001
 
// This is a generated file - do not edit
 
#ifndef __ASSEMBLER__
#include <cyg/infra/cyg_type.h>
#include <stddef.h>
 
#endif
#define CYGMEM_REGION_sram (0)
#define CYGMEM_REGION_sram_SIZE (0x1000)
#define CYGMEM_REGION_sram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
#define CYGMEM_REGION_ram (0x2000000)
#define CYGMEM_REGION_ram_SIZE (0x80000)
#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__heap1) [];
#endif
#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
#define CYGMEM_SECTION_heap1_SIZE (0x2080000 - (size_t) CYG_LABEL_NAME (__heap1))
/v2_0/include/pkgconf/mlt_arm_at91_eb40_ram.ldi
0,0 → 1,28
// eCos memory layout - Mon Jul 23 11:49:04 2001
 
// This is a generated file - do not edit
 
#include <cyg/infra/cyg_type.inc>
 
MEMORY
{
sram : ORIGIN = 0, LENGTH = 0x1000
ram : ORIGIN = 0x2000000, LENGTH = 0x80000
}
 
SECTIONS
{
SECTIONS_BEGIN
SECTION_fixed_vectors (sram, 0x20, LMA_EQ_VMA)
SECTION_rom_vectors (ram, 0x2020000, LMA_EQ_VMA)
SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata1 (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_data (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
SECTIONS_END
}
/v2_0/include/pkgconf/mlt_arm_at91_eb40_rom.mlt
0,0 → 1,16
version 0
region sram 0 80000 00100000 !
region ram 0 80000 00100000 !
region rom 01000000 20000 1 !
section fixed_vectors 0 1 0 1 1 0 1 0 20 20 !
section data 0 1 1 1 1 1 0 0 00100000 bss !
section bss 0 4 0 1 0 1 0 1 heap1 heap1 !
section heap1 0 8 0 0 0 0 0 0 !
section reserved_bootmon 10000 1 0 0 1 1 1 1 01000000 01000000 rom_vectors rom_vectors !
section rom_vectors 0 8 0 1 0 1 0 1 text text !
section text 0 1 0 1 0 1 0 1 fini fini !
section fini 0 4 0 1 0 1 0 1 rodata rodata !
section rodata 0 4 0 1 0 1 0 1 rodata1 rodata1 !
section rodata1 0 4 0 1 0 1 0 1 fixup fixup !
section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
section gcc_except_table 0 4 0 1 0 0 0 1 data !
/v2_0/include/pkgconf/mlt_arm_at91_eb40_romram.mlt
0,0 → 1,14
version 0
region sram 0 1000 0 !On-chip SRAM
region ram 2000000 80000 0 !
section fixed_vectors 0 1 0 1 1 0 1 0 20 20 !
section rom_vectors 0 1 0 1 1 1 1 1 2000000 2000000 text text !
section text 0 4 0 1 0 1 0 1 fini fini !
section fini 0 4 0 1 0 1 0 1 rodata rodata !
section rodata 0 4 0 1 0 1 0 1 rodata1 rodata1 !
section rodata1 0 4 0 1 0 1 0 1 fixup fixup !
section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
section gcc_except_table 0 4 0 1 0 1 0 1 data data !
section data 0 4 0 1 0 1 0 1 bss bss !
section bss 0 4 0 1 0 1 0 1 heap1 heap1 !
section heap1 0 8 0 0 0 0 0 0 !
/v2_0/include/pkgconf/mlt_arm_at91_eb40_ram.mlt
0,0 → 1,14
version 0
region sram 0 1000 0 !On-chip SRAM
region ram 2000000 80000 0 !
section fixed_vectors 0 1 0 1 1 0 1 0 20 20 !
section rom_vectors 0 1 0 1 1 1 1 1 2020000 2020000 text text !
section text 0 4 0 1 0 1 0 1 fini fini !
section fini 0 4 0 1 0 1 0 1 rodata rodata !
section rodata 0 4 0 1 0 1 0 1 rodata1 rodata1 !
section rodata1 0 4 0 1 0 1 0 1 fixup fixup !
section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
section gcc_except_table 0 4 0 1 0 1 0 1 data data !
section data 0 4 0 1 0 1 0 1 bss bss !
section bss 0 4 0 1 0 1 0 1 heap1 heap1 !
section heap1 0 8 0 0 0 0 0 0 !
/v2_0/include/hal_platform_ints.h
0,0 → 1,86
#ifndef CYGONCE_HAL_PLATFORM_INTS_H
#define CYGONCE_HAL_PLATFORM_INTS_H
//==========================================================================
//
// hal_platform_ints.h
//
// HAL Interrupt and clock assignments for AT91/EB40
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): gthomas
// Contributors: gthomas
// Date: 2001-07-12
// Purpose: Define Interrupt support
// Description: The interrupt specifics for the AT91/EB40 board/platform are
// defined here.
//
// Usage: #include <cyg/hal/hal_platform_ints.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#define CYGNUM_HAL_INTERRUPT_USART0 2
#define CYGNUM_HAL_INTERRUPT_USART1 3
#define CYGNUM_HAL_INTERRUPT_TIMER0 4
#define CYGNUM_HAL_INTERRUPT_TIMER1 5
#define CYGNUM_HAL_INTERRUPT_TIMER2 6
#define CYGNUM_HAL_INTERRUPT_WATCHDOG 7
#define CYGNUM_HAL_INTERRUPT_PIO 8
#define CYGNUM_HAL_INTERRUPT_EXT0 16
#define CYGNUM_HAL_INTERRUPT_EXT1 17
#define CYGNUM_HAL_INTERRUPT_EXT2 18
 
#define CYGNUM_HAL_ISR_MIN 2
#define CYGNUM_HAL_ISR_MAX 18
// Note: extra slots (0,1) to avoid messing with vector translation
#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX + 1)
 
// The vector used by the Real time clock
#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER0
 
 
//----------------------------------------------------------------------------
// Reset.
#define HAL_PLATFORM_RESET()
 
#define HAL_PLATFORM_RESET_ENTRY 0x01010000
 
#endif // CYGONCE_HAL_PLATFORM_INTS_H
/v2_0/include/hal_cache.h
0,0 → 1,192
#ifndef CYGONCE_HAL_CACHE_H
#define CYGONCE_HAL_CACHE_H
 
//=============================================================================
//
// hal_cache.h
//
// HAL cache control API
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg, gthomas
// Contributors: nickg, gthomas
// Date: 1998-09-28
// Purpose: Cache control API
// Description: The macros defined here provide the HAL APIs for handling
// cache control operations.
// Usage:
// #include <cyg/hal/hal_cache.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <cyg/infra/cyg_type.h>
 
//-----------------------------------------------------------------------------
// Cache dimensions
 
// Data cache
//#define HAL_DCACHE_SIZE 0 // Size of data cache in bytes
//#define HAL_DCACHE_LINE_SIZE 0 // Size of a data cache line
//#define HAL_DCACHE_WAYS 0 // Associativity of the cache
 
// Instruction cache
//#define HAL_ICACHE_SIZE 0 // Size of cache in bytes
//#define HAL_ICACHE_LINE_SIZE 0 // Size of a cache line
//#define HAL_ICACHE_WAYS 0 // Associativity of the cache
 
//#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
//#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
 
//-----------------------------------------------------------------------------
// Global control of data cache
 
// Enable the data cache
#define HAL_DCACHE_ENABLE()
 
// Disable the data cache
#define HAL_DCACHE_DISABLE()
 
// Invalidate the entire cache
#define HAL_DCACHE_INVALIDATE_ALL()
 
// Synchronize the contents of the cache with memory.
#define HAL_DCACHE_SYNC()
 
// Purge contents of data cache
#define HAL_DCACHE_PURGE_ALL()
 
// Query the state of the data cache (does not affect the caching)
#define HAL_DCACHE_IS_ENABLED(_state_) \
CYG_MACRO_START \
(_state_) = 0; \
CYG_MACRO_END
 
// Set the data cache refill burst size
//#define HAL_DCACHE_BURST_SIZE(_size_)
 
// Set the data cache write mode
//#define HAL_DCACHE_WRITE_MODE( _mode_ )
 
//#define HAL_DCACHE_WRITETHRU_MODE 0
//#define HAL_DCACHE_WRITEBACK_MODE 1
 
// Load the contents of the given address range into the data cache
// and then lock the cache so that it stays there.
//#define HAL_DCACHE_LOCK(_base_, _size_)
 
// Undo a previous lock operation
//#define HAL_DCACHE_UNLOCK(_base_, _size_)
 
// Unlock entire cache
//#define HAL_DCACHE_UNLOCK_ALL()
 
//-----------------------------------------------------------------------------
// Data cache line control
 
// Allocate cache lines for the given address range without reading its
// contents from memory.
//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
 
// Write dirty cache lines to memory and invalidate the cache entries
// for the given address range.
//#define HAL_DCACHE_FLUSH( _base_ , _size_ )
 
// Invalidate cache lines in the given range without writing to memory.
//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
 
// Write dirty cache lines to memory for the given address range.
//#define HAL_DCACHE_STORE( _base_ , _size_ )
 
// Preread the given range into the cache with the intention of reading
// from it later.
//#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
 
// Preread the given range into the cache with the intention of writing
// to it later.
//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
 
// Allocate and zero the cache lines associated with the given range.
//#define HAL_DCACHE_ZERO( _base_ , _size_ )
 
//-----------------------------------------------------------------------------
// Global control of Instruction cache
 
// Enable the instruction cache
#define HAL_ICACHE_ENABLE()
 
// Disable the instruction cache
#define HAL_ICACHE_DISABLE()
 
// Invalidate the entire cache
#define HAL_ICACHE_INVALIDATE_ALL()
 
// Synchronize the contents of the cache with memory.
#define HAL_ICACHE_SYNC()
 
// Query the state of the instruction cache (does not affect the caching)
#define HAL_ICACHE_IS_ENABLED(_state_) \
CYG_MACRO_START \
(_state_) = 0; \
CYG_MACRO_END
 
// Set the instruction cache refill burst size
//#define HAL_ICACHE_BURST_SIZE(_size_)
 
// Load the contents of the given address range into the instruction cache
// and then lock the cache so that it stays there.
//#define HAL_ICACHE_LOCK(_base_, _size_)
 
// Undo a previous lock operation
//#define HAL_ICACHE_UNLOCK(_base_, _size_)
 
// Unlock entire cache
//#define HAL_ICACHE_UNLOCK_ALL()
 
//-----------------------------------------------------------------------------
// Instruction cache line control
 
// Invalidate cache lines in the given range without writing to memory.
//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
 
//-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_CACHE_H
// End of hal_cache.h
/v2_0/include/hal_diag.h
0,0 → 1,79
#ifndef CYGONCE_HAL_DIAG_H
#define CYGONCE_HAL_DIAG_H
 
//=============================================================================
//
// hal_diag.h
//
// HAL Support for Kernel Diagnostic Routines
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
// Contributors:jskov, gthomas
// Date: 2001-07-12
// Purpose: HAL Support for Kernel Diagnostic Routines
// Description: Diagnostic routines for use during kernel development.
// Usage: #include <cyg/hal/hal_diag.h>
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h>
 
#include <cyg/hal/hal_if.h>
 
#define HAL_DIAG_INIT() hal_if_diag_init()
#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_)
#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_)
 
//-----------------------------------------------------------------------------
// LED
externC void hal_diag_led(int mask);
 
//-----------------------------------------------------------------------------
// delay
 
extern void hal_delay_us(cyg_int32 usecs);
#define HAL_DELAY_US(n) hal_delay_us(n);
 
//-----------------------------------------------------------------------------
// end of hal_diag.h
#endif // CYGONCE_HAL_DIAG_H
/v2_0/include/hal_platform_setup.h
0,0 → 1,122
#ifndef CYGONCE_HAL_PLATFORM_SETUP_H
#define CYGONCE_HAL_PLATFORM_SETUP_H
 
/*=============================================================================
//
// hal_platform_setup.h
//
// Platform specific support for HAL (assembly code)
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): gthomas
// Contributors:gthomas
// Date: 2001-07-12
// Purpose: AT91/EB40 platform specific support routines
// Description:
// Usage: #include <cyg/hal/hal_platform_setup.h>
//
//####DESCRIPTIONEND####
//
//===========================================================================*/
 
#include <cyg/hal/plf_io.h>
 
#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
 
.macro _setup
ldr r10,=_InitMemory // Initialize memory controller
movs r0,pc,lsr #20 // If ROM startup, PC < 0x100000
moveq r10,r10,lsl #12 // mask address to low 20 bits
moveq r10,r10,lsr #12
ldmia r10!,{r0-r9,r11-r12} // Table of initialization constants
#if defined(CYG_HAL_STARTUP_ROMRAM)
ldr r10,=0x0000FFFF
and r12,r12,r10
ldr r10,=0x01010000
orr r12,r12,r10
#endif
stmia r11!,{r0-r9} // Write to controller
mov pc,r12 // Change address space, break pipeline
_InitMemory:
.long 0x01002535 // 0x01000000, 16MB, 2 cycles added after transfer, 16-bit, 6 wait states
.long 0x02002121 // 0x02000000, 16MB, 0 cycles added after transfer, 16-bit, 1 wait state
.long 0x20000000 // unused
.long 0x30000000 // unused
.long 0x40000000 // unused
.long 0x50000000 // unused
.long 0x60000000 // unused
.long 0x70000000 // unused
.long 0x00000001 // REMAP commande
.long 0x00000006 // 7 memory regions, standard read
.long AT91_EBI // External Bus Interface address
.long 10f // address where to jump
10:
#if defined(CYG_HAL_STARTUP_ROMRAM)
ldr r0,=0x01010000 // Relocate FLASH/ROM to on-chip RAM
ldr r1,=0x02000000 // RAM base & length
ldr r2,=0x02010000
20: ldr r3,[r0],#4
str r3,[r1],#4
cmp r1,r2
bne 20b
ldr r0,=30f
mov pc,r0
30:
#endif
ldr r0,=AT91_PS // Power saving interface
ldr r1,=0xFFFFFFFF // Enable all peripheral [clocks]
str r1,[r0,#AT91_PS_PCER]
ldr r0,=AT91_PIO // Disable PIO (so peripherals can use bits)
ldr r1,=0x0070FE49 // UART, FIQ, EINT, Timer clocks
str r1,[r0,#AT91_PIO_PDR]
ldr r1,=0x000001B6 // LEDs
str r1,[r0,#AT91_PIO_OER]
str r1,[r0,#AT91_PIO_SODR]
.endm
 
#define CYGSEM_HAL_ROM_RESET_USES_JUMP
#define PLATFORM_SETUP1 _setup
#else
#define PLATFORM_SETUP1
#endif
 
//-----------------------------------------------------------------------------
// end of hal_platform_setup.h
#endif // CYGONCE_HAL_PLATFORM_SETUP_H
/v2_0/include/plf_io.h
0,0 → 1,396
#ifndef CYGONCE_HAL_PLF_IO_H
#define CYGONCE_HAL_PLF_IO_H
//=============================================================================
//
// plf_io.h
//
// Platform specific registers
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
// Contributors:jskov, gthomas
// Date: 2001-07-12
// Purpose: AT91/EB40 platform specific registers
// Description:
// Usage: #include <cyg/hal/plf_io.h>
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
// USART
 
#define AT91_USART0 0xFFFD0000
#define AT91_USART1 0xFFFCC000
 
#define AT91_US_CR 0x00 // Control register
#define AT91_US_CR_RxRESET (1<<2)
#define AT91_US_CR_TxRESET (1<<3)
#define AT91_US_CR_RxENAB (1<<4)
#define AT91_US_CR_RxDISAB (1<<5)
#define AT91_US_CR_TxENAB (1<<6)
#define AT91_US_CR_TxDISAB (1<<7)
#define AT91_US_CR_RSTATUS (1<<8)
#define AT91_US_MR 0x04 // Mode register
#define AT91_US_MR_CLOCK 4
#define AT91_US_MR_CLOCK_MCK (0<<AT91_US_MR_CLOCK)
#define AT91_US_MR_CLOCK_MCK8 (1<<AT91_US_MR_CLOCK)
#define AT91_US_MR_CLOCK_SCK (2<<AT91_US_MR_CLOCK)
#define AT91_US_MR_LENGTH 6
#define AT91_US_MR_LENGTH_5 (0<<AT91_US_MR_LENGTH)
#define AT91_US_MR_LENGTH_6 (1<<AT91_US_MR_LENGTH)
#define AT91_US_MR_LENGTH_7 (2<<AT91_US_MR_LENGTH)
#define AT91_US_MR_LENGTH_8 (3<<AT91_US_MR_LENGTH)
#define AT91_US_MR_SYNC 8
#define AT91_US_MR_SYNC_ASYNC (0<<AT91_US_MR_SYNC)
#define AT91_US_MR_SYNC_SYNC (1<<AT91_US_MR_SYNC)
#define AT91_US_MR_PARITY 9
#define AT91_US_MR_PARITY_EVEN (0<<AT91_US_MR_PARITY)
#define AT91_US_MR_PARITY_ODD (1<<AT91_US_MR_PARITY)
#define AT91_US_MR_PARITY_SPACE (2<<AT91_US_MR_PARITY)
#define AT91_US_MR_PARITY_MARK (3<<AT91_US_MR_PARITY)
#define AT91_US_MR_PARITY_NONE (4<<AT91_US_MR_PARITY)
#define AT91_US_MR_PARITY_MULTI (6<<AT91_US_MR_PARITY)
#define AT91_US_MR_STOP 12
#define AT91_US_MR_STOP_1 (0<<AT91_US_MR_STOP)
#define AT91_US_MR_STOP_1_5 (1<<AT91_US_MR_STOP)
#define AT91_US_MR_STOP_2 (2<<AT91_US_MR_STOP)
#define AT91_US_MR_MODE 14
#define AT91_US_MR_MODE_NORMAL (0<<AT91_US_MR_MODE)
#define AT91_US_MR_MODE_ECHO (1<<AT91_US_MR_MODE)
#define AT91_US_MR_MODE_LOCAL (2<<AT91_US_MR_MODE)
#define AT91_US_MR_MODE_REMOTE (3<<AT91_US_MR_MODE)
#define AT91_US_MR_MODE9 17
#define AT91_US_MR_CLKO 18
#define AT91_US_IER 0x08 // Interrupt enable register
#define AT91_US_IER_RxRDY (1<<0) // Receive data ready
#define AT91_US_IER_TxRDY (1<<1) // Transmitter ready
#define AT91_US_IER_RxBRK (1<<2) // Break received
#define AT91_US_IER_ENDRX (1<<3) // Rx end
#define AT91_US_IER_ENDTX (1<<4) // Tx end
#define AT91_US_IER_OVRE (1<<5) // Rx overflow
#define AT91_US_IER_FRAME (1<<6) // Rx framing error
#define AT91_US_IER_PARITY (1<<7) // Rx parity
#define AT91_US_IER_TIMEOUT (1<<8) // Rx timeout
#define AT91_US_IER_TxEMPTY (1<<9) // Tx empty
#define AT91_US_IDR 0x0C // Interrupt disable register
#define AT91_US_IMR 0x10 // Interrupt mask register
#define AT91_US_CSR 0x14 // Channel status register
#define AT91_US_CSR_RxRDY 0x01 // Receive data ready
#define AT91_US_CSR_TxRDY 0x02 // Transmit ready
#define AT91_US_RHR 0x18 // Receive holding register
#define AT91_US_THR 0x1C // Transmit holding register
#define AT91_US_BRG 0x20 // Baud rate generator
#define AT91_US_RTO 0x24 // Receive time out
#define AT91_US_TTG 0x28 // Transmit timer guard
 
#define AT91_US_BAUD(baud) (CYGNUM_HAL_ARM_AT91_CLOCK_SPEED/(16*(baud)))
 
// PIO
 
#define AT91_PIO 0xFFFF0000
 
#define AT91_PIO_PER 0x00 // PIO enable
#define AT91_PIO_PDR 0x04 // PIO disable
#define AT91_PIO_PSR 0x08 // PIO status
#define AT91_PIO_OER 0x10 // Output enable
#define AT91_PIO_ODR 0x14 // Output disable
#define AT91_PIO_OSR 0x1C // Output status register
#define AT91_PIO_IFER 0x20 // Input Filter enable
#define AT91_PIO_IFDR 0x24 // Input Filter disable
#define AT91_PIO_IFSR 0x28 // Input Filter status register
#define AT91_PIO_SODR 0x30 // Set out bits
#define AT91_PIO_CODR 0x34 // Clear out bits
#define AT91_PIO_ODSR 0x38 // Output data status register
#define AT91_PIO_IER 0x40 // Interrupt enable
#define AT91_PIO_IDR 0x44 // Interrupt disable
#define AT91_PIO_IMR 0x48 // Interrupt mask
#define AT91_PIO_ISR 0x4C // Interrupt status register
 
 
// Advanced Interrupt Controller (AIC)
 
#define AT91_AIC 0xFFFFF000
 
#define AT91_AIC_SMR0 ((0*4)+0x000)
#define AT91_AIC_SMR1 ((1*4)+0x000)
#define AT91_AIC_SMR2 ((2*4)+0x000)
#define AT91_AIC_SMR3 ((3*4)+0x000)
#define AT91_AIC_SMR4 ((4*4)+0x000)
#define AT91_AIC_SMR5 ((5*4)+0x000)
#define AT91_AIC_SMR6 ((6*4)+0x000)
#define AT91_AIC_SMR7 ((7*4)+0x000)
#define AT91_AIC_SMR8 ((8*4)+0x000)
#define AT91_AIC_SMR9 ((9*4)+0x000)
#define AT91_AIC_SMR10 ((10*4)+0x000)
#define AT91_AIC_SMR11 ((11*4)+0x000)
#define AT91_AIC_SMR12 ((12*4)+0x000)
#define AT91_AIC_SMR13 ((13*4)+0x000)
#define AT91_AIC_SMR14 ((14*4)+0x000)
#define AT91_AIC_SMR15 ((15*4)+0x000)
#define AT91_AIC_SMR16 ((16*4)+0x000)
#define AT91_AIC_SMR17 ((17*4)+0x000)
#define AT91_AIC_SMR18 ((18*4)+0x000)
#define AT91_AIC_SMR19 ((19*4)+0x000)
#define AT91_AIC_SMR20 ((20*4)+0x000)
#define AT91_AIC_SMR21 ((21*4)+0x000)
#define AT91_AIC_SMR22 ((22*4)+0x000)
#define AT91_AIC_SMR23 ((23*4)+0x000)
#define AT91_AIC_SMR24 ((24*4)+0x000)
#define AT91_AIC_SMR25 ((25*4)+0x000)
#define AT91_AIC_SMR26 ((26*4)+0x000)
#define AT91_AIC_SMR27 ((27*4)+0x000)
#define AT91_AIC_SMR28 ((28*4)+0x000)
#define AT91_AIC_SMR29 ((29*4)+0x000)
#define AT91_AIC_SMR30 ((30*4)+0x000)
#define AT91_AIC_SMR31 ((31*4)+0x000)
#define AT91_AIC_SMR_LEVEL_LOW (0<<5)
#define AT91_AIC_SMR_LEVEL_HI (2<<5)
#define AT91_AIC_SMR_EDGE_NEG (1<<5)
#define AT91_AIC_SMR_EDGE_POS (3<<5)
#define AT91_AIC_SMR_PRIORITY 0x07
#define AT91_AIC_SVR0 ((0*4)+0x080)
#define AT91_AIC_SVR1 ((1*4)+0x080)
#define AT91_AIC_SVR2 ((2*4)+0x080)
#define AT91_AIC_SVR3 ((3*4)+0x080)
#define AT91_AIC_SVR4 ((4*4)+0x080)
#define AT91_AIC_SVR5 ((5*4)+0x080)
#define AT91_AIC_SVR6 ((6*4)+0x080)
#define AT91_AIC_SVR7 ((7*4)+0x080)
#define AT91_AIC_SVR8 ((8*4)+0x080)
#define AT91_AIC_SVR9 ((9*4)+0x080)
#define AT91_AIC_SVR10 ((10*4)+0x080)
#define AT91_AIC_SVR11 ((11*4)+0x080)
#define AT91_AIC_SVR12 ((12*4)+0x080)
#define AT91_AIC_SVR13 ((13*4)+0x080)
#define AT91_AIC_SVR14 ((14*4)+0x080)
#define AT91_AIC_SVR15 ((15*4)+0x080)
#define AT91_AIC_SVR16 ((16*4)+0x080)
#define AT91_AIC_SVR17 ((17*4)+0x080)
#define AT91_AIC_SVR18 ((18*4)+0x080)
#define AT91_AIC_SVR19 ((19*4)+0x080)
#define AT91_AIC_SVR20 ((20*4)+0x080)
#define AT91_AIC_SVR21 ((21*4)+0x080)
#define AT91_AIC_SVR22 ((22*4)+0x080)
#define AT91_AIC_SVR23 ((23*4)+0x080)
#define AT91_AIC_SVR24 ((24*4)+0x080)
#define AT91_AIC_SVR25 ((25*4)+0x080)
#define AT91_AIC_SVR26 ((26*4)+0x080)
#define AT91_AIC_SVR27 ((27*4)+0x080)
#define AT91_AIC_SVR28 ((28*4)+0x080)
#define AT91_AIC_SVR29 ((29*4)+0x080)
#define AT91_AIC_SVR30 ((30*4)+0x080)
#define AT91_AIC_SVR31 ((31*4)+0x080)
#define AT91_AIC_IVR 0x100
#define AT91_AIC_FVR 0x104
#define AT91_AIC_ISR 0x108
#define AT91_AIC_IPR 0x10C
#define AT91_AIC_IMR 0x110
#define AT91_AIC_CISR 0x114
#define AT91_AIC_IECR 0x120
#define AT91_AIC_IDCR 0x124
#define AT91_AIC_ICCR 0x128
#define AT91_AIC_ISCR 0x12C
#define AT91_AIC_EOI 0x130
#define AT91_AIC_SVR 0x134
 
// Timer / counter
 
#define AT91_TC 0xFFFE0000
#define AT91_TC_TC0 0x00
#define AT91_TC_CCR 0x00
#define AT91_TC_CCR_CLKEN 0x01
#define AT91_TC_CCR_CLKDIS 0x02
#define AT91_TC_CCR_TRIG 0x04
#define AT91_TC_CMR 0x04
// Capture mode definitions
#define AT91_TC_CMR_CLKS 0
#define AT91_TC_CMR_CLKS_MCK2 (0<<0)
#define AT91_TC_CMR_CLKS_MCK8 (1<<0)
#define AT91_TC_CMR_CLKS_MCK32 (2<<0)
#define AT91_TC_CMR_CLKS_MCK128 (3<<0)
#define AT91_TC_CMR_CLKS_MCK1024 (4<<0)
#define AT91_TC_CMR_CLKS_XC0 (5<<0)
#define AT91_TC_CMR_CLKS_XC1 (6<<0)
#define AT91_TC_CMR_CLKS_XC2 (7<<0)
#define AT91_TC_CMR_CLKI (1<<3)
#define AT91_TC_CMR_BURST_NONE (0<<4)
#define AT91_TC_CMR_BURST_XC0 (1<<4)
#define AT91_TC_CMR_BURST_XC1 (2<<4)
#define AT91_TC_CMR_BURST_XC2 (3<<4)
#define AT91_TC_CMR_LDBSTOP (1<<6)
#define AT91_TC_CMR_LDBDIS (1<<7)
#define AT91_TC_CMR_TRIG_NONE (0<<8)
#define AT91_TC_CMR_TRIG_NEG (1<<8)
#define AT91_TC_CMR_TRIG_POS (2<<8)
#define AT91_TC_CMR_TRIG_BOTH (3<<8)
#define AT91_TC_CMR_EXT_TRIG_TIOB (0<<10)
#define AT91_TC_CMR_EXT_TRIG_TIOA (1<<10)
#define AT91_TC_CMR_CPCTRG (1<<14)
#define AT91_TC_CMR_LDRA_NONE (0<<16)
#define AT91_TC_CMR_LDRA_TIOA_NEG (1<<16)
#define AT91_TC_CMR_LDRA_TIOA_POS (2<<16)
#define AT91_TC_CMR_LDRA_TIOA_BOTH (3<<16)
#define AT91_TC_CMR_LDRB_NONE (0<<16)
#define AT91_TC_CMR_LDRB_TIOA_NEG (1<<16)
#define AT91_TC_CMR_LDRB_TIOA_POS (2<<16)
#define AT91_TC_CMR_LDRB_TIOA_BOTH (3<<16)
// Waveform mode definitions [missing]
#define AT91_TC_CV 0x10
#define AT91_TC_RA 0x14
#define AT91_TC_RB 0x18
#define AT91_TC_RC 0x1C
#define AT91_TC_SR 0x20
#define AT91_TC_SR_COVF (1<<0) // Counter overrun
#define AT91_TC_SR_LOVR (1<<1) // Load overrun
#define AT91_TC_SR_CPA (1<<2) // RA compare
#define AT91_TC_SR_CPB (1<<3) // RB compare
#define AT91_TC_SR_CPC (1<<4) // RC compare
#define AT91_TC_SR_LDRA (1<<5) // Load A status
#define AT91_TC_SR_LDRB (1<<6) // Load B status
#define AT91_TC_SR_EXT (1<<7) // External trigger
#define AT91_TC_SR_CLKSTA (1<<16) // Clock enable/disable status
#define AT91_TC_SR_MTIOA (1<<17) // TIOA mirror
#define AT91_TC_SR_MTIOB (1<<18) // TIOB mirror
#define AT91_TC_IER 0x24
#define AT91_TC_IER_COVF (1<<0) // Counter overrun
#define AT91_TC_IER_LOVR (1<<1) // Load overrun
#define AT91_TC_IER_CPA (1<<2) // RA compare
#define AT91_TC_IER_CPB (1<<3) // RB compare
#define AT91_TC_IER_CPC (1<<4) // RC compare
#define AT91_TC_IER_LDRA (1<<5) // Load A status
#define AT91_TC_IER_LDRB (1<<6) // Load B status
#define AT91_TC_IER_EXT (1<<7) // External trigger
#define AT91_TC_IDR 0x28
#define AT91_TC_IMR 0x2C
#define AT91_TC_TC1 0x40
#define AT91_TC_TC2 0x80
#define AT91_TC_BCR 0xC0
#define AT91_TC_BCR_SYNC 0x01
#define AT91_TC_BMR 0xC4
 
// External Bus Interface
 
#define AT91_EBI 0xFFE00000 // Base
 
#define AT91_EBI_CSR0 0x00 // Chip selects 0 - 7
#define AT91_EBI_CSR1 0x04
#define AT91_EBI_CSR2 0x08
#define AT91_EBI_CSR3 0x0C
#define AT91_EBI_CSR4 0x10
#define AT91_EBI_CSR5 0x14
#define AT91_EBI_CSR6 0x18
#define AT91_EBI_CSR7 0x1C
 
#define AT91_EBI_RCR 0x20 // Reset control
#define AT91_EBI_MCR 0x24 // Memory control
 
#define AT91_EBI_CSEN (1<<13) // Chip Select enable
#define AT91_EBI_BAT_BYTE_WRITE (0<<12) // Byte write access
#define AT91_EBI_BAT_BYTE_SELECT (1<<12) // Byte select access type
#define AT91_EBI_TDF0 (0<<9) // 0 cycles of data float time
#define AT91_EBI_TDF1 (1<<9) // 1
#define AT91_EBI_TDF2 (2<<9) // 2, etc
#define AT91_EBI_TDF3 (3<<9) //
#define AT91_EBI_TDF4 (4<<9) //
#define AT91_EBI_TDF5 (5<<9) //
#define AT91_EBI_TDF6 (6<<9) //
#define AT91_EBI_TDF7 (7<<9) //
 
#define AT91_EBI_PAGES_1M (0<<7) // 1MByte page size
#define AT91_EBI_PAGES_4M (1<<7) // 4MByte page size
#define AT91_EBI_PAGES_16M (2<<7) // 16MByte page size
#define AT91_EBI_PAGES_64M (3<<7) // 64MByte page size
 
#define AT91_EBI_WSE (1<<5) // Wait State enable
 
#define AT91_EBI_NWS_1 (0<<2) // 1 wait state
#define AT91_EBI_NWS_2 (1<<2) // 1 wait state
#define AT91_EBI_NWS_3 (2<<2) // 1 wait state
#define AT91_EBI_NWS_4 (3<<2) // 1 wait state
#define AT91_EBI_NWS_5 (4<<2) // 1 wait state
#define AT91_EBI_NWS_6 (5<<2) // 1 wait state
#define AT91_EBI_NWS_7 (6<<2) // 1 wait state
#define AT91_EBI_NWS_8 (7<<2) // 1 wait state
 
#define AT91_EBI_DBW_8 (2<<0) // 8-bit data bus width
#define AT91_EBI_DBW_16 (1<<0) // 16-bit data bus width
 
#define AT91_EBI_RCB (1<<0) // Remap command bit
 
#define AT91_EBI_ALE_16M (0<<0) // Address line enable: A20,A21,A22,A23
#define AT91_EBI_ALE_8M (4<<0) // " " A20,A21,A22 CS4
#define AT91_EBI_ALE_4M (5<<0) // " " A20,A21 CS4,CS5
#define AT91_EBI_ALE_2M (6<<0) // " " A20 CS4,CS5,CS6
#define AT91_EBI_ALE_1M (7<<0) // " " CS4,CS5,CS6,CS7
 
#define AT91_EBI_DRP_STANDARD (0<<4) // Standard data read protocol
#define AT91_EBI_DRP_EARLY (1<<4) // Early data read protocol
 
 
 
// Power Savings control
 
#define AT91_PS 0xFFFF4000
#define AT91_PS_CR 0x000 // Control
#define AT91_PS_PCER 0x004 // Peripheral clock enable
#define AT91_PS_PCDR 0x004 // Peripheral clock disable
#define AT91_PS_PCSR 0x004 // Peripheral clock status
 
// Watchdog
 
#define AT91_WD 0xFFFF8000
#define AT91_WD_OMR 0x00
#define AT91_WD_OMR_WDEN 0x00000001
#define AT91_WD_OMR_RSTEN 0x00000002
#define AT91_WD_OMR_IRQEN 0x00000004
#define AT91_WD_OMR_EXTEN 0x00000008
#define AT91_WD_OMR_OKEY (0x00000234 << 4)
#define AT91_WD_CMR 0x04
#define AT91_WD_CMR_WDCLKS 0x00000003
#define AT91_WD_CMR_HPCV 0x0000003C
#define AT91_WD_CMR_CKEY (0x0000006E << 7)
#define AT91_WD_CR 0x08
#define AT91_WD_CR_RSTKEY 0x0000C071
#define AT91_WD_SR 0x0C
#define AT91_WD_SR_WDOVF 0x00000001
 
 
//-----------------------------------------------------------------------------
// end of plf_io.h
#endif // CYGONCE_HAL_PLF_IO_H
/v2_0/ChangeLog
0,0 → 1,154
2002-12-07 Gary Thomas <gthomas@ecoscentric.com>
 
* misc/redboot_ROMRAM.ecm:
* misc/redboot_ROM.ecm:
* misc/redboot_RAM.ecm: Suppress building Linux 'exec' command
(which makes little sense on this platform).
 
2002-09-23 Gary Thomas <gthomas@ecoscentric.com> on behalf of
2002-11-23 Scott Dattalo <scott@dattalo.com>
 
* include/plf_io.h: Add some missing register definitions.
 
2002-05-28 Thomas Koeller <Thomas.Koeller@baslerweb.com>
 
* include/plf_io.h: Add watchdog definitions.
 
2002-05-08 Gary Thomas <gthomas@redhat.com>
 
* misc/redboot_ROMRAM.ecm:
* misc/redboot_ROM.ecm: Disable 'fconfig' since the FLASH is too small.
 
2001-08-17 George Hampton <george.hampton@intel.com>
2001-08-17 Gary Thomas <gthomas@redhat.com>
 
* include/hal_platform_ints.h (CYGNUM_HAL_ISR_COUNT): PR 22864
Don't adjust by "min" value if not doing translations.
2001-07-26 Gary Thomas <gthomas@redhat.com>
 
* src/at91_misc.c (hal_clock_initialize):
* cdl/hal_arm_at91.cdl: Increase system clock (RTC) to run at 1MHz for
better timing resolution. CAUTION! this means that the system clock tick
can never be more than 64ms.
 
2001-07-23 Gary Thomas <gthomas@redhat.com>
 
* include/pkgconf/mlt_arm_at91_eb40_romram.mlt:
* include/pkgconf/mlt_arm_at91_eb40_romram.ldi:
* include/pkgconf/mlt_arm_at91_eb40_romram.h:
* include/pkgconf/mlt_arm_at91_eb40_ram.mlt:
* include/pkgconf/mlt_arm_at91_eb40_ram.ldi:
* include/pkgconf/mlt_arm_at91_eb40_ram.h:
* cdl/hal_arm_at91.cdl: Fix MLT files (names, layout).
 
2001-07-20 Gary Thomas <gthomas@redhat.com>
 
* include/plf_io.h: Add UART interrupt definitions.
 
* src/hal_diag.c (cyg_hal_plf_serial_control): Enable ^C support.
 
* src/at91_misc.c (hal_clock_initialize): Add clock/rtc implementation.
 
* include/pkgconf/mlt_arm_at91_eb40_romram.ldi:
Replace missing 'fixed vectors'.
 
2001-07-19 Gary Thomas <gthomas@redhat.com>
 
* misc/redboot_ROMRAM.ecm: New exported config.
 
* include/pkgconf/mlt_arm_at91_eb40_romram.ldi:
* include/pkgconf/mlt_arm_at91_eb40_ram.mlt:
* include/pkgconf/mlt_arm_at91_eb40_ram.ldi:
* include/hal_platform_setup.h: Fix ROMRAM startup mode. Note: I
can't get the onboard SRAM at 0x00100000 to work, so for now, this
will just have to go in low external RAM. Thus the change for the
RAM base address in startup=RAM mode.
 
* src/hal_diag.c (cyg_hal_plf_serial_getc_timeout): Remove debug code.
 
* src/at91_misc.c (set_leds): LEDs are on D4/D2/D1.
 
* misc/redboot_ROM.ecm:
* misc/redboot_RAM.ecm: Exported configurations.
 
* include/pkgconf/mlt_arm_at91_eb40_romram.mlt:
* include/pkgconf/mlt_arm_at91_eb40_romram.ldi:
* include/pkgconf/mlt_arm_at91_eb40_romram.h: New startup type.
* include/pkgconf/mlt_arm_at91_eb40_rom.h: Fix heap layout.
 
* include/pkgconf/mlt_arm_at91_eb40_ram.mlt:
* include/pkgconf/mlt_arm_at91_eb40_ram.ldi:
* include/pkgconf/mlt_arm_at91_eb40_ram.h:
Fix heap layout. Move RAM load address to leave room for RedBoot/GDB.
 
* include/plf_io.h: Add definitions for PIO, EBI and PS.
 
* include/hal_platform_setup.h: ROM startup mode now works.
First attempt at ROMRAM startup - not yet working.
 
* cdl/hal_arm_at91.cdl: Add ROMRAM startup mode.
 
2001-07-18 Gary Thomas <gthomas@redhat.com>
 
* src/hal_diag.c: More complete initialization.
 
* src/at91_misc.c: Support interrupt controller, delay_us().
 
* include/plf_io.h: Add interrupt controller, timer definitions.
 
* cdl/hal_arm_at91.cdl: Fix clock speed, number I/O channels.
 
2001-07-16 Gary Thomas <gthomas@redhat.com>
 
* src/hal_diag.c:
* src/at91_misc.c:
* include/pkgconf/mlt_arm_at91_eb40_rom.mlt:
* include/pkgconf/mlt_arm_at91_eb40_rom.ldi:
* include/pkgconf/mlt_arm_at91_eb40_rom.h:
* include/pkgconf/mlt_arm_at91_eb40_ram.mlt:
* include/pkgconf/mlt_arm_at91_eb40_ram.ldi:
* include/pkgconf/mlt_arm_at91_eb40_ram.h:
* include/plf_stub.h:
* include/plf_io.h:
* include/hal_platform_setup.h:
* include/hal_platform_ints.h:
* include/hal_diag.h:
* include/hal_cache.h:
* cdl/hal_arm_at91.cdl: New port - cloned from E7T.
 
//===========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//===========================================================================
/v2_0/src/hal_diag.c
0,0 → 1,324
/*=============================================================================
//
// hal_diag.c
//
// HAL diagnostic output code
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
// Contributors:jskov, gthomas
// Date: 2001-07-12
// Purpose: HAL diagnostic output
// Description: Implementations of HAL diagnostic output support.
//
//####DESCRIPTIONEND####
//
//===========================================================================*/
 
#include <pkgconf/hal.h>
#include CYGBLD_HAL_PLATFORM_H
 
#include <cyg/infra/cyg_type.h> // base types
 
#include <cyg/hal/hal_arch.h> // SAVE/RESTORE GP macros
#include <cyg/hal/hal_io.h> // IO macros
#include <cyg/hal/hal_if.h> // interface API
#include <cyg/hal/hal_intr.h> // HAL_ENABLE/MASK/UNMASK_INTERRUPTS
#include <cyg/hal/hal_misc.h> // Helper functions
#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED
 
#include <cyg/hal/plf_io.h> // USART registers
 
//-----------------------------------------------------------------------------
typedef struct {
cyg_uint8* base;
cyg_int32 msec_timeout;
int isr_vector;
} channel_data_t;
 
//-----------------------------------------------------------------------------
 
static void
cyg_hal_plf_serial_init_channel(void* __ch_data)
{
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
 
// Reset device
HAL_WRITE_UINT32(base+AT91_US_CR, AT91_US_CR_RxRESET | AT91_US_CR_TxRESET);
 
// 8-1-no parity.
HAL_WRITE_UINT32(base+AT91_US_MR,
AT91_US_MR_CLOCK_MCK | AT91_US_MR_LENGTH_8 |
AT91_US_MR_PARITY_NONE | AT91_US_MR_STOP_1);
 
HAL_WRITE_UINT32(base+AT91_US_BRG, AT91_US_BAUD(CYGNUM_HAL_VIRTUAL_VECTOR_CHANNELS_DEFAULT_BAUD));
 
// Enable RX and TX
HAL_WRITE_UINT32(base+AT91_US_CR, AT91_US_CR_RxENAB | AT91_US_CR_TxENAB);
}
 
void
cyg_hal_plf_serial_putc(void *__ch_data, char c)
{
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
cyg_uint32 status, ch;
CYGARC_HAL_SAVE_GP();
 
do {
HAL_READ_UINT32(base+AT91_US_CSR, status);
} while ((status & AT91_US_CSR_TxRDY) == 0);
 
ch = (cyg_uint32)c;
HAL_WRITE_UINT32(base+AT91_US_THR, ch);
 
CYGARC_HAL_RESTORE_GP();
}
 
static cyg_bool
cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
{
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_uint8* base = chan->base;
cyg_uint32 stat;
cyg_uint32 c;
 
HAL_READ_UINT32(base+AT91_US_CSR, stat);
if ((stat & AT91_US_CSR_RxRDY) == 0)
return false;
 
HAL_READ_UINT32(base+AT91_US_RHR, c);
*ch = (cyg_uint8)(c & 0xff);
 
return true;
}
 
cyg_uint8
cyg_hal_plf_serial_getc(void* __ch_data)
{
cyg_uint8 ch;
CYGARC_HAL_SAVE_GP();
 
while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
 
CYGARC_HAL_RESTORE_GP();
return ch;
}
 
static void
cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
cyg_uint32 __len)
{
CYGARC_HAL_SAVE_GP();
 
while(__len-- > 0)
cyg_hal_plf_serial_putc(__ch_data, *__buf++);
 
CYGARC_HAL_RESTORE_GP();
}
 
static void
cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
{
CYGARC_HAL_SAVE_GP();
 
while(__len-- > 0)
*__buf++ = cyg_hal_plf_serial_getc(__ch_data);
 
CYGARC_HAL_RESTORE_GP();
}
 
cyg_bool
cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
{
int delay_count;
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_bool res;
CYGARC_HAL_SAVE_GP();
 
delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
 
for(;;) {
res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
if (res || 0 == delay_count--)
break;
CYGACC_CALL_IF_DELAY_US(100);
}
 
CYGARC_HAL_RESTORE_GP();
return res;
}
 
static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
int ret = 0;
CYGARC_HAL_SAVE_GP();
 
switch (__func) {
case __COMMCTL_IRQ_ENABLE:
irq_state = 1;
HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
HAL_INTERRUPT_UNMASK(chan->isr_vector);
HAL_WRITE_UINT32(base+AT91_US_IER, AT91_US_IER_RxRDY);
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
HAL_INTERRUPT_MASK(chan->isr_vector);
HAL_WRITE_UINT32(base+AT91_US_IDR, AT91_US_IER_RxRDY);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
 
va_start(ap, __func);
 
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
 
va_end(ap);
}
default:
break;
}
CYGARC_HAL_RESTORE_GP();
return ret;
}
 
static int
cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
int res = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_uint32 c;
cyg_uint8 ch;
cyg_uint32 stat;
CYGARC_HAL_SAVE_GP();
 
*__ctrlc = 0;
HAL_READ_UINT32(chan->base+AT91_US_CSR, stat);
if ( (stat & AT91_US_CSR_RxRDY) != 0 ) {
 
HAL_READ_UINT32(chan->base+AT91_US_RHR, c);
ch = (cyg_uint8)(c & 0xff);
if( cyg_hal_is_break( &ch , 1 ) )
*__ctrlc = 1;
 
res = CYG_ISR_HANDLED;
}
 
HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
 
CYGARC_HAL_RESTORE_GP();
return res;
}
 
static channel_data_t at91_ser_channels[2] = {
{ (cyg_uint8*)AT91_USART0, 1000, CYGNUM_HAL_INTERRUPT_USART0},
{ (cyg_uint8*)AT91_USART1, 1000, CYGNUM_HAL_INTERRUPT_USART1}
};
 
static void
cyg_hal_plf_serial_init(void)
{
hal_virtual_comm_table_t* comm;
int cur;
 
cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
 
// Init channels
cyg_hal_plf_serial_init_channel(&at91_ser_channels[0]);
#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1
cyg_hal_plf_serial_init_channel(&at91_ser_channels[1]);
#endif
 
// Setup procs in the vector table
 
// Set channel 0
CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &at91_ser_channels[0]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
 
#if CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS > 1
// Set channel 1
CYGACC_CALL_IF_SET_CONSOLE_COMM(1);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &at91_ser_channels[1]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
#endif
 
// Restore original console
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
}
 
void
cyg_hal_plf_comms_init(void)
{
static int initialized = 0;
 
if (initialized)
return;
 
initialized = 1;
 
cyg_hal_plf_serial_init();
}
 
//-----------------------------------------------------------------------------
// End of hal_diag.c
/v2_0/src/at91_misc.c
0,0 → 1,286
//==========================================================================
//
// at91_misc.c
//
// HAL misc board support code for Atmel AT91/EB40
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): gthomas
// Contributors: gthomas, jskov
// Date: 2001-07-12
// Purpose: HAL board support
// Description: Implementations of HAL board interfaces
//
//####DESCRIPTIONEND####
//
//========================================================================*/
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h> // base types
#include <cyg/infra/cyg_trac.h> // tracing macros
#include <cyg/infra/cyg_ass.h> // assertion macros
 
#include <cyg/hal/hal_io.h> // IO macros
#include <cyg/hal/hal_arch.h> // Register state info
#include <cyg/hal/hal_diag.h>
#include <cyg/hal/hal_intr.h> // necessary?
#include <cyg/hal/hal_cache.h>
#include <cyg/hal/hal_if.h> // calling interface
#include <cyg/hal/hal_misc.h> // helper functions
#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
#include <cyg/hal/drv_api.h> // HAL ISR support
#endif
#include <cyg/hal/plf_io.h> // platform registers
 
static cyg_uint32 _period;
 
void hal_clock_initialize(cyg_uint32 period)
{
CYG_ADDRESS timer = AT91_TC+AT91_TC_TC0;
 
CYG_ASSERT(period < 0x10000, "Invalid clock period");
 
// Disable counter
HAL_WRITE_UINT32(timer+AT91_TC_CCR, AT91_TC_CCR_CLKDIS);
 
// Set registers
HAL_WRITE_UINT32(timer+AT91_TC_CMR, AT91_TC_CMR_CPCTRG | // Reset counter on CPC
AT91_TC_CMR_CLKS_MCK32); // 1 MHz
HAL_WRITE_UINT32(timer+AT91_TC_RC, period);
 
// Start timer
HAL_WRITE_UINT32(timer+AT91_TC_CCR, AT91_TC_CCR_TRIG | AT91_TC_CCR_CLKEN);
 
// Enable timer 0 interrupt
HAL_WRITE_UINT32(timer+AT91_TC_IER, AT91_TC_IER_CPC);
}
 
void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
{
CYG_ADDRESS timer = AT91_TC+AT91_TC_TC0;
cyg_uint32 sr;
 
CYG_ASSERT(period < 0x10000, "Invalid clock period");
 
HAL_READ_UINT32(timer+AT91_TC_SR, sr); // Clear interrupt
HAL_INTERRUPT_ACKNOWLEDGE(CYGNUM_HAL_INTERRUPT_RTC);
 
if (period != _period) {
hal_clock_initialize(period);
}
_period = period;
 
}
 
void hal_clock_read(cyg_uint32 *pvalue)
{
CYG_ADDRESS timer = AT91_TC+AT91_TC_TC0;
cyg_uint32 val;
 
HAL_READ_UINT32(timer+AT91_TC_CV, val);
*pvalue = val;
}
 
// -------------------------------------------------------------------------
//
// Delay for some number of micro-seconds
// Use timer #2 in 1MHz mode
//
void hal_delay_us(cyg_int32 usecs)
{
CYG_ADDRESS timer = AT91_TC+AT91_TC_TC2;
cyg_uint32 stat;
 
// Disable counter
HAL_WRITE_UINT32(timer+AT91_TC_CCR, AT91_TC_CCR_CLKDIS);
 
// Set registers
HAL_WRITE_UINT32(timer+AT91_TC_CMR, AT91_TC_CMR_CLKS_MCK32); // 1MHz
HAL_WRITE_UINT32(timer+AT91_TC_RA, 0);
HAL_WRITE_UINT32(timer+AT91_TC_RC, usecs);
 
// Start timer
HAL_WRITE_UINT32(timer+AT91_TC_CCR, AT91_TC_CCR_TRIG | AT91_TC_CCR_CLKEN);
 
// Wait for the compare
do {
HAL_READ_UINT32(timer+AT91_TC_SR, stat);
} while ((stat & AT91_TC_SR_CPC) == 0);
}
 
// -------------------------------------------------------------------------
// Hardware init
void hal_hardware_init(void)
{
// Set up eCos/ROM interfaces
hal_if_init();
 
// Reset all interrupts
HAL_WRITE_UINT32(AT91_AIC+AT91_AIC_IDCR, 0xFFFFFFFF);
 
// Make sure interrupt controller is happy
HAL_WRITE_UINT32(AT91_AIC+AT91_AIC_EOI, 0xFFFFFFFF);
}
 
//
// This routine is called to respond to a hardware interrupt (IRQ). It
// should interrogate the hardware and return the IRQ vector number.
 
int hal_IRQ_handler(void)
{
cyg_uint32 irq_num;
cyg_uint32 ipr, imr;
 
HAL_READ_UINT32(AT91_AIC+AT91_AIC_IPR, ipr);
HAL_READ_UINT32(AT91_AIC+AT91_AIC_IMR, imr);
ipr &= imr;
for (irq_num = 0; irq_num < 19; irq_num++) {
if (ipr & (1 << irq_num)) {
break;
}
}
 
return irq_num;
}
 
//
// Interrupt control
//
 
void hal_interrupt_mask(int vector)
{
CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
 
HAL_WRITE_UINT32(AT91_AIC+AT91_AIC_IDCR, (1<<vector));
}
 
void hal_interrupt_unmask(int vector)
{
CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
 
HAL_WRITE_UINT32(AT91_AIC+AT91_AIC_IECR, (1<<vector));
}
 
void hal_interrupt_acknowledge(int vector)
{
CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
 
HAL_WRITE_UINT32(AT91_AIC+AT91_AIC_ICCR, (1<<vector));
 
// FIXME - This isn't 100% correct
HAL_WRITE_UINT32(AT91_AIC+AT91_AIC_EOI, 0xFFFFFFFF);
}
 
void hal_interrupt_configure(int vector, int level, int up)
{
cyg_uint32 mode;
 
CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
 
if (level) {
if (up) {
mode = AT91_AIC_SMR_LEVEL_HI;
} else {
mode = AT91_AIC_SMR_LEVEL_LOW;
}
} else {
if (up) {
mode = AT91_AIC_SMR_EDGE_POS;
} else {
mode = AT91_AIC_SMR_EDGE_NEG;
}
}
mode |= 7; // Default priority
HAL_WRITE_UINT32(AT91_AIC+(AT91_AIC_SMR0+(vector*4)), mode);
}
 
void hal_interrupt_set_level(int vector, int level)
{
cyg_uint32 mode;
 
CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
CYG_ASSERT(level >= 1 && level <= 7, "Invalid level");
 
HAL_READ_UINT32(AT91_AIC+(AT91_AIC_SMR0+(vector*4)), mode);
mode = (mode & ~AT91_AIC_SMR_PRIORITY) | level;
HAL_WRITE_UINT32(AT91_AIC+(AT91_AIC_SMR0+(vector*4)), mode);
}
 
void hal_show_IRQ(int vector, int data, int handler)
{
// UNDEFINED(__FUNCTION__); // FIXME
}
 
//
// Diagnostic LEDs - there are three colored LEDs which can be used
// to send a simple diagnostic value (8 bits)
//
 
void
_at91_led(int val)
{
int i, to;
 
HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_CODR, 0x06); // DATA+CLOCK LEDs off
for (to = 0; to < 0x200000; to++) ;
for (i = 0; i < 8; i++) {
HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_SODR, ((val>>(7-i)) & 0x01)<<2); // DATA LED
HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_SODR, 0x02); // CLOCK LED on
for (to = 0; to < 0x80000; to++) ;
HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_CODR, 0x02); // CLOCK LED off
for (to = 0; to < 0x40000; to++) ;
HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_CODR, 0x04); // DATA LED off
}
}
 
void
set_leds(int val)
{
HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_CODR, 0x16);
HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_SODR, val);
}
 
 
//--------------------------------------------------------------------------
// EOF hal_misc.c
/v2_0/misc/redboot_RAM.ecm
0,0 → 1,58
cdl_savefile_version 1;
cdl_savefile_command cdl_savefile_version {};
cdl_savefile_command cdl_savefile_command {};
cdl_savefile_command cdl_configuration { description hardware template package };
cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
 
cdl_configuration eCos {
description "" ;
hardware at91 ;
template redboot ;
package -hardware CYGPKG_HAL_ARM v2_0 ;
package -hardware CYGPKG_HAL_ARM_AT91 v2_0 ;
package -hardware CYGPKG_DEVS_FLASH_AT91 v2_0 ;
package -template CYGPKG_HAL v2_0 ;
package -template CYGPKG_INFRA v2_0 ;
package -template CYGPKG_REDBOOT v2_0 ;
package CYGPKG_IO_FLASH v2_0 ;
};
 
cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
user_value 6144
};
 
cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
user_value 0
};
 
cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
inferred_value 0
};
 
cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
inferred_value 1
};
 
cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
inferred_value 0 0
};
 
cdl_component CYGBLD_BUILD_REDBOOT {
user_value 1
};
 
cdl_option CYGOPT_REDBOOT_FIS {
user_value 0
};
 
cdl_component CYGSEM_REDBOOT_FLASH_CONFIG {
user_value 0
};
 
cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC {
user_value 0
};
 
/v2_0/misc/redboot_ROM.ecm
0,0 → 1,66
cdl_savefile_version 1;
cdl_savefile_command cdl_savefile_version {};
cdl_savefile_command cdl_savefile_command {};
cdl_savefile_command cdl_configuration { description hardware template package };
cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
 
cdl_configuration eCos {
description "" ;
hardware at91 ;
template redboot ;
package -hardware CYGPKG_HAL_ARM v2_0 ;
package -hardware CYGPKG_HAL_ARM_AT91 v2_0 ;
package -hardware CYGPKG_DEVS_FLASH_AT91 v2_0 ;
package -template CYGPKG_HAL v2_0 ;
package -template CYGPKG_INFRA v2_0 ;
package -template CYGPKG_REDBOOT v2_0 ;
package CYGPKG_IO_FLASH v2_0 ;
};
 
cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
user_value 6144
};
 
cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
user_value 0
};
 
cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
inferred_value 0
};
 
cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
inferred_value 1
};
 
cdl_option CYGSEM_HAL_ROM_MONITOR {
inferred_value 1
};
 
cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
inferred_value 0 0
};
 
cdl_component CYG_HAL_STARTUP {
user_value ROM
};
 
cdl_component CYGBLD_BUILD_REDBOOT {
user_value 1
};
 
cdl_option CYGOPT_REDBOOT_FIS {
user_value 0
};
 
cdl_component CYGSEM_REDBOOT_FLASH_CONFIG {
user_value 0
};
 
 
cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC {
user_value 0
};
/v2_0/misc/redboot_ROMRAM.ecm
0,0 → 1,69
cdl_savefile_version 1;
cdl_savefile_command cdl_savefile_version {};
cdl_savefile_command cdl_savefile_command {};
cdl_savefile_command cdl_configuration { description hardware template package };
cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
 
cdl_configuration eCos {
description "" ;
hardware at91 ;
template redboot ;
package -hardware CYGPKG_HAL_ARM v2_0 ;
package -hardware CYGPKG_HAL_ARM_AT91 v2_0 ;
package -hardware CYGPKG_DEVS_FLASH_AT91 v2_0 ;
package -template CYGPKG_HAL v2_0 ;
package -template CYGPKG_INFRA v2_0 ;
package -template CYGPKG_REDBOOT v2_0 ;
package CYGPKG_IO_FLASH v2_0 ;
};
 
cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
user_value 6144
};
 
cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
user_value 0
};
 
cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
inferred_value 0
};
 
cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
inferred_value 1
};
 
cdl_option CYGSEM_HAL_ROM_MONITOR {
user_value 1
};
 
cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
inferred_value 0 0
};
 
cdl_component CYG_HAL_STARTUP {
user_value ROMRAM
};
 
cdl_component CYGBLD_BUILD_REDBOOT {
user_value 1
};
 
cdl_option CYGOPT_REDBOOT_FIS {
user_value 0
};
 
cdl_component CYGSEM_REDBOOT_FLASH_CONFIG {
user_value 0
};
 
cdl_option CYGNUM_FLASH_WORKSPACE_SIZE {
user_value 0x00000200
};
 
cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC {
user_value 0
};

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