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    /openrisc/trunk/rtos/ecos-2.0/packages/hal/arm/e7t/v2_0
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  •

Rev 27 → Rev 174

/cdl/hal_arm_e7t.cdl
0,0 → 1,304
# ====================================================================
#
# hal_arm_e7t.cdl
#
# Evaluator7T (AEB2) board HAL package configuration data
#
# ====================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
# ====================================================================
######DESCRIPTIONBEGIN####
#
# Author(s): gthomas
# Contributors: gthomas, jskov
# Date: 2001-03-16
#
#####DESCRIPTIONEND####
#
# ====================================================================
 
cdl_package CYGPKG_HAL_ARM_E7T {
display "ARM Evaluator7T (AEB2) evaluation board"
parent CYGPKG_HAL_ARM
define_header hal_arm_e7t.h
include_dir cyg/hal
hardware
description "
The E7T HAL package provides the support needed to run
eCos on an ARM E7T eval board."
 
compile hal_diag.c e7t_misc.c
 
implements CYGINT_HAL_DEBUG_GDB_STUBS
implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
implements CYGINT_HAL_ARM_ARCH_ARM7
implements CYGINT_HAL_ARM_THUMB_ARCH
 
define_proc {
puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_arm.h>"
puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_e7t.h>"
}
 
cdl_component CYG_HAL_STARTUP {
display "Startup type"
flavor data
default_value {"RAM"}
legal_values {"RAM" "ROM"}
no_define
define -file system.h CYG_HAL_STARTUP
description "
When targetting the E7T eval board it is possible to build
the system for either RAM bootstrap or ROM bootstrap(s). Select
'ram' when building programs to load into RAM using onboard
debug software such as Angel or eCos GDB stubs. Select 'rom'
when building a stand-alone application which will be put
into ROM."
}
 
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
display "Number of communication channels on the board"
flavor data
calculated 2
}
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
display "Debug serial port"
active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
flavor data
legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
default_value 1
description "
The E7T board has two serial ports. This option
chooses which port will be used to connect to a host
running GDB."
}
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
display "Diagnostic serial port"
active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
flavor data
legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
default_value 1
description "
The E7T board has two serial ports. This option
chooses which port will be used for diagnostic output."
}
 
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CHANNELS_DEFAULT_BAUD {
display "Console/GDB serial port baud rate"
flavor data
legal_values 9600 19200 38400 57600 115200
default_value 38400
description "
This option controls the default baud rate used for the
Console/GDB connection."
}
 
# Real-time clock/counter specifics
cdl_option CYGNUM_HAL_ARM_E7T_CLOCK_SPEED {
display "CPU clock speed"
flavor data
calculated 50000000
}
 
cdl_component CYGNUM_HAL_RTC_CONSTANTS {
display "Real-time clock constants"
flavor none
cdl_option CYGNUM_HAL_RTC_NUMERATOR {
display "Real-time clock numerator"
flavor data
calculated 1000000000
}
cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
display "Real-time clock denominator"
flavor data
calculated 100
}
cdl_option CYGNUM_HAL_RTC_PERIOD {
display "Real-time clock period"
flavor data
calculated (CYGNUM_HAL_ARM_E7T_CLOCK_SPEED / CYGNUM_HAL_RTC_DENOMINATOR)
}
}
 
cdl_component CYGBLD_GLOBAL_OPTIONS {
display "Global build options"
flavor none
parent CYGPKG_NONE
description "
Global build options including control over
compiler flags, linker flags and choice of toolchain."
 
 
cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
display "Global command prefix"
flavor data
no_define
default_value { "arm-elf" }
description "
This option specifies the command prefix used when
invoking the build tools."
}
 
cdl_option CYGBLD_GLOBAL_CFLAGS {
display "Global compiler flags"
flavor data
no_define
default_value { "-mcpu=arm7tdmi -mno-short-load-words -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
description "
This option controls the global compiler flags which are used to
compile all packages by default. Individual packages may define
options which override these global flags."
}
 
cdl_option CYGBLD_GLOBAL_LDFLAGS {
display "Global linker flags"
flavor data
no_define
default_value { "-mcpu=arm7tdmi -mno-short-load-words -Wl,--gc-sections -Wl,-static -g -nostdlib" }
description "
This option controls the global linker flags. Individual
packages may define options which override these global flags."
}
}
 
cdl_component CYGHWR_MEMORY_LAYOUT {
display "Memory layout"
flavor data
no_define
calculated { (CYG_HAL_STARTUP == "RAM") ? "arm_e7t_ram" : "arm_e7t_rom" }
 
cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
display "Memory layout linker script fragment"
flavor data
no_define
define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_arm_e7t_ram.ldi>" :
"<pkgconf/mlt_arm_e7t_rom.ldi>" }
}
 
cdl_option CYGHWR_MEMORY_LAYOUT_H {
display "Memory layout header file"
flavor data
no_define
define -file system.h CYGHWR_MEMORY_LAYOUT_H
calculated { (CYG_HAL_STARTUP == "RAM") ? "<pkgconf/mlt_arm_e7t_ram.h>" : \
"<pkgconf/mlt_arm_e7t_rom.h>" }
}
}
 
cdl_option CYGSEM_HAL_ROM_MONITOR {
display "Behave as a ROM monitor"
flavor bool
default_value 0
parent CYGPKG_HAL_ROM_MONITOR
requires { CYG_HAL_STARTUP == "ROM" }
description "
Enable this option if this program is to be used as a ROM monitor,
i.e. applications will be loaded into RAM on the board, and this
ROM monitor may process exceptions or interrupts generated from the
application. This enables features such as utilizing a separate
interrupt stack when exceptions are generated."
}
 
cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
display "Work with a ROM monitor"
flavor booldata
legal_values { "Generic" "GDB_stubs" }
default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
parent CYGPKG_HAL_ROM_MONITOR
requires { CYG_HAL_STARTUP == "RAM" }
description "
Support can be enabled for different varieties of ROM monitor.
This support changes various eCos semantics such as the encoding
of diagnostic output, or the overriding of hardware interrupt
vectors.
Firstly there is \"Generic\" support which prevents the HAL
from overriding the hardware vectors that it does not use, to
instead allow an installed ROM monitor to handle them. This is
the most basic support which is likely to be common to most
implementations of ROM monitor.
\"GDB_stubs\" provides support when GDB stubs are included in
the ROM monitor or boot ROM."
}
 
cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
display "Redboot HAL options"
flavor none
no_define
parent CYGPKG_REDBOOT
active_if CYGPKG_REDBOOT
description "
This option lists the target's requirements for a valid Redboot
configuration."
 
cdl_option CYGBLD_BUILD_REDBOOT_BIN {
display "Build Redboot ROM binary image"
active_if CYGBLD_BUILD_REDBOOT
default_value 1
no_define
description "This option enables the conversion of the Redboot ELF
image to a binary image suitable for ROM programming."
make -priority 325 {
<PREFIX>/bin/redboot.bin : <PACKAGE>/src/redboot_module.c $(PREFIX)/lib/target.ld $(PREFIX)/lib/vectors.o $(PREFIX)/lib/libtarget.a $(PREFIX)/lib/libextras.a
@sh -c "mkdir -p src $(dir $@)"
# First build version with no checksum.
$(CC) -c $(INCLUDE_PATH) -Wp,-MD,deps.tmp -I$(dir $<) $(CFLAGS) -o src/redboot_ncs.o $<
$(CC) $(LDFLAGS) -L$(PREFIX)/lib -Ttarget.ld -o src/redboot_ncs.tmp $(PREFIX)/lib/version.o src/redboot_ncs.o
$(OBJCOPY) --strip-debug src/redboot_ncs.tmp src/redboot_ncs.img
$(OBJCOPY) -O binary src/redboot_ncs.img src/redboot_ncs.bin
# @rm src/redboot_ncs.tmp src/redboot_ncs.img
# Prepare dependency file
@echo $@ ": \\" > $(notdir $@).deps
@echo $(wildcard $(PREFIX)/lib/*) " \\" >> $(notdir $@).deps
@tail +2 deps.tmp >> $(notdir $@).deps
@echo >> $(notdir $@).deps
@rm deps.tmp
# Then build version with checksum from previously built image.
@cp $(dir $<)flash_cksum.tcl src/
$(CC) -c -DCHECKSUM=`src/flash_cksum.tcl src/redboot_ncs.bin` $(INCLUDE_PATH) -I$(dir $<) $(CFLAGS) -o src/redboot.o $<
$(CC) $(LDFLAGS) -L$(PREFIX)/lib -Ttarget.ld -o src/redboot.tmp $(PREFIX)/lib/version.o src/redboot.o
$(OBJCOPY) --strip-debug src/redboot.tmp $(@:.bin=.img)
$(OBJCOPY) -O binary $(@:.bin=.img) src/redboot.bin
uuencode src/redboot.bin redboot.bin | tr '`' ' ' > $(@:.bin=.UU)
@rm src/redboot.tmp src/redboot_ncs.bin
@mv src/redboot.bin $@
}
 
}
}
}
/include/plf_stub.h
0,0 → 1,86
#ifndef CYGONCE_HAL_PLF_STUB_H
#define CYGONCE_HAL_PLF_STUB_H
 
//=============================================================================
//
// plf_stub.h
//
// Platform header for GDB stub support.
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
// Contributors:jskov, gthomas
// Date: 2001-03-16
// Purpose: Platform HAL stub support for ARM/E7T boards.
// Usage: #include <cyg/hal/plf_stub.h>
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
#include CYGBLD_HAL_PLATFORM_H
 
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 
#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM
 
#include <cyg/hal/arm_stub.h> // architecture stub support
 
//----------------------------------------------------------------------------
// Define some platform specific communication details. This is mostly
// handled by hal_if now, but we need to make sure the comms tables are
// properly initialized.
 
externC void cyg_hal_plf_comms_init(void);
 
#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init()
 
#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud))
#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0
#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT
 
//----------------------------------------------------------------------------
// Stub initializer.
#define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT
 
#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 
//-----------------------------------------------------------------------------
#endif // CYGONCE_HAL_PLF_STUB_H
// End of plf_stub.h
/include/pkgconf/mlt_arm_e7t_ram.h
0,0 → 1,17
// eCos memory layout - Wed Apr 11 13:43:10 2001
 
// This is a generated file - do not edit
 
#ifndef __ASSEMBLER__
#include <cyg/infra/cyg_type.h>
#include <stddef.h>
 
#endif
#define CYGMEM_REGION_ram (0)
#define CYGMEM_REGION_ram_SIZE (0x80000)
#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__heap1) [];
#endif
#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
#define CYGMEM_SECTION_heap1_SIZE (0x80000 - (size_t) CYG_LABEL_NAME (__heap1))
/include/pkgconf/mlt_arm_e7t_ram.ldi
0,0 → 1,27
// eCos memory layout - Wed Apr 11 13:43:10 2001
 
// This is a generated file - do not edit
 
#include <cyg/infra/cyg_type.inc>
 
MEMORY
{
ram : ORIGIN = 0, LENGTH = 0x80000
}
 
SECTIONS
{
SECTIONS_BEGIN
SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA)
SECTION_rom_vectors (ram, 0x10000, LMA_EQ_VMA)
SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata1 (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_data (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
SECTIONS_END
}
/include/pkgconf/mlt_arm_e7t_rom.mlt
0,0 → 1,15
version 0
region ram 0 80000 0 !
region rom 1800000 80000 1 !
section fixed_vectors 0 1 0 1 1 0 1 0 20 20 !
section data 0 1 1 1 1 1 0 0 8000 bss !
section bss 0 4 0 1 0 1 0 1 heap1 heap1 !
section heap1 0 8 0 0 0 0 0 0 !
section reserved_bootmon 20000 1 0 0 1 1 1 1 1800000 1800000 rom_vectors rom_vectors !
section rom_vectors 0 8 0 1 0 1 0 1 text text !
section text 0 1 0 1 0 1 0 1 fini fini !
section fini 0 4 0 1 0 1 0 1 rodata rodata !
section rodata 0 4 0 1 0 1 0 1 rodata1 rodata1 !
section rodata1 0 4 0 1 0 1 0 1 fixup fixup !
section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
section gcc_except_table 0 4 0 1 0 0 0 1 data !
/include/pkgconf/mlt_arm_e7t_ram.mlt
0,0 → 1,13
version 0
region ram 0 80000 0 !
section fixed_vectors 0 1 0 1 1 0 1 0 20 20 !
section rom_vectors 0 1 0 1 1 1 1 1 10000 10000 text text !
section text 0 4 0 1 0 1 0 1 fini fini !
section fini 0 4 0 1 0 1 0 1 rodata rodata !
section rodata 0 4 0 1 0 1 0 1 rodata1 rodata1 !
section rodata1 0 4 0 1 0 1 0 1 fixup fixup !
section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
section gcc_except_table 0 4 0 1 0 1 0 1 data data !
section data 0 4 0 1 0 1 0 1 bss bss !
section bss 0 4 0 1 0 1 0 1 heap1 heap1 !
section heap1 0 8 0 0 0 0 0 0 !
/include/pkgconf/mlt_arm_e7t_rom.h
0,0 → 1,25
// eCos memory layout - Wed Apr 11 13:49:55 2001
 
// This is a generated file - do not edit
 
#ifndef __ASSEMBLER__
#include <cyg/infra/cyg_type.h>
#include <stddef.h>
 
#endif
#define CYGMEM_REGION_ram (0)
#define CYGMEM_REGION_ram_SIZE (0x80000)
#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
#define CYGMEM_REGION_rom (0x1800000)
#define CYGMEM_REGION_rom_SIZE (0x80000)
#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__reserved_bootmon) [];
#endif
#define CYGMEM_SECTION_reserved_bootmon (CYG_LABEL_NAME (__reserved_bootmon))
#define CYGMEM_SECTION_reserved_bootmon_SIZE (0x20000)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__heap1) [];
#endif
#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
#define CYGMEM_SECTION_heap1_SIZE (0x80000 - (size_t) CYG_LABEL_NAME (__heap1))
/include/pkgconf/mlt_arm_e7t_rom.ldi
0,0 → 1,29
// eCos memory layout - Wed Apr 11 13:49:55 2001
 
// This is a generated file - do not edit
 
#include <cyg/infra/cyg_type.inc>
 
MEMORY
{
ram : ORIGIN = 0, LENGTH = 0x80000
rom : ORIGIN = 0x1800000, LENGTH = 0x80000
}
 
SECTIONS
{
SECTIONS_BEGIN
CYG_LABEL_DEFN(__reserved_bootmon) = 0x1800000; . = CYG_LABEL_DEFN(__reserved_bootmon) + 0x20000;
SECTION_rom_vectors (rom, ALIGN (0x8), LMA_EQ_VMA)
SECTION_text (rom, ALIGN (0x1), LMA_EQ_VMA)
SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA)
SECTION_data (ram, 0x8000, FOLLOWING (.gcc_except_table))
SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
SECTIONS_END
}
/include/hal_platform_ints.h
0,0 → 1,96
#ifndef CYGONCE_HAL_PLATFORM_INTS_H
#define CYGONCE_HAL_PLATFORM_INTS_H
//==========================================================================
//
// hal_platform_ints.h
//
// HAL Interrupt and clock assignments for E7T (AEB-2)
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): gthomas
// Contributors: gthomas
// Date: 1999-02-20
// Purpose: Define Interrupt support
// Description: The interrupt specifics for the AEB-1 board/platform are
// defined here.
//
// Usage: #include <cyg/hal/hal_platform_ints.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#define CYGNUM_HAL_INTERRUPT_EXT0 0
#define CYGNUM_HAL_INTERRUPT_EXT1 1
#define CYGNUM_HAL_INTERRUPT_EXT2 2
#define CYGNUM_HAL_INTERRUPT_EXT3 3
#define CYGNUM_HAL_INTERRUPT_UART0_TX 4
#define CYGNUM_HAL_INTERRUPT_UART0_RX 5
#define CYGNUM_HAL_INTERRUPT_UART1_TX 6
#define CYGNUM_HAL_INTERRUPT_UART1_RX 7
#define CYGNUM_HAL_INTERRUPT_GDMA0 8
#define CYGNUM_HAL_INTERRUPT_GDMA1 9
#define CYGNUM_HAL_INTERRUPT_TIMER0 10
#define CYGNUM_HAL_INTERRUPT_TIMER1 11
#define CYGNUM_HAL_INTERRUPT_HDLCA_TX 12
#define CYGNUM_HAL_INTERRUPT_HDLCA_RX 13
#define CYGNUM_HAL_INTERRUPT_HDLCB_TX 14
#define CYGNUM_HAL_INTERRUPT_HDLCB_RX 15
#define CYGNUM_HAL_INTERRUPT_ETH_BDMA_TX 16
#define CYGNUM_HAL_INTERRUPT_ETH_BDMA_RX 17
#define CYGNUM_HAL_INTERRUPT_ETH_MAC_TX 18
#define CYGNUM_HAL_INTERRUPT_ETH_MAC_RX 19
#define CYGNUM_HAL_INTERRUPT_I2C 20
 
#define CYGNUM_HAL_ISR_MIN 0
#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_I2C
#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX - CYGNUM_HAL_ISR_MIN + 1)
 
// The vector used by the Real time clock
#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER0
 
 
//----------------------------------------------------------------------------
// Reset.
#define HAL_PLATFORM_RESET()
 
#define HAL_PLATFORM_RESET_ENTRY 0x01820000
 
#endif // CYGONCE_HAL_PLATFORM_INTS_H
/include/hal_cache.h
0,0 → 1,292
#ifndef CYGONCE_HAL_CACHE_H
#define CYGONCE_HAL_CACHE_H
 
//=============================================================================
//
// hal_cache.h
//
// HAL cache control API
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg, gthomas
// Contributors: nickg, gthomas
// Date: 1998-09-28
// Purpose: Cache control API
// Description: The macros defined here provide the HAL APIs for handling
// cache control operations.
// Usage:
// #include <cyg/hal/hal_cache.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <cyg/infra/cyg_type.h>
#include <cyg/hal/hal_io.h>
#include <cyg/hal/plf_io.h>
 
//-----------------------------------------------------------------------------
// Cache dimensions - one unified cache
 
#define HAL_CACHE_UNIFIED
 
#define HAL_UCACHE_SIZE 0x2000 // Size of cache in bytes
#define HAL_UCACHE_LINE_SIZE 16 // Size of a cache line
#define HAL_UCACHE_WAYS 2 // Associativity of the cache
 
#define HAL_UCACHE_SETS (HAL_UCACHE_SIZE/(HAL_UCACHE_LINE_SIZE*HAL_UCACHE_WAYS))
 
//-----------------------------------------------------------------------------
// Global control of cache
 
// Enable the cache
#define HAL_UCACHE_ENABLE() \
CYG_MACRO_START \
cyg_uint32 syscfg; \
HAL_READ_UINT32(E7T_SYSCFG, syscfg); \
syscfg |= E7T_SYSCFG_CE; \
HAL_WRITE_UINT32(E7T_SYSCFG, syscfg); \
CYG_MACRO_END
 
// Disable the cache
#define HAL_UCACHE_DISABLE() \
CYG_MACRO_START \
cyg_uint32 syscfg; \
HAL_READ_UINT32(E7T_SYSCFG, syscfg); \
syscfg &= ~E7T_SYSCFG_CE; \
HAL_WRITE_UINT32(E7T_SYSCFG, syscfg); \
CYG_MACRO_END
 
// Invalidate the entire cache
#define HAL_UCACHE_INVALIDATE_ALL() \
CYG_MACRO_START \
register cyg_uint32* tag = (cyg_uint32*)E7T_CACHE_TAG_ADDR; \
register int i; \
for (i = 0; i < HAL_UCACHE_SETS/4; i++) { \
*tag++ = 0; \
*tag++ = 0; \
*tag++ = 0; \
*tag++ = 0; \
} \
CYG_MACRO_END
 
// Synchronize the contents of the cache with memory.
// No action necessary. Cache is write-through.
#define HAL_UCACHE_SYNC()
 
// Query the state of the cache
#define HAL_UCACHE_IS_ENABLED(_state_) \
CYG_MACRO_START \
cyg_uint32 syscfg; \
HAL_READ_UINT32(E7T_SYSCFG, syscfg); \
(_state_) = (syscfg & E7T_SYSCFG_CE) ? 1 : 0; \
CYG_MACRO_END
 
// Purge contents of cache
#define HAL_UCACHE_PURGE_ALL() HAL_UCACHE_INVALIDATE_ALL()
 
// Set the cache refill burst size
//#define HAL_UCACHE_BURST_SIZE(_size_)
 
// Set the cache write mode
//#define HAL_UCACHE_WRITE_MODE( _mode_ )
 
//#define HAL_UCACHE_WRITETHRU_MODE 0
//#define HAL_UCACHE_WRITEBACK_MODE 1
 
// Load the contents of the given address range into the cache
// and then lock the cache so that it stays there.
//#define HAL_UCACHE_LOCK(_base_, _size_)
 
// Undo a previous lock operation
//#define HAL_UCACHE_UNLOCK(_base_, _size_)
 
// Unlock entire cache
//#define HAL_UCACHE_UNLOCK_ALL()
 
//-----------------------------------------------------------------------------
// Cache line control
 
// Allocate cache lines for the given address range without reading its
// contents from memory.
//#define HAL_UCACHE_ALLOCATE( _base_ , _size_ )
 
// Write dirty cache lines to memory and invalidate the cache entries
// for the given address range.
//#define HAL_UCACHE_FLUSH( _base_ , _size_ )
 
// Invalidate cache lines in the given range without writing to memory.
//#define HAL_UCACHE_INVALIDATE( _base_ , _size_ )
 
// Write dirty cache lines to memory for the given address range.
//#define HAL_UCACHE_STORE( _base_ , _size_ )
 
// Preread the given range into the cache with the intention of reading
// from it later.
//#define HAL_UCACHE_READ_HINT( _base_ , _size_ )
 
// Preread the given range into the cache with the intention of writing
// to it later.
//#define HAL_UCACHE_WRITE_HINT( _base_ , _size_ )
 
// Allocate and zero the cache lines associated with the given range.
//#define HAL_UCACHE_ZERO( _base_ , _size_ )
 
//-----------------------------------------------------------------------------
 
//-----------------------------------------------------------------------------
// Data and instruction cache macros map onto the both-cache macros
 
//-----------------------------------------------------------------------------
// Global control of data cache
 
#define HAL_DCACHE_SIZE HAL_UCACHE_SIZE
#define HAL_DCACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE
#define HAL_DCACHE_WAYS HAL_UCACHE_WAYS
#define HAL_DCACHE_SETS HAL_UCACHE_SETS
 
// Enable the data cache
#define HAL_DCACHE_ENABLE() HAL_UCACHE_ENABLE()
 
// Disable the data cache
#define HAL_DCACHE_DISABLE() HAL_UCACHE_DISABLE()
 
// Invalidate the entire cache
#define HAL_DCACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL()
 
// Synchronize the contents of the cache with memory.
#define HAL_DCACHE_SYNC() HAL_UCACHE_SYNC()
 
// Query the state of the data cache
#define HAL_DCACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_)
 
// Set the data cache refill burst size
//#define HAL_DCACHE_BURST_SIZE(_size_)
 
// Set the data cache write mode
//#define HAL_DCACHE_WRITE_MODE( _mode_ )
 
//#define HAL_DCACHE_WRITETHRU_MODE 0
//#define HAL_DCACHE_WRITEBACK_MODE 1
 
// Load the contents of the given address range into the data cache
// and then lock the cache so that it stays there.
//#define HAL_DCACHE_LOCK(_base_, _size_)
 
// Undo a previous lock operation
//#define HAL_DCACHE_UNLOCK(_base_, _size_)
 
// Unlock entire cache
//#define HAL_DCACHE_UNLOCK_ALL()
 
//-----------------------------------------------------------------------------
// Data cache line control
 
// Allocate cache lines for the given address range without reading its
// contents from memory.
//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
 
// Write dirty cache lines to memory and invalidate the cache entries
// for the given address range.
//#define HAL_DCACHE_FLUSH( _base_ , _size_ )
 
// Invalidate cache lines in the given range without writing to memory.
//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
 
// Write dirty cache lines to memory for the given address range.
//#define HAL_DCACHE_STORE( _base_ , _size_ )
 
// Preread the given range into the cache with the intention of reading
// from it later.
//#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
 
// Preread the given range into the cache with the intention of writing
// to it later.
//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
 
// Allocate and zero the cache lines associated with the given range.
//#define HAL_DCACHE_ZERO( _base_ , _size_ )
 
//-----------------------------------------------------------------------------
// Global control of Instruction cache
 
#define HAL_ICACHE_SIZE HAL_UCACHE_SIZE
#define HAL_ICACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE
#define HAL_ICACHE_WAYS HAL_UCACHE_WAYS
#define HAL_ICACHE_SETS HAL_UCACHE_SETS
 
// Enable the instruction cache
#define HAL_ICACHE_ENABLE() HAL_UCACHE_ENABLE()
 
// Disable the instruction cache
#define HAL_ICACHE_DISABLE() HAL_UCACHE_DISABLE()
 
// Invalidate the entire cache
#define HAL_ICACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL()
 
 
// Synchronize the contents of the cache with memory.
#define HAL_ICACHE_SYNC() HAL_UCACHE_SYNC()
 
// Query the state of the instruction cache
#define HAL_ICACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_)
 
// Set the instruction cache refill burst size
//#define HAL_ICACHE_BURST_SIZE(_size_)
 
// Load the contents of the given address range into the instruction cache
// and then lock the cache so that it stays there.
 
//#define HAL_ICACHE_LOCK(_base_, _size_)
 
// Undo a previous lock operation
//#define HAL_ICACHE_UNLOCK(_base_, _size_)
 
// Unlock entire cache
//#define HAL_ICACHE_UNLOCK_ALL()
 
//-----------------------------------------------------------------------------
// Instruction cache line control
 
// Invalidate cache lines in the given range without writing to memory.
//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
 
#endif // ifndef CYGONCE_HAL_CACHE_H
// End of hal_cache.h
/include/hal_diag.h
0,0 → 1,79
#ifndef CYGONCE_HAL_DIAG_H
#define CYGONCE_HAL_DIAG_H
 
//=============================================================================
//
// hal_diag.h
//
// HAL Support for Kernel Diagnostic Routines
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
// Contributors:jskov
// Date: 2001-03-16
// Purpose: HAL Support for Kernel Diagnostic Routines
// Description: Diagnostic routines for use during kernel development.
// Usage: #include <cyg/hal/hal_diag.h>
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h>
 
#include <cyg/hal/hal_if.h>
 
#define HAL_DIAG_INIT() hal_if_diag_init()
#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_)
#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_)
 
//-----------------------------------------------------------------------------
// LED
externC void hal_diag_led(int mask);
 
//-----------------------------------------------------------------------------
// delay
 
extern void hal_delay_us(cyg_int32 usecs);
#define HAL_DELAY_US(n) hal_delay_us(n);
 
//-----------------------------------------------------------------------------
// end of hal_diag.h
#endif // CYGONCE_HAL_DIAG_H
/include/hal_platform_setup.h
0,0 → 1,138
#ifndef CYGONCE_HAL_PLATFORM_SETUP_H
#define CYGONCE_HAL_PLATFORM_SETUP_H
 
/*=============================================================================
//
// hal_platform_setup.h
//
// Platform specific support for HAL (assembly code)
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
// Contributors:jskov
// Date: 2001-03-16
// Purpose: E7T platform specific support routines
// Description:
// Usage: #include <cyg/hal/hal_platform_setup.h>
//
//####DESCRIPTIONEND####
//
//===========================================================================*/
 
#include <cyg/hal/plf_io.h>
 
#define CYGHWR_LED_MACRO \
ldr r0,=E7T_IOPDATA ;\
mov r1, #((15 & (\x)) << 4) ;\
str r1, [r0] ;
 
#if CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE==4096
// Override default to a more sensible value
#undef CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
#define CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE 2048
#endif
 
#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
#define PLATFORM_SETUP1 ;\
ldr r1,=E7T_IOPMOD ;\
ldr r2,=0x0001fcf0 /* set led + seg to output */ ;\
str r2,[r1,#0x00] ;\
ldr r1,=E7T_IOPDATA ;\
ldr r2,=0x00000050 /* set leds */ ;\
str r2,[r1,#0x00] ;\
;\
20: ldr lr,=33f ;\
ldr r0,=12f ;\
ldmia r0,{r1-r12} ;\
ldr r0,=E7T_EXTDBWTH ;\
stmia r0,{r1-r12} ;\
mov pc,lr ;\
;\
/* The below are set with a store-multiple instruction */ ;\
/* Flash is 16 bit, SRAM is 32 bit */ ;\
/* .long E7T_EXTDBWTH */ ;\
12: .long ( (E7T_EXTDBWTH_16BIT<<E7T_EXTDBWTH_DSR0_shift) \
|(E7T_EXTDBWTH_32BIT<<E7T_EXTDBWTH_DSR1_shift) \
|(E7T_EXTDBWTH_32BIT<<E7T_EXTDBWTH_DSR2_shift) ) ;\
/* Flash at 0x01800000-0x01880000, 5 cycles, 4 cycles */ ;\
/* .long E7T_ROMCON0 */ ;\
.long ( (E7T_ROMCON_PMC_ROM) \
|(E7T_ROMCON_TPA_5C) \
|(E7T_ROMCON_TACC_4C) \
|((0x01800000 >> 16) << E7T_ROMCON_BASE_shift) \
|((0x01880000 >> 16) << E7T_ROMCON_NEXT_shift)) ;\
/* SRAM at 0x00000000-0x00400000, 5 cycles, 2 cycles */ ;\
/* .long E7T_ROMCON1 */ ;\
.long ( (E7T_ROMCON_PMC_ROM) \
|(E7T_ROMCON_TPA_5C) \
|(E7T_ROMCON_TACC_2C) \
|((0x00000000 >> 16) << E7T_ROMCON_BASE_shift) \
|((0x00040000 >> 16) << E7T_ROMCON_NEXT_shift)) ;\
/* SRAM at 0x00400000-0x00800000, 5 cycles, 2 cycles */ ;\
/* .long E7T_ROMCON2 */ ;\
.long ( (E7T_ROMCON_PMC_ROM) \
|(E7T_ROMCON_TPA_5C) \
|(E7T_ROMCON_TACC_2C) \
|((0x00040000 >> 16) << E7T_ROMCON_BASE_shift) \
|((0x00080000 >> 16) << E7T_ROMCON_NEXT_shift)) ;\
/* Below values are what Boot Monitor sets up */ ;\
/* .long E7T_ROMCON3 */ ;\
.long 0x08018020 ;\
/* .long E7T_ROMCON4 */ ;\
.long 0x0a020040 ;\
/* .long E7T_ROMCON5 */ ;\
.long 0x0c028040 ;\
/* .long E7T_DRAMCON0 */ ;\
.long 0x00000000 ;\
/* .long E7T_DRAMCON1 */ ;\
.long 0x00000000 ;\
/* .long E7T_DRAMCON2 */ ;\
.long 0x00000000 ;\
/* .long E7T_DRAMCON3 */ ;\
.long 0x00000000 ;\
/* .long E7T_REFEXTCON */ ;\
.long 0x9c218360 ;\
;\
33:
#else
#define PLATFORM_SETUP1
#endif
 
//-----------------------------------------------------------------------------
// end of hal_platform_setup.h
#endif // CYGONCE_HAL_PLATFORM_SETUP_H
/include/plf_io.h
0,0 → 1,247
#ifndef CYGONCE_HAL_PLF_IO_H
#define CYGONCE_HAL_PLF_IO_H
//=============================================================================
//
// plf_io.h
//
// Platform specific registers
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
// Contributors:jskov
// Date: 2001-03-16
// Purpose: ARM/E7T platform specific registers
// Description:
// Usage: #include <cyg/hal/plf_io.h>
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
// non-caching by accessing addr|0x04000000
 
#define E7T_REG_BASE 0x07ff0000
 
// -----------------------------------------------------------------------------
// System config (register bases and caching)
#define E7T_SYSCFG (E7T_REG_BASE + 0x0000)
 
#define E7T_SYSCFG_SDM 0x80000000
#define E7T_SYSCFG_PD_ID_MASK 0x3c000000
#define E7T_SYSCFG_SRBBP_MASK 0x03ff0000 // address/64k
#define E7T_SYSCFG_ISBBP_MASK 0x0000ffc0 // a25-a16
#define E7T_SYSCFG_CM_MASK 0x00000030
#define E7T_SYSCFG_CM_4R_4C 0x00000000
#define E7T_SYSCFG_CM_0R_8C 0x00000010
#define E7T_SYSCFG_CM_8R_0C 0x00000020
#define E7T_SYSCFG_WE 0x00000004 // only KS32C50100?
#define E7T_SYSCFG_CE 0x00000002
#define E7T_SYSCFG_SE 0x00000001
 
#define E7T_CLKCON (E7T_REG_BASE + 0x3000)
 
#define E7T_EXTACON0 (E7T_REG_BASE + 0x3008)
#define E7T_EXTACON1 (E7T_REG_BASE + 0x300c)
 
//-----------------------------------------------------------------------------
// Memory banks data width
#define E7T_EXTDBWTH (E7T_REG_BASE + 0x3010)
 
#define E7T_EXTDBWTH_MASK 3
#define E7T_EXTDBWTH_8BIT 1
#define E7T_EXTDBWTH_16BIT 2
#define E7T_EXTDBWTH_32BIT 3
 
#define E7T_EXTDBWTH_DSR0_shift 0
#define E7T_EXTDBWTH_DSR1_shift 2
#define E7T_EXTDBWTH_DSR2_shift 4
#define E7T_EXTDBWTH_DSR3_shift 6
#define E7T_EXTDBWTH_DSR4_shift 8
#define E7T_EXTDBWTH_DSR5_shift 10
#define E7T_EXTDBWTH_DSD0_shift 12
#define E7T_EXTDBWTH_DSD1_shift 14
#define E7T_EXTDBWTH_DSD2_shift 16
#define E7T_EXTDBWTH_DSD3_shift 18
#define E7T_EXTDBWTH_DSX0_shift 20
#define E7T_EXTDBWTH_DSX1_shift 22
#define E7T_EXTDBWTH_DSX2_shift 24
#define E7T_EXTDBWTH_DSX3_shift 26
 
// -----------------------------------------------------------------------------
// Bank locations and timing
#define E7T_ROMCON0 (E7T_REG_BASE + 0x3014)
#define E7T_ROMCON1 (E7T_REG_BASE + 0x3018)
#define E7T_ROMCON2 (E7T_REG_BASE + 0x301c)
#define E7T_ROMCON3 (E7T_REG_BASE + 0x3020)
#define E7T_ROMCON4 (E7T_REG_BASE + 0x3024)
#define E7T_ROMCON5 (E7T_REG_BASE + 0x3028)
 
#define E7T_ROMCON_PMC_MASK 0x00000003
#define E7T_ROMCON_PMC_ROM 0x00000000
#define E7T_ROMCON_PMC_4W_PAGE 0x00000001
#define E7T_ROMCON_PMC_8W_PAGE 0x00000002
#define E7T_ROMCON_PMC_16W_PAGE 0x00000003
 
#define E7T_ROMCON_TPA_MASK 0x0000000c
#define E7T_ROMCON_TPA_5C 0x00000000
#define E7T_ROMCON_TPA_2C 0x00000004
#define E7T_ROMCON_TPA_3C 0x00000008
#define E7T_ROMCON_TPA_4C 0x0000000c
 
#define E7T_ROMCON_TACC_MASK 0x00000070
#define E7T_ROMCON_TACC_DISABLE 0x00000000
#define E7T_ROMCON_TACC_2C 0x00000010
#define E7T_ROMCON_TACC_3C 0x00000020
#define E7T_ROMCON_TACC_4C 0x00000030
#define E7T_ROMCON_TACC_5C 0x00000040
#define E7T_ROMCON_TACC_6C 0x00000050
#define E7T_ROMCON_TACC_7C 0x00000060
 
#define E7T_ROMCON_BASE_MASK 0x000ff700
#define E7T_ROMCON_BASE_shift 10
 
#define E7T_ROMCON_NEXT_MASK 0x7ff00000
#define E7T_ROMCON_NEXT_shift 20
 
 
 
#define E7T_DRAMCON0 (E7T_REG_BASE + 0x302c)
#define E7T_DRAMCON1 (E7T_REG_BASE + 0x3030)
#define E7T_DRAMCON2 (E7T_REG_BASE + 0x3034)
#define E7T_DRAMCON3 (E7T_REG_BASE + 0x3038)
#define E7T_REFEXTCON (E7T_REG_BASE + 0x303c)
 
//-----------------------------------------------------------------------------
// INTC
 
#define E7T_INTMOD (E7T_REG_BASE + 0x4000)
#define E7T_INTPND (E7T_REG_BASE + 0x4004)
#define E7T_INTMSK (E7T_REG_BASE + 0x4008)
#define E7T_INTPRI0 (E7T_REG_BASE + 0x400c)
#define E7T_INTPRI1 (E7T_REG_BASE + 0x4010)
#define E7T_INTPRI2 (E7T_REG_BASE + 0x4014)
#define E7T_INTPRI3 (E7T_REG_BASE + 0x4018)
#define E7T_INTPRI4 (E7T_REG_BASE + 0x401c)
#define E7T_INTPRI5 (E7T_REG_BASE + 0x4020)
#define E7T_INTOFFSET (E7T_REG_BASE + 0x4024)
#define E7T_PNDPRI (E7T_REG_BASE + 0x4028)
#define E7T_PNDTEST (E7T_REG_BASE + 0x402c)
#define E7T_INTOFFSET_FIQ (E7T_REG_BASE + 0x4030)
#define E7T_INTOFFSET_IRQ (E7T_REG_BASE + 0x4034)
 
#define E7T_INTMSK_GLOBAL (1<<21)
 
//-----------------------------------------------------------------------------
// PIO
 
#define E7T_IOPMOD (E7T_REG_BASE + 0x5000)
#define E7T_IOPCON (E7T_REG_BASE + 0x5004)
#define E7T_IOPDATA (E7T_REG_BASE + 0x5008)
 
//-----------------------------------------------------------------------------
// Timers
 
#define E7T_TMOD (E7T_REG_BASE + 0x6000)
#define E7T_TDATA0 (E7T_REG_BASE + 0x6004)
#define E7T_TDATA1 (E7T_REG_BASE + 0x6008)
#define E7T_TCNT0 (E7T_REG_BASE + 0x600c)
#define E7T_TCNT1 (E7T_REG_BASE + 0x6010)
 
#define E7T_TMOD_TE0 0x00000001
#define E7T_TMOD_TMD0 0x00000002
#define E7T_TMOD_TCLR0 0x00000004
#define E7T_TMOD_TE1 0x00000008
#define E7T_TMOD_TMD1 0x00000010
#define E7T_TMOD_TCLR1 0x00000020
 
 
//-----------------------------------------------------------------------------
// UART
 
#define E7T_UART0_BASE (E7T_REG_BASE + 0xd000)
#define E7T_UART1_BASE (E7T_REG_BASE + 0xe000)
 
#define E7T_UART_LCON 0x0000
#define E7T_UART_CON 0x0004
#define E7T_UART_STAT 0x0008
#define E7T_UART_TXBUF 0x000c
#define E7T_UART_RXBUF 0x0010
#define E7T_UART_BRDIV 0x0014
#define E7T_UART_BRDCNT 0x0018
#define E7T_UART_BRDCLK 0x001c
 
#define E7T_UART_LCON_5_DBITS 0x00
#define E7T_UART_LCON_6_DBITS 0x01
#define E7T_UART_LCON_7_DBITS 0x02
#define E7T_UART_LCON_8_DBITS 0x03
#define E7T_UART_LCON_1_SBITS 0x00
#define E7T_UART_LCON_2_SBITS 0x04
#define E7T_UART_LCON_NO_PARITY 0x00
#define E7T_UART_LCON_EVEN_PARITY 0x00
#define E7T_UART_LCON_ODD_PARITY 0x28
#define E7T_UART_LCON_1_PARITY 0x30
#define E7T_UART_LCON_0_PARITY 0x38
#define E7T_UART_LCON_SCS 0x40
#define E7T_UART_LCON_IR 0x80
 
#define E7T_UART_CON_RXM_MASK 0x03
#define E7T_UART_CON_RXM_INT 0x01
#define E7T_UART_CON_TXM_MASK 0x0c
#define E7T_UART_CON_TXM_INT 0x08
#define E7T_UART_CON_RX_ERR_INT 0x04
 
 
#define E7T_UART_STAT_DTR 0x10
#define E7T_UART_STAT_RDR 0x20
#define E7T_UART_STAT_TXE 0x40 // tx empty
#define E7T_UART_STAT_TC 0x80 // tx complete
 
//-----------------------------------------------------------------------------
// Cache
#define E7T_CACHE_SET0_ADDR 0x14000000
#define E7T_CACHE_SET1_ADDR 0x14800000
#define E7T_CACHE_TAG_ADDR 0x15000000
 
//-----------------------------------------------------------------------------
// Memory map is 1-1
 
#define CYGARC_PHYSICAL_ADDRESS(_x_) (_x_)
 
//-----------------------------------------------------------------------------
// end of plf_io.h
#endif // CYGONCE_HAL_PLF_IO_H
/ChangeLog
0,0 → 1,174
2003-02-05 Nick Garnett <nickg@calivar.com>
 
* include/plf_io.h (CYGARC_PHYSICAL_ADDRESS): Added this
definition to keep redboot_linux_exec.c happy.
 
2003-01-29 John Dallaway <jld@ecoscentric.com>
 
* src/flash_cksum.tcl: Accommodate latest Cygwin Tcl shell
(tclsh83.exe)
 
2002-10-19 Jonathan Larmour <jifl@eCosCentric.com>
 
* include/hal_platform_setup.h (PLATFORM_SETUP1): Only define if
ROM or ROMRAM, not if STUBS which can be RAM.
 
2002-04-15 Jesper Skov <jskov@redhat.com>
 
* include/hal_platform_setup.h (PLATFORM_SETUP1): Changed ldm/stm
to ldmia/stmia.
 
2002-03-06 Jesper Skov <jskov@redhat.com>
 
* misc/redboot_ROM.ecm: Added zlib package.
 
2001-10-02 Jonathan Larmour <jlarmour@redhat.com>
 
* cdl/hal_arm_e7t.cdl (CYGBLD_BUILD_REDBOOT_BIN): cygtclsh80 on
Cygwin can't deal with absolute paths correctly, so copy
flash_cksum.tcl into build directory.
 
2001-07-02 Jesper Skov <jskov@redhat.com>
 
* src/hal_diag.c (cyg_hal_plf_serial_getc_nonblock): Ack RX
interrupt after reading.
 
* include/pkgconf/mlt_arm_e7t_ram.mlt: Reserve 64kB for RedBoot.
* include/pkgconf/mlt_arm_e7t_ram.ldi: Same.
 
* src/hal_diag.c: Make some data type fixes. Try to ack interrupt
after reading data. Unable to test though due to some other
problem on diag output.
 
2001-04-17 Jesper Skov <jskov@redhat.com>
 
* cdl/hal_arm_e7t.cdl: Fix compiler flags. In particular, do now
allow unaligned access since the CPU doesn't handle it.
 
* include/hal_platform_setup.h (PLATFORM_SETUP1): Use proper
spells to init memory interface.
 
* src/e7t_misc.c (hal_hardware_init): Removed debug code, fix
cache init code.
 
* include/plf_io.h: Use uncached addresses for IO registers.
 
* include/hal_platform_setup.h: Found a hint for problems with
memory init.
 
* include/hal_cache.h (HAL_UCACHE_INVALIDATE_ALL): Tried to make
this a bit faster. Didn't help much though.
 
* src/hal_diag.c (cyg_hal_plf_serial_init): Remove unused variable.
 
2001-04-16 Gary Thomas <gthomas@redhat.com>
 
* cdl/hal_arm_e7t.cdl: Add CDL to describe CPU family.
 
2001-04-11 Jesper Skov <jskov@redhat.com>
 
* src/e7t_misc.c (hal_delay_us): Fixed.
 
* include/pkgconf/mlt_arm_e7t_rom.ldi: Updated.
* include/pkgconf/mlt_arm_e7t_rom.mlt: Same.
* include/pkgconf/mlt_arm_e7t_rom.h: Same.
* include/pkgconf/mlt_arm_e7t_ram.ldi: Updated.
* include/pkgconf/mlt_arm_e7t_ram.mlt: Same.
* include/pkgconf/mlt_arm_e7t_ram.h: Same.
 
2001-04-05 Jesper Skov <jskov@redhat.com>
 
* misc/redboot_ROM.ecm: Only read from debug port.
 
* src/redboot_module.c: Fail if attempted built in wrong config.
 
* src/e7t_misc.c (hal_IRQ_handler): Fixed comparisons.
 
2001-03-19 Jesper Skov <jskov@redhat.com>
 
* src/e7t_misc.c (hal_delay_us): Made it work. Not sure why the
interrupts don't actually fire. This will probably break when that
gets sorted out later.
 
* src/hal_diag.c (cyg_hal_plf_serial_getc_nonblock): Rename a
register.
 
* src/e7t_misc.c (hal_hardware_init): Init caches, clear global
interrupt mask flag.
(hal_delay_us): Added.
 
* include/plf_io.h: Added cache definitions.
 
* include/hal_diag.h (HAL_DELAY_US): Added.
 
* include/hal_cache.h: Rewrote for KS32C50100.
 
* misc/redboot_ROM.ecm: Added.
 
* src/redboot_module.c: Added.
* src/gdb_module.c: Removed.
 
* src/e7t_misc.c: Comment out test code, but keep it around for
now.
 
* cdl/hal_arm_e7t.cdl: Added RedBoot build magic. Removed stubs
build magic.
 
* include/hal_platform_setup.h: Set PIO directions and IO
widths. The rest cannot be set wo hanging the board.
 
* src/hal_diag.c: Baud rate is computed from 1/2 core clock. All
register access is 32 bit. Added simple functions to print out
values without use of RAM.
Enabling TX/RX means allowing interrupts. Rely on vector mask only
for controlling ctrl-c interrupts.
 
2001-03-16 Jesper Skov <jskov@redhat.com>
 
* src/e7t_misc.c: Rewrote timer and interrupt code for
E7T. Removed reset code.
 
* include/plf_io.h: Added interrupt controller and timer
registers.
 
* include/hal_platform_ints.h: Updated interrupt defintions to
match E7T. No reset magic.
 
* src/hal_diag.c: Use correct interrupt definitions.
 
* Cloned from AEB HAL.
 
//===========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//===========================================================================
/src/flash_cksum.tcl
0,0 → 1,179
#!/bin/bash
# restart using a Tcl shell \
exec sh -c 'for tclshell in tclsh tclsh83 cygtclsh80 ; do \
( echo | $tclshell ) 2> /dev/null && exec $tclshell "`( cygpath -w \"$0\" ) 2> /dev/null || echo $0`" "$@" ; \
done ; \
echo "flash_cksum.tcl: cannot find Tcl shell" ; exit 1' "$0" "$@"
 
#===============================================================================
#
# flash_cksum.tcl
#
# Compute the checksum for a AEB-1 flash module
#
#===============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
#===============================================================================
######DESCRIPTIONBEGIN####
#
# Author(s): gthomas
# Contact(s): gthomas
# Date: 1999/01/06
# Version: 0.01 $RcsVersion$
# Purpose: Compute the checksum for a FLASH ROM module.
# Description:
# Requires: A working Tcl interpreter, V8.0 or later.
# Provides: Command line operation only.
# Inputs:
# Side FX:
# Outputs:
# See also: 'Notes' which describes the process of creating the GDB stubs
# module.
# Known bugs:
# Usage:
#
#####DESCRIPTIONEND####
#===============================================================================
 
#
# This ckecksum is the 32-bit XOR of all 32 bit words in the file.
# The output of the program is a single number, suitable for use in
# a Makefile/script used to create an AEB-1 module for FLASH ROM.
#
 
proc checksum { name } {
 
set status [ catch {
set fd [open $name "r"]
fconfigure $fd -translation binary
set data [read $fd]
close $fd
} message]
 
if { $status != 0 } {
puts "Unable to read file $name: $message"
exit 1
}
 
set sum 0
set length [string length $data]
for { set i 0 } { $i < $length } { incr i 4 } {
# Fetch the next 32 bit word. The funky tests are to handle the case
# of zero bytes.
set char0 [string index $data [expr $i + 0]]
if { "$char0" != "" } {
scan $char0 "%c" ascii0
} else {
set ascii0 0
}
set char1 [string index $data [expr $i + 1]]
if { "$char1" != "" } {
scan $char1 "%c" ascii1
} else {
set ascii1 0
}
set char2 [string index $data [expr $i + 2]]
if { "$char2" != "" } {
scan $char2 "%c" ascii2
} else {
set ascii2 0
}
set char3 [string index $data [expr $i + 3]]
if { "$char3" != "" } {
scan $char3 "%c" ascii3
} else {
set ascii3 0
}
set word [expr $ascii0 << 24]
set word [expr $word | [expr $ascii1 << 16]]
set word [expr $word | [expr $ascii2 << 8]]
set word [expr $word | $ascii3]
set sum [expr $sum ^ $word]
# puts "sum: [format %8.8X $sum], word: [format %8.8X $word]"
}
 
return $sum
}
 
proc bswap { native } {
set byte0 [expr [expr $native >> 24] & 255]
set byte1 [expr [expr $native >> 16] & 255]
set byte2 [expr [expr $native >> 8] & 255]
set byte3 [expr [expr $native >> 0] & 255]
set swapped [expr $byte3 << 24]
set swapped [expr $swapped | [expr $byte2 << 16]]
set swapped [expr $swapped | [expr $byte1 << 8]]
set swapped [expr $swapped | [expr $byte0 << 0]]
# puts "native: [format %8.8X $native], swapped: [format %8.8X $swapped]"
return $swapped
}
 
global tcl_platform
set byteOrder $tcl_platform(byteOrder)
# puts "platform byte order = $byteOrder"
 
# Parse command line arguments
set argc 0
array set args { }
foreach arg $argv {
set args([incr argc]) $arg
}
 
if { "$argc" != "1" } {
puts "usage: flash_cksum <file>"
exit 1
}
 
set cksum [checksum $args(1)]
 
# if { "$byteOrder" == "littleEndian" } {
# puts "Swap bytes!"
set cksum [bswap $cksum]
# }
 
# Tcl up to at least version 8.3 has problems on alphas,
# Tcl_FormatObjCmd() invokes Tcl_GetIntFromObj() which
# ends up doing dodgy conversions between int and long.
# This results in an error if bit 32 is set. Rewriting
# the format string to output one byte at a time is
# safer.
 
# puts "[format 0x%8.8X $cksum]"
 
puts [format "0x%02X%02X%02X%02X" \
[expr (($cksum >> 24) & 0x0FF)] \
[expr (($cksum >> 16) & 0x0FF)] \
[expr (($cksum >> 8) & 0x0FF)] \
[expr (($cksum ) & 0x0FF)]]
 
/src/redboot_module.c
0,0 → 1,133
//==========================================================================
//
// redboot_module.c
//
// ARM E7T board RedBoot module wrapper
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): gthomas
// Contributors: gthomas, jskov
// Date: 2001-03-19
// Description: AEB-2 FLASH module for RedBoot
//####DESCRIPTIONEND####
 
//
// This is the module 'wrapper' for RedBoot
//
 
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>
#include <cyg/hal/hal_stub.h>
 
// ARM AEB-2 module stuff
 
#ifdef CYGPKG_REDBOOT
 
#include <redboot.h>
 
#ifndef CHECKSUM
#define CHECKSUM 0x0
#endif
 
extern char __exception_handlers, __rom_data_end;
 
const char __title[] = "RedBoot";
const char __help[] = "RedBoot " __DATE__;
 
struct ModuleHeader {
cyg_uint32 magic;
cyg_uint16 flags;
cyg_uint8 major;
cyg_uint8 minor;
cyg_uint32 checksum;
cyg_uint32 ro_base;
cyg_uint32 ro_limit;
cyg_uint32 rw_base;
cyg_uint32 zi_base;
cyg_uint32 zi_limit;
cyg_uint32 self;
cyg_uint32 start;
cyg_uint32 init;
cyg_uint32 final;
cyg_uint32 service;
cyg_uint32 title;
cyg_uint32 help;
cyg_uint32 cmdtbl;
cyg_uint32 swi_base;
cyg_uint32 swi_handler;
};
 
const static struct ModuleHeader __hdr = {
0x4D484944, // MHID
2, // flags = auto start
1, // major
0, // minor
CHECKSUM, // checksum
(cyg_uint32) &__exception_handlers, // start of module (read-only) image
(cyg_uint32) &__rom_data_end, // end of image
0, // r/w base - unused
0, // bss base - unused
0, // bss limit - unused
(cyg_uint32) &__hdr, // self (for module identification)
(cyg_uint32) &__exception_handlers, // startup
0, // init - unused
0, // final - unused
0, // service - unused
(cyg_uint32) &__title, // title
(cyg_uint32) &__help, // help string
0, // command table - unused
0, // SWI table - unused
0 // SWI handler - unused
};
 
static void
__dummy(void *p)
{
}
 
void __dummy_init(void)
{
__dummy((void*)&__hdr);
}
 
_RedBoot_init(__dummy_init, RedBoot_INIT_LAST);
 
 
#else
#error "Stand-alone RedBoot only"
#endif
/src/hal_diag.c
0,0 → 1,376
/*=============================================================================
//
// hal_diag.c
//
// HAL diagnostic output code
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
// Contributors:jskov
// Date: 2001-03-16
// Purpose: HAL diagnostic output
// Description: Implementations of HAL diagnostic output support.
//
//####DESCRIPTIONEND####
//
//===========================================================================*/
 
#include <pkgconf/hal.h>
#include CYGBLD_HAL_PLATFORM_H
 
#include <cyg/infra/cyg_type.h> // base types
 
#include <cyg/hal/hal_arch.h> // SAVE/RESTORE GP macros
#include <cyg/hal/hal_io.h> // IO macros
#include <cyg/hal/hal_if.h> // interface API
#include <cyg/hal/hal_intr.h> // HAL_ENABLE/MASK/UNMASK_INTERRUPTS
#include <cyg/hal/hal_misc.h> // Helper functions
#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED
 
#include <cyg/hal/plf_io.h> // SIO registers
 
#define SIO_BRDDIV (((CYGNUM_HAL_ARM_E7T_CLOCK_SPEED/2/16/CYGNUM_HAL_VIRTUAL_VECTOR_CHANNELS_DEFAULT_BAUD)<<4))
 
//-----------------------------------------------------------------------------
typedef struct {
cyg_uint8* base;
cyg_int32 msec_timeout;
int isr_vector_rx;
int isr_vector_tx;
} channel_data_t;
 
//-----------------------------------------------------------------------------
 
char hextab[] = "0123456789ABCDEF";
 
void putc_ser(int c)
{
cyg_uint8* base = (cyg_uint8*)E7T_UART1_BASE;
cyg_uint32 status;
do {
HAL_READ_UINT32(base+E7T_UART_STAT, status);
} while ((status & E7T_UART_STAT_TXE) == 0);
 
HAL_WRITE_UINT32(base+E7T_UART_TXBUF, c);
}
 
void putint(int a)
{
int i;
putc_ser('0');
putc_ser('x');
for (i = 0; i < 8; i++) {
putc_ser(hextab[(a>>(28-(4*i))) & 0x0f]);
}
putc_ser('\r');
putc_ser('\n');
}
 
void
init_ser(void)
{
cyg_uint8* base = (cyg_uint8*)E7T_UART1_BASE;
 
// 8-1-no parity.
HAL_WRITE_UINT32(base+E7T_UART_LCON,
E7T_UART_LCON_8_DBITS|E7T_UART_LCON_1_SBITS|E7T_UART_LCON_NO_PARITY);
 
// Mask interrupts.
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_UART0_RX);
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_UART0_TX);
 
HAL_WRITE_UINT32(base+E7T_UART_BRDIV, SIO_BRDDIV);
}
 
//-----------------------------------------------------------------------------
 
static void
cyg_hal_plf_serial_init_channel(void* __ch_data)
{
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
 
// 8-1-no parity.
HAL_WRITE_UINT32(base+E7T_UART_LCON,
E7T_UART_LCON_8_DBITS|E7T_UART_LCON_1_SBITS|E7T_UART_LCON_NO_PARITY);
 
HAL_WRITE_UINT32(base+E7T_UART_BRDIV, SIO_BRDDIV);
 
// Mask interrupts
HAL_INTERRUPT_MASK(((channel_data_t*)__ch_data)->isr_vector_rx);
HAL_INTERRUPT_MASK(((channel_data_t*)__ch_data)->isr_vector_tx);
 
// Enable RX and TX
HAL_WRITE_UINT32(base+E7T_UART_CON, E7T_UART_CON_RXM_INT|E7T_UART_CON_TXM_INT);
}
 
void
cyg_hal_plf_serial_putc(void *__ch_data, char c)
{
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
cyg_uint32 status, ch;
CYGARC_HAL_SAVE_GP();
 
do {
HAL_READ_UINT32(base+E7T_UART_STAT, status);
} while ((status & E7T_UART_STAT_TXE) == 0);
 
ch = (cyg_uint32)c;
HAL_WRITE_UINT32(base+E7T_UART_TXBUF, ch);
 
CYGARC_HAL_RESTORE_GP();
}
 
static cyg_bool
cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
{
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_uint8* base = chan->base;
cyg_uint32 stat;
cyg_uint32 c;
 
HAL_READ_UINT32(base+E7T_UART_STAT, stat);
if ((stat & E7T_UART_STAT_RDR) == 0)
return false;
 
HAL_READ_UINT32(base+E7T_UART_RXBUF, c);
*ch = (cyg_uint8)(c & 0xff);
 
HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector_rx);
 
return true;
}
 
cyg_uint8
cyg_hal_plf_serial_getc(void* __ch_data)
{
cyg_uint8 ch;
CYGARC_HAL_SAVE_GP();
 
while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
 
CYGARC_HAL_RESTORE_GP();
return ch;
}
 
static void
cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
cyg_uint32 __len)
{
CYGARC_HAL_SAVE_GP();
 
while(__len-- > 0)
cyg_hal_plf_serial_putc(__ch_data, *__buf++);
 
CYGARC_HAL_RESTORE_GP();
}
 
static void
cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
{
CYGARC_HAL_SAVE_GP();
 
while(__len-- > 0)
*__buf++ = cyg_hal_plf_serial_getc(__ch_data);
 
CYGARC_HAL_RESTORE_GP();
}
 
cyg_bool
cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
{
int delay_count;
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_bool res;
CYGARC_HAL_SAVE_GP();
 
delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
 
for(;;) {
res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
if (res || 0 == delay_count--)
break;
CYGACC_CALL_IF_DELAY_US(100);
}
 
CYGARC_HAL_RESTORE_GP();
return res;
}
 
static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
int ret = 0;
CYGARC_HAL_SAVE_GP();
 
switch (__func) {
case __COMMCTL_IRQ_ENABLE:
irq_state = 1;
HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector_rx);
HAL_INTERRUPT_UNMASK(chan->isr_vector_rx);
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
HAL_INTERRUPT_MASK(chan->isr_vector_rx);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector_rx;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
 
va_start(ap, __func);
 
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
 
va_end(ap);
}
default:
break;
}
CYGARC_HAL_RESTORE_GP();
return ret;
}
 
static int
cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
int res = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_uint32 c;
cyg_uint8 ch;
cyg_uint32 stat;
CYGARC_HAL_SAVE_GP();
 
*__ctrlc = 0;
HAL_READ_UINT32(chan->base+E7T_UART_STAT, stat);
if ( (stat & E7T_UART_STAT_RDR) != 0 ) {
 
HAL_READ_UINT32(chan->base+E7T_UART_RXBUF, c);
ch = (cyg_uint8)(c & 0xff);
if( cyg_hal_is_break( &ch , 1 ) )
*__ctrlc = 1;
 
res = CYG_ISR_HANDLED;
}
 
HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector_rx);
 
CYGARC_HAL_RESTORE_GP();
return res;
}
 
static channel_data_t e7t_ser_channels[2] = {
{ (cyg_uint8*)E7T_UART0_BASE, 1000, CYGNUM_HAL_INTERRUPT_UART0_RX, CYGNUM_HAL_INTERRUPT_UART0_TX },
{ (cyg_uint8*)E7T_UART1_BASE, 1000, CYGNUM_HAL_INTERRUPT_UART1_RX, CYGNUM_HAL_INTERRUPT_UART1_TX }
};
 
static void
cyg_hal_plf_serial_init(void)
{
hal_virtual_comm_table_t* comm;
int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
 
// Init channels
cyg_hal_plf_serial_init_channel(&e7t_ser_channels[0]);
cyg_hal_plf_serial_init_channel(&e7t_ser_channels[1]);
 
// Setup procs in the vector table
 
// Set channel 0
CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &e7t_ser_channels[0]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
 
// Set channel 1
CYGACC_CALL_IF_SET_CONSOLE_COMM(1);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &e7t_ser_channels[1]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
 
// Restore original console
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
}
 
void
cyg_hal_plf_comms_init(void)
{
static int initialized = 0;
 
if (initialized)
return;
 
initialized = 1;
 
cyg_hal_plf_serial_init();
}
 
//-----------------------------------------------------------------------------
// LED
void
hal_diag_led(int mask)
{
cyg_uint32 l;
 
HAL_READ_UINT32(E7T_IOPDATA, l);
l &= ~0x000000f0;
l |= (mask & 0xf) << 4;
HAL_WRITE_UINT32(E7T_IOPDATA, l);
}
 
//-----------------------------------------------------------------------------
// End of hal_diag.c
/src/e7t_misc.c
0,0 → 1,261
//==========================================================================
//
// e7t_misc.c
//
// HAL misc board support code for ARM E7T
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): gthomas
// Contributors: gthomas, jskov
// Date: 2001-03-16
// Purpose: HAL board support
// Description: Implementations of HAL board interfaces
//
//####DESCRIPTIONEND####
//
//========================================================================*/
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h> // base types
#include <cyg/infra/cyg_trac.h> // tracing macros
#include <cyg/infra/cyg_ass.h> // assertion macros
 
#include <cyg/hal/hal_io.h> // IO macros
#include <cyg/hal/hal_arch.h> // Register state info
#include <cyg/hal/hal_diag.h>
#include <cyg/hal/hal_intr.h> // necessary?
#include <cyg/hal/hal_cache.h>
#include <cyg/hal/hal_if.h> // calling interface
#include <cyg/hal/hal_misc.h> // helper functions
#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
#include <cyg/hal/drv_api.h> // HAL ISR support
#endif
#include <cyg/hal/plf_io.h> // platform registers
 
static cyg_uint32 _period;
 
#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
static cyg_interrupt abort_interrupt;
static cyg_handle_t abort_interrupt_handle;
 
// This ISR is called only for the Abort button interrupt
static int
e7t_abort_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs)
{
cyg_hal_user_break((CYG_ADDRWORD*)regs);
cyg_drv_interrupt_acknowledge(CYGNUM_HAL_INTERRUPT_EXT0);
return 0; // No need to run DSR
}
#endif
 
void hal_clock_initialize(cyg_uint32 period)
{
cyg_uint32 tmod;
 
// Disable timer 0
HAL_READ_UINT32(E7T_TMOD, tmod);
tmod &= ~(E7T_TMOD_TE0);
HAL_WRITE_UINT32(E7T_TMOD, 0);
 
tmod &= ~(E7T_TMOD_TMD0 | E7T_TMOD_TCLR0);
tmod |= E7T_TMOD_TE0;
 
// Set counter
HAL_WRITE_UINT32(E7T_TDATA0, period);
 
// And enable timer
HAL_WRITE_UINT32(E7T_TMOD, tmod);
 
_period = period;
 
#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_EXT0,
99, // Priority
0, // Data item passed to interrupt handler
e7t_abort_isr,
0,
&abort_interrupt_handle,
&abort_interrupt);
cyg_drv_interrupt_attach(abort_interrupt_handle);
cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_EXT0);
#endif
}
 
void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
{
_period = period;
}
 
void hal_clock_read(cyg_uint32 *pvalue)
{
cyg_uint32 value;
 
HAL_READ_UINT32(E7T_TCNT0, value);
*pvalue = _period - value;
}
 
// -------------------------------------------------------------------------
//
// Delay for some number of micro-seconds
//
void hal_delay_us(cyg_int32 usecs)
{
cyg_uint32 count;
cyg_uint32 ticks = ((CYGNUM_HAL_RTC_PERIOD*CYGNUM_HAL_RTC_DENOMINATOR)/1000000) * usecs;
cyg_uint32 tmod;
 
// Disable timer 1
HAL_READ_UINT32(E7T_TMOD, tmod);
tmod &= ~(E7T_TMOD_TE1);
HAL_WRITE_UINT32(E7T_TMOD, tmod);
 
tmod &= ~(E7T_TMOD_TMD1 | E7T_TMOD_TCLR1);
tmod |= E7T_TMOD_TE1;
 
// Clear pending flag
HAL_WRITE_UINT32(E7T_INTPND, (1 << CYGNUM_HAL_INTERRUPT_TIMER1));
 
// Set counter
HAL_WRITE_UINT32(E7T_TDATA1, ticks);
 
// And enable timer
HAL_WRITE_UINT32(E7T_TMOD, tmod);
 
// Wait for timer to underflow. Can't test the timer completion
// bit without actually enabling the interrupt. So instead watch
// the counter.
ticks /= 2; // wait for this threshold
 
// Wait till timer counts below threshold
do {
HAL_READ_UINT32(E7T_TCNT1, count);
} while (count >= ticks);
// then wait for it to be reloaded
do {
HAL_READ_UINT32(E7T_TCNT1, count);
} while (count < ticks);
 
// Then disable timer 1 again
tmod &= ~E7T_TMOD_TE1;
HAL_WRITE_UINT32(E7T_TMOD, tmod);
}
 
// -------------------------------------------------------------------------
// Hardware init
void hal_hardware_init(void)
{
cyg_uint32 intmask;
 
// Set up eCos/ROM interfaces
hal_if_init();
 
// Enable cache
HAL_WRITE_UINT32(E7T_SYSCFG,
0x07FFFF80|E7T_SYSCFG_CM_0R_8C|E7T_SYSCFG_WE);
HAL_UCACHE_INVALIDATE_ALL();
HAL_UCACHE_ENABLE();
 
// Clear global interrupt mask bit
HAL_READ_UINT32(E7T_INTMSK, intmask);
intmask &= ~E7T_INTMSK_GLOBAL;
HAL_WRITE_UINT32(E7T_INTMSK, intmask);
}
 
//
// This routine is called to respond to a hardware interrupt (IRQ). It
// should interrogate the hardware and return the IRQ vector number.
 
int hal_IRQ_handler(void)
{
// Do hardware-level IRQ handling
cyg_uint32 irq_status;
HAL_READ_UINT32(E7T_INTOFFSET_IRQ, irq_status);
irq_status = irq_status / 4;
if (CYGNUM_HAL_ISR_MAX >= irq_status)
return irq_status;
// It's a bit bogus to test for FIQs after IRQs, but we use the
// latter more, so don't impose the overhead of checking for FIQs
HAL_READ_UINT32(E7T_INTOFFSET_FIQ, irq_status);
irq_status = irq_status / 4;
if (CYGNUM_HAL_ISR_MAX >= irq_status)
return irq_status;
return CYGNUM_HAL_INTERRUPT_NONE;
}
 
//
// Interrupt control
//
 
void hal_interrupt_mask(int vector)
{
cyg_uint32 mask, old_mask;
HAL_READ_UINT32(E7T_INTMSK, mask);
old_mask = mask;
mask |= (1<<vector);
HAL_WRITE_UINT32(E7T_INTMSK, mask);
}
 
void hal_interrupt_unmask(int vector)
{
cyg_uint32 mask, old_mask;
HAL_READ_UINT32(E7T_INTMSK, mask);
old_mask = mask;
mask &= ~(1<<vector);
HAL_WRITE_UINT32(E7T_INTMSK, mask);
}
 
void hal_interrupt_acknowledge(int vector)
{
HAL_WRITE_UINT32(E7T_INTPND, (1<<vector));
}
 
void hal_interrupt_configure(int vector, int level, int up)
{
}
 
void hal_interrupt_set_level(int vector, int level)
{
}
 
void hal_show_IRQ(int vector, int data, int handler)
{
}
 
//--------------------------------------------------------------------------
// EOF hal_misc.c
/misc/redboot_ROM.ecm
0,0 → 1,95
cdl_savefile_version 1;
cdl_savefile_command cdl_savefile_version {};
cdl_savefile_command cdl_savefile_command {};
cdl_savefile_command cdl_configuration { description hardware template package };
cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
 
cdl_configuration eCos {
description "" ;
hardware e7t ;
template redboot ;
package -hardware CYGPKG_HAL_ARM v2_0 ;
package -hardware CYGPKG_HAL_ARM_E7T v2_0 ;
package -hardware CYGPKG_IO_SERIAL_ARM_E7T v2_0 ;
package -template CYGPKG_HAL v2_0 ;
package -template CYGPKG_INFRA v2_0 ;
package -template CYGPKG_REDBOOT v2_0 ;
package -template CYGPKG_ISOINFRA v2_0 ;
package -template CYGPKG_LIBC_STRING v2_0 ;
package -template CYGPKG_NS_DNS v2_0 ;
package CYGPKG_MEMALLOC v2_0 ;
package CYGPKG_COMPRESS_ZLIB v2_0 ;
};
 
cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
inferred_value 0
};
 
cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
user_value 4096
};
 
cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
user_value 0
};
 
cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
inferred_value 0
};
 
cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
inferred_value 1
};
 
cdl_option CYGSEM_HAL_ROM_MONITOR {
inferred_value 1
};
 
cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
inferred_value 0 0
};
 
cdl_component CYG_HAL_STARTUP {
user_value ROM
};
 
cdl_component CYGBLD_BUILD_REDBOOT {
user_value 1
};
 
cdl_option CYGPKG_REDBOOT_ANY_CONSOLE {
user_value 0
};
 
cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
inferred_value 1 <cyg/libc/string/bsdstring.h>
};
 
cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_DNS_HEADER {
inferred_value 1 <cyg/ns/dns/dns.h>
};
 
cdl_option CYGPKG_NS_DNS_BUILD {
inferred_value 0
};
 
 

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