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    /openrisc/trunk/rtos/ecos-2.0/packages/hal/arm/snds
    from Rev 27 to Rev 174
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  •

Rev 27 → Rev 174

/v2_0/cdl/hal_arm_snds.cdl
0,0 → 1,389
#==========================================================================
#
# hal_arm_snds.cdl
#
#
#
#==========================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
#==========================================================================
######DESCRIPTIONBEGIN####
#
# Author(s): gthomas
# Contributors: gthomas, jskov
# Grant Edwards <grante@visi.com>
# Date: 2001-07-31
# Purpose:
# Description:
#
#####DESCRIPTIONEND####
#
#========================================================================*/
 
 
cdl_package CYGPKG_HAL_ARM_SNDS {
display "Samsung SNDS Evaluation Board"
parent CYGPKG_HAL_ARM
define_header hal_arm_snds.h
include_dir cyg/hal
hardware
description "
The SNDS HAL package provides the support needed to run
eCos on a Samsung SNDS Eval board"
 
compile hal_diag.c snds100_misc.c
 
implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
implements CYGINT_HAL_DEBUG_GDB_STUBS
implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
implements CYGINT_HAL_ARM_ARCH_ARM7
implements CYGINT_HAL_ARM_THUMB_ARCH
# FIXME: Add endian option
 
define_proc {
puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_arm.h>"
puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_snds.h>"
puts $::cdl_header ""
puts $::cdl_header "#define HAL_PLATFORM_CPU \"ARM 7TDMI\""
puts $::cdl_header "#define HAL_PLATFORM_BOARD \"Samsung SNDS\""
puts $::cdl_header "#define HAL_PLATFORM_EXTRA \"\""
puts $::cdl_header ""
}
 
cdl_component CYG_HAL_STARTUP {
display "Startup type"
flavor data
legal_values {"RAM" "ROM"}
default_value {"RAM"}
no_define
define -file system.h CYG_HAL_STARTUP
description "
When targetting the SNDS board it is possible to build
the system for either RAM bootstrap or ROM bootstrap.
RAM bootstrap generally requires that the board
is equipped with ROMs containing a suitable ROM monitor or
equivalent software that allows GDB to download the eCos
application on to the board. The ROM bootstrap typically
requires that the eCos application be blown into EPROMs or
equivalent technology."
}
cdl_component CYG_HAL_CPUTYPE {
display "cpu type"
flavor data
legal_values {"KS32C5000A" "S3C4510A"}
default_value {"S3C4510A"}
no_define
define -file system.h CYG_HAL_CPUTYPE
description "Which version of processor is on board."
}
cdl_component CYGNUM_HAL_CPUCLOCK {
display "cpu clock"
flavor data
legal_values 10000000 to 100000000
default_value 50000000
no_define
define -file system.h CYGNUM_HAL_CPUCLOCK
description "Frequency of cpu clock in Hz."
}
 
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
display "Number of diag/debug communication channels on the board"
flavor data
calculated 2
}
 
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT {
display "Default console channel."
flavor data
legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
calculated 0
}
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
display "Debug serial port"
flavor data
legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
default_value 0
description "The SNDS board has two diag/debug
serial ports. This option chooses which port will
be used to connect to a host running GDB."
}
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
display "Diagnostic serial port"
flavor data
legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
description "
The SNDS board has two diag/debug serial ports. This option
chooses which port will be used for diagnostic output."
}
 
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CHANNELS_DEFAULT_BAUD {
display "Console/GDB serial port baud rate"
flavor data
legal_values 9600 19200 38400 57600 115200
default_value 38400
description "
This option controls the default baud rate used for the
Console/GDB connection."
}
 
# Real-time clock/counter specifics
cdl_component CYGNUM_HAL_RTC_CONSTANTS {
display "Real-time clock constants"
flavor none
cdl_option CYGNUM_HAL_RTC_NUMERATOR {
display "Real-time clock numerator"
flavor data
calculated 1000000000
}
cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
display "Real-time clock denominator"
flavor data
calculated 100
}
cdl_option CYGNUM_HAL_RTC_PERIOD {
display "Real-time clock period"
flavor data
calculated (CYGNUM_HAL_CPUCLOCK/CYGNUM_HAL_RTC_DENOMINATOR)
}
}
 
cdl_component CYGBLD_GLOBAL_OPTIONS {
display "Global build options"
flavor none
parent CYGPKG_NONE
description "
Global build options including control over
compiler flags, linker flags and choice of toolchain."
 
cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
display "Global command prefix"
flavor data
no_define
default_value { "arm-elf" }
description "
This option specifies the command prefix used when
invoking the build tools."
}
 
cdl_option CYGBLD_GLOBAL_CFLAGS {
display "Global compiler flags"
flavor data
no_define
if {1} {
default_value { (CYGHWR_THUMB && CYGHWR_HAL_ARM_BIGENDIAN) ? "-mthumb-interwork -mbig-endian -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" :
CYGHWR_THUMB ? "-mthumb-interwork -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" :
(CYGHWR_HAL_ARM_CPU_FAMILY == "ARM9") && CYGHWR_HAL_ARM_BIGENDIAN ? "-mcpu=arm9 -mbig-endian -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" :
(CYGHWR_HAL_ARM_CPU_FAMILY == "ARM9") && ! CYGHWR_HAL_ARM_BIGENDIAN ? "-mcpu=arm9 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" :
(CYGHWR_HAL_ARM_CPU_FAMILY != "ARM9") && CYGHWR_HAL_ARM_BIGENDIAN ? "-mcpu=arm7tdmi -mbig-endian -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" :
"-mcpu=arm7tdmi -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
} else {
default_value { (CYGHWR_HAL_ARM_CPU_FAMILY == "ARM9") && CYGHWR_HAL_ARM_BIGENDIAN ? "-mcpu=arm9 -mbig-endian -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" :
(CYGHWR_HAL_ARM_CPU_FAMILY == "ARM9") && ! CYGHWR_HAL_ARM_BIGENDIAN ? "-mcpu=arm9 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" :
(CYGHWR_HAL_ARM_CPU_FAMILY != "ARM9") && CYGHWR_HAL_ARM_BIGENDIAN ? "-mcpu=arm7tdmi -mbig-endian -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" :
"-mcpu=arm7tdmi -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
}
description "
This option controls the global compiler flags which are used to
compile all packages by default. Individual packages may define
options which override these global flags."
}
 
cdl_option CYGBLD_GLOBAL_LDFLAGS {
display "Global linker flags"
flavor data
no_define
if {1} {
default_value { (CYGHWR_THUMB && CYGHWR_HAL_ARM_BIGENDIAN) ? "-mthumb-interwork -mbig-endian -g -nostdlib -Wl,--gc-sections -Wl,-static" :
CYGHWR_THUMB ? "-mthumb-interwork -g -nostdlib -Wl,--gc-sections -Wl,-static" :
(CYGHWR_HAL_ARM_CPU_FAMILY == "ARM9") && CYGHWR_HAL_ARM_BIGENDIAN ? "-mcpu=arm9 -mbig-endian -g -nostdlib -Wl,--gc-sections -Wl,-static" :
(CYGHWR_HAL_ARM_CPU_FAMILY == "ARM9") && ! CYGHWR_HAL_ARM_BIGENDIAN ? "-mcpu=arm9 -g -nostdlib -Wl,--gc-sections -Wl,-static" :
(CYGHWR_HAL_ARM_CPU_FAMILY != "ARM9") && CYGHWR_HAL_ARM_BIGENDIAN ? "-mcpu=arm7tdmi -mbig-endian -g -nostdlib -Wl,--gc-sections -Wl,-static" :
"-mcpu=arm7tdmi -g -nostdlib -Wl,--gc-sections -Wl,-static" }
} else {
default_value { (CYGHWR_HAL_ARM_CPU_FAMILY == "ARM9") && CYGHWR_HAL_ARM_BIGENDIAN ? "-mcpu=arm9 -mbig-endian -g -nostdlib -Wl,--gc-sections -Wl,-static" :
(CYGHWR_HAL_ARM_CPU_FAMILY == "ARM9") && ! CYGHWR_HAL_ARM_BIGENDIAN ? "-mcpu=arm9 -g -nostdlib -Wl,--gc-sections -Wl,-static" :
(CYGHWR_HAL_ARM_CPU_FAMILY != "ARM9") && CYGHWR_HAL_ARM_BIGENDIAN ? "-mcpu=arm7tdmi -mbig-endian -g -nostdlib -Wl,--gc-sections -Wl,-static" :
"-mcpu=arm7tdmi -g -nostdlib -Wl,--gc-sections -Wl,-static" }
}
description "
This option controls the global linker flags. Individual
packages may define options which override these global flags."
}
cdl_option CYGBLD_BUILD_GDB_STUBS {
display "Build GDB stub ROM image"
default_value 0
requires { CYG_HAL_STARTUP == "ROM" }
requires CYGSEM_HAL_ROM_MONITOR
requires CYGBLD_BUILD_COMMON_GDB_STUBS
requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
no_define
description "
This option enables the building of the GDB stubs for the
board. The common HAL controls takes care of most of the
build process, but the final conversion from ELF image to
binary data is handled by the platform CDL, allowing
relocation of the data if necessary."
 
make -priority 320 {
<PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img
$(OBJCOPY) -O binary $< $@
}
}
}
 
cdl_component CYGHWR_MEMORY_LAYOUT {
display "Memory layout"
flavor data
no_define
calculated { CYG_HAL_STARTUP == "RAM" ? "arm_snds_ram" : \
"arm_snds_rom" }
cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
display "Memory layout linker script fragment"
flavor data
no_define
define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_arm_snds_ram.ldi>" : \
"<pkgconf/mlt_arm_snds_rom.ldi>"}
}
 
cdl_option CYGHWR_MEMORY_LAYOUT_H {
display "Memory layout header file"
flavor data
no_define
define -file system.h CYGHWR_MEMORY_LAYOUT_H
calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_arm_snds_ram.h>" : \
"<pkgconf/mlt_arm_snds_rom.h>"}
}
}
 
 
cdl_option CYGSEM_HAL_ROM_MONITOR {
display "Behave as a ROM monitor"
flavor bool
default_value 0
parent CYGPKG_HAL_ROM_MONITOR
requires { CYG_HAL_STARTUP == "ROM" }
description "
Enable this option if this program is to be used as a ROM monitor,
i.e. applications will be loaded into RAM on the board, and this
ROM monitor may process exceptions or interrupts generated from the
application. This enables features such as utilizing a separate
interrupt stack when exceptions are generated."
}
 
cdl_component CYGPKG_CYGMON_HAL_OPTIONS {
display "CygMon HAL options"
flavor none
no_define
parent CYGPKG_CYGMON
active_if CYGPKG_CYGMON
requires CYGPKG_IO_SERIAL_ARM_SNDS
requires {(CYGDAT_CYGMON_CONSOLE_DEV != "\"/dev/ser0\"") || \
(CYGPKG_IO_SERIAL_ARM_SNDS_SERIAL0 && \
(CYGNUM_IO_SERIAL_ARM_SNDS_SERIAL0_BUFSIZE == 512))}
requires {(CYGDAT_CYGMON_CONSOLE_DEV != "\"/dev/ser1\"") || \
(CYGPKG_IO_SERIAL_ARM_SNDS_SERIAL1 && \
(CYGNUM_IO_SERIAL_ARM_SNDS_SERIAL1_BUFSIZE == 512))}
description "
This option also lists the target's requirements for a valid CygMon
configuration."
 
 
cdl_option CYGDAT_CYGMON_CONSOLE_DEV {
display "Serial port for default console"
flavor data
default_value { "\"/dev/ser0\"" }
description "
This option selects the physical device to use as the default
console device for CygMon."
 
}
 
cdl_option CYGBLD_BUILD_CYGMON_BIN {
display "Build CygMon ROM binary image"
active_if CYGBLD_BUILD_CYGMON
default_value 1
no_define
description "This option enables the conversion of the CygMon ELF
image to a binary image suitable for ROM programming."
make -priority 325 {
<PREFIX>/bin/cygmon.bin : <PREFIX>/bin/cygmon.elf
$(OBJCOPY) --strip-debug --change-addresses=0xFC060000 $< $(@:.bin=.img)
$(OBJCOPY) -O srec $< $(@:.bin=.srec)
$(OBJCOPY) -O binary $< $@
}
}
}
 
cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
display "Redboot HAL options"
flavor none
no_define
parent CYGPKG_REDBOOT
active_if CYGPKG_REDBOOT
description "
This option lists the target's requirements for a valid Redboot
configuration."
 
cdl_option CYGBLD_BUILD_REDBOOT_BIN {
display "Build Redboot ROM binary image"
active_if CYGBLD_BUILD_REDBOOT
default_value 1
no_define
description "This option enables the conversion of the Redboot ELF
image to a binary image suitable for ROM programming."
make -priority 325 {
<PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
$(OBJCOPY) --strip-debug $< $(@:.bin=.img)
$(OBJCOPY) -O srec $< $(@:.bin=.srec)
$(OBJCOPY) -O binary $< $@
}
}
}
 
}
/v2_0/include/plf_stub.h
0,0 → 1,77
//==========================================================================
//
// plf_stub.h
//
//
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): gthomas
// Contributors: gthomas, jskov
// Grant Edwards <grante@visi.com>
// Date: 2001-07-31
// Purpose:
// Description:
//
//####DESCRIPTIONEND####
//
//========================================================================*/
 
#ifndef CYGONCE_HAL_PLF_STUB_H
#define CYGONCE_HAL_PLF_STUB_H
 
#include <pkgconf/hal.h>
 
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM
#include <cyg/hal/arm_stub.h> // architecture stub support
// Define serial stuff.
externC void cyg_hal_plf_comms_init(void);
#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init()
#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud))
#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0
#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT
// Stub initializer.
#define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT
#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 
// Reset.
externC void hal_reset(void);
#define HAL_STUB_PLATFORM_RESET() hal_reset()
#define HAL_STUB_PLATFORM_RESET_ENTRY 0
 
#endif // CYGONCE_HAL_PLF_STUB_H
/v2_0/include/pkgconf/mlt_arm_snds_rom.h
0,0 → 1,20
// eCos memory layout - Wed Apr 11 13:49:55 2001
 
// This is a generated file - do not edit
 
#ifndef __ASSEMBLER__
#include <cyg/infra/cyg_type.h>
#include <stddef.h>
 
#endif
#define CYGMEM_REGION_ram (0)
#define CYGMEM_REGION_ram_SIZE (0x1000000)
#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
#define CYGMEM_REGION_rom (0x1800000)
#define CYGMEM_REGION_rom_SIZE (0x80000)
#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__heap1) [];
#endif
#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
#define CYGMEM_SECTION_heap1_SIZE (0x1000000 - (size_t) CYG_LABEL_NAME (__heap1))
/v2_0/include/pkgconf/mlt_arm_snds_rom.ldi
0,0 → 1,28
// eCos memory layout - Wed Apr 11 13:49:55 2001
 
// This is a generated file - do not edit
 
#include <cyg/infra/cyg_type.inc>
 
MEMORY
{
ram : ORIGIN = 0, LENGTH = 0x1000000
rom : ORIGIN = 0x1800000, LENGTH = 0x80000
}
 
SECTIONS
{
SECTIONS_BEGIN
SECTION_rom_vectors (rom, 0x1800000, LMA_EQ_VMA)
SECTION_text (rom, ALIGN (0x1), LMA_EQ_VMA)
SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA)
SECTION_data (ram, 0x20000, FOLLOWING (.gcc_except_table))
SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
SECTIONS_END
}
/v2_0/include/pkgconf/mlt_arm_snds_ram.h
0,0 → 1,15
// eCos memory layout - Tue Feb 29 14:11:30 2000
 
// This is a generated file - do not edit
 
#include <cyg/infra/cyg_type.h>
#include <stddef.h>
 
#define CYGMEM_REGION_ram (0)
#define CYGMEM_REGION_ram_SIZE (0x01000000)
#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__heap1) [];
#endif
#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
#define CYGMEM_SECTION_heap1_SIZE (0x01000000 - (size_t) CYG_LABEL_NAME (__heap1))
/v2_0/include/pkgconf/mlt_arm_snds_ram.ldi
0,0 → 1,27
// eCos memory layout - Tue Feb 29 14:11:30 2000
 
// This is a generated file - do not edit
 
#include <cyg/infra/cyg_type.inc>
 
MEMORY
{
ram : ORIGIN = 0x000000, LENGTH = 0x01000000
}
 
SECTIONS
{
SECTIONS_BEGIN
SECTION_fixed_vectors (ram, 0x200, LMA_EQ_VMA)
SECTION_rom_vectors (ram, 0x00020000, LMA_EQ_VMA)
SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata1 (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_data (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
SECTIONS_END
}
/v2_0/include/pkgconf/mlt_arm_snds_rom.mlt
0,0 → 1,15
version 0
region ram 0 1000000 0 !
region rom 1800000 80000 1 !
section fixed_vectors 0 1 0 1 1 0 1 0 20 20 !
section data 0 1 1 1 1 1 0 0 1000000 bss !
section bss 0 4 0 1 0 1 0 1 heap1 heap1 !
section heap1 0 8 0 0 0 0 0 0 !
section reserved_bootmon 20000 1 0 0 1 1 1 1 1800000 1800000 rom_vectors rom_vectors !
section rom_vectors 0 8 0 1 0 1 0 1 text text !
section text 0 1 0 1 0 1 0 1 fini fini !
section fini 0 4 0 1 0 1 0 1 rodata rodata !
section rodata 0 4 0 1 0 1 0 1 rodata1 rodata1 !
section rodata1 0 4 0 1 0 1 0 1 fixup fixup !
section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
section gcc_except_table 0 4 0 1 0 0 0 1 data !
/v2_0/include/pkgconf/mlt_arm_snds_ram.mlt
0,0 → 1,13
version 0
region ram 0 1000000 0 !
section fixed_vectors 0 1 0 1 1 0 1 0 20 20 !
section rom_vectors 0 1 0 1 1 1 1 1 20000 20000 text text !
section text 0 4 0 1 0 1 0 1 fini fini !
section fini 0 4 0 1 0 1 0 1 rodata rodata !
section rodata 0 4 0 1 0 1 0 1 rodata1 rodata1 !
section rodata1 0 4 0 1 0 1 0 1 fixup fixup !
section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
section gcc_except_table 0 4 0 1 0 1 0 1 data data !
section data 0 4 0 1 0 1 0 1 bss bss !
section bss 0 4 0 1 0 1 0 1 heap1 heap1 !
section heap1 0 8 0 0 0 0 0 0 !
/v2_0/include/hal_platform_ints.h
0,0 → 1,108
#ifndef CYGONCE_HAL_PLATFORM_INTS_H
#define CYGONCE_HAL_PLATFORM_INTS_H
//==========================================================================
//
// hal_platform_ints.h
//
//
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): gthomas
// Contributors: gthomas, jskov
// Grant Edwards <grante@visi.com>
// Date: 2001-07-31
// Purpose:
// Description:
//
//####DESCRIPTIONEND####
//
//========================================================================*/
 
#define CYGNUM_HAL_INTERRUPT_EXT0 0
#define CYGNUM_HAL_INTERRUPT_EXT1 1
#define CYGNUM_HAL_INTERRUPT_EXT2 2
#define CYGNUM_HAL_INTERRUPT_EXT3 3
#define CYGNUM_HAL_INTERRUPT_UART0_TX 4
#define CYGNUM_HAL_INTERRUPT_UART0_RX 5
#if !defined(CYG_HAL_CPUTYPE)
#error CYG_HAL_CPUTYPE not defined
#endif
#if defined(CYG_HAL_CPUTYPE_KS32C5000A)
#define CYGNUM_HAL_INTERRUPT_UART0_ERR 6
#define CYGNUM_HAL_INTERRUPT_UART1_TX 7
#define CYGNUM_HAL_INTERRUPT_UART1_RX 8
#define CYGNUM_HAL_INTERRUPT_UART1_ERR 9
#define CYGNUM_HAL_INTERRUPT_DMA0 10
#define CYGNUM_HAL_INTERRUPT_DMA1 11
#define CYGNUM_HAL_INTERRUPT_TIMER0 12
#define CYGNUM_HAL_INTERRUPT_TIMER1 13
#define CYGNUM_HAL_INTERRUPT_HDLCA 14
#define CYGNUM_HAL_INTERRUPT_HDLCB 15
#else
#define CYGNUM_HAL_INTERRUPT_UART1_TX 6
#define CYGNUM_HAL_INTERRUPT_UART1_RX 7
#define CYGNUM_HAL_INTERRUPT_DMA0 8
#define CYGNUM_HAL_INTERRUPT_DMA1 9
#define CYGNUM_HAL_INTERRUPT_TIMER0 10
#define CYGNUM_HAL_INTERRUPT_TIMER1 11
#define CYGNUM_HAL_INTERRUPT_HDLCA_TX 12
#define CYGNUM_HAL_INTERRUPT_HDLCA_RX 13
#define CYGNUM_HAL_INTERRUPT_HDLCB_TX 14
#define CYGNUM_HAL_INTERRUPT_HDLCB_RX 15
#endif
#define CYGNUM_HAL_INTERRUPT_ETH_BDMA_TX 16
#define CYGNUM_HAL_INTERRUPT_ETH_BDMA_RX 17
#define CYGNUM_HAL_INTERRUPT_ETH_MAC_TX 18
#define CYGNUM_HAL_INTERRUPT_ETH_MAC_RX 19
#define CYGNUM_HAL_INTERRUPT_I2C 20
 
#define CYGNUM_HAL_ISR_MIN 0
#define CYGNUM_HAL_ISR_MAX 20
#define CYGNUM_HAL_ISR_COUNT 21
 
// The vector used by the Real time clock
 
#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER0
 
//----------------------------------------------------------------------------
// Reset.
#define HAL_PLATFORM_RESET()
 
#define HAL_PLATFORM_RESET_ENTRY 0x01010000
 
#endif // CYGONCE_HAL_PLATFORM_INTS_H
/v2_0/include/hal_cache.h
0,0 → 1,291
#ifndef CYGONCE_HAL_CACHE_H
#define CYGONCE_HAL_CACHE_H
//=============================================================================
//
// hal_cache.h
//
// HAL cache control API
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg, gthomas
// Contributors: nickg, gthomas
// Date: 1998-09-28
// Purpose: Cache control API
// Description: The macros defined here provide the HAL APIs for handling
// cache control operations.
// Usage:
// #include <cyg/hal/hal_cache.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <cyg/infra/cyg_type.h>
#include <cyg/hal/hal_io.h>
#include <cyg/hal/plf_io.h>
 
//-----------------------------------------------------------------------------
// Cache dimensions - one unified cache
 
#define HAL_CACHE_UNIFIED
 
#define HAL_UCACHE_SIZE 0x2000 // Size of cache in bytes
#define HAL_UCACHE_LINE_SIZE 16 // Size of a cache line
#define HAL_UCACHE_WAYS 2 // Associativity of the cache
 
#define HAL_UCACHE_SETS (HAL_UCACHE_SIZE/(HAL_UCACHE_LINE_SIZE*HAL_UCACHE_WAYS))
 
//-----------------------------------------------------------------------------
// Global control of cache
 
// Enable the cache
#define HAL_UCACHE_ENABLE() \
CYG_MACRO_START \
cyg_uint32 syscfg; \
HAL_READ_UINT32(KS32C_SYSCFG, syscfg); \
syscfg |= KS32C_SYSCFG_CE; \
HAL_WRITE_UINT32(KS32C_SYSCFG, syscfg); \
CYG_MACRO_END
 
// Disable the cache
#define HAL_UCACHE_DISABLE() \
CYG_MACRO_START \
cyg_uint32 syscfg; \
HAL_READ_UINT32(KS32C_SYSCFG, syscfg); \
syscfg &= ~KS32C_SYSCFG_CE; \
HAL_WRITE_UINT32(KS32C_SYSCFG, syscfg); \
CYG_MACRO_END
 
// Invalidate the entire cache
#define HAL_UCACHE_INVALIDATE_ALL() \
CYG_MACRO_START \
register cyg_uint32* tag = (cyg_uint32*)KS32C_CACHE_TAG_ADDR; \
register int i; \
for (i = 0; i < HAL_UCACHE_SETS/4; i++) { \
*tag++ = 0; \
*tag++ = 0; \
*tag++ = 0; \
*tag++ = 0; \
} \
CYG_MACRO_END
 
// Synchronize the contents of the cache with memory.
// No action necessary. Cache is write-through.
#define HAL_UCACHE_SYNC()
 
// Query the state of the cache
#define HAL_UCACHE_IS_ENABLED(_state_) \
CYG_MACRO_START \
cyg_uint32 syscfg; \
HAL_READ_UINT32(KS32C_SYSCFG, syscfg); \
(_state_) = (syscfg & KS32C_SYSCFG_CE) ? 1 : 0; \
CYG_MACRO_END
 
// Purge contents of cache
#define HAL_UCACHE_PURGE_ALL() HAL_UCACHE_INVALIDATE_ALL()
 
// Set the cache refill burst size
//#define HAL_UCACHE_BURST_SIZE(_size_)
 
// Set the cache write mode
//#define HAL_UCACHE_WRITE_MODE( _mode_ )
 
//#define HAL_UCACHE_WRITETHRU_MODE 0
//#define HAL_UCACHE_WRITEBACK_MODE 1
 
// Load the contents of the given address range into the cache
// and then lock the cache so that it stays there.
//#define HAL_UCACHE_LOCK(_base_, _size_)
 
// Undo a previous lock operation
//#define HAL_UCACHE_UNLOCK(_base_, _size_)
 
// Unlock entire cache
//#define HAL_UCACHE_UNLOCK_ALL()
 
//-----------------------------------------------------------------------------
// Cache line control
 
// Allocate cache lines for the given address range without reading its
// contents from memory.
//#define HAL_UCACHE_ALLOCATE( _base_ , _size_ )
 
// Write dirty cache lines to memory and invalidate the cache entries
// for the given address range.
//#define HAL_UCACHE_FLUSH( _base_ , _size_ )
 
// Invalidate cache lines in the given range without writing to memory.
//#define HAL_UCACHE_INVALIDATE( _base_ , _size_ )
 
// Write dirty cache lines to memory for the given address range.
//#define HAL_UCACHE_STORE( _base_ , _size_ )
 
// Preread the given range into the cache with the intention of reading
// from it later.
//#define HAL_UCACHE_READ_HINT( _base_ , _size_ )
 
// Preread the given range into the cache with the intention of writing
// to it later.
//#define HAL_UCACHE_WRITE_HINT( _base_ , _size_ )
 
// Allocate and zero the cache lines associated with the given range.
//#define HAL_UCACHE_ZERO( _base_ , _size_ )
 
//-----------------------------------------------------------------------------
 
//-----------------------------------------------------------------------------
// Data and instruction cache macros map onto the both-cache macros
 
//-----------------------------------------------------------------------------
// Global control of data cache
 
#define HAL_DCACHE_SIZE HAL_UCACHE_SIZE
#define HAL_DCACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE
#define HAL_DCACHE_WAYS HAL_UCACHE_WAYS
#define HAL_DCACHE_SETS HAL_UCACHE_SETS
 
// Enable the data cache
#define HAL_DCACHE_ENABLE() HAL_UCACHE_ENABLE()
 
// Disable the data cache
#define HAL_DCACHE_DISABLE() HAL_UCACHE_DISABLE()
 
// Invalidate the entire cache
#define HAL_DCACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL()
 
// Synchronize the contents of the cache with memory.
#define HAL_DCACHE_SYNC() HAL_UCACHE_SYNC()
 
// Query the state of the data cache
#define HAL_DCACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_)
 
// Set the data cache refill burst size
//#define HAL_DCACHE_BURST_SIZE(_size_)
 
// Set the data cache write mode
//#define HAL_DCACHE_WRITE_MODE( _mode_ )
 
//#define HAL_DCACHE_WRITETHRU_MODE 0
//#define HAL_DCACHE_WRITEBACK_MODE 1
 
// Load the contents of the given address range into the data cache
// and then lock the cache so that it stays there.
//#define HAL_DCACHE_LOCK(_base_, _size_)
 
// Undo a previous lock operation
//#define HAL_DCACHE_UNLOCK(_base_, _size_)
 
// Unlock entire cache
//#define HAL_DCACHE_UNLOCK_ALL()
 
//-----------------------------------------------------------------------------
// Data cache line control
 
// Allocate cache lines for the given address range without reading its
// contents from memory.
//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
 
// Write dirty cache lines to memory and invalidate the cache entries
// for the given address range.
//#define HAL_DCACHE_FLUSH( _base_ , _size_ )
 
// Invalidate cache lines in the given range without writing to memory.
//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
 
// Write dirty cache lines to memory for the given address range.
//#define HAL_DCACHE_STORE( _base_ , _size_ )
 
// Preread the given range into the cache with the intention of reading
// from it later.
//#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
 
// Preread the given range into the cache with the intention of writing
// to it later.
//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
 
// Allocate and zero the cache lines associated with the given range.
//#define HAL_DCACHE_ZERO( _base_ , _size_ )
 
//-----------------------------------------------------------------------------
// Global control of Instruction cache
 
#define HAL_ICACHE_SIZE HAL_UCACHE_SIZE
#define HAL_ICACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE
#define HAL_ICACHE_WAYS HAL_UCACHE_WAYS
#define HAL_ICACHE_SETS HAL_UCACHE_SETS
 
// Enable the instruction cache
#define HAL_ICACHE_ENABLE() HAL_UCACHE_ENABLE()
 
// Disable the instruction cache
#define HAL_ICACHE_DISABLE() HAL_UCACHE_DISABLE()
 
// Invalidate the entire cache
#define HAL_ICACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL()
 
 
// Synchronize the contents of the cache with memory.
#define HAL_ICACHE_SYNC() HAL_UCACHE_SYNC()
 
// Query the state of the instruction cache
#define HAL_ICACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_)
 
// Set the instruction cache refill burst size
//#define HAL_ICACHE_BURST_SIZE(_size_)
 
// Load the contents of the given address range into the instruction cache
// and then lock the cache so that it stays there.
 
//#define HAL_ICACHE_LOCK(_base_, _size_)
 
// Undo a previous lock operation
//#define HAL_ICACHE_UNLOCK(_base_, _size_)
 
// Unlock entire cache
//#define HAL_ICACHE_UNLOCK_ALL()
 
//-----------------------------------------------------------------------------
// Instruction cache line control
 
// Invalidate cache lines in the given range without writing to memory.
//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
 
#endif // ifndef CYGONCE_HAL_CACHE_H
// End of hal_cache.h
/v2_0/include/hal_diag.h
0,0 → 1,83
//==========================================================================
//
// hal_diag.h
//
//
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): gthomas
// Contributors: gthomas, jskov
// Grant Edwards <grante@visi.com>
// Date: 2001-07-31
// Purpose:
// Description:
//
//####DESCRIPTIONEND####
//
//========================================================================*/
 
#ifndef CYGONCE_HAL_DIAG_H
#define CYGONCE_HAL_DIAG_H
 
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>
 
#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
 
#include <cyg/hal/hal_if.h>
 
#define HAL_DIAG_INIT() hal_if_diag_init()
#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_)
#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_)
 
//// Not the best place for this, but ...
extern void hal_delay_us(cyg_int32 usecs);
#define HAL_DELAY_US(n) hal_delay_us(n);
 
#else // old way of doing diagnostic I/O
 
externC void hal_diag_init(void);
externC void hal_diag_write_char(char c);
externC void hal_diag_read_char(char *c);
 
#define HAL_DIAG_INIT() hal_diag_init()
#define HAL_DIAG_WRITE_CHAR(_c_) hal_diag_write_char(_c_)
#define HAL_DIAG_READ_CHAR(_c_) hal_diag_read_char(&_c_)
 
#endif // defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
#endif /* CYGONCE_HAL_DIAG_H */
/v2_0/include/hal_platform_setup.h
0,0 → 1,328
#ifndef CYGONCE_HAL_PLATFORM_SETUP_H
#define CYGONCE_HAL_PLATFORM_SETUP_H
//==========================================================================
//
// hal_platform_setup.h
//
//
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): gthomas
// Contributors: gthomas, jskov
// Grant Edwards <grante@visi.com>
// Date: 2001-07-31
// Purpose:
// Description:
//
//####DESCRIPTIONEND####
//
//========================================================================*/
 
// does normal DRAM setup, which doesn't fail?!?!
 
#include <cyg/hal/plf_io.h>
 
#define CYGHWR_LED_MACRO \
ldr r0,=KS32C_IOPDATA ;\
mov r1, #((255 & (~(\x)))) ;\
str r1, [r0] ;
#if CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE==4096
// Override default to a more sensible value
#undef CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
#define CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE 2048
#endif
 
// Use relative branch since we are going to switch the address space
// around.
#define CYGSEM_HAL_ROM_RESET_USES_JUMP
 
#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
#define PLATFORM_SETUP1 \
ldr r1,=KS32C_IOPMOD ;\
ldr r2,=0xff /* set led display to output */ ;\
str r2,[r1,#0x00] ;\
LED 0xaa ;\
;\
/* Normal DRAM mode */ ;\
ldr r3, =0x03ffff90 /* cache+wb disabled, regs @ 0x03ff0000 */;\
ldr r0, =KS32C_SYSCFG ;\
str r3,[r0] ;\
ldr lr,=10f ;\
1: mov r1,pc ;\
sub r1,r1,#8 ;\
ldr r0,=1b ;\
sub r1,r1,r0 ;\
ldr r0,=30f ;\
add r0,r0,r1 ;\
ldmia r0,{r1-r12} ;\
ldr r0,=KS32C_EXTDBWTH ;\
stmia r0,{r1-r12} ;\
mov pc,lr ;\
10: LED 0x80 ;\
\
/* Check that it worked, otherwise try Sync DRAM setup */ ;\
ldr r1,=0x00000000 ;\
str r1,[r1] ;\
ldr r2,[r1] ;\
cmp r2,r1 ;\
beq 99f ;\
\
/* Sync DRAM mode */ ;\
LED 0x81 ;\
ldr r3, =0x83ffff90 /* sdram c+wb disabled, regs @ 0x03ff0000 */;\
ldr r0, =KS32C_SYSCFG ;\
str r3,[r0] ;\
ldr lr,=99f ;\
1: mov r1,pc ;\
sub r1,r1,#8 ;\
ldr r0,=1b ;\
sub r1,r1,r0 ;\
ldr r0,=40f ;\
add r0,r0,r1 ;\
ldmia r0,{r1-r12} ;\
ldr r0,=KS32C_EXTDBWTH ;\
stmia r0,{r1-r12} ;\
mov pc,lr ;\
;\
/* The below are set with a store-multiple instruction */ ;\
;\
/* Normal DRAM setup */ ;\
/* Flash is 16 bit, everything else 32 bit */ ;\
/* .long KS32C_EXTDBWTH */ ;\
30: .long ( (KS32C_EXTDBWTH_16BIT<<KS32C_EXTDBWTH_DSR0_shift) \
|(KS32C_EXTDBWTH_16BIT<<KS32C_EXTDBWTH_DSR1_shift) \
|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSR2_shift) \
|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSR3_shift) \
|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSR4_shift) \
|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSR5_shift) \
|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSD0_shift) \
|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSD1_shift) \
|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSD2_shift) \
|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSD3_shift) \
|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSX0_shift) \
|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSX1_shift) \
|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSX2_shift) \
|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSX3_shift) ) ;\
/* Flash at 0x01800000-0x01880000, 5 cycles, 7 cycles */ ;\
/* .long KS32C_ROMCON0 */ ;\
.long ( (KS32C_ROMCON_PMC_ROM) \
|(KS32C_ROMCON_TPA_5C) \
|(KS32C_ROMCON_TACC_7C) \
|((0x01800000 >> 16) << KS32C_ROMCON_BASE_shift) \
|((0x01880000 >> 16) << KS32C_ROMCON_NEXT_shift)) ;\
/* .long KS32C_ROMCON1 */ ;\
.long ( (KS32C_ROMCON_PMC_ROM) \
|(KS32C_ROMCON_TPA_5C) \
|(KS32C_ROMCON_TACC_5C) \
|((0x00000000 >> 16) << KS32C_ROMCON_BASE_shift) \
|((0x00000000 >> 16) << KS32C_ROMCON_NEXT_shift)) ;\
/* .long KS32C_ROMCON2 */ ;\
.long ( (KS32C_ROMCON_PMC_ROM) \
|(KS32C_ROMCON_TPA_5C) \
|(KS32C_ROMCON_TACC_5C) \
|((0x00000000 >> 16) << KS32C_ROMCON_BASE_shift) \
|((0x00000000 >> 16) << KS32C_ROMCON_NEXT_shift)) ;\
/* .long KS32C_ROMCON3 */ ;\
.long ( (KS32C_ROMCON_PMC_ROM) \
|(KS32C_ROMCON_TPA_5C) \
|(KS32C_ROMCON_TACC_3C) \
|((0x00000000 >> 16) << KS32C_ROMCON_BASE_shift) \
|((0x00000000 >> 16) << KS32C_ROMCON_NEXT_shift)) ;\
/* .long KS32C_ROMCON4 */ ;\
.long ( (KS32C_ROMCON_PMC_ROM) \
|(KS32C_ROMCON_TPA_5C) \
|(KS32C_ROMCON_TACC_5C) \
|((0x00000000 >> 16) << KS32C_ROMCON_BASE_shift) \
|((0x00000000 >> 16) << KS32C_ROMCON_NEXT_shift)) ;\
/* .long KS32C_ROMCON5 */ ;\
.long ( (KS32C_ROMCON_PMC_ROM) \
|(KS32C_ROMCON_TPA_5C) \
|(KS32C_ROMCON_TACC_5C) \
|((0x00000000 >> 16) << KS32C_ROMCON_BASE_shift) \
|((0x00000000 >> 16) << KS32C_ROMCON_NEXT_shift)) ;\
/* .long KS32C_DRAMCON0 */ ;\
.long ( (KS32C_DRAMCON_RESERVED) \
|(KS32C_DRAMCON_CAN_10) \
|(KS32C_DRAMCON_TRP_3C) \
|(KS32C_DRAMCON_TRC_1C) \
|(KS32C_DRAMCON_TCP_1C) \
|(KS32C_DRAMCON_TCS_2C) \
|(KS32C_DRAMCON_EDO) \
|((0x00000000 >> 16) << KS32C_DRAMCON_BASE_shift) \
|((0x00400000 >> 16) << KS32C_DRAMCON_NEXT_shift)) ;\
/* .long KS32C_DRAMCON1 */ ;\
.long ( (KS32C_DRAMCON_RESERVED) \
|(KS32C_DRAMCON_CAN_10) \
|(KS32C_DRAMCON_TRP_1C) \
|(KS32C_DRAMCON_TRC_1C) \
|(KS32C_DRAMCON_TCP_1C) \
|(KS32C_DRAMCON_TCS_2C) \
|(KS32C_DRAMCON_EDO) \
|((0x00400000 >> 16) << KS32C_DRAMCON_BASE_shift) \
|((0x00800000 >> 16) << KS32C_DRAMCON_NEXT_shift)) ;\
/* .long KS32C_DRAMCON2 */ ;\
.long ( (KS32C_DRAMCON_RESERVED) \
|(KS32C_DRAMCON_CAN_10) \
|(KS32C_DRAMCON_TRP_1C) \
|(KS32C_DRAMCON_TRC_1C) \
|(KS32C_DRAMCON_TCP_1C) \
|(KS32C_DRAMCON_TCS_2C) \
|((0x00800000 >> 16) << KS32C_DRAMCON_BASE_shift) \
|((0x00c00000 >> 16) << KS32C_DRAMCON_NEXT_shift)) ;\
/* .long KS32C_DRAMCON3 */ ;\
.long ( (KS32C_DRAMCON_RESERVED) \
|(KS32C_DRAMCON_CAN_10) \
|(KS32C_DRAMCON_TRP_1C) \
|(KS32C_DRAMCON_TRC_1C) \
|(KS32C_DRAMCON_TCP_1C) \
|(KS32C_DRAMCON_TCS_2C) \
|((0x00c00000 >> 16) << KS32C_DRAMCON_BASE_shift) \
|((0x01000000 >> 16) << KS32C_DRAMCON_NEXT_shift)) ;\
/* .long KS32C_REFEXTCON */ ;\
.long (((2048+1-(16*CYGNUM_HAL_CPUCLOCK/1000000)) << KS32C_REFEXTCON_RCV_shift) \
|(KS32C_REFEXTCON_TCSR_1C) \
|(KS32C_REFEXTCON_TCHR_1C) \
|(KS32C_REFEXTCON_REN) \
|(KS32C_REFEXTCON_VSF) \
|(KS32C_REFEXTCON_BASE)) ;\
;\
/* Sync DRAM setup */ ;\
/* Flash is 16 bit, everything else 32 bit */ ;\
/* .long KS32C_EXTDBWTH */ ;\
40: .long ( (KS32C_EXTDBWTH_16BIT<<KS32C_EXTDBWTH_DSR0_shift) \
|(KS32C_EXTDBWTH_16BIT<<KS32C_EXTDBWTH_DSR1_shift) \
|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSR2_shift) \
|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSR3_shift) \
|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSR4_shift) \
|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSR5_shift) \
|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSD0_shift) \
|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSD1_shift) \
|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSD2_shift) \
|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSD3_shift) \
|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSX0_shift) \
|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSX1_shift) \
|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSX2_shift) \
|(KS32C_EXTDBWTH_32BIT<<KS32C_EXTDBWTH_DSX3_shift) ) ;\
/* Flash at 0x01800000-0x01880000, 5 cycles, 7 cycles */ ;\
/* .long KS32C_ROMCON0 */ ;\
.long ( (KS32C_ROMCON_PMC_ROM) \
|(KS32C_ROMCON_TPA_5C) \
|(KS32C_ROMCON_TACC_7C) \
|((0x01800000 >> 16) << KS32C_ROMCON_BASE_shift) \
|((0x01880000 >> 16) << KS32C_ROMCON_NEXT_shift)) ;\
/* .long KS32C_ROMCON1 */ ;\
.long ( (KS32C_ROMCON_PMC_ROM) \
|(KS32C_ROMCON_TPA_5C) \
|(KS32C_ROMCON_TACC_5C) \
|((0x00000000 >> 16) << KS32C_ROMCON_BASE_shift) \
|((0x00000000 >> 16) << KS32C_ROMCON_NEXT_shift)) ;\
/* .long KS32C_ROMCON2 */ ;\
.long ( (KS32C_ROMCON_PMC_ROM) \
|(KS32C_ROMCON_TPA_5C) \
|(KS32C_ROMCON_TACC_5C) \
|((0x00000000 >> 16) << KS32C_ROMCON_BASE_shift) \
|((0x00000000 >> 16) << KS32C_ROMCON_NEXT_shift)) ;\
/* .long KS32C_ROMCON3 */ ;\
.long ( (KS32C_ROMCON_PMC_ROM) \
|(KS32C_ROMCON_TPA_5C) \
|(KS32C_ROMCON_TACC_5C) \
|((0x00000000 >> 16) << KS32C_ROMCON_BASE_shift) \
|((0x00000000 >> 16) << KS32C_ROMCON_NEXT_shift)) ;\
/* .long KS32C_ROMCON4 */ ;\
.long ( (KS32C_ROMCON_PMC_ROM) \
|(KS32C_ROMCON_TPA_5C) \
|(KS32C_ROMCON_TACC_5C) \
|((0x00000000 >> 16) << KS32C_ROMCON_BASE_shift) \
|((0x00000000 >> 16) << KS32C_ROMCON_NEXT_shift)) ;\
/* .long KS32C_ROMCON5 */ ;\
.long ( (KS32C_ROMCON_PMC_ROM) \
|(KS32C_ROMCON_TPA_5C) \
|(KS32C_ROMCON_TACC_5C) \
|((0x00000000 >> 16) << KS32C_ROMCON_BASE_shift) \
|((0x00000000 >> 16) << KS32C_ROMCON_NEXT_shift)) ;\
/* .long KS32C_DRAMCON0 */ ;\
.long ( (KS32C_DRAMCON_RESERVED) \
|(KS32C_DRAMCON_CAN_8) \
|(KS32C_DRAMCON_TRP_4C) \
|(KS32C_DRAMCON_TRC_2C) \
|((0x00000000 >> 16) << KS32C_DRAMCON_BASE_shift) \
|((0x00400000 >> 16) << KS32C_DRAMCON_NEXT_shift)) ;\
/* .long KS32C_DRAMCON1 */ ;\
.long ( (KS32C_DRAMCON_RESERVED) \
|(KS32C_DRAMCON_CAN_8) \
|(KS32C_DRAMCON_TRP_2C) \
|(KS32C_DRAMCON_TRC_2C) \
|((0x00400000 >> 16) << KS32C_DRAMCON_BASE_shift) \
|((0x00800000 >> 16) << KS32C_DRAMCON_NEXT_shift)) ;\
/* .long KS32C_DRAMCON2 */ ;\
.long ( (KS32C_DRAMCON_RESERVED) \
|(KS32C_DRAMCON_CAN_8) \
|(KS32C_DRAMCON_TRP_2C) \
|(KS32C_DRAMCON_TRC_2C) \
|((0x00800000 >> 16) << KS32C_DRAMCON_BASE_shift) \
|((0x00c00000 >> 16) << KS32C_DRAMCON_NEXT_shift)) ;\
/* .long KS32C_DRAMCON3 */ ;\
.long ( (KS32C_DRAMCON_RESERVED) \
|(KS32C_DRAMCON_CAN_8) \
|(KS32C_DRAMCON_TRP_2C) \
|(KS32C_DRAMCON_TRC_2C) \
|((0x00c00000 >> 16) << KS32C_DRAMCON_BASE_shift) \
|((0x01000000 >> 16) << KS32C_DRAMCON_NEXT_shift)) ;\
/* .long KS32C_REFEXTCON */ ;\
.long (((2048+1-(8*CYGNUM_HAL_CPUCLOCK/1000000)) << KS32C_REFEXTCON_RCV_shift) \
|(KS32C_REFEXTCON_TRC_4C) \
|(KS32C_REFEXTCON_REN) \
|(KS32C_REFEXTCON_VSF) \
|(KS32C_REFEXTCON_BASE)) ;\
99: LED 0x82 ;\
ldr r3,=0x00000000 ;\
str r3,[r3] ;\
ldr r4,[r3] ;\
cmp r4,r3 ;\
beq 15f ;\
11: LED 0x83 ;\
b 11b ;\
15: LED 0x84
#else
#define PLATFORM_SETUP1
#endif
 
//-----------------------------------------------------------------------------
// end of hal_platform_setup.h
#endif // CYGONCE_HAL_PLATFORM_SETUP_H
/v2_0/include/plf_io.h
0,0 → 1,286
#ifndef CYGONCE_HAL_PLF_IO_H
#define CYGONCE_HAL_PLF_IO_H
//=============================================================================
//
// plf_io.h
//
// Platform specific registers
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
// Contributors:jskov
// Date: 2001-03-16
// Purpose: ARM/KS32C platform specific registers
// Description:
// Usage: #include <cyg/hal/plf_io.h>
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
// non-caching by accessing addr|0x04000000
 
#define KS32C_REG_BASE 0x07ff0000
 
// -----------------------------------------------------------------------------
// System config (register bases and caching)
#define KS32C_SYSCFG (KS32C_REG_BASE + 0x0000)
 
#define KS32C_SYSCFG_SDM 0x80000000
#define KS32C_SYSCFG_PD_ID_MASK 0x3c000000
#define KS32C_SYSCFG_SRBBP_MASK 0x03ff0000 // address/64k
#define KS32C_SYSCFG_ISBBP_MASK 0x0000ffc0 // a25-a16
#define KS32C_SYSCFG_CM_MASK 0x00000030
#define KS32C_SYSCFG_CM_4R_4C 0x00000000
#define KS32C_SYSCFG_CM_0R_8C 0x00000010
#define KS32C_SYSCFG_CM_8R_0C 0x00000020
#define KS32C_SYSCFG_WE 0x00000004 // only KS32C50100?
#define KS32C_SYSCFG_CE 0x00000002
#define KS32C_SYSCFG_SE 0x00000001
 
#define KS32C_CLKCON (KS32C_REG_BASE + 0x3000)
 
#define KS32C_EXTACON0 (KS32C_REG_BASE + 0x3008)
#define KS32C_EXTACON1 (KS32C_REG_BASE + 0x300c)
 
//-----------------------------------------------------------------------------
// Memory banks data width
#define KS32C_EXTDBWTH (KS32C_REG_BASE + 0x3010)
 
#define KS32C_EXTDBWTH_MASK 3
#define KS32C_EXTDBWTH_8BIT 1
#define KS32C_EXTDBWTH_16BIT 2
#define KS32C_EXTDBWTH_32BIT 3
 
#define KS32C_EXTDBWTH_DSR0_shift 0
#define KS32C_EXTDBWTH_DSR1_shift 2
#define KS32C_EXTDBWTH_DSR2_shift 4
#define KS32C_EXTDBWTH_DSR3_shift 6
#define KS32C_EXTDBWTH_DSR4_shift 8
#define KS32C_EXTDBWTH_DSR5_shift 10
#define KS32C_EXTDBWTH_DSD0_shift 12
#define KS32C_EXTDBWTH_DSD1_shift 14
#define KS32C_EXTDBWTH_DSD2_shift 16
#define KS32C_EXTDBWTH_DSD3_shift 18
#define KS32C_EXTDBWTH_DSX0_shift 20
#define KS32C_EXTDBWTH_DSX1_shift 22
#define KS32C_EXTDBWTH_DSX2_shift 24
#define KS32C_EXTDBWTH_DSX3_shift 26
 
// -----------------------------------------------------------------------------
// Bank locations and timing
#define KS32C_ROMCON0 (KS32C_REG_BASE + 0x3014)
#define KS32C_ROMCON1 (KS32C_REG_BASE + 0x3018)
#define KS32C_ROMCON2 (KS32C_REG_BASE + 0x301c)
#define KS32C_ROMCON3 (KS32C_REG_BASE + 0x3020)
#define KS32C_ROMCON4 (KS32C_REG_BASE + 0x3024)
#define KS32C_ROMCON5 (KS32C_REG_BASE + 0x3028)
 
#define KS32C_ROMCON_PMC_MASK 0x00000003
#define KS32C_ROMCON_PMC_ROM 0x00000000
#define KS32C_ROMCON_PMC_4W_PAGE 0x00000001
#define KS32C_ROMCON_PMC_8W_PAGE 0x00000002
#define KS32C_ROMCON_PMC_16W_PAGE 0x00000003
 
#define KS32C_ROMCON_TPA_MASK 0x0000000c
#define KS32C_ROMCON_TPA_5C 0x00000000
#define KS32C_ROMCON_TPA_2C 0x00000004
#define KS32C_ROMCON_TPA_3C 0x00000008
#define KS32C_ROMCON_TPA_4C 0x0000000c
 
#define KS32C_ROMCON_TACC_MASK 0x00000070
#define KS32C_ROMCON_TACC_DISABLE 0x00000000
#define KS32C_ROMCON_TACC_2C 0x00000010
#define KS32C_ROMCON_TACC_3C 0x00000020
#define KS32C_ROMCON_TACC_4C 0x00000030
#define KS32C_ROMCON_TACC_5C 0x00000040
#define KS32C_ROMCON_TACC_6C 0x00000050
#define KS32C_ROMCON_TACC_7C 0x00000060
 
#define KS32C_ROMCON_BASE_MASK 0x000ff700
#define KS32C_ROMCON_BASE_shift 10
 
#define KS32C_ROMCON_NEXT_MASK 0x7ff00000
#define KS32C_ROMCON_NEXT_shift 20
 
 
 
#define KS32C_DRAMCON0 (KS32C_REG_BASE + 0x302c)
#define KS32C_DRAMCON1 (KS32C_REG_BASE + 0x3030)
#define KS32C_DRAMCON2 (KS32C_REG_BASE + 0x3034)
#define KS32C_DRAMCON3 (KS32C_REG_BASE + 0x3038)
 
#define KS32C_DRAMCON_CAN_8 0x00000000
#define KS32C_DRAMCON_CAN_9 0x40000000
#define KS32C_DRAMCON_CAN_10 0x80000000
#define KS32C_DRAMCON_CAN_11 0xc0000000
#define KS32C_DRAMCON_TRP_1C 0x00000000
#define KS32C_DRAMCON_TRP_2C 0x00000100
#define KS32C_DRAMCON_TRP_3C 0x00000200
#define KS32C_DRAMCON_TRP_4C 0x00000300
#define KS32C_DRAMCON_TRC_1C 0x00000000
#define KS32C_DRAMCON_TRC_2C 0x00000080
#define KS32C_DRAMCON_RESERVED 0x00000010
#define KS32C_DRAMCON_TCP_1C 0x00000000
#define KS32C_DRAMCON_TCP_2C 0x00000008
#define KS32C_DRAMCON_TCS_1C 0x00000000
#define KS32C_DRAMCON_TCS_2C 0x00000002
#define KS32C_DRAMCON_TCS_3C 0x00000004
#define KS32C_DRAMCON_TCS_4C 0x00000006
#define KS32C_DRAMCON_EDO 0x00000001
 
#define KS32C_DRAMCON_BASE_MASK 0x000ff700
#define KS32C_DRAMCON_BASE_shift 10
 
#define KS32C_DRAMCON_NEXT_MASK 0x7ff00000
#define KS32C_DRAMCON_NEXT_shift 20
 
 
#define KS32C_REFEXTCON (KS32C_REG_BASE + 0x303c)
 
// DRAM
#define KS32C_REFEXTCON_TCSR_1C 0x00000000
#define KS32C_REFEXTCON_TCHR_1C 0x00000000
// SDRAM
#define KS32C_REFEXTCON_TRC_4C 0x00060000
// DRAM+SDRAM
#define KS32C_REFEXTCON_REN 0x00010000
#define KS32C_REFEXTCON_VSF 0x00008000
#define KS32C_REFEXTCON_BASE 0x00000360
 
#define KS32C_REFEXTCON_RCV_shift 21
 
//-----------------------------------------------------------------------------
// INTC
 
#define KS32C_INTMOD (KS32C_REG_BASE + 0x4000)
#define KS32C_INTPND (KS32C_REG_BASE + 0x4004)
#define KS32C_INTMSK (KS32C_REG_BASE + 0x4008)
#define KS32C_INTPRI0 (KS32C_REG_BASE + 0x400c)
#define KS32C_INTPRI1 (KS32C_REG_BASE + 0x4010)
#define KS32C_INTPRI2 (KS32C_REG_BASE + 0x4014)
#define KS32C_INTPRI3 (KS32C_REG_BASE + 0x4018)
#define KS32C_INTPRI4 (KS32C_REG_BASE + 0x401c)
#define KS32C_INTPRI5 (KS32C_REG_BASE + 0x4020)
#define KS32C_INTOFFSET (KS32C_REG_BASE + 0x4024)
#define KS32C_PNDPRI (KS32C_REG_BASE + 0x4028)
#define KS32C_PNDTEST (KS32C_REG_BASE + 0x402c)
#define KS32C_INTOFFSET_FIQ (KS32C_REG_BASE + 0x4030)
#define KS32C_INTOFFSET_IRQ (KS32C_REG_BASE + 0x4034)
 
#define KS32C_INTMSK_GLOBAL (1<<21)
 
//-----------------------------------------------------------------------------
// PIO
 
#define KS32C_IOPMOD (KS32C_REG_BASE + 0x5000)
#define KS32C_IOPCON (KS32C_REG_BASE + 0x5004)
#define KS32C_IOPDATA (KS32C_REG_BASE + 0x5008)
 
//-----------------------------------------------------------------------------
// Timers
 
#define KS32C_TMOD (KS32C_REG_BASE + 0x6000)
#define KS32C_TDATA0 (KS32C_REG_BASE + 0x6004)
#define KS32C_TDATA1 (KS32C_REG_BASE + 0x6008)
#define KS32C_TCNT0 (KS32C_REG_BASE + 0x600c)
#define KS32C_TCNT1 (KS32C_REG_BASE + 0x6010)
 
#define KS32C_TMOD_TE0 0x00000001
#define KS32C_TMOD_TMD0 0x00000002
#define KS32C_TMOD_TCLR0 0x00000004
#define KS32C_TMOD_TE1 0x00000008
#define KS32C_TMOD_TMD1 0x00000010
#define KS32C_TMOD_TCLR1 0x00000020
 
 
//-----------------------------------------------------------------------------
// UART
 
#define KS32C_UART0_BASE (KS32C_REG_BASE + 0xd000)
#define KS32C_UART1_BASE (KS32C_REG_BASE + 0xe000)
 
#define KS32C_UART_LCON 0x0000
#define KS32C_UART_CON 0x0004
#define KS32C_UART_STAT 0x0008
#define KS32C_UART_TXBUF 0x000c
#define KS32C_UART_RXBUF 0x0010
#define KS32C_UART_BRDIV 0x0014
#define KS32C_UART_BRDCNT 0x0018
#define KS32C_UART_BRDCLK 0x001c
 
#define KS32C_UART_LCON_5_DBITS 0x00
#define KS32C_UART_LCON_6_DBITS 0x01
#define KS32C_UART_LCON_7_DBITS 0x02
#define KS32C_UART_LCON_8_DBITS 0x03
#define KS32C_UART_LCON_1_SBITS 0x00
#define KS32C_UART_LCON_2_SBITS 0x04
#define KS32C_UART_LCON_NO_PARITY 0x00
#define KS32C_UART_LCON_EVEN_PARITY 0x00
#define KS32C_UART_LCON_ODD_PARITY 0x28
#define KS32C_UART_LCON_1_PARITY 0x30
#define KS32C_UART_LCON_0_PARITY 0x38
#define KS32C_UART_LCON_SCS 0x40
#define KS32C_UART_LCON_IR 0x80
 
#define KS32C_UART_CON_RXM_MASK 0x03
#define KS32C_UART_CON_RXM_INT 0x01
#define KS32C_UART_CON_TXM_MASK 0x0c
#define KS32C_UART_CON_TXM_INT 0x08
#define KS32C_UART_CON_RX_ERR_INT 0x04
 
 
#define KS32C_UART_STAT_DTR 0x10
#define KS32C_UART_STAT_RDR 0x20
#define KS32C_UART_STAT_TXE 0x40 // tx empty
#define KS32C_UART_STAT_TC 0x80 // tx complete
 
//-----------------------------------------------------------------------------
// Cache
#define KS32C_CACHE_SET0_ADDR 0x14000000
#define KS32C_CACHE_SET1_ADDR 0x14800000
#define KS32C_CACHE_TAG_ADDR 0x15000000
 
//-----------------------------------------------------------------------------
// Memory map is 1-1
 
#define CYGARC_PHYSICAL_ADDRESS(_x_) (_x_)
 
//-----------------------------------------------------------------------------
// end of plf_io.h
#endif // CYGONCE_HAL_PLF_IO_H
/v2_0/ChangeLog
0,0 → 1,127
2002-10-19 Jonathan Larmour <jifl@eCosCentric.com>
 
* include/hal_platform_setup.h (PLATFORM_SETUP1): Only define if
ROM or ROMRAM, not if STUBS which can be RAM.
 
2003-02-05 Nick Garnett <nickg@calivar.com>
 
* include/plf_io.h (CYGARC_PHYSICAL_ADDRESS): Added this
definition to keep redboot_linux_exec.c happy.
 
2002-10-03 Jonathan Larmour <jifl@eCosCentric.com>
 
* include/pkgconf/mlt_arm_snds_ram.ldi: Add definition of heap1.
 
2002-05-07 Gary Thomas <gthomas@redhat.com>
 
* cdl/hal_arm_snds.cdl:
Standardize CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT usage.
 
2001-12-06 Jesper Skov <jskov@redhat.com>
 
* include/hal_platform_setup.h (PLATFORM_SETUP1): Don't trust the
syscfg SDRAM request bit as suggested by manual - always set it to
what works. Use relative loads to get a pointer to the tables with
system controller setup data.
 
* src/snds100_misc.c: Don't mess up the syscfg register.
 
2001-10-19 Jesper Skov <jskov@redhat.com>
 
* include/plf_io.h (KS32C_REFEXTCON): Split in DRAM and SDRAM
settings.
 
* include/hal_platform_setup.h: Fix KS32C_REFEXTCON parameters,
and set some LEDs to help debugging.
 
* cdl/hal_arm_snds.cdl: On the SNDS100 board the CPU runs at
50MHZ.
 
* include/pkgconf/mlt_arm_snds_rom.ldi: Moved flash to
0x01800000.
* include/pkgconf/mlt_arm_snds_rom.mlt: Same.
* include/pkgconf/mlt_arm_snds_rom.h: Same.
 
* include/hal_platform_setup.h: Added LED macro. Use relative
branch in reset vector. Moved flash to 0x01800000.
 
2001-10-18 Jesper Skov <jskov@redhat.com>
 
* src/hal_diag.c: Definition names updated.
* src/snds100_misc.c: Same.
 
* include/pkgconf/mlt_arm_snds_rom.ldi: Added.
* include/pkgconf/mlt_arm_snds_rom.mlt: Same.
* include/pkgconf/mlt_arm_snds_rom.h: Same.
 
* include/pkgconf/mlt_arm_snds_ram.ldi: Updated layout.
* include/pkgconf/mlt_arm_snds_ram.mlt: Same.
* include/pkgconf/mlt_arm_snds_ram.h: Same.
 
* include/hal_platform_setup.h: Fixed instruction typo.
 
* include/hal_platform_ints.h: Vector definitions renamed to match
those in E7T HAL.
 
* include/hal_cache.h: Replaced with E7T HAL version.
 
* cdl/hal_arm_snds.cdl: Added default baud rate option, ROM
startup mode, and removed PID tools make rules.
 
2001-10-12 Jesper Skov <jskov@redhat.com>
 
* src/hal_diag.c: Copied here from E7T HAL.
* src/snds100_misc.c: Functions replaced with E7T HAL
versions.
 
* include/plf_io.h: Added.
 
* include/hal_platform_setup.h (PLATFORM_SETUP1): Code matching
board mon.
 
2001-10-05 Jonathan Larmour <jlarmour@redhat.com>
 
* include/hal_cache.h: Don't define cache dimensions at all rather
than using 0.
 
2001-08-22 Gary Thomas <gthomas@redhat.com>
 
* src/snds100_misc.c:
* src/hal_diag.c:
printf() is no longer a part of RedBoot. Thus all programs
must use diag_printf() and related functions instead.
 
//===========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//===========================================================================
/v2_0/src/ks32c5000.h
0,0 → 1,240
//==========================================================================
//
// ks32c5000.h
//
//
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): gthomas
// Contributors: gthomas, jskov
// Grant Edwards <grante@visi.com>
// Date: 2001-07-31
// Purpose:
// Description:
//
//####DESCRIPTIONEND####
//
//========================================================================*/
 
/*
* structure definitions for Samsung KS32C5000 peripheral registers
*/
 
typedef volatile unsigned int reg;
 
#define Bit(n) (1<<(n))
 
 
/*
* Interrupt Controller
*/
 
typedef struct
{
reg intmod; // Interrupt mode register
reg intpnd; // Interrupt pending register
reg intmsk; // Interrupt mask register
reg intpri0; // Interrupt priority register
reg intpri1;
reg intpri2;
reg intpri3;
reg intpri4;
reg intpri5;
reg intoffset; // Interrupt offset register
} tInterruptController;
 
 
/* The following bit masks are for use in the intmod, intpnd, and
* intmsk registers
*/
 
#define IntMaskExt0 Bit(0)
#define IntMaskExt1 Bit(1)
#define IntMaskExt2 Bit(2)
#define IntMaskExt3 Bit(3)
#define IntMaskUart0Tx Bit(4)
#define IntMaskUart0Rx Bit(5)
#if defined(CYG_HAL_CPUTYPE_KS32C5000A)
#define IntMaskUart0Err Bit(6)
#define IntMaskUart1Tx Bit(7)
#define IntMaskUart1Rx Bit(8)
#define IntMaskUart1Err Bit(9)
#define IntMaskDma0 Bit(10)
#define IntMaskDma1 Bit(11)
#define IntMaskTimer0 Bit(12)
#define IntMaskTimer1 Bit(13)
#define IntMaskHDLCA Bit(14)
#define IntMaskHDLCB Bit(15)
#else
#define IntMaskUart1Tx Bit(6)
#define IntMaskUart1Rx Bit(7)
#define IntMaskDma0 Bit(8)
#define IntMaskDma1 Bit(9)
#define IntMaskTimer0 Bit(10)
#define IntMaskTimer1 Bit(11)
#define IntMaskHDLCATx Bit(12)
#define IntMaskHDLCARx Bit(13)
#define IntMaskHDLCBTx Bit(14)
#define IntMaskHDLCBRx Bit(15)
#endif
#define IntMaskEtherBDMATx Bit(16)
#define IntMaskEtherBDMARx Bit(17)
#define IntMaskEtherMacTx Bit(18)
#define IntMaskEtherMacRx Bit(19)
#define IntMaskI2C Bit(20)
#define IntMaskGlobal Bit(21)
 
/*
* Timers
*/
 
typedef struct
{
reg tmod; // Timer mode
reg tdata0; // Timer 0 Data
reg tdata1; // Timer 1 Data
reg tcnt0; // Timer 0 Count
reg tcnt1; // Timer 1 Count
}tTimers;
 
#define TimerModeEnable0 Bit(0)
#define TimerModeToggle0 Bit(1)
#define TimerModeInitOut0 Bit(2)
#define TimerModeEnable1 Bit(3)
#define TimerModeToggle1 Bit(4)
#define TimerModeInitOut1 Bit(5)
 
 
/*
* UART
*/
 
typedef struct
{
reg ulcon; // UART Line Control
reg ucon; // UART Control
reg ustat; // UART Status
reg utxbuf; // UART Tx Buffer
reg urxbuf; // UART Rx Buffer
reg brdiv; // UART Baud Rate Divisor
reg brdcnt; // UART Baud Rate Counter
reg brdclk; // UART Baud Rate Clock
}tUart;
 
/* UART Line Control */
 
#define UartLineWordLenMask 0x03
#define UartLineWordLen5 0
#define UartLineWordLen6 1
#define UartLineWordLen7 2
#define UartLineWordLen8 3
 
#define UartLineStopMask (1 << 2)
#define UartLineStop1 (0 << 2)
#define UartLineStop2 (1 << 2)
 
#define UartLineParityMask (0x07 << 3)
#define UartLineParityNone (0 << 3)
#define UartLineParityOdd (4 << 3)
#define UartLineParityEven (5 << 3)
#define UartLineParityMark (6 << 3)
#define UartLineParitySpace (7 << 3)
 
#define UartLineInfraRedEnable Bit(7)
 
 
/* UART Control */
 
 
#define UartControlRxModeMask 3
#define UartControlRxModeDisabled 0
#define UartControlRxModeInterrupt 1
#define UartControlRxModeDma0 2
#define UartControlRxModeDma1 3
 
#define UartControlRxStatusIntEnable Bit(2)
 
#define UartControlTxModeMask (0x3 <<3)
#define UartControlTxModeDisable (0 <<3)
#define UartControlTxModeInterrupt (1 <<3)
#define UartControlTxModeDma0 (2 <<3)
#define UartControlTxModeDma1 (3 <<3)
 
#define UartControlDSR Bit(5)
 
#define UartControlSendBreak Bit(6)
 
#define UartControlLoopback Bit(7)
 
 
/* UART Status */
 
#define UartStatusRxOverrunError Bit(0)
#define UartStatusRxParityError Bit(1)
#define UartStatusRxFrameError Bit(2)
#define UartStatusRxBreak Bit(3)
#define UartStatusDTR Bit(4)
#define UartStatusRxDataAvail Bit(5)
#define UartStatusTxBufEmpty Bit(6)
#define UartStatusTxDone Bit(7)
 
 
 
 
// macros for external timing control registers
 
#define Tcos0(n) (((n)&7)<<0)
#define Tacs0(n) (((n)&7)<<3)
#define Tcoh0(n) (((n)&7)<<6)
#define Tacc0(n) (((n)&7)<<9)
 
#define Tcos1(n) (((n)&7)<<16)
#define Tacs1(n) (((n)&7)<<19)
#define Tcoh1(n) (((n)&7)<<22)
#define Tacc1(n) (((n)&7)<<25)
#define Tcos2(n) (((n)&7)<<0)
#define Tacs2(n) (((n)&7)<<3)
#define Tcoh2(n) (((n)&7)<<6)
#define Tacc2(n) (((n)&7)<<9)
 
#define Tcos3(n) (((n)&7)<<16)
#define Tacs3(n) (((n)&7)<<19)
#define Tcoh3(n) (((n)&7)<<22)
#define Tacc3(n) (((n)&7)<<25)
/v2_0/src/snds100_misc.c
0,0 → 1,286
//==========================================================================
//
// snds100_misc.c
//
// HAL misc board support code for Samsung SNDS100
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): gthomas
// Contributors: gthomas, jskov
// Grant Edwards <grante@visi.com>
// Date: 2001-07-31
// Purpose: HAL board support
// Description: Implementations of HAL board interfaces
//
//####DESCRIPTIONEND####
//
//========================================================================*/
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h> // base types
#include <cyg/infra/cyg_trac.h> // tracing macros
#include <cyg/infra/cyg_ass.h> // assertion macros
#include <cyg/infra/diag.h> // diag_printf()
 
#include <cyg/hal/hal_io.h> // IO macros
#include <cyg/hal/hal_arch.h> // Register state info
#include <cyg/hal/hal_diag.h>
#include <cyg/hal/hal_cache.h>
#include <cyg/hal/hal_intr.h> // necessary?
#include <cyg/hal/hal_if.h> // calling interface
#include <cyg/hal/hal_misc.h> // helper functions
#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
#include <cyg/hal/drv_api.h> // HAL ISR support
#endif
 
#include "ks32c5000.h"
#include <cyg/hal/plf_io.h>
 
//======================================================================
// Use Timer0 for kernel clock
 
static cyg_uint32 _period;
 
#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
static cyg_interrupt abort_interrupt;
static cyg_handle_t abort_interrupt_handle;
 
// This ISR is called only for the Abort button interrupt
static int
ks32c_abort_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs)
{
cyg_hal_user_break((CYG_ADDRWORD*)regs);
cyg_drv_interrupt_acknowledge(CYGNUM_HAL_INTERRUPT_EXT0);
return 0; // No need to run DSR
}
#endif
 
void hal_clock_initialize(cyg_uint32 period)
{
cyg_uint32 tmod;
 
// Disable timer 0
HAL_READ_UINT32(KS32C_TMOD, tmod);
tmod &= ~(KS32C_TMOD_TE0);
HAL_WRITE_UINT32(KS32C_TMOD, 0);
 
tmod &= ~(KS32C_TMOD_TMD0 | KS32C_TMOD_TCLR0);
tmod |= KS32C_TMOD_TE0;
 
// Set counter
HAL_WRITE_UINT32(KS32C_TDATA0, period);
 
// And enable timer
HAL_WRITE_UINT32(KS32C_TMOD, tmod);
 
_period = period;
 
#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_EXT0,
99, // Priority
0, // Data item passed to interrupt handler
ks32c_abort_isr,
0,
&abort_interrupt_handle,
&abort_interrupt);
cyg_drv_interrupt_attach(abort_interrupt_handle);
cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_EXT0);
#endif
}
 
void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
{
_period = period;
}
 
void hal_clock_read(cyg_uint32 *pvalue)
{
cyg_uint32 value;
 
HAL_READ_UINT32(KS32C_TCNT0, value);
*pvalue = _period - value;
}
 
//======================================================================
// Interrupt controller stuff
 
extern volatile tInterruptController ks32c5000_int; // Interrupt controller registers
extern volatile unsigned long EXTACON0; // Extern access control reg
extern volatile unsigned long EXTACON1; // Extern access control reg
extern volatile unsigned long IOPCON; // I/O Port Control reg
extern volatile unsigned long IOPMOD;
extern volatile unsigned long SYSCON;
 
void hal_hardware_init(void)
{
cyg_uint32 intmask, syscfg;
 
// Set up eCos/ROM interfaces
hal_if_init();
 
// Enable cache
HAL_READ_UINT32(KS32C_SYSCFG, syscfg);
syscfg &= ~KS32C_SYSCFG_CM_MASK;
syscfg |= KS32C_SYSCFG_CM_0R_8C|KS32C_SYSCFG_WE;
HAL_WRITE_UINT32(KS32C_SYSCFG, syscfg);
HAL_UCACHE_INVALIDATE_ALL();
HAL_UCACHE_ENABLE();
 
// Clear global interrupt mask bit
HAL_READ_UINT32(KS32C_INTMSK, intmask);
intmask &= ~KS32C_INTMSK_GLOBAL;
HAL_WRITE_UINT32(KS32C_INTMSK, intmask);
}
 
 
// This routine is called to respond to a hardware interrupt (IRQ). It
// should interrogate the hardware and return the IRQ vector number.
 
int hal_IRQ_handler(void)
{
// Do hardware-level IRQ handling
cyg_uint32 irq_status;
HAL_READ_UINT32(KS32C_INTOFFSET_IRQ, irq_status);
irq_status = irq_status / 4;
if (CYGNUM_HAL_ISR_MAX >= irq_status)
return irq_status;
// It's a bit bogus to test for FIQs after IRQs, but we use the
// latter more, so don't impose the overhead of checking for FIQs
HAL_READ_UINT32(KS32C_INTOFFSET_FIQ, irq_status);
irq_status = irq_status / 4;
if (CYGNUM_HAL_ISR_MAX >= irq_status)
return irq_status;
return CYGNUM_HAL_INTERRUPT_NONE;
}
 
 
//
// Interrupt control
//
 
void hal_interrupt_mask(int vector)
{
cyg_uint32 mask, old_mask;
HAL_READ_UINT32(KS32C_INTMSK, mask);
old_mask = mask;
mask |= (1<<vector);
HAL_WRITE_UINT32(KS32C_INTMSK, mask);
}
 
void hal_interrupt_unmask(int vector)
{
cyg_uint32 mask, old_mask;
HAL_READ_UINT32(KS32C_INTMSK, mask);
old_mask = mask;
mask &= ~(1<<vector);
HAL_WRITE_UINT32(KS32C_INTMSK, mask);
}
 
void hal_interrupt_acknowledge(int vector)
{
HAL_WRITE_UINT32(KS32C_INTPND, (1<<vector));
}
 
void hal_interrupt_configure(int vector, int level, int up)
{
}
 
void hal_interrupt_set_level(int vector, int level)
{
}
 
void hal_show_IRQ(int vector, int data, int handler)
{
}
 
// -------------------------------------------------------------------------
//
// Delay for some number of micro-seconds
//
void hal_delay_us(cyg_int32 usecs)
{
cyg_uint32 count;
cyg_uint32 ticks = ((CYGNUM_HAL_RTC_PERIOD*CYGNUM_HAL_RTC_DENOMINATOR)/1000000) * usecs;
cyg_uint32 tmod;
 
// Disable timer 1
HAL_READ_UINT32(KS32C_TMOD, tmod);
tmod &= ~(KS32C_TMOD_TE1);
HAL_WRITE_UINT32(KS32C_TMOD, tmod);
 
tmod &= ~(KS32C_TMOD_TMD1 | KS32C_TMOD_TCLR1);
tmod |= KS32C_TMOD_TE1;
 
// Clear pending flag
HAL_WRITE_UINT32(KS32C_INTPND, (1 << CYGNUM_HAL_INTERRUPT_TIMER1));
 
// Set counter
HAL_WRITE_UINT32(KS32C_TDATA1, ticks);
 
// And enable timer
HAL_WRITE_UINT32(KS32C_TMOD, tmod);
 
// Wait for timer to underflow. Can't test the timer completion
// bit without actually enabling the interrupt. So instead watch
// the counter.
ticks /= 2; // wait for this threshold
 
// Wait till timer counts below threshold
do {
HAL_READ_UINT32(KS32C_TCNT1, count);
} while (count >= ticks);
// then wait for it to be reloaded
do {
HAL_READ_UINT32(KS32C_TCNT1, count);
} while (count < ticks);
 
// Then disable timer 1 again
tmod &= ~KS32C_TMOD_TE1;
HAL_WRITE_UINT32(KS32C_TMOD, tmod);
}
 
// No way to reset board
 
void hal_reset(void)
{
CYG_INTERRUPT_STATE old;
HAL_DISABLE_INTERRUPTS(old);
while (1)
;
}
/v2_0/src/hal_diag.c
0,0 → 1,378
/*=============================================================================
//
// hal_diag.c
//
// HAL diagnostic output code
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
// Contributors:jskov
// Date: 2001-03-16
// Purpose: HAL diagnostic output
// Description: Implementations of HAL diagnostic output support.
//
//####DESCRIPTIONEND####
//
//===========================================================================*/
 
#include <pkgconf/hal.h>
#include CYGBLD_HAL_PLATFORM_H
 
#include <cyg/infra/cyg_type.h> // base types
 
#include <cyg/hal/hal_arch.h> // SAVE/RESTORE GP macros
#include <cyg/hal/hal_io.h> // IO macros
#include <cyg/hal/hal_if.h> // interface API
#include <cyg/hal/hal_intr.h> // HAL_ENABLE/MASK/UNMASK_INTERRUPTS
#include <cyg/hal/hal_misc.h> // Helper functions
#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED
 
#include <cyg/hal/plf_io.h> // SIO registers
 
#define SIO_BRDDIV (((CYGNUM_HAL_CPUCLOCK/2/16/CYGNUM_HAL_VIRTUAL_VECTOR_CHANNELS_DEFAULT_BAUD)<<4))
 
//-----------------------------------------------------------------------------
typedef struct {
cyg_uint8* base;
cyg_int32 msec_timeout;
int isr_vector_rx;
int isr_vector_tx;
} channel_data_t;
 
//-----------------------------------------------------------------------------
 
char hextab[] = "0123456789ABCDEF";
 
void putc_ser(int c)
{
cyg_uint8* base = (cyg_uint8*)KS32C_UART1_BASE;
cyg_uint32 status;
do {
HAL_READ_UINT32(base+KS32C_UART_STAT, status);
} while ((status & KS32C_UART_STAT_TXE) == 0);
 
HAL_WRITE_UINT32(base+KS32C_UART_TXBUF, c);
}
 
void putint(int a)
{
int i;
putc_ser('0');
putc_ser('x');
for (i = 0; i < 8; i++) {
putc_ser(hextab[(a>>(28-(4*i))) & 0x0f]);
}
putc_ser('\r');
putc_ser('\n');
}
 
void
init_ser(void)
{
cyg_uint8* base = (cyg_uint8*)KS32C_UART1_BASE;
 
// 8-1-no parity.
HAL_WRITE_UINT32(base+KS32C_UART_LCON,
KS32C_UART_LCON_8_DBITS|KS32C_UART_LCON_1_SBITS|KS32C_UART_LCON_NO_PARITY);
 
// Mask interrupts.
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_UART0_RX);
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_UART0_TX);
 
HAL_WRITE_UINT32(base+KS32C_UART_BRDIV, SIO_BRDDIV);
}
 
//-----------------------------------------------------------------------------
 
static void
cyg_hal_plf_serial_init_channel(void* __ch_data)
{
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
 
// 8-1-no parity.
HAL_WRITE_UINT32(base+KS32C_UART_LCON,
KS32C_UART_LCON_8_DBITS|KS32C_UART_LCON_1_SBITS|KS32C_UART_LCON_NO_PARITY);
 
HAL_WRITE_UINT32(base+KS32C_UART_BRDIV, SIO_BRDDIV);
 
// Mask interrupts
HAL_INTERRUPT_MASK(((channel_data_t*)__ch_data)->isr_vector_rx);
HAL_INTERRUPT_MASK(((channel_data_t*)__ch_data)->isr_vector_tx);
 
// Enable RX and TX
HAL_WRITE_UINT32(base+KS32C_UART_CON, KS32C_UART_CON_RXM_INT|KS32C_UART_CON_TXM_INT);
}
 
void
cyg_hal_plf_serial_putc(void *__ch_data, char c)
{
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
cyg_uint32 status, ch;
CYGARC_HAL_SAVE_GP();
 
do {
HAL_READ_UINT32(base+KS32C_UART_STAT, status);
} while ((status & KS32C_UART_STAT_TXE) == 0);
 
ch = (cyg_uint32)c;
HAL_WRITE_UINT32(base+KS32C_UART_TXBUF, ch);
 
CYGARC_HAL_RESTORE_GP();
}
 
static cyg_bool
cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
{
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_uint8* base = chan->base;
cyg_uint32 stat;
cyg_uint32 c;
 
HAL_READ_UINT32(base+KS32C_UART_STAT, stat);
if ((stat & KS32C_UART_STAT_RDR) == 0)
return false;
 
HAL_READ_UINT32(base+KS32C_UART_RXBUF, c);
*ch = (cyg_uint8)(c & 0xff);
 
HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector_rx);
 
return true;
}
 
cyg_uint8
cyg_hal_plf_serial_getc(void* __ch_data)
{
cyg_uint8 ch;
CYGARC_HAL_SAVE_GP();
 
while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
 
CYGARC_HAL_RESTORE_GP();
return ch;
}
 
static void
cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
cyg_uint32 __len)
{
CYGARC_HAL_SAVE_GP();
 
while(__len-- > 0)
cyg_hal_plf_serial_putc(__ch_data, *__buf++);
 
CYGARC_HAL_RESTORE_GP();
}
 
static void
cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
{
CYGARC_HAL_SAVE_GP();
 
while(__len-- > 0)
*__buf++ = cyg_hal_plf_serial_getc(__ch_data);
 
CYGARC_HAL_RESTORE_GP();
}
 
cyg_bool
cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
{
int delay_count;
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_bool res;
CYGARC_HAL_SAVE_GP();
 
delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
 
for(;;) {
res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
if (res || 0 == delay_count--)
break;
CYGACC_CALL_IF_DELAY_US(100);
}
 
CYGARC_HAL_RESTORE_GP();
return res;
}
 
static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
int ret = 0;
CYGARC_HAL_SAVE_GP();
 
switch (__func) {
case __COMMCTL_IRQ_ENABLE:
irq_state = 1;
HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector_rx);
HAL_INTERRUPT_UNMASK(chan->isr_vector_rx);
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
HAL_INTERRUPT_MASK(chan->isr_vector_rx);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector_rx;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
 
va_start(ap, __func);
 
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
 
va_end(ap);
}
default:
break;
}
CYGARC_HAL_RESTORE_GP();
return ret;
}
 
static int
cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
int res = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_uint32 c;
cyg_uint8 ch;
cyg_uint32 stat;
CYGARC_HAL_SAVE_GP();
 
*__ctrlc = 0;
HAL_READ_UINT32(chan->base+KS32C_UART_STAT, stat);
if ( (stat & KS32C_UART_STAT_RDR) != 0 ) {
 
HAL_READ_UINT32(chan->base+KS32C_UART_RXBUF, c);
ch = (cyg_uint8)(c & 0xff);
if( cyg_hal_is_break( &ch , 1 ) )
*__ctrlc = 1;
 
res = CYG_ISR_HANDLED;
}
 
HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector_rx);
 
CYGARC_HAL_RESTORE_GP();
return res;
}
 
static channel_data_t ks32c_ser_channels[2] = {
{ (cyg_uint8*)KS32C_UART0_BASE, 1000, CYGNUM_HAL_INTERRUPT_UART0_RX, CYGNUM_HAL_INTERRUPT_UART0_TX },
{ (cyg_uint8*)KS32C_UART1_BASE, 1000, CYGNUM_HAL_INTERRUPT_UART1_RX, CYGNUM_HAL_INTERRUPT_UART1_TX }
};
 
static void
cyg_hal_plf_serial_init(void)
{
hal_virtual_comm_table_t* comm;
int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
 
// Init channels
cyg_hal_plf_serial_init_channel(&ks32c_ser_channels[0]);
cyg_hal_plf_serial_init_channel(&ks32c_ser_channels[1]);
 
// Setup procs in the vector table
 
// Set channel 0
CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &ks32c_ser_channels[0]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
 
// Set channel 1
CYGACC_CALL_IF_SET_CONSOLE_COMM(1);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &ks32c_ser_channels[1]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
 
// Restore original console
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
}
 
void
cyg_hal_plf_comms_init(void)
{
static int initialized = 0;
 
if (initialized)
return;
 
initialized = 1;
 
cyg_hal_plf_serial_init();
}
 
//-----------------------------------------------------------------------------
// LED
void
hal_diag_led(int mask)
{
#if 0
cyg_uint32 l;
 
HAL_READ_UINT32(KS32C_IOPDATA, l);
l &= ~0x000000f0;
l |= (mask & 0xf) << 4;
HAL_WRITE_UINT32(KS32C_IOPDATA, l);
#endif
}
 
//-----------------------------------------------------------------------------
// End of hal_diag.c
/v2_0/misc/redboot_RAM.ecm
0,0 → 1,72
cdl_savefile_version 1;
cdl_savefile_command cdl_savefile_version {};
cdl_savefile_command cdl_savefile_command {};
cdl_savefile_command cdl_configuration { description hardware template package };
cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
 
cdl_configuration eCos {
description "" ;
hardware snds ;
template redboot ;
package -hardware CYGPKG_HAL_ARM v2_0 ;
package -hardware CYGPKG_HAL_ARM_SNDS v2_0 ;
package -template CYGPKG_HAL v2_0 ;
package -template CYGPKG_INFRA v2_0 ;
package -template CYGPKG_REDBOOT v2_0 ;
package -template CYGPKG_ISOINFRA v2_0 ;
package -template CYGPKG_LIBC_STRING v2_0 ;
package -template CYGPKG_NS_DNS v2_0 ;
};
 
cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
user_value 6144
};
 
cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
user_value 0
};
 
cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
inferred_value 0
};
 
cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
inferred_value 1
};
 
cdl_option CYGHWR_HAL_ARM_BIGENDIAN {
user_value 1
};
 
cdl_component CYGBLD_BUILD_REDBOOT {
user_value 1
};
 
cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_DNS_HEADER {
inferred_value 1 <cyg/ns/dns/dns.h>
};
 
cdl_option CYGPKG_NS_DNS_BUILD {
inferred_value 0
};
 
 
/v2_0/misc/redboot_ROM.ecm
0,0 → 1,80
cdl_savefile_version 1;
cdl_savefile_command cdl_savefile_version {};
cdl_savefile_command cdl_savefile_command {};
cdl_savefile_command cdl_configuration { description hardware template package };
cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
 
cdl_configuration eCos {
description "" ;
hardware snds ;
template redboot ;
package -hardware CYGPKG_HAL_ARM v2_0 ;
package -hardware CYGPKG_HAL_ARM_SNDS v2_0 ;
package -template CYGPKG_HAL v2_0 ;
package -template CYGPKG_INFRA v2_0 ;
package -template CYGPKG_REDBOOT v2_0 ;
package -template CYGPKG_ISOINFRA v2_0 ;
package -template CYGPKG_LIBC_STRING v2_0 ;
package -template CYGPKG_NS_DNS v2_0 ;
};
 
cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
user_value 6144
};
 
cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
user_value 0
};
 
cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
inferred_value 0
};
 
cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
inferred_value 1
};
 
cdl_option CYGSEM_HAL_ROM_MONITOR {
inferred_value 1
};
 
cdl_option CYGHWR_HAL_ARM_BIGENDIAN {
user_value 1
};
 
cdl_component CYG_HAL_STARTUP {
user_value ROM
};
 
cdl_component CYGBLD_BUILD_REDBOOT {
user_value 1
};
 
cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
inferred_value 1 <cyg/libc/string/string.h>
};
 
cdl_option CYGBLD_ISO_DNS_HEADER {
inferred_value 1 <cyg/ns/dns/dns.h>
};
 
cdl_option CYGPKG_NS_DNS_BUILD {
inferred_value 0
};
 
 

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