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Rev 27 → Rev 174

/mcf52xx/mcf5272/proc/v2_0/cdl/hal_m68k_mcf52xx_mcf5272.cdl
0,0 → 1,62
# ====================================================================
#
# hal_m68k_m68000.cdl
#
# M68K/M68000 variant architectural HAL package configuration data
#
# ====================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
# ====================================================================
 
cdl_package CYGPKG_HAL_M68K_MCF52xx_MCF5272 {
display "mcf5272 68k/Coldfire variant HAL"
parent CYGPKG_HAL_M68K_MCF52xx
requires CYGPKG_HAL_M68K_MCF52xx
implements CYGINT_HAL_M68K_VARIANT
hardware
include_dir cyg/hal
define_header hal_m68k_mcf52xx_mcf5272.h
 
description "The mcf5272 68k/Coldfire variant HAL package provides
generic support for this processor architecture. It is also
necessary to select a specific target platform HAL package."
 
define_proc {
puts $::cdl_header "#include <pkgconf/hal_m68k_mcf52xx.h>"
}
 
compile proc_startup.c proc_arch.S proc_misc.c memcpy.c
 
}
 
/mcf52xx/mcf5272/proc/v2_0/include/mcf5272_sim.h
0,0 → 1,568
#ifndef MCF5272_SIM_H
#define MCF5272_SIM_H
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
 
/*
 
Defines for the mcf5272 System Integration Module (SIM)
 
*/
 
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>
 
/* General configuration registers. */
typedef struct mcf5272_sim_cfg_t
{
 
u32_t mbar; /* Module base address register */
/* (MBAR), after initialization */
 
u16_t scr; /* System configuration register */
 
u16_t spr; /* System protection register */
 
u32_t pmr; /* Power management register */
 
u16_t res1;
 
u16_t alpr; /* Active low power register */
 
u32_t dir; /* Device identification register */
 
u32_t res2[3];
 
} __attribute__ ((aligned (4), packed)) mcf5272_sim_cfg_t;
 
/* Interrupt controller registers. */
typedef struct mcf5272_sim_int_t
{
 
u32_t icr[4]; /* Interrupt control register 1-4 */
 
u32_t isr; /* Interrupt source register */
 
u32_t pitr; /* Programmable interrupt */
/* transition register */
 
u32_t piwr; /* Programmable interrupt wakeup */
/* register */
 
u8_t res1[3];
 
u8_t ipvr; /* Programmable interrupt vector */
/* register */
 
} __attribute__ ((aligned (4), packed)) mcf5272_sim_int_t;
 
/* Chip Select Module */
typedef struct mcf5272_sim_cs_t
{
 
u32_t csbr; /* CS base register. */
 
u32_t csor; /* CS option register. */
 
} __attribute__ ((aligned (4), packed)) mcf5272_sim_cs_t;
 
/* General Purpose I/O Module */
typedef struct mcf5272_sim_gpio_t
{
 
/* Use the following labels to initialize the bits in the data */
/* direction registers. Setting the bit to zero indicates that this */
/* pin is an input, one indicates an input. */
 
#define MCF5272_GPIO_DDR_IN (0)
#define MCF5272_GPIO_DDR_OUT (1)
 
u32_t pacnt; /* Port A control register. */
 
u16_t paddr; /* Port A data direction */
/* register. */
 
u16_t padat; /* Port A data register. */
 
u32_t pbcnt; /* Port B control register. */
 
/* Set these bits in the port B control register to enable the */
/* Ethernet, UART0, and data transfer acknowledge pins. */
 
#define MCF5272_GPIO_PBCNT_ETH_EN (0x55550000)
#define MCF5272_GPIO_PBCNT_ETH_DE (0x00000000)
#define MCF5272_GPIO_PBCNT_ETH_MSK (0xFFFF0000)
 
#define MCF5272_GPIO_PBCNT_TA_EN (0x00000400)
#define MCF5272_GPIO_PBCNT_TA_DE (0x00000000)
#define MCF5272_GPIO_PBCNT_TA_MSK (0x00000C00)
 
#define MCF5272_GPIO_PBCNT_URT0_EN (0x00000155)
#define MCF5272_GPIO_PBCNT_URT0_DE (0x00000000)
#define MCF5272_GPIO_PBCNT_URT0_MSK (0x000003FF)
 
u16_t pbddr; /* Port B data direction */
/* register. */
 
u16_t pbdat; /* Port B data register. */
 
u32_t res1;
 
u16_t pcddr; /* Port C data direction */
/* register. */
 
u16_t pcdat; /* Port C data register. */
 
u32_t pdcnt; /* Port D control register. */
 
/* Set these bits in the port D control register to enable the UART1 */
/* and interrupt 4 pins. */
 
#define MCF5272_GPIO_PDCNT_INT4_EN (0x00000C00)
#define MCF5272_GPIO_PDCNT_INT4_DE (0x00000000)
#define MCF5272_GPIO_PDCNT_INT4_MSK (0x00000C00)
 
#define MCF5272_GPIO_PDCNT_URT1_EN (0x000002AA)
#define MCF5272_GPIO_PDCNT_URT1_DE (0x00000000)
#define MCF5272_GPIO_PDCNT_URT1_MSK (0x000003FF)
 
u16_t res2;
u16_t res3;
 
} __attribute__ ((aligned (4), packed)) mcf5272_sim_gpio_t;
 
/* UART Module */
typedef struct mcf5272_sim_uart_t
{
 
u8_t umr; /* UART mode register. */
u8_t res1[3];
 
#define MCF5272_UART_UMR_8BNP (0x13) /* Write this value to umr1 to */
/* program the device for 8 bits */
/* and no parity. */
 
#define MCF5272_UART_UMR_1S (0x07) /* Write this value to umr2 to */
/* program the device for 1 stop */
/* bit. */
 
u8_t usr_ucsr; /* UART status register (R) and */
u8_t res2[3]; /* UART clock-select register (W). */
 
#define MCF5272_UART_USR_RRDY (1<<0) /* Bit 0 of the device status */
/* register is set when the receive */
/* data register contains data. If */
/* the data is not removed from the */
/* holding register, additional */
/* data will be placed in the FIFO */
/* until the FIFO is overrun. */
 
#define MCF5272_UART_USR_FFUL (1<<1) /* Bit 1 of the device status */
/* register is set when the receive */
/* data FIFO is full. If a */
/* character is not removed before */
/* the next character is received, */
/* overrun will occur. */
 
#define MCF5272_UART_USR_TXRDY (1<<2) /* Bit 2 of the device status */
/* register is set when the */
/* transmit data holding register */
/* is empty. Note that this is */
/* different than the FIFO being */
/* empty as the FIFO may still */
/* contain characters even if the */
/* holding register is empty. */
 
#define MCF5272_UART_USR_TXEMP (1<<3) /* Bit 3 of the device status */
/* register is set when the */
/* transmit data FIFO is empty. */
 
#define MCF5272_UART_USR_OE (1<<4) /* Bit 4 of the device status */
/* register is set when an overrun */
/* error has occurred. */
 
#define MCF5272_UART_USR_PE (1<<5) /* Bit 5 of the device status */
/* register is set when a parity */
/* error has occurred. */
 
#define MCF5272_UART_USR_FE (1<<6) /* Bit 6 of the device status */
/* register is set when a framing */
/* error has occurred. */
 
#define MCF5272_UART_USR_RB (1<<7) /* Bit 7 of the device status */
/* register is set when a change in */
/* break status has occurred on the */
/* port. */
 
#define MCF5272_UART_UCSR_CLKIN (0xDD) /* Writing this value to the ucsr */
/* selects CLKIN/16 as the UART's */
/* clock source. */
 
u8_t ucr; /* UART command register (W). */
u8_t res3[3];
 
#define MCF5272_UART_UCR_RMR (0x01<<4) /* Write this value to ucr to */
/* reset the mode register to umr1. */
 
#define MCF5272_UART_UCR_RRX (0x02<<4) /* Write this value to ucr to */
/* reset the receiver. */
 
#define MCF5272_UART_UCR_RTX (0x03<<4) /* Write this value to ucr to */
/* reset the transmitter. */
 
#define MCF5272_UART_UCR_RES (0x04<<4) /* Write this value to ucr to */
/* reset the error status. */
 
#define MCF5272_UART_UCR_RBC (0x05<<4) /* Write this value to ucr to */
/* reset the break change */
/* interrupt. */
 
#define MCF5272_UART_UCR_TXEN (1<<2) /* Write this value to ucr to */
/* enable the transmitter. */
 
#define MCF5272_UART_UCR_TXDE (1<<3) /* Write this value to ucr to */
/* disable the transmitter. */
 
#define MCF5272_UART_UCR_RXEN (1<<0) /* Write this value to ucr to */
/* enable the receiver. */
 
#define MCF5272_UART_UCR_RXDE (1<<1) /* Write this value to ucr to */
/* disable the receiver. */
 
/* Write this value to the ucr to */
/* enablt the transmitter and */
/* receiver. */
 
#define MCF5272_UART_UCR_TXRXEN \
(MCF5272_UART_UCR_TXEN | \
MCF5272_UART_UCR_RXEN)
 
u8_t urb_utb; /* UART receiver buffers (R) and */
u8_t res4[3]; /* UART transmitter buffers (W). */
 
u8_t uipcr_uacr; /* UART input port change */
u8_t res5[3]; /* register (R) and UART auxiliary */
/* control register (W). */
 
u8_t uisr_uimr; /* UART interrupt status register */
u8_t res6[3]; /* (R) and UART interrupt mask */
/* register (W). */
 
u8_t udu; /* UART divider upper register */
u8_t res7[3]; /* (W). */
 
u8_t udl; /* UART divider lower register */
u8_t res8[3]; /* (W). */
 
u8_t uabu; /* UART autobaud register MSB */
u8_t res9[3]; /* (R). */
 
u8_t uabl; /* UART autobaud register LSB */
u8_t res10[3]; /* (R). */
 
u8_t utf; /* UART transmitter FIFO */
u8_t res11[3]; /* register. */
 
#define MCF5272_UART_UTF_TXB (0x1F) /* Transmitter buffer data level. */
/* Indicates the number of bytes */
/* (0-24) currently stored in the */
/* transmitter FIFO. */
 
u8_t urf; /* UART receiver FIFO register. */
u8_t res12[3];
 
u8_t ufpd; /* UART Fractional Precision */
u8_t res13[3]; /* Divider Control register. */
 
u8_t uip; /* UART input port register (CTS) */
u8_t res14[3]; /* (R). */
 
u8_t uop1; /* UART output port bit set */
u8_t res15[3]; /* command register (RTS) (W). */
 
u8_t uop0; /* UART output port bit reset */
u8_t res16[3]; /* command register (RTS) (W). */
 
} __attribute__ ((aligned (4), packed)) mcf5272_sim_uart_t;
 
/* Timer Module */
typedef struct mcf5272_sim_timer_t
{
 
u16_t tmr; /* Timer Mode Register */
u16_t res1;
 
#define MCF5272_TIMER_TMR_PS 0xFF00 /* Prescaler. Programmed to */
#define MCF5272_TIMER_TMR_PS_BIT 8 /* divide the clock input by values */
/* from 1 to 256. The value */
/* 0000_0000 divides the clock by */
/* 1; the value 1111_1111 divides */
/* the clock by 256. */
 
#define MCF5272_TIMER_TMR_CE 0x00C0 /* Capture edge and enable */
#define MCF5272_TIMER_TMR_CE_BIT 6 /* interrupt. 00 Disable capture */
/* and interrupt on capture event */
/* 01 Capture on rising edge only */
/* and generate interrupt on */
/* capture event 10 Capture on */
/* falling edge only and generate */
/* interrupt on capture event 11 */
/* Capture on any edge and generate */
/* interrupt on capture event. */
 
#define MCF5272_TIMER_TMR_OM 0x0020 /* Output mode (TMR0 and TMR1 */
#define MCF5272_TIMER_TMR_OM_BIT 5 /* only. Reserved in TMR2 and */
/* TMR3). 0 Active-low pulse for */
/* one system clock cycle (15 nS at */
/* 66 MHz). 1 Toggle output; TOUTn */
/* is high at reset but is */
/* unavailable externally until the */
/* appropriate port control */
/* register is configured for this */
/* function. */
 
#define MCF5272_TIMER_TMR_ORI 0x0010 /* Output reference interrupt */
#define MCF5272_TIMER_TMR_ORI_BIT 4 /* enable. 0 Disable interrupt for */
/* reference reached (does not */
/* affect interrupt on capture */
/* function). 1 Enable interrupt */
/* upon reaching the reference */
/* value. If ORI is 1 when the */
/* TER[REF] is set, an immediate */
/* interrupt occurs. */
 
#define MCF5272_TIMER_TMR_FRR 0x0008 /* Free run/restart. 0 Free run. */
#define MCF5272_TIMER_TMR_FRR_BIT 3 /* Timer count continues to */
/* increment after the reference */
/* value is reached. 1 Restart. */
/* Timer count is reset immediately */
/* after the reference value is */
/* reached. */
 
#define MCF5272_TIMER_TMR_CLK 0x0006 /* Input clock source for the */
#define MCF5272_TIMER_TMR_CLK_BIT 1 /* timer. 00 Stop count. 01 */
/* Master system clock. 10 Master */
/* system clock divided by 16. */
/* TIN0 and TIN1 are external to */
/* the MCF5272 and are not */
/* synchronized to the system */
/* clock, so successive timeout */
/* lengths may vary slightly. 11 */
/* Corresponding TIN pin, TIN0 or */
/* TIN1 (falling edge), unused in */
/* TMR2 and TMR3. The minimum high */
/* and low periods for TIN as the */
/* clock source is 1 system clock, */
/* which gives a maximum TIN */
/* frequency of clock/2. */
 
#define MCF5272_TIMER_TMR_RST 0x0001 /* Reset timer. 0 A transition */
#define MCF5272_TIMER_TMR_RST_BIT 0 /* from 1 to 0 resets the timer. */
/* Other register values can be */
/* written. The */
/* counter/timer/prescaler are not */
/* clocked unless the timer is */
/* enabled. 1 Enable timer. */
 
u16_t trr; /* Timer Reference Register */
u16_t res2;
 
u16_t tcap; /* Timer Capture Register */
u16_t res3;
 
u16_t tcn; /* Timer Counter */
u16_t res4;
 
u16_t ter; /* Timer Event Register */
u16_t res5;
 
#define MCF5272_TIMER_TER_REF (0x0002) /* Output reference event. If */
#define MCF5272_TIMER_TER_REF_BIT (1) /* the bit is 0, the counter has */
/* not reached the TRR value; */
/* otherwise, the counter has */
/* reached the TRR value. Writing */
/* a 1 clears this bit. */
 
#define MCF5272_TIMER_TER_CAP (0x0001) /* Captuer event. If this bit is */
#define MCF5272_TIMER_TER_CAP_BIT (0) /* 0, the counter value has not */
/* been latched into the TCR; */
/* otherwise, the counter value is */
/* latched into the TCR. Writing a */
/* 1 clears this bit. */
 
u32_t res6[3];
 
} __attribute__ ((aligned (4), packed)) mcf5272_sim_timer_t;
 
/* Watchdog timer */
typedef struct mcf5272_sim_wdtmr_t
{
 
u16_t wrrr; /* Watchdog reset reference */
u16_t res1; /* register. */
 
u16_t wirr; /* Watchdog interrupt reference */
u16_t res2; /* register. */
 
u16_t wcr; /* Watchdog counter register. */
u16_t res3;
 
u16_t wer; /* Watchdog event register. */
u16_t res4;
 
u32_t res5[28];
 
} __attribute__ ((aligned (4), packed)) mcf5272_sim_wdtmr_t;
 
/* Ethernet Module */
typedef struct mcf5272_sim_enet_t
{
 
u8_t res1[0x40];
 
u32_t ecr; /* Ethernet control register */
 
u32_t eir; /* Interrupt event register */
 
u32_t eimr; /* Interrupt mask register */
 
u32_t ivsr; /* Interrupt vector status */
/* register */
 
u32_t rdar; /* Receive descriptor active */
/* register */
 
u32_t tdar; /* Transmit descriptor active */
/* register */
 
u8_t res2[0x0880-0x0858];
 
u32_t mmfr; /* MII management frame register */
 
u32_t mscr; /* MII speed control register */
 
u8_t res3[0x08cc-0x0888];
 
u32_t frbr; /* FIFO receive bound register */
 
u32_t frsr; /* FIFO receive start register */
 
u8_t res4[0x08e4-0x08d4];
 
u32_t tfwr; /* Transmit FIFO watermark */
 
u8_t res5[0x08ec-0x08e8];
 
u32_t tfsr; /* Transmit FIFO start register */
 
u8_t res6[0x0944-0x08f0];
 
u32_t rcr; /* Receive control register */
 
u32_t mflr; /* Maximum frame length register */
 
u8_t res7[0x0984-0x094c];
 
u32_t tcr; /* Transmit control register */
 
u8_t res8[0x0c00-0x0988];
 
u32_t malr; /* Lower 32-bits of MAC address */
 
u32_t maur; /* Upper 16-bits of MAC address */
 
u32_t htur; /* Upper 32-bits of hash table */
 
u32_t htlr; /* Lower 32-bits of hash table */
 
u32_t erdsr; /* Pointer to receive descriptor */
/* ring */
 
u32_t etdsr; /* Pointer to transmit descriptor */
/* ring */
 
u32_t emrbr; /* Maximum receive buffer size */
 
u8_t res9[0x0c40-0x0c1c];
 
u8_t efifo[448]; /* FIFO RAM space */
 
u8_t res10[0x1000-0x0e00];
 
} __attribute__ ((aligned (4), packed)) mcf5272_sim_enet_t;
 
/* System Integration Module (SIM) This structure defines each */
/* register's offset from the current value of the mbar register. */
typedef struct mcf5272_sim_t
{
 
mcf5272_sim_cfg_t cfg; /* 0x0000: General configuration */
/* registers. */
 
mcf5272_sim_int_t intc; /* 0x0020: Interrupt controller */
/* registers. */
 
mcf5272_sim_cs_t cs[8]; /* 0x0040: Chip Select Module */
 
mcf5272_sim_gpio_t gpio; /* 0x0080: General purpose I/O */
/* control registers */
 
u32_t qspi[8]; /* 0x00a0: Queued serial */
/* peripheral interface module. */
 
u32_t pwm[8]; /* 0x00c0: Pulse Width Modulation */
/* (PWM) Module */
 
u32_t dmac[8]; /* 0x00e0: DMA Controller */
 
mcf5272_sim_uart_t uart[2]; /* 0x0100: UART Modules */
 
u32_t sdramc[32]; /* 0x0180: SDRAM Controller */
 
mcf5272_sim_timer_t timer[4]; /* 0x0200: Timer Module */
 
mcf5272_sim_wdtmr_t wdtimer; /* 0x0280: Watchdog Timer Module */
 
u32_t plic[320]; /* 0x0300: Physical Layer */
/* Interface Controller */
 
mcf5272_sim_enet_t enet; /* 0x0800: Ethernet Module */
 
u32_t usb[512]; /* 0x1000: Universal Serial Bus */
 
} __attribute__ ((aligned (4), packed)) mcf5272_sim_t;
 
#endif /* MCF5272_SIM_H */
 
/mcf52xx/mcf5272/proc/v2_0/include/proc_intr.h
0,0 → 1,211
#ifndef CYGONCE_HAL_PROC_INTR_H
#define CYGONCE_HAL_PROC_INTR_H
 
//==========================================================================
//
// proc_intr.h
//
// mcf5272 Processor variant interrupt and clock support
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
 
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>
 
// Include any platform specific interrupt definitions.
#include <cyg/hal/plf_intr.h>
 
// Include for the SIM address (MCF5272_SIM).
#include <cyg/hal/proc_arch.h>
 
//---------------------------------------------------------------------------
// Interrupt controller management
 
// This chip has a programmable interrupt vector base which is different
// from the vector base register (VBR). All interrupts from the interrupt
// controller are offsets from the programmable interrupt vector register
// (PIVR).
 
#define HAL_PROG_INT_VEC_BASE 64
 
// Vector numbers defined by the interrupt controller.
// These are all relative to the interrupt vector base number.
#define CYGNUM_HAL_VECTOR_USR_SPUR_INT (0 + HAL_PROG_INT_VEC_BASE)
#define CYGNUM_HAL_VECTOR_EXTINT1 (1 + HAL_PROG_INT_VEC_BASE)
#define CYGNUM_HAL_VECTOR_EXTINT2 (2 + HAL_PROG_INT_VEC_BASE)
#define CYGNUM_HAL_VECTOR_EXTINT3 (3 + HAL_PROG_INT_VEC_BASE)
#define CYGNUM_HAL_VECTOR_EXTINT4 (4 + HAL_PROG_INT_VEC_BASE)
#define CYGNUM_HAL_VECTOR_TMR1 (5 + HAL_PROG_INT_VEC_BASE)
#define CYGNUM_HAL_VECTOR_TMR2 (6 + HAL_PROG_INT_VEC_BASE)
#define CYGNUM_HAL_VECTOR_TMR3 (7 + HAL_PROG_INT_VEC_BASE)
#define CYGNUM_HAL_VECTOR_TMR4 (8 + HAL_PROG_INT_VEC_BASE)
#define CYGNUM_HAL_VECTOR_UART1 (9 + HAL_PROG_INT_VEC_BASE)
#define CYGNUM_HAL_VECTOR_UART2 (10 + HAL_PROG_INT_VEC_BASE)
#define CYGNUM_HAL_VECTOR_PLIP (11 + HAL_PROG_INT_VEC_BASE)
#define CYGNUM_HAL_VECTOR_PLIA (12 + HAL_PROG_INT_VEC_BASE)
#define CYGNUM_HAL_VECTOR_USB0 (13 + HAL_PROG_INT_VEC_BASE)
#define CYGNUM_HAL_VECTOR_USB1 (14 + HAL_PROG_INT_VEC_BASE)
#define CYGNUM_HAL_VECTOR_USB2 (15 + HAL_PROG_INT_VEC_BASE)
#define CYGNUM_HAL_VECTOR_USB3 (16 + HAL_PROG_INT_VEC_BASE)
#define CYGNUM_HAL_VECTOR_USB4 (17 + HAL_PROG_INT_VEC_BASE)
#define CYGNUM_HAL_VECTOR_USB5 (18 + HAL_PROG_INT_VEC_BASE)
#define CYGNUM_HAL_VECTOR_USB6 (19 + HAL_PROG_INT_VEC_BASE)
#define CYGNUM_HAL_VECTOR_USB7 (20 + HAL_PROG_INT_VEC_BASE)
#define CYGNUM_HAL_VECTOR_DMA (21 + HAL_PROG_INT_VEC_BASE)
#define CYGNUM_HAL_VECTOR_ERX (22 + HAL_PROG_INT_VEC_BASE)
#define CYGNUM_HAL_VECTOR_ETX (23 + HAL_PROG_INT_VEC_BASE)
#define CYGNUM_HAL_VECTOR_ENTC (24 + HAL_PROG_INT_VEC_BASE)
#define CYGNUM_HAL_VECTOR_QSPI (25 + HAL_PROG_INT_VEC_BASE)
#define CYGNUM_HAL_VECTOR_EXTINT5 (26 + HAL_PROG_INT_VEC_BASE)
#define CYGNUM_HAL_VECTOR_EXTINT6 (27 + HAL_PROG_INT_VEC_BASE)
#define CYGNUM_HAL_VECTOR_SWTO (28 + HAL_PROG_INT_VEC_BASE)
#define CYGNUM_HAL_VECTOR_RES1 (29 + HAL_PROG_INT_VEC_BASE)
#define CYGNUM_HAL_VECTOR_RES2 (30 + HAL_PROG_INT_VEC_BASE)
#define CYGNUM_HAL_VECTOR_RES3 (31 + HAL_PROG_INT_VEC_BASE)
 
//---------------------------------------------------------------------------
// Interrupt controller macros.
 
// Declare a mirror copy of the interrupt control registers used to set
// interrupt priorities. In order to mask and unmask a specific interrupt, we
// must be able to set its priority to zero and then restore it to ist
// original priority. We use these locations to determine the level to
// restore the interrupt to in the unmask macro.
 
externC cyg_uint32 hal_icr_pri_mirror[4];
 
// Block the interrupt associated with the given vector. To do this, we
// set the interrupt priority level to zero for the specified interrupt. To
// set the interrupt priority level, we simultaneously write a 1 to the
// pending interrupt field. The other interrupts are unaffected. Disable all
// interrupts while we access the hardware registers.
 
#define HAL_INTERRUPT_MASK( _vector_ ) \
CYG_MACRO_START \
cyg_uint32 _vec_offset = (_vector_) - HAL_PROG_INT_VEC_BASE - 1; \
cyg_uint32 _icr = _vec_offset / 8; \
cyg_uint32 _icr_msk = 0xf0000000 >> ((_vec_offset % 8) * 4); \
CYG_INTERRUPT_STATE _intr_state; \
HAL_DISABLE_INTERRUPTS(_intr_state); \
MCF5272_SIM->intc.icr[_icr] &= _icr_msk ^ 0x77777777; \
HAL_RESTORE_INTERRUPTS(_intr_state); \
CYG_MACRO_END
 
// Unblock the interrupt associated with the given vector. Set the
// interrupt priority using the value from the icr mirror variable. Disable
// all interrupts while we access the hardware registers.
 
#define HAL_INTERRUPT_UNMASK( _vector_ ) \
CYG_MACRO_START \
cyg_uint32 _vec_offset = (_vector_) - HAL_PROG_INT_VEC_BASE - 1; \
cyg_uint32 _icr = _vec_offset / 8; \
cyg_uint32 _icr_msk_offset = ((8-1)*4) - (_vec_offset % 8) * 4; \
cyg_uint32 _icr_msk = 0x0F << (_icr_msk_offset); \
cyg_uint32 _icr_val; \
CYG_INTERRUPT_STATE _intr_state; \
HAL_DISABLE_INTERRUPTS(_intr_state); \
_icr_val = MCF5272_SIM->intc.icr[_icr] & 0x77777777 & ~_icr_msk; \
_icr_val |= hal_icr_pri_mirror[_icr] & _icr_msk; \
_icr_val |= 0x08 << _icr_msk_offset; \
MCF5272_SIM->intc.icr[_icr] = _icr_val; \
HAL_RESTORE_INTERRUPTS(_intr_state); \
CYG_MACRO_END
 
// Acknowledge the interrupt by writing a 1 to the corresponding
// interrupt pending bit. Write 0 to all other interrupt pending bits. Leave
// all priority levels unchanged. Disable all interrupts while we access the
// hardware registers.
 
#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
CYG_MACRO_START \
cyg_uint32 _vec_offset = (_vector_) - HAL_PROG_INT_VEC_BASE - 1; \
cyg_uint32 _icr = _vec_offset / 8; \
cyg_uint32 _icr_msk = 0x80000000 >> ((_vec_offset % 8) * 4); \
CYG_INTERRUPT_STATE _intr_state; \
HAL_DISABLE_INTERRUPTS(_intr_state); \
MCF5272_SIM->intc.icr[_icr] &= _icr_msk | 0x77777777; \
HAL_RESTORE_INTERRUPTS(_intr_state); \
CYG_MACRO_END
 
// Set the priority in the interrupt control register and the icr mirror.
// Do not copy the icr mirror into the icr because some interrupts may be
// masked. Disable all interrupts while we access the hardware registers.
 
#define HAL_INTERRUPT_SET_LEVEL( _vector_, _prilevel_ ) \
CYG_MACRO_START \
cyg_uint32 _vec_offset = (_vector_) - HAL_PROG_INT_VEC_BASE - 1; \
cyg_uint32 _icr = _vec_offset / 8; \
cyg_uint32 _icr_msk_offset = ((8-1)*4) - (_vec_offset % 8) * 4; \
cyg_uint32 _icr_msk = 0x0F << (_icr_msk_offset); \
cyg_uint32 _icr_val = (0x08 | (_prilevel_ & 0x07)) << _icr_msk_offset; \
CYG_INTERRUPT_STATE _intr_state; \
HAL_DISABLE_INTERRUPTS(_intr_state); \
cyg_uint32 _mir_val = hal_icr_pri_mirror[_icr] & 0x77777777 & ~_icr_msk; \
hal_icr_pri_mirror[_icr] = _mir_val | _icr_val; \
_icr_val |= MCF5272_SIM->intc.icr[_icr] & 0x77777777 & ~_icr_msk; \
MCF5272_SIM->intc.icr[_icr] = _icr_val; \
HAL_RESTORE_INTERRUPTS(_intr_state); \
CYG_MACRO_END
 
// Set/clear the interrupt transition register bit. Disable all
// interrupts while we access the hardware registers.
 
// WARNING: It seems that manual currently has the polarity of this bit
// wrong.
 
#define HAL_INTERRUPT_CONFIGURE( _vector_, _leveltriggered_, _up_ ) \
CYG_MACRO_START \
if (!(_leveltriggered_)) \
{ \
cyg_uint32 _vec_offset = (_vector_) - HAL_PROG_INT_VEC_BASE - 1; \
cyg_uint32 _itr_bit = 0x80000000 >> _vec_offset; \
CYG_INTERRUPT_STATE _intr_state; \
HAL_DISABLE_INTERRUPTS(_intr_state); \
if (_up_) \
{ \
MCF5272_SIM->intc.pitr |= _itr_bit; \
} \
else \
{ \
MCF5272_SIM->intc.pitr &= ~_itr_bit; \
} \
HAL_RESTORE_INTERRUPTS(_intr_state); \
} \
CYG_MACRO_END
 
//--------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_PROC_INTR_H
 
/mcf52xx/mcf5272/proc/v2_0/include/proc_arch.h
0,0 → 1,65
#ifndef CYGONCE_HAL_PROC_ARCH_H
#define CYGONCE_HAL_PROC_ARCH_H
//=============================================================================
//
// proc_arch.h
//
// Processor variant specific abstractions
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
 
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>
 
#include <cyg/hal/mcf5272_sim.h>
//#include <cyg/hal/hal_memmap.h>
 
// Declare the global pointer to the SIM registers.
// Everyone should use the MCF5272_SIM macro so it can be easily changed.
externC volatile mcf5272_sim_t * const mcf5272_sim_p;
#define MCF5272_SIM mcf5272_sim_p
//#define MCF5272_SIM ((volatile mcf5272_sim_t *) MCF5272_MBAR)
 
/* ************************************************************************ */
/* These routines write to the special purpose registers in the ColdFire */
/* core. Since these registers are write-only in the supervisor model, no */
/* corresponding read routines exist. */
 
externC void mcf5272_wr_mbar(CYG_WORD32);
 
//-----------------------------------------------------------------------------
#endif // CYGONCE_HAL_PROC_ARCH_H
 
/mcf52xx/mcf5272/proc/v2_0/include/proc_startup.h
0,0 → 1,49
#ifndef _PROC_STARTUP_H
#define _PROC_STARTUP_H
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
 
#include <cyg/infra/cyg_type.h>
 
// Include the platform-specific startup header.
 
#include <cyg/hal/plf_startup.h>
 
// Processor-specific reset vector initialization routine
 
externC void proc_reset(void);
 
#endif // _PROC_STARTUP_H
 
/mcf52xx/mcf5272/proc/v2_0/src/proc_misc.c
0,0 → 1,62
//==========================================================================
//
// proc_misc.c
//
// HAL implementation miscellaneous functions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
 
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>
 
#include <cyg/hal/proc_arch.h>
#include <cyg/hal/hal_memmap.h>
 
// Define the global pointer to the SIM registers.
 
volatile mcf5272_sim_t * const mcf5272_sim_p = (mcf5272_sim_t *)MCF5272_MBAR;
 
// Define a mirror copy of the interrupt control registers used to set
// interrupt priorities. In order to mask and unmask a specific interrupt, we
// must be able to set its priority to zero and then restore it to ist
// original priority. We use these locations to determine the level to
// restore the interrupt to in the unmask macro.
 
cyg_uint32 hal_icr_pri_mirror[4];
 
//--------------------------------------------------------------------------
// End of var_misc.c
 
/mcf52xx/mcf5272/proc/v2_0/src/proc_arch.S
0,0 → 1,68
##=============================================================================
##
## proc_arch.S
##
## mcf5272 processor code
##
##=============================================================================
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
##=============================================================================
 
#include <pkgconf/hal.h>
 
#------------------------------------------------------------------------------
# function declaration macro
 
#define FUNC_START(name) \
.text; \
.even; \
.globl name; \
name:
 
/* ************************************************************************ */
/* These routines write to the special purpose registers in the ColdFire */
/* core. Since these registers are write-only in the supervisor model, no */
/* corresponding read routines exist. */
 
FUNC_START(mcf5272_wr_mbar)
move.l 4(%sp),%d0
movec %d0,%mbar
nop
rts
 
##=============================================================================
##=============================================================================
 
 
/mcf52xx/mcf5272/proc/v2_0/src/proc_startup.c
0,0 → 1,90
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
 
#include <cyg/infra/cyg_type.h>
#include <pkgconf/hal.h>
#include <cyg/hal/hal_startup.h>
#include <cyg/hal/hal_memmap.h>
#include <cyg/hal/hal_arch.h>
#include <cyg/hal/hal_intr.h>
 
/*****************************************************************************
proc_reset -- Processor-specific reset vector initialization routine
 
This routine must be called with interrupts disabled.
 
INPUT:
 
OUTPUT:
 
RETURN VALUE:
 
None
 
*****************************************************************************/
void proc_reset(void)
{
int i;
 
// Set up the mapping of our internal registers. The LSB indicates that
// the registers are valid.
 
mcf5272_wr_mbar((CYG_WORD32)(MCF5272_MBAR | 1));
 
// Initialize the vector base register in the interrupt controller.
 
MCF5272_SIM->intc.ipvr = HAL_PROG_INT_VEC_BASE;
 
// Initialize the interrupt control register and the icr priority
// mirror. Disable all interrupts by setting all priorities to zero.
 
for (i=0; i < 4; i++)
{
MCF5272_SIM->intc.icr[i] = hal_icr_pri_mirror[i] = 0x88888888;
}
 
// Enable/disable the data transfter acknowledge output pin.
 
MCF5272_SIM->gpio.pbcnt = ((MCF5272_SIM->gpio.pbcnt &
~(MCF5272_GPIO_PBCNT_TA_MSK)) |
((HAL_MCF5272_ENABLE_DATA_TA) ?
(MCF5272_GPIO_PBCNT_TA_EN) :
(MCF5272_GPIO_PBCNT_TA_DE)));
 
// Do any platform-specific reset initialization.
 
plf_reset();
}
 
/mcf52xx/mcf5272/proc/v2_0/src/memcpy.c
0,0 → 1,123
//==========================================================================
//
// memcpy.c
//
// memcpy() routine for coldfire
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
 
/* INCLUDES */
 
#include <cyg/infra/cyg_type.h> /* Common type definitions */
#include <stddef.h> /* Compiler defns such as size_t, NULL etc. */
 
/* EXPORTED SYMBOLS */
 
externC void *
memcpy( void * s1, const void * s2, size_t n ) __attribute__((alias("_memcpy")));
 
/* FUNCTIONS */
 
void *
_memcpy( void * s1, const void * s2, size_t n )
{
char * dst = (char *) s1;
const char * src = (const char *) s2;
long longwords;
int_t rem_bytes;
int_t loops;
int_t loop_index;
 
/* Don't worry about alignment on the coldfire. Most large */
/* structures should be aligned anyway. */
 
longwords = (long)(n / 4);
rem_bytes = n % 4;
loops = (int_t)(longwords / 32);
loop_index = (int_t)(longwords % 32);
 
switch (loop_index)
{
do
{
*((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
case 31: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
case 30: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
case 29: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
case 28: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
case 27: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
case 26: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
case 25: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
case 24: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
case 23: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
case 22: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
case 21: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
case 20: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
case 19: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
case 18: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
case 17: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
case 16: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
case 15: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
case 14: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
case 13: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
case 12: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
case 11: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
case 10: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
case 9: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
case 8: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
case 7: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
case 6: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
case 5: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
case 4: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
case 3: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
case 2: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
case 1: *((cyg_uint32*)dst)++ = *((cyg_uint32*)src)++;
case 0: ; /* Keep compiler from complaining. */
} while (--loops >= 0);
}
 
/* Clean up the remaining bytes. */
 
while (--rem_bytes >= 0)
{
*dst++ = *src++;
}
 
return s1;
 
} /* _memcpy() */
 
/* EOF memcpy.c */
/mcf52xx/mcf5272/mcf5272c3/plf/v2_0/cdl/hal_m68k_mcf52xx_mcf5272_mcf5272c3.cdl
0,0 → 1,270
# ====================================================================
#
# hal_m68k_mcf52xx_mcf5272_mcf5272c3.cdl
#
# Motorola mcf5272c3 evaluation board HAL package configuration data
#
# ====================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
# ====================================================================
 
cdl_package CYGPKG_HAL_M68K_MCF52xx_MCF5272_MCF5272C3 {
display "Motorola mcf5272c3 evaluation board"
parent CYGPKG_HAL_M68K_MCF52xx_MCF5272
define_header hal_m68k_mcf52xx_mcf5272_mcf5272c3.h
include_dir cyg/hal
 
description "The Motorola mcf5272c3 evaluation board platform HAL
package should be used when targeting the actual hardware for
the Motorola mcf5272c3 evaluation board platform."
 
define_proc {
puts $::cdl_header "#include <pkgconf/hal_m68k_mcf52xx_mcf5272.h>"
}
 
compile plf_startup.c hal_diag.c
 
# implements CYGINT_HAL_DEBUG_GDB_STUBS
# implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
 
define_proc {
puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_m68k.h>"
puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H <pkgconf/hal_m68k_mcf52xx_mcf5272.h>"
puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_m68k_mcf52xx_mcf5272_mcf5272c3.h>"
}
 
cdl_component CYG_HAL_STARTUP {
display "Startup type"
flavor data
legal_values {"RAM" "ROM"}
default_value {"RAM"}
no_define
define -file system.h CYG_HAL_STARTUP
 
description "When targeting the Motorola mcf5272c3 evaluation board
it is expected that the image will be downloaded into RAM
via the Motorola dBUG monitor."
 
}
 
cdl_option CYGHWR_HAL_SYSTEM_CLOCK_MHZ {
display "System clock speed in MHz"
flavor data
legal_values 66
default_value 66
 
description "This option identifies the system clock that the
processor uses. This value is used to set clock dividers
for some devices."
 
}
 
cdl_option CYGHWR_HAL_M68K_MCF52xx_MCF5272_MCF5272C3_DIAG_BAUD {
display "Diagnostic Serial Port Baud Rate"
flavor data
legal_values 9600 19200 38400 115200
default_value 9600
 
description "This option selects the baud rate used for the
diagnostic port. Note: this should match the value chosen
for the GDB port if the diagnostic and GDB port are the
same."
 
}
 
cdl_option CYGHWR_HAL_M68K_MCF52xx_MCF5272_MCF5272C3_GDB_BAUD {
display "GDB Serial Port Baud Rate"
flavor data
legal_values 9600 19200 38400 115200
default_value 9600
 
description "This option controls the baud rate used for the GDB
connection."
 
}
 
# Real-time clock/counter specifics
cdl_component CYGNUM_HAL_RTC_CONSTANTS {
display "Real-time clock constants."
flavor none
 
description "Set the periodic timer on the mcf5272 to 1 ms or
1000000 ns."
 
cdl_option CYGNUM_HAL_RTC_NUMERATOR {
display "Real-time clock numerator"
flavor data
calculated 1000000000
}
cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
display "Real-time clock denominator"
flavor data
calculated 1000
}
cdl_option CYGNUM_HAL_RTC_PERIOD {
display "Real-time clock period"
flavor data
calculated 1000000
}
}
 
cdl_component CYGBLD_GLOBAL_OPTIONS {
display "Global build options"
flavor none
parent CYGPKG_NONE
 
description "Global build options including control over compiler
flags, linker flags and choice of toolchain."
 
cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
display "Global command prefix"
flavor data
no_define
default_value { "m68k-elf" }
 
description "This option specifies the command prefix used
when invoking the build tools."
 
}
 
cdl_option CYGBLD_GLOBAL_CFLAGS {
display "Global compiler flags"
flavor data
no_define
default_value { "-m5200 -malign-int -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-thunks=3 -finit-priority -fomit-frame-pointer" }
description "This option controls the global compiler flags
which are used to compile all packages by default.
Individual packages may define options which
override these global flags."
 
}
 
cdl_option CYGBLD_GLOBAL_LDFLAGS {
display "Global linker flags"
flavor data
no_define
default_value { "-m5200 -g -nostdlib -Wl,--gc-sections -Wl,-static" }
 
description "This option controls the global linker flags.
Individual packages may define options which
override these global flags."
 
}
 
cdl_option CYGBLD_BUILD_GDB_STUBS {
display "Build GDB stub ROM image"
default_value 0
requires { CYG_HAL_STARTUP == "ROM" }
requires CYGSEM_HAL_ROM_MONITOR
requires CYGBLD_BUILD_COMMON_GDB_STUBS
requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
requires ! CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
requires ! CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
no_define
 
description "This option enables the building of the GDB
stubs for the board. The common HAL controls
takes care of most of the build process, but the
final conversion from ELF image to binary data is
handled by the platform CDL, allowing relocation
of the data if necessary."
 
make -priority 320 {
<PREFIX>/bin/gdb_module.srec : <PREFIX>/bin/gdb_module.img
$(OBJCOPY) -O srec $< $@
}
}
}
 
cdl_component CYGHWR_MEMORY_LAYOUT {
display "Memory layout"
flavor data
no_define
calculated { CYG_HAL_STARTUP == "RAM" ? "m68k_mcf52xx_mcf5272_mcf5272c3_ram" : \
"m68k_mcf52xx_mcf5272_mcf5272c3_rom" }
 
cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
display "Memory layout linker script fragment"
flavor data
no_define
define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_m68k_mcf52xx_mcf5272_mcf5272c3_ram.ldi>" : \
"<pkgconf/mlt_m68k_mcf52xx_mcf5272_mcf5272c3_rom.ldi>" }
}
 
cdl_option CYGHWR_MEMORY_LAYOUT_H {
display "Memory layout header file"
flavor data
no_define
define -file system.h CYGHWR_MEMORY_LAYOUT_H
calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_m68k_mcf52xx_mcf5272_mcf5272c3_ram.h>" : \
"<pkgconf/mlt_m68k_mcf52xx_mcf5272_mcf5272c3_rom.h>" }
}
}
 
cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
display "Work with a ROM monitor"
flavor booldata
legal_values { "GDB_stubs" }
default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
requires { CYG_HAL_STARTUP == "RAM" }
parent CYGPKG_HAL_ROM_MONITOR
 
description "Support can be enabled for boot ROMs or ROM
monitors which contain GDB stubs. This support
changes various eCos semantics such as the encoding of
diagnostic output, and the overriding of hardware
interrupt vectors."
 
}
 
cdl_option CYGSEM_HAL_ROM_MONITOR {
display "Behave as a ROM monitor"
flavor bool
default_value 0
parent CYGPKG_HAL_ROM_MONITOR
requires { CYG_HAL_STARTUP == "ROM" }
 
description "Enable this option if this program is to be used as
a ROM monitor, i.e. applications will be loaded into
RAM on the board, and this ROM monitor may process
exceptions or interrupts generated from the
application. This enables features such as utilizing
a separate interrupt stack when exceptions are
generated."
 
}
}
/mcf52xx/mcf5272/mcf5272c3/plf/v2_0/include/plf_intr.h
0,0 → 1,109
#ifndef CYGONCE_HAL_PLF_INTR_H
#define CYGONCE_HAL_PLF_INTR_H
 
//==========================================================================
//
// plf_intr.h
//
// Platform specific interrupt and clock support
//
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
 
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>
 
//--------------------------------------------------------------------------
// Interrupt vectors.
 
/* The vector used by the Real time clock */
 
#define CYGNUM_HAL_INTERRUPT_RTC (CYGNUM_HAL_VECTOR_TMR4)
 
//---------------------------------------------------------------------------
// Clock control
 
/* The mcf5272 has 4 timers 0-3. Define the timer number that we want */
/* to use for the OS's clock. */
 
#define CYGNUM_HAL_RTC_TIMER_NUM (3)
 
/* Set the timer to generate 1 ms or 1000000 ns period interrupts. */
 
#define HAL_M68K_MCF52xx_MCF5272_CLOCK_NS 1000000
#if CYGNUM_HAL_RTC_PERIOD != HAL_M68K_MCF52xx_MCF5272_CLOCK_NS
#warning Unexpected clock period for this board!!!
#endif
 
/* Initialize the timer to generate an interrupt every 1 ms. Use the */
/* system clock divided by 16 as the source. Using 11*3 as the prescaler */
/* gives a 8 us counter. When this counter reaches 125 (1 ms) generate an */
/* interrupt. */
 
#define HAL_CLOCK_INITIALIZE(_period_) \
CYG_MACRO_START \
MCF5272_SIM->timer[CYGNUM_HAL_RTC_TIMER_NUM].tmr = 0x0000; \
MCF5272_SIM->timer[CYGNUM_HAL_RTC_TIMER_NUM].trr = 125-1; \
MCF5272_SIM->timer[CYGNUM_HAL_RTC_TIMER_NUM].tcn = 0; \
MCF5272_SIM->timer[CYGNUM_HAL_RTC_TIMER_NUM].ter = 0x0003; \
MCF5272_SIM->timer[CYGNUM_HAL_RTC_TIMER_NUM].tmr = \
(((3*11)-1) << MCF5272_TIMER_TMR_PS_BIT) | \
(0 << MCF5272_TIMER_TMR_CE_BIT) | \
(0 << MCF5272_TIMER_TMR_OM_BIT) | \
(1 << MCF5272_TIMER_TMR_ORI_BIT) | \
(1 << MCF5272_TIMER_TMR_FRR_BIT) | \
(2 << MCF5272_TIMER_TMR_CLK_BIT) | \
(1 << MCF5272_TIMER_TMR_RST_BIT); \
CYG_MACRO_END
 
/* We must clear the bit in the timer event register before we can get */
/* another interrupt. */
 
#define HAL_CLOCK_RESET( _vector_, _period_ ) \
CYG_MACRO_START \
MCF5272_SIM->timer[CYGNUM_HAL_RTC_TIMER_NUM].ter = 0x0002; \
CYG_MACRO_END
 
/* Read the current counter from the timer. */
 
#define HAL_CLOCK_READ( _pvalue_ ) \
CYG_MACRO_START \
*(_pvalue_) = MCF5272_SIM->timer[CYGNUM_HAL_RTC_TIMER_NUM].tcn; \
CYG_MACRO_END
 
//---------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_PLF_INTR_H
 
/mcf52xx/mcf5272/mcf5272c3/plf/v2_0/include/hal_memmap.h
0,0 → 1,66
#ifndef HAL_MEMMAP_H
#define HAL_MEMMAP_H
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
 
#include <cyg/infra/cyg_type.h>
 
// WARNING: DO NOT CHANGE THE TYPES OF THESE LABELS. THE LINKER DEFINES
// THESE AND WE WANT TO USE THE VARIABLES NOT THE VARIABLES THEMSELVES.
 
#define SECTION_DEC(_name_) \
externC unsigned char __ ## _name_ ## _start[]; \
externC unsigned char __ ## _name_ ## _end[]; \
externC unsigned char __ ## _name_ ## _size[];
 
SECTION_DEC(rom)
SECTION_DEC(ram)
SECTION_DEC(bss)
SECTION_DEC(sbss)
SECTION_DEC(ram_data)
SECTION_DEC(rom_data)
SECTION_DEC(heap1)
SECTION_DEC(uninvar)
SECTION_DEC(romvec)
SECTION_DEC(ramvec)
 
/*****************************************************************************
On-chip registers, System Integration Module (SIM)
*****************************************************************************/
 
#define MCF5272_MBAR (0x10000000)
 
#endif /* HAL_MEMMAP_H */
 
/mcf52xx/mcf5272/mcf5272c3/plf/v2_0/include/pkgconf/mlt_m68k_mcf52xx_mcf5272_mcf5272c3_ram.h
0,0 → 1,50
#ifndef _MLT_M68K_RAM_H
#define _MLT_M68K_RAM_H
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
 
// eCos memory layout
 
#ifndef __ASSEMBLER__
 
#include <cyg/hal/hal_memmap.h>
 
#endif
 
#define CYGMEM_SECTION_heap1 (__heap1_start)
#define CYGMEM_SECTION_heap1_SIZE ((size_t)(__heap1_size))
 
#endif // _MLT_M68K_RAM_H
 
/mcf52xx/mcf5272/mcf5272c3/plf/v2_0/include/pkgconf/mlt_m68k_mcf52xx_mcf5272_mcf5272c3_ram.ldi
0,0 → 1,80
//===========================================================================
//
// RAM startup linker control script
//
//===========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//===========================================================================
 
MEMORY
{
rom (rx) : ORIGIN = 0x00020000, LENGTH = 0x001E0000
ram (wx) : ORIGIN = 0x00200000, LENGTH = 0x00200000
}
 
SECTIONS
{
SECTIONS_BEGIN
 
GENERIC_SECTION (rom, rom, 0x00020000 (NOLOAD), LMA_EQ_VMA, 0x001E0000)
GENERIC_SECTION (ram, ram, 0x00200000 (NOLOAD), LMA_EQ_VMA, 0x00200000)
 
GENERIC_SECTION (romvec, rom, __rom_start, LMA_EQ_VMA, 0x400)
SECTION_text (rom, ALIGN (0x4), FOLLOWING (.romvec))
SECTION_fini (rom, ALIGN (0x4), FOLLOWING (.text))
SECTION_rodata1 (rom, ALIGN (0x4), FOLLOWING (.fini))
SECTION_rodata (rom, ALIGN (0x4), FOLLOWING (.rodata1))
SECTION_fixup (rom, ALIGN (0x4), FOLLOWING (.rodata))
 
// WARNING: If you change the order of these sections, be sure to change
// the location of the data section.
 
SECTION_gcc_except_table (rom, ALIGN (0x4), FOLLOWING (.fixup))
__rom_data_addr = ABSOLUTE(.);
 
GENERIC_SECTION (ramvec, ram, __ram_start (NOLOAD), LMA_EQ_VMA, 0x400)
SECTION_data (ram, ALIGN (0x4), FOLLOWING (.gcc_except_table), __rom_data_addr)
SECTION_sbss (ram, ALIGN (0x4) (NOLOAD), LMA_EQ_VMA)
SECTION_bss (ram, ALIGN (0x4) (NOLOAD), LMA_EQ_VMA)
SECTION_uninvar (ram, ALIGN (0x4) (NOLOAD), LMA_EQ_VMA)
 
// Allocate a heap section.
 
SECTION_heap1 (ram, ALIGN (0x4), LMA_EQ_VMA, 0x20000)
// The build tool looks for this "CYG_LABEL_DEFN..." string.
CYG_LABEL_DEFN(__heap1) = ABSOLUTE (__heap1_start);
 
SECTIONS_END
}
 
/mcf52xx/mcf5272/mcf5272c3/plf/v2_0/include/plf_startup.h
0,0 → 1,55
#ifndef _PLF_STARTUP_H
#define _PLF_STARTUP_H
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
 
#include <cyg/infra/cyg_type.h>
 
// The following label specifies whether the HAL should enable or disable
// the data transfer acknowledge output pin on the mcf5272 device.
 
#define HAL_MCF5272_ENABLE_DATA_TA (false)
 
// Platform-specific reset vector initialization routine
 
externC void plf_reset(void);
 
// Initialize the cache and access control registers for the current
// platform.
 
void plf_init_cache_acr(void);
 
#endif // _PLF_STARTUP_H
 
/mcf52xx/mcf5272/mcf5272c3/plf/v2_0/src/plf_startup.c
0,0 → 1,95
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
 
#include <cyg/infra/cyg_type.h>
#include <pkgconf/hal.h>
#include <cyg/hal/hal_startup.h>
#include <cyg/hal/hal_memmap.h>
#include <cyg/hal/hal_arch.h>
 
/*****************************************************************************
plf_init_cache_acr -- Initialize the cache and access control registers
 
The var_init_cache_acr routine already invalidated the cache and ACRs.
This routine only needs to enable the ACRs that it will use.
 
INPUT:
 
OUTPUT:
 
RETURN VALUE:
 
None
 
*****************************************************************************/
void plf_init_cache_acr(void)
{
 
// Enable the instruction cache with the following options:
// Enable CPUSHL invalidation.
// No freeze.
// Invalidate all cache lines (flush).
// No external arbiter control.
// Disable non-cacheable instruction bursting.
// Default memory is cacheable.
// Enable buffered writes.
// Read and write access permitted by default.
// Instruction fetch size is cache line.
 
mcf52xx_wr_cacr((CYG_WORD32)0x81000102);
 
// Leave the access control registers disabled by default.
 
}
 
/*****************************************************************************
plf_reset -- Platform-specific reset vector initialization routine
 
This routine must be called with interrupts disabled.
 
INPUT:
 
OUTPUT:
 
RETURN VALUE:
 
None
 
*****************************************************************************/
void plf_reset(void)
{
 
}
 
/mcf52xx/mcf5272/mcf5272c3/plf/v2_0/src/hal_diag.c
0,0 → 1,149
//=============================================================================
//
// hal_diag.c
//
// HAL diagnostic output code
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/hal/hal_diag.h> // our header.
 
#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
#include <cyg/hal/hal_stub.h> // hal_output_gdb_string
#endif
 
#include <cyg/infra/cyg_type.h> // base types, externC
#include <cyg/hal/hal_io.h> // IO macros
#include <cyg/hal/hal_intr.h> // Interrupt macros
 
#include <cyg/hal/hal_arch.h>
 
#define CYG_KERNEL_DIAG_SERIAL
 
//-----------------------------------------------------------------------------
// Serial diag functions.
#ifdef CYG_KERNEL_DIAG_SERIAL
 
// Include the serial driver.
 
void hal_diag_init(void)
{
CYG_WORD16 clk_div;
 
/* We must first enable the UART output pins from the general-purpose */
/* I/O module. */
 
/* Enable the UART0 pins in the port B control register. */
 
MCF5272_SIM->gpio.pbcnt = ((MCF5272_SIM->gpio.pbcnt &
~(MCF5272_GPIO_PBCNT_URT0_MSK)) |
(MCF5272_GPIO_PBCNT_URT0_EN));
 
/* Before we do anything else, make sure we have enabled CTS (our */
/* RTS) in case the device we are using relies on hardware flow */
/* control. Note that this step is our only attempt at hardware flow */
/* control. */
 
MCF5272_SIM->uart[0].uop1 = 1;
 
/* Initialize UART0 */
/* Reset Transmitter */
MCF5272_SIM->uart[0].ucr = MCF5272_UART_UCR_RTX;
 
/* Reset Receiver */
MCF5272_SIM->uart[0].ucr = MCF5272_UART_UCR_RRX;
 
/* Reset Mode Register */
MCF5272_SIM->uart[0].ucr = MCF5272_UART_UCR_RMR;
 
MCF5272_SIM->uart[0].ucr = MCF5272_UART_UCR_RES;
MCF5272_SIM->uart[0].ucr = MCF5272_UART_UCR_RBC;
 
/* Mode register 1 sets the UART to 8 data bits with no parity, and */
/* mode register 2 forces 1 stop bit. Reading or write to the mode */
/* register switches it from umr1 to umr2. To set it to umr1, we must */
/* write a reset mode register command to the command register. */
 
MCF5272_SIM->uart[0].umr = MCF5272_UART_UMR_8BNP;
MCF5272_SIM->uart[0].umr = MCF5272_UART_UMR_1S;
 
/* Select a prescaled (by 1/32) CLKIN for the clock source. */
 
MCF5272_SIM->uart[0].usr_ucsr = MCF5272_UART_UCSR_CLKIN;
 
/* Calculate baud settings */
clk_div = (CYG_WORD16)
((CYGHWR_HAL_SYSTEM_CLOCK_MHZ*1000000)/
(CYGHWR_HAL_M68K_MCF52xx_MCF5272_MCF5272C3_DIAG_BAUD * 32));
MCF5272_SIM->uart[0].udu = clk_div >> 8;
MCF5272_SIM->uart[0].udl = clk_div & 0x00ff;
 
/* Enable the transmitter and receiver. */
MCF5272_SIM->uart[0].ucr = MCF5272_UART_UCR_TXRXEN;
 
}
 
void hal_diag_write_char(cyg_int8 ch)
{
 
/* Loop until the transmit data holding register is empty. */
while (!(MCF5272_SIM->uart[0].usr_ucsr & MCF5272_UART_USR_TXRDY));
 
/* Write the character to the transmit status register. */
MCF5272_SIM->uart[0].urb_utb = ch;
 
/* Loop until the transmit data FIFO and the shift register are */
/* empty. */
 
while ((MCF5272_SIM->uart[0].utf & MCF5272_UART_UTF_TXB) ||
(!(MCF5272_SIM->uart[0].usr_ucsr & MCF5272_UART_USR_TXEMP)));
 
}
 
cyg_int8 hal_diag_read_char(void)
{
 
return 0;
}
 
#endif // ifdef CYG_KERNEL_DIAG_SERIAL
 
//-----------------------------------------------------------------------------
// End of hal_diag.c
 
/mcf52xx/var/v2_0/cdl/hal_m68k_mcf52xx.cdl
0,0 → 1,70
# ====================================================================
#
# hal_m68k_mcf52xx.cdl
#
# mcf52xx variant architectural HAL package configuration data
#
# ====================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
# ====================================================================
 
cdl_package CYGPKG_HAL_M68K_MCF52xx {
display "68k/Coldfire version 2 core HAL"
parent CYGPKG_HAL_M68K
requires CYGPKG_HAL_M68K
hardware
include_dir cyg/hal
define_header hal_m68k_mcf52xx.h
 
description "The 68k/Coldfire version 2 core HAL package provides
generic support for the version 2 Coldfire core. It is also
necessary to select a specific target platform HAL package."
 
define_proc {
puts $::cdl_header "#include <pkgconf/hal_m68k.h>"
}
 
compile var_startup.c var_misc.c var_arch.S
 
make {
<PREFIX>/lib/vectors.o : <PACKAGE>/src/vectors.S
$(CC) -Wp,-MD,vectors.tmp $(INCLUDE_PATH) $(CFLAGS) -c -o $@ $<
@echo $@ ": \\" > $(notdir $@).deps
@tail +2 vectors.tmp >> $(notdir $@).deps
@echo >> $(notdir $@).deps
@rm vectors.tmp
}
 
}
 
/mcf52xx/var/v2_0/include/var_startup.h
0,0 → 1,49
#ifndef _VAR_STARTUP_H
#define _VAR_STARTUP_H
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
 
#include <cyg/infra/cyg_type.h>
 
// Include the processor-specific startup header.
 
#include <cyg/hal/proc_startup.h>
 
// Variant-specific reset vector initialization routine
 
externC void var_reset(void);
 
#endif // _VAR_STARTUP_H
 
/mcf52xx/var/v2_0/include/var_cache.h
0,0 → 1,174
#ifndef CYGONCE_VAR_CACHE_H
#define CYGONCE_VAR_CACHE_H
//=============================================================================
//
// var_cache.h
//
// Variant HAL cache control API
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
 
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>
 
// We currently just enable the instruction cache on startup. There is
// no data cache.
 
//-----------------------------------------------------------------------------
// Cache dimensions - these vary between the 8xx sub-models
 
// Data cache
#define HAL_DCACHE_SIZE 0 // Size of data cache in bytes
#define HAL_DCACHE_LINE_SIZE 0 // Size of a data cache line
#define HAL_DCACHE_WAYS 1 // Associativity of the cache
 
// Instruction cache
#define HAL_ICACHE_SIZE 0 // Size of cache in bytes
#define HAL_ICACHE_LINE_SIZE 0 // Size of a cache line
#define HAL_ICACHE_WAYS 1 // Associativity of the cache
 
#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
 
//-----------------------------------------------------------------------------
// Global control of data cache
 
// Enable the data cache
#define HAL_DCACHE_ENABLE()
 
// Disable the data cache
#define HAL_DCACHE_DISABLE()
 
// Invalidate the entire cache
// Note: Any locked lines will not be invalidated.
#define HAL_DCACHE_INVALIDATE_ALL()
 
// Synchronize the contents of the cache with memory.
#define HAL_DCACHE_SYNC()
 
// Query the state of the data cache
#define HAL_DCACHE_IS_ENABLED(_state_)
 
// Set the data cache refill burst size
//#define HAL_DCACHE_BURST_SIZE(_size_)
 
// Set the data cache write mode
//#define HAL_DCACHE_WRITE_MODE( _mode_ )
 
//#define HAL_DCACHE_WRITETHRU_MODE 0
//#define HAL_DCACHE_WRITEBACK_MODE 1
 
 
// Load the contents of the given address range into the data cache
// and then lock the cache so that it stays there.
#define HAL_DCACHE_LOCK(_base_, _size_)
 
// Undo a previous lock operation
#define HAL_DCACHE_UNLOCK(_base_, _size_)
 
// Unlock entire cache
#define HAL_DCACHE_UNLOCK_ALL()
 
//-----------------------------------------------------------------------------
// Data cache line control
 
// Allocate cache lines for the given address range without reading its
// contents from memory.
//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
 
// Write dirty cache lines to memory and invalidate the cache entries
// for the given address range.
#define HAL_DCACHE_FLUSH( _base_ , _size_ )
 
// Invalidate cache lines in the given range without writing to memory.
#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
 
// Write dirty cache lines to memory for the given address range.
#define HAL_DCACHE_STORE( _base_ , _size_ )
 
// Preread the given range into the cache with the intention of reading
// from it later.
#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
 
// Preread the given range into the cache with the intention of writing
// to it later.
#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
 
// Allocate and zero the cache lines associated with the given range.
#define HAL_DCACHE_ZERO( _base_ , _size_ )
 
//-----------------------------------------------------------------------------
// Global control of Instruction cache
 
// Enable the instruction cache
#define HAL_ICACHE_ENABLE()
 
// Disable the instruction cache
#define HAL_ICACHE_DISABLE()
 
// Invalidate the entire cache
#define HAL_ICACHE_INVALIDATE_ALL()
 
// Synchronize the contents of the cache with memory.
#define HAL_ICACHE_SYNC()
 
// Query the state of the instruction cache
#define HAL_ICACHE_IS_ENABLED(_state_)
 
// Set the instruction cache refill burst size
//#define HAL_ICACHE_BURST_SIZE(_size_)
 
 
// Load the contents of the given address range into the instruction cache
// and then lock the cache so that it stays there.
#define HAL_ICACHE_LOCK(_base_, _size_)
 
// Undo a previous lock operation
#define HAL_ICACHE_UNLOCK(_base_, _size_)
 
// Unlock entire cache
#define HAL_ICACHE_UNLOCK_ALL()
 
//-----------------------------------------------------------------------------
// Instruction cache line control
 
// Invalidate cache lines in the given range without writing to memory.
//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
 
//-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_VAR_CACHE_H
// End of var_cache.h
 
/mcf52xx/var/v2_0/include/var_basetype.h
0,0 → 1,59
#ifndef CYGONCE_HAL_VAR_BASETYPE_H
#define CYGONCE_HAL_VAR_BASETYPE_H
 
//=============================================================================
//
// var_basetype.h
//
// Standard types for this architecture variant.
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
 
// Use defaults for this architecture.
 
// TEMPORARY TO REMOVE WARNINGS! The 68k architecture compiler complains
// when the object file alignment is greater than 2.
 
#ifndef CYGARC_ALIGNMENT
#define CYGARC_ALIGNMENT 2
#endif
#ifndef CYGARC_P2ALIGNMENT
#define CYGARC_P2ALIGNMENT 1
#endif
 
//-----------------------------------------------------------------------------
#endif // CYGONCE_HAL_VAR_BASETYPE_H
 
/mcf52xx/var/v2_0/include/var_intr.h
0,0 → 1,53
#ifndef CYGONCE_HAL_VAR_INTR_H
#define CYGONCE_HAL_VAR_INTR_H
//==========================================================================
//
// var_intr.h
//
// mcf52xx Variant interrupt and clock support
//
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
 
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>
 
// Include any processor specific interrupt definitions.
#include <cyg/hal/proc_intr.h>
 
//---------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_VAR_INTR_H
 
/mcf52xx/var/v2_0/include/var_arch.h
0,0 → 1,217
#ifndef CYGONCE_HAL_VAR_ARCH_H
#define CYGONCE_HAL_VAR_ARCH_H
//=============================================================================
//
// var_arch.h
//
// Architecture variant specific abstractions
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
 
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>
 
#include <cyg/hal/proc_arch.h>
 
// The ColdFire family of processors has a simplified exception stack
// frame that looks like the following:
//
// 3322222222221111 111111
// 1098765432109876 5432109876543210
// 8 +----------------+----------------+
// | Program Counter |
// 4 +----------------+----------------+
// |Fmt/FS/Vector/FS| SR |
// SP --> 0 +----------------+----------------+
//
// The stack self-aligns to a 4-byte boundary at an exception, with
// the Fmt/FS/Vector/FS field indicating the size of the adjustment
// (SP += 0,1,2,3 bytes).
 
// Define the Fmt/FS/Vector/FS word.
// The first four bits are the format word which tells the
// RTI instruction how to align the stack.
#define HAL_MCF52XX_RD_SF_FORMAT_MSK ((CYG_WORD16)0xF000)
// These bits are the vector number of the exception.
#define HAL_MCF52XX_RD_SF_VECTOR_MSK ((CYG_WORD16)0x03FC)
// These are bits 3-2, and 1-0 of the fault status used
// for bus and address errors.
#define HAL_MCF52XX_RD_SF_FS32_MSK ((CYG_WORD16)0x0C00)
#define HAL_MCF52XX_RD_SF_FS10_MSK ((CYG_WORD16)0x0003)
 
// Macros to access fields in the format vector word.
 
#define HAL_MCF52XX_RD_SF_FORMAT(_fmt_vec_word_) \
((((CYG_WORD16)(_fmt_vec_word_)) & HAL_MCF52XX_RD_SF_FORMAT_MSK) >> 12)
 
#define HAL_MCF52XX_RD_SF_VECTOR(_fmt_vec_word_) \
((((CYG_WORD16)(_fmt_vec_word_)) & HAL_MCF52XX_RD_SF_VECTOR_MSK) >> 2)
 
#define HAL_MCF52XX_RD_SF_FS(_fmt_vec_word_) \
(((((CYG_WORD16)(_fmt_vec_word_)) & HAL_MCF52XX_RD_SF_FS32_MSK) >> 8) \
| (((CYG_WORD16)(_fmt_vec_word_)) & HAL_MCF52XX_RD_SF_FS10_MSK))
 
/*****************************************************************************
Exception handler saved context. Some exceptions contain extra
information following this common exception handler context.
*****************************************************************************/
typedef struct
{
 
// Data regs D0-D7
 
#define HAL_EXC_NUM_D_REGS 8
CYG_WORD32 d[HAL_EXC_NUM_D_REGS];
 
// Address regs A0-A6
 
#define HAL_EXC_NUM_A_REGS 7
CYG_ADDRESS a[HAL_EXC_NUM_A_REGS];
 
// Stack Pointer
 
CYG_ADDRESS sp;
 
// 16-bit format/vector word
 
CYG_WORD16 fmt_vec_word;
 
// Status Reg
 
CYG_WORD16 sr;
 
// Program Counter
 
CYG_ADDRESS pc;
 
} __attribute__ ((aligned, packed)) HAL_SavedRegisters_exception;
 
#ifndef HAL_GENERIC_SAVED_CONTEXT
/*****************************************************************************
HAL_GENERIC_SAVED_CONTEXT -- Generic saved context structure
 
This structure could contain a normal saved context or an exception
context.
 
*****************************************************************************/
#define HAL_GENERIC_SAVED_CONTEXT \
typedef union \
{ \
HAL_SavedRegisters_normal normal; \
HAL_SavedRegisters_exception exception; \
} __attribute__ ((aligned, packed)) HAL_SavedRegisters;
#endif // HAL_GENERIC_SAVED_CONTEXT
 
//-----------------------------------------------------------------------------
// Thread register state manipulation for GDB support.
 
// Translate a stack pointer as saved by the thread context macros above into
// a pointer to a HAL_SavedRegisters structure.
#define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ ) \
(_regs_) = (HAL_SavedRegisters *)(_sp_)
 
// Copy a set of registers from a HAL_SavedRegisters structure into a
// GDB ordered array.
 
/* there are 180 bytes of registers on a 68020 w/68881 */
/* many of the fpa registers are 12 byte (96 bit) registers */
/*
#define NUMREGBYTES 180
enum regnames {D0,D1,D2,D3,D4,D5,D6,D7,
A0,A1,A2,A3,A4,A5,A6,A7,
PS,PC,
FP0,FP1,FP2,FP3,FP4,FP5,FP6,FP7,
FPCONTROL,FPSTATUS,FPIADDR
};
*/
 
#define HAL_GET_GDB_REGISTERS( _aregval_, _regs_ ) \
CYG_MACRO_START \
CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \
int _i_; \
\
for( _i_ = 0; _i_ < HAL_NUM_D_REGS; _i_++ ) \
*_regval_++ = (_regs_)->nml_ctxt.d[_i_]; \
\
for( _i_ = 0; _i_ < HAL_NUM_A_REGS; _i_++ ) \
*_regval_++ = (_regs_)->nml_ctxt.a[_i_]; \
\
*_regval_++ = (_regs_)->nml_ctxt.sp; \
*_regval_++ = (CYG_ADDRWORD) ((_regs_)->nml_ctxt.sr); \
*_regval_++ = (_regs_)->nml_ctxt.pc; \
/* Undefined registers */ \
for ( _i_ = 0; _i_ < 8; _i_++ ) \
{ \
*((CYG_WORD16*)_regval_)++ = _i_; \
*((CYG_WORD16*)_regval_)++ = _i_; \
*((CYG_WORD16*)_regval_)++ = _i_; \
} \
*_regval_++ = 0xBADC0DE0; \
*_regval_++ = 0xBADC0DE1; \
*_regval_++ = 0xBADC0DE2; \
CYG_MACRO_END
 
// Copy a GDB ordered array into a HAL_SavedRegisters structure.
#define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ ) \
CYG_MACRO_START \
CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \
int _i_; \
\
for( _i_ = 0; _i_ < HAL_NUM_D_REGS; _i_++ ) \
(_regs_)->nml_ctxt.d[_i_] = *_regval_++; \
\
for( _i_ = 0; _i_ < HAL_NUM_A_REGS; _i_++ ) \
(_regs_)->nml_ctxt.a[_i_] = *_regval_++; \
\
(_regs_)->nml_ctxt.sp = *_regval_++; \
(_regs_)->nml_ctxt.sr = (CYG_WORD16) (*_regval_++); \
(_regs_)->nml_ctxt.pc = *_regval_++; \
CYG_MACRO_END
 
/* ************************************************************************ */
/* These routines write to the special purpose registers in the ColdFire */
/* core. Since these registers are write-only in the supervisor model, no */
/* corresponding read routines exist. */
 
externC void mcf52xx_wr_vbr(CYG_WORD32);
externC void mcf52xx_wr_cacr(CYG_WORD32);
externC void mcf52xx_wr_acr0(CYG_WORD32);
externC void mcf52xx_wr_acr1(CYG_WORD32);
externC void mcf52xx_wr_rambar(CYG_WORD32);
 
//-----------------------------------------------------------------------------
#endif // CYGONCE_HAL_VAR_ARCH_H
 
/mcf52xx/var/v2_0/include/var_gen_types.h
0,0 → 1,53
#ifndef _VAR_GEN_TYPES_H
#define _VAR_GEN_TYPES_H
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
 
/*
 
*********************
* *
* General Types *
* *
*********************
 
Define some simple variable sizes for the mcf52xx architecture.
 
*/
 
// We use the defaults for the m68k architecture.
 
#endif // _VAR_GEN_TYPES_H
 
/mcf52xx/var/v2_0/src/var_misc.c
0,0 → 1,69
//==========================================================================
//
// var_misc.c
//
// HAL implementation miscellaneous functions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h>
 
#include <cyg/hal/hal_intr.h>
#include <cyg/hal/hal_arch.h>
 
//--------------------------------------------------------------------------
// VSR table
 
// For the mcf52xx, we can point the VBR directly to the VSR table.
// However, the table must be on a 1 MB boundary. Locate the VSR table where
// the linker tells us to.
 
volatile CYG_ADDRESS cyg_hal_vsr_table[CYGNUM_HAL_VSR_COUNT]
__attribute__ ((section (".ramvec")));
 
//--------------------------------------------------------------------------
void hal_variant_init(void)
{
 
// Don't need to do anything yet.
 
}
 
//--------------------------------------------------------------------------
// End of var_misc.c
 
/mcf52xx/var/v2_0/src/context.S
0,0 → 1,105
##=============================================================================
##
## context.S
##
## mcf52xx context switch code
##
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
##=============================================================================
 
#include <pkgconf/hal.h>
 
#------------------------------------------------------------------------------
# function declaration macro
 
#define FUNC_START(name) \
.text; \
.even; \
.globl name; \
name:
 
#------------------------------------------------------------------------------
# hal_thread_switch_context
# Switch thread contexts
# : 0(%sp) : return address
# : 4(%sp) : to - address of sp of next thread to execute
# : 8(%sp) : from - address of sp save location of current thread
#
# d0, d1, a0, a1 are ours to abuse.
#
# externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from );
 
FUNC_START(hal_thread_switch_context)
 
move.l 4(%sp),%a0 /* Read the to and from from */
move.l 8(%sp),%a1 /* parameters from the stack. */
 
lea -(6+5)*4(%sp),%sp /* Save all of the registers */
movem.l %d2-%d7/%a2-%a6,(%sp) /* that the C calling */
/* convention expects us to */
/* preserve. */
 
move.l %sp,(%a1) /* Store this threads current */
/* stack pointer to *from. */
 
move.l (%a0),%sp /* Load the stack pointer for */
/* the next thread from *to. */
 
movem.l (%sp),%d2-%d7/%a2-%a6 /* Load all of the preserved */
lea (6+5)*4(%sp),%sp /* registers from the stack. */
 
rts /* Restore the PC. */
 
#------------------------------------------------------------------------------
# hal_thread_load_context
# Load thread context
# : 4(%sp) : to - address of sp of next thread to execute
#
# d0, d1, a0, a1 are ours to abuse.
 
FUNC_START(hal_thread_load_context)
 
move.l 4(%sp),%a0 /* Read the to parameter from */
move.l (%a0),%sp /* the stack and switch to that */
/* stack pointer. */
 
movem.l (%sp),%d2-%d7/%a2-%a6 /* Load all of the preserved */
lea (6+5)*4(%sp),%sp /* registers from the stack. */
 
rts /* Restore the PC. */
 
##=============================================================================
##=============================================================================
 
/mcf52xx/var/v2_0/src/vectors.S
0,0 → 1,489
/*****************************************************************************
vectors.S -- mcf52xx exception vectors
*****************************************************************************/
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
##=============================================================================
 
#include <pkgconf/system.h>
#include <pkgconf/hal.h>
 
#ifdef CYGPKG_KERNEL
#include <pkgconf/kernel.h>
#endif /* CYGPKG_KERNEL */
 
/****************************************************************************/
 
.file "vectors.S"
 
/****************************************************************************/
 
/****************************************************************************/
 
/* The mcf52xx core allows us to move the VBR to our RAM vector table */
/* at cyg_hal_vsr_table provided the table is at a 1MB boundary. */
 
/****************************************************************************/
/* ROM vector table */
 
/* Create the ROM vector table. We use this table to initialize */
/* cyg_hal_vsr_table which we point the VBR to. */
 
.macro hw_vsr name
.long hw_vsr_\name
.endm
 
.section ".romvec","ax"
 
.globl rom_vsr_table
rom_vsr_table:
 
/* 0 - Initial SSP */
hw_vsr stack
 
/* 1 - Initial PC */
hw_vsr reset
 
/* 2-24 - Default exception handlers */
.rept 24-2+1
hw_vsr default
.endr
 
/* 25-31 - Autovector interrupts 1-7 */
.rept 31-25+1
hw_vsr autovec
.endr
 
/* 32-63 - Default exception handlers */
.rept 63-32+1
hw_vsr default
.endr
 
/* 64-255 - User interrupt vectors */
.rept 255-64+1
hw_vsr interrupt
.endr
 
.equ rom_vsr_table_size, . - rom_vsr_table
 
/****************************************************************************/
/* The default excetpion vector handler */
 
/* The default handler for all machine exceptions. We save the */
/* machine state and call the default C VSR handler. This routine passes a */
/* pointer to the saved state to the C VSR handler. The stack pointer in */
/* the saved state points to the byte following the PC on the exception */
/* stack (the sp before the exception). The format/vector word in the */
/* exception stack contains the vector number. */
 
/*
void hal_default_exception_handler(CYG_WORD vector, HAL_SavedRegisters *regs);
*/
 
.text
.balign 4
hw_vsr_default:
 
lea.l -(16*4)(%sp),%sp /* Preserve the entire state. */
movem.l %d0-%d7/%a0-%a6,(%sp) /* Allocate space for all */
lea.l ((16+1+1)*4)(%sp),%a0 /* registers (including the */
move.l %a0,(15*4)(%sp) /* stack pointer). Write all */
/* registers to the stack */
/* space. Write the original */
/* stack pointer value to the */
/* stack. The format/vector */
/* word, sr, and pc are already */
/* on the stack. */
 
move.w (16*4)(%sp),%d0 /* Calculate the vector */
and.l #0x000003fc,%d0 /* number. The format/vector */
lsr.l #2,%d0 /* word on the stack contains */
/* the vector number. */
 
pea.l (%sp) /* Pass a pointer to the */
/* saved state to the exception */
/* handler. */
 
move.l %d0,-(%sp) /* Push the vector number */
/* parameter. */
 
.extern hal_default_exception_handler /* Call the default */
jbsr hal_default_exception_handler /* exception VSR. This */
/* routine may (and */
/* probably will) modify */
/* the exception context. */
 
addq.l #2*4,%sp /* Remove the vector number */
/* and the state pointer from */
/* the stack. */
 
/* Restore the state. There */
/* is a chance that a debugger */
/* changed the state (including */
/* the stack pointer, PC, */
/* etc.). We must be very */
/* careful to restore the new */
/* state without first */
/* overwriting the values on */
/* the stack. We must copy the */
/* format/vector word, SR, and */
/* PC to the new stack, but we */
/* must make sure that the new */
/* stack is not in the middle */
/* of our current stack */
/* variables that we are using. */
 
movem.l (%sp),%d0-%d7/%a0-%a4 /* Restore all of the */
/* registers that we do not */
/* need in the following code. */
/* We will copy all registers */
/* that are not restored here */
/* to the new stack before */
/* restoring them. */
 
move.l (15*4)(%sp),%a6 /* Load the address of the */
/* new SP. */
 
lea.l (18*4)(%sp),%a5 /* Get a pointer to the */
/* location following the */
/* exception context. */
 
cmp.l %a5,%a6 /* Compare the new stack */
jcc 1f /*jcc=jhs*/ /* address to the end of the */
/* exception context. This */
/* will tell us the order that */
/* we need to copy the */
/* exception stack and the */
/* remaining registers from the */
/* exception context to the new */
/* stack. The order is */
/* important because the stack */
/* frames might (and in many */
/* cases do) overlap. */
 
/* The new SP is at a lower */
/* address than the end of the */
/* exception context. Copy */
/* from the lowest address to */
/* the highest address. */
 
lea.l -5*4(%a6),%a6 /* Copy A5, A6, FVW, SR, and */
move.l -5*4(%a5),(%a6) /* PC from the old stack to the */
move.l -4*4(%a5),1*4(%a6) /* new stack. Note that we do */
move.l -2*4(%a5),3*4(%a6) /* not copy the SP location but */
move.l -1*4(%a5),4*4(%a6) /* we leave a space for it on */
/* the new stack. If we do not */
/* leave space for the SP, */
/* there is a possibility of */
/* overwriting some of our */
/* data. Note that we copy in */
/* increasing order. */
 
move.l %a6,%sp /* A6 points to the top of */
move.l (%sp)+,%a5 /* the new stack with our */
move.l (%sp)+,%a6 /* registers on it. Restore */
addq.l #1*4,%sp /* the remaining registers and */
rte /* use the exception stack to */
/* return. Note that we also */
/* remove the unused space left */
/* for the SP. */
 
1:
 
move.l -(%a5),-(%a6) /* The new SP is at a higher */
move.l -(%a5),-(%a6) /* or the same address as the */
subq.l #4,%a5 /* end of the exception */
move.l -(%a5),-(%a6) /* context. Copy from the */
move.l -(%a5),-(%a6) /* highest address to the */
/* lowest address. Note that */
/* we do not copy the stack */
/* pointer. When copying in */
/* this direction, there is no */
/* reason to leave space for */
/* the stack pointer. */
 
move.l %a6,%sp /* A6 points to the top of */
move.l (%sp)+,%a5 /* the new stack with our */
move.l (%sp)+,%a6 /* registers on it. Restore */
rte /* the remaining registers and */
/* use the exception stack to */
/* return. */
 
/****************************************************************************/
/* User interrupt vector handler */
 
/* Control is transferred here from a user interrupt vector (#64-255). */
 
/* Before branching to common code, load a value to translate the */
/* vector table offset to the ISR table offset. The ISR vector table */
/* contains the autovectors (0-6) followed by the interrupt vectors */
/* (7-198). */
 
.equ int_pres_regs_sz,((2+3)*4)
.macro int_pres_regs
lea.l -int_pres_regs_sz(%sp),%sp
movem.l %d0-%d2/%a0-%a1,(%sp)
.endm
.macro int_rest_regs
movem.l (%sp),%d0-%d2/%a0-%a1
lea.l int_pres_regs_sz(%sp),%sp
.endm
 
.text
.balign 4
hw_vsr_interrupt:
 
int_pres_regs /* Preserve all registers */
/* that this ISR routine needs */
/* to preserve. The C code */
/* will preserve all other */
/* registers. */
 
move.l #(-64+7)*4,%d0 /* Adding this value to the */
/* vector table offset will */
/* result in the corresponding */
/* offset into the ISR table. */
 
/* Fall through to common code. */
 
hw_vsr_int_common: /* Common code. */
 
/* d0.l: Contains a value to translate the vector table offset to */
/* the ISR table offset. */
 
move.w int_pres_regs_sz(%sp),%d1 /* Calculate the vector */
and.l #0x000003fc,%d1 /* offset. The format/vector */
/* word on the stack contains */
/* the vector number. Mask off */
/* all unused bits. The bit */
/* position of the vector */
/* number field makes it */
/* automatically multiplied by */
/* four. */
 
add.l %d1,%d0 /* Calculate the ISR table */
/* offset. Add the vector */
/* table offset to the */
/* translation value. */
 
asr.l #2,%d1 /* Calculate the vector */
/* number using the vector */
/* table offset. */
 
/* d0.l: Contains the offset into the ISR table. */
 
/* d1.l: Contains the vector number. */
 
#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
 
.extern cyg_scheduler_sched_lock /* Lock the scheduler if */
addq.l #1,cyg_scheduler_sched_lock /* we are using the kernel. */
 
#endif /* CYGFUN_HAL_COMMON_KERNEL_SUPPORT */
 
/* We need to call the following routines. The isr address, data, and */
/* intr are all from the ISR table. interrupt_end is a C routine and is */
/* only called if we are using the kernel. regs points to the saved */
/* registers on the stack. isr_ret is the return address from isr. vector */
/* is the vector number. */
 
/*
static cyg_uint32 isr(CYG_ADDRWORD vector,
CYG_ADDRWORD data)
 
externC void interrupt_end(cyg_uint32 isr_ret,
Cyg_Interrupt *intr,
HAL_SavedRegisters *regs)
*/
 
pea (%sp) /* Push the regs pointer. */
 
.extern cyg_hal_interrupt_objects /* Push the intr object */
lea cyg_hal_interrupt_objects,%a0 /* pointer from the table. */
move.l (%a0,%d0.l),-(%sp)
 
.extern cyg_hal_interrupt_data /* Push the data value */
lea cyg_hal_interrupt_data,%a0 /* from the table. */
move.l (%a0,%d0.l),-(%sp)
 
.extern cyg_hal_interrupt_handlers /* Get the address of the */
lea cyg_hal_interrupt_handlers,%a0 /* ISR from the table. */
move.l (%a0,%d0.l),%a0
 
move.l %d1,-(%sp) /* Push the vector number */
/* parameter. */
 
jbsr (%a0) /* Call the ISR. */
 
addq.l #4*1,%sp /* Remove the vector */
/* parameter from the stack. */
 
move.l %d0,(%sp) /* d0.l contains the return */
/* value from the ISR. */
/* Overwrite the data parameter */
/* with the ISR return value to */
/* pass as a parameter */
/* (isr_ret) to interrupt_end. */
/* The intr object and regs */
/* parameters are still on the */
/* stack. */
 
#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
 
/* We only need to call interrupt_end() when there is a kernel */
/* present to do any tidying up. */
 
/* The interrupt_end routine will call the DSRs and do */
/* rescheduling when it decrements the scheduler lock from 1 to */
/* zero. In this case, we do not want to have interrupts masked */
/* while the DSRs run. Restore the interrupt mask to the value */
/* prior to this interrupt. Do not completely unmask all */
/* interrupts because this interrupt may be a nested interrupt. We */
/* do not want to lower the interrupt mask on the lower priority */
/* interrupt. */
 
move.w (4*3)+int_pres_regs_sz+2(%sp),%d2
move.w %d2,%sr
 
/* If the interrupt mask was not previously zero, we want to make */
/* sure that the DSRs to not run and no preemption occurs. Add the */
/* value of the previous interrupt mask to the scheduler lock. If */
/* the previous mask was zero, the scheduler lock will remain at */
/* one and the interrupt end function will decrement it to zero. */
/* Otherwise, we want to prevent the interrupt end function from */
/* unlocking the scheduler. We do this because there is a chance */
/* that someone had interrupts masked with the scheduler lock at */
/* zero. If a higher priority interrupt occurs, we could be */
/* running DSRs and doing preemption with the interrupts masked! */
 
and.l #0x0700,%d2
lsr.l #8,%d2
add.l %d2,cyg_scheduler_sched_lock
 
.extern interrupt_end /* Call the interrupt_end C */
jbsr interrupt_end /* routine. This routine might */
/* preempt the currently */
/* running thread. */
 
/* Now that interrupt end is complete, subtract the previous */
/* interrupt level back out of the scheduler lock. */
 
sub.l %d2,cyg_scheduler_sched_lock
 
#endif
 
lea (4*3)(%sp),%sp /* Remove the isr_ret, intr, */
/* and regs parameters from the */
/* stack. */
 
int_rest_regs /* Restore the preserved */
/* registers for the current */
/* thread. */
 
rte /* Restore the SR and PC. */
 
/****************************************************************************/
/* Autovector interrupt vector handler. */
 
/* Control is transferred here from an interrupt autovector (#25-31). */
 
/* Before branching to common code, load a value to translate the */
/* vector table offset to the ISR table offset. The ISR vector table */
/* contains the autovectors (0-6) followed by the interrupt vectors */
/* (7-198). */
 
.text
.balign 4
hw_vsr_autovec:
 
int_pres_regs /* Preserve all registers */
/* that this ISR routine needs */
/* to preserve. The C code */
/* will preserve all other */
/* registers. */
 
move.l #(-25+0)*4,%d0 /* Adding this value to the */
/* vector table offset will */
/* result in the corresponding */
/* offset into the ISR table. */
 
jra hw_vsr_int_common /* Branch into common code. */
 
/****************************************************************************/
/* hw_vsr_reset -- Hardware Reset Vector */
 
/* We assume that most of the chip selects are configured by the boot */
/* loader. */
 
.text
.balign 4
.globl hw_vsr_reset
hw_vsr_reset:
 
.globl __exception_reset /* Define the entry point for */
__exception_reset: /* the linker. */
 
move.w #0x2700,%sr /* Make sure that all */
/* interrupts are masked. */
 
lea hw_vsr_stack,%sp /* Load the reset and */
/* interrupt stack pointer. */
 
lea 0,%fp /* Set up the initial frame */
link %fp,#0 /* pointer. */
 
.extern hal_reset /* Call the C routine to */
jbsr hal_reset /* complete the reset process. */
 
9: stop #0x2000 /* If we return, stop. */
jra 9b
 
/****************************************************************************/
/* Interrupt and reset stack */
 
/* WARNING: Do not put this in any memory section that gets */
/* initialized. Doing so may cause the C code to initialize its own stack. */
 
.section ".uninvar","aw",@nobits
 
.balign 16
.global hw_vsr_stack_bottom
hw_vsr_stack_bottom:
.skip 0x2000
.balign 16
.global hw_vsr_stack
hw_vsr_stack:
.skip 0x10
 
/****************************************************************************/
 
/mcf52xx/var/v2_0/src/var_arch.S
0,0 → 1,87
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
##=============================================================================
/*****************************************************************************
var_arch.S -- mcf52xx variant code
*****************************************************************************/
 
#include <pkgconf/hal.h>
 
/*****************************************************************************
FUNC_START -- Function declaration macro
*****************************************************************************/
#define FUNC_START(name) \
.text; \
.even; \
.globl name; \
name:
 
/* ************************************************************************ */
/* These routines write to the special purpose registers in the ColdFire */
/* core. Since these registers are write-only in the supervisor model, no */
/* corresponding read routines exist. */
 
FUNC_START(mcf52xx_wr_vbr)
move.l 4(%sp),%d0
andi.l #0xFFF00000,%d0 /* align to 1M boundary */
movec %d0,%vbr
nop
rts
 
FUNC_START(mcf52xx_wr_cacr)
move.l 4(%sp),%d0
movec %d0,%cacr
nop
rts
 
FUNC_START(mcf52xx_wr_acr0)
move.l 4(%sp),%d0
movec %d0,%acr0
nop
rts
 
FUNC_START(mcf52xx_wr_acr1)
move.l 4(%sp),%d0
movec %d0,%acr1
nop
rts
 
FUNC_START(mcf52xx_wr_rambar)
move.l 4(%sp),%d0
.equ rambar,0xc04 /* Rc for movec */
movec %d0,#rambar
nop
rts
 
 
/mcf52xx/var/v2_0/src/var_startup.c
0,0 → 1,100
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
 
#include <cyg/infra/cyg_type.h>
#include <pkgconf/hal.h>
#include <cyg/hal/hal_startup.h>
#include <cyg/hal/hal_memmap.h>
#include <cyg/hal/hal_arch.h>
 
/*****************************************************************************
var_init_cache_acr -- Initialize the cache and access control registers
 
INPUT:
 
OUTPUT:
 
RETURN VALUE:
 
None
 
*****************************************************************************/
static void var_init_cache_acr(void)
{
 
// Invalidate and disable the cache and ACRs.
 
mcf52xx_wr_cacr((CYG_WORD32)0x01000000);
mcf52xx_wr_acr0((CYG_WORD32)0);
mcf52xx_wr_acr1((CYG_WORD32)0);
 
// Call a routine to set up the cache and ACRs for this specific
// platform.
 
plf_init_cache_acr();
 
}
 
/*****************************************************************************
var_reset -- Variant-specific reset vector initialization routine
 
This routine must be called with interrupts disabled.
 
INPUT:
 
OUTPUT:
 
RETURN VALUE:
 
None
 
*****************************************************************************/
void var_reset(void)
{
 
// Initialize the processor's vector base register.
 
mcf52xx_wr_vbr((CYG_WORD32)__ramvec_start);
 
// Initialize the cache and access control registers.
 
var_init_cache_acr();
 
// Do any processor-specific reset initialization.
 
proc_reset();
}
 
 
/arch/v2_0/cdl/hal_m68k.cdl
0,0 → 1,77
# ====================================================================
#
# hal_m68k.cdl
#
# m68k architectural HAL package configuration data
#
# ====================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
# ====================================================================
 
cdl_package CYGPKG_HAL_M68K {
display "m68k architecture"
parent CYGPKG_HAL
hardware
include_dir cyg/hal
define_header hal_m68k.h
description "
The m68k architecture HAL package provides generic
support for this processor architecture. It is also
necessary to select a specific target platform HAL
package."
 
cdl_interface CYGINT_HAL_M68K_VARIANT {
display "Number of variant implementations in this configuration"
requires 1 == CYGINT_HAL_M68K_VARIANT
}
 
compile hal_startup.c hal_misc.c m68k_stub.c hal_arch.S
 
make {
<PREFIX>/lib/target.ld: <PACKAGE>/src/m68k.ld
$(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(CFLAGS) -o $@ $<
@echo $@ ": \\" > $(notdir $@).deps
@tail +2 target.tmp >> $(notdir $@).deps
@echo >> $(notdir $@).deps
@rm target.tmp
}
 
cdl_option CYGBLD_LINKER_SCRIPT {
display "Linker script"
flavor data
no_define
calculated { "src/m68k.ld" }
}
 
}
/arch/v2_0/include/hal_io.h
0,0 → 1,146
#ifndef CYGONCE_HAL_HAL_IO_H
#define CYGONCE_HAL_HAL_IO_H
 
//=============================================================================
//
// hal_io.h
//
// HAL device IO register support.
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
 
#include <cyg/infra/cyg_type.h>
 
//-----------------------------------------------------------------------------
// IO Register address.
// This type is for recording the address of an IO register.
 
typedef volatile CYG_ADDRWORD HAL_IO_REGISTER;
 
//-----------------------------------------------------------------------------
// BYTE Register access.
// Individual and vectorized access to 8 bit registers.
 
#define HAL_READ_UINT8( _register_, _value_ ) \
CYG_MACRO_START \
((_value_) = *((volatile CYG_BYTE *)(_register_))); \
CYG_MACRO_END
 
#define HAL_WRITE_UINT8( _register_, _value_ ) \
CYG_MACRO_START \
(*((volatile CYG_BYTE *)(_register_)) = (_value_)); \
CYG_MACRO_END
 
#define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \
CYG_MACRO_START \
cyg_count32 _i_,_j_; \
for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \
(_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_j_]; \
} \
CYG_MACRO_END
 
#define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \
CYG_MACRO_START \
cyg_count32 _i_,_j_; \
for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \
((volatile CYG_BYTE *)(_register_))[_j_] = (_buf_)[_i_]; \
} \
CYG_MACRO_END
 
 
//-----------------------------------------------------------------------------
// 16 bit access.
// Individual and vectorized access to 16 bit registers.
 
#define HAL_READ_UINT16( _register_, _value_ ) \
CYG_MACRO_START \
((_value_) = *((volatile CYG_WORD16 *)(_register_))); \
CYG_MACRO_END
 
#define HAL_WRITE_UINT16( _register_, _value_ ) \
CYG_MACRO_START \
(*((volatile CYG_WORD16 *)(_register_)) = (_value_)); \
CYG_MACRO_END
 
#define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \
CYG_MACRO_START \
cyg_count32 _i_,_j_; \
for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \
(_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_j_]; \
} \
CYG_MACRO_END
 
#define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \
CYG_MACRO_START \
cyg_count32 _i_,_j_; \
for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \
((volatile CYG_WORD16 *)(_register_))[_j_] = (_buf_)[_i_]; \
} \
CYG_MACRO_END
 
//-----------------------------------------------------------------------------
// 32 bit access.
// Individual and vectorized access to 32 bit registers.
 
#define HAL_READ_UINT32( _register_, _value_ ) \
CYG_MACRO_START \
((_value_) = *((volatile CYG_WORD32 *)(_register_))); \
CYG_MACRO_END
 
#define HAL_WRITE_UINT32( _register_, _value_ ) \
CYG_MACRO_START \
(*((volatile CYG_WORD32 *)(_register_)) = (_value_)); \
CYG_MACRO_END
 
#define HAL_READ_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \
CYG_MACRO_START \
cyg_count32 _i_,_j_; \
for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \
(_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_j_]; \
} \
CYG_MACRO_END
 
#define HAL_WRITE_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \
CYG_MACRO_START \
cyg_count32 _i_,_j_; \
for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \
((volatile CYG_WORD32 *)(_register_))[_j_] = (_buf_)[_i_]; \
} \
CYG_MACRO_END
 
//-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_HAL_IO_H
// End of hal_io.h
/arch/v2_0/include/basetype.h
0,0 → 1,91
#ifndef CYGONCE_HAL_BASETYPE_H
#define CYGONCE_HAL_BASETYPE_H
 
//=============================================================================
//
// basetype.h
//
// Standard types for this architecture.
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
 
// Include variant specific types.
#include <cyg/hal/var_basetype.h>
 
// Include the standard variable sizes.
#include <cyg/hal/gen_types.h>
 
//-----------------------------------------------------------------------------
// Characterize the architecture
 
#define CYG_BYTEORDER CYG_MSBFIRST // Big endian
 
//-----------------------------------------------------------------------------
// 68k does not usually use labels with underscores. Some labels generated
// by the linker do, so add an underscore where required.
 
#define CYG_LABEL_NAME(_name_) _##_name_
 
// The 68k architecture uses the default definitions of the base types,
// so we do not need to define any here.
 
//-----------------------------------------------------------------------------
// Override the alignment definitions from cyg_type.h.
// Most 68k variants use a 4 byte alignment.
// A few variants (68000) may override this setting to use a 2 byte alignment.
#ifndef CYGARC_ALIGNMENT
#define CYGARC_ALIGNMENT 4
#endif
// the corresponding power of two alignment
#ifndef CYGARC_P2ALIGNMENT
#define CYGARC_P2ALIGNMENT 2
#endif
 
 
//-----------------------------------------------------------------------------
// Define a compiler-specific rune for saying a function doesn't return
 
// WARNING: There is a bug in some versions of gcc for the m68k that does
// not handle the noreturn attribute correctly. It is safe to just disable
// this attribute.
 
#ifndef CYGBLD_ATTRIB_NORET
# define CYGBLD_ATTRIB_NORET
#endif
 
//-----------------------------------------------------------------------------
#endif // CYGONCE_HAL_BASETYPE_H
 
/arch/v2_0/include/gen_types.h
0,0 → 1,136
#ifndef _GEN_TYPES_H
#define _GEN_TYPES_H
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
 
/*****************************************************************************
 
*********************
* *
* General Types *
* *
*********************
 
Define some simple variable sizes for this platform.
 
Note that these types are useful for making user threads that are
not eCos-specific.
 
*****************************************************************************/
 
// Include some architecture variant specific types.
 
#include <cyg/hal/var_gen_types.h>
 
// Define types to use for specific sized variables. Note that the above
// include file could have defined some of these types differently. If the
// type is already defined, always use the previous definition.
 
#ifndef _GEN_TYPES_I8_T
#define _GEN_TYPES_I8_T char
#endif
#ifndef _GEN_TYPES_I16_T
#define _GEN_TYPES_I16_T short
#endif
#ifndef _GEN_TYPES_I32_T
#define _GEN_TYPES_I32_T int
#endif
#ifndef _GEN_TYPES_I64_T
#define _GEN_TYPES_I64_T long long
#endif
#ifndef _GEN_TYPES_S8_T
#define _GEN_TYPES_S8_T signed _GEN_TYPES_I8_T
#endif
#ifndef _GEN_TYPES_S16_T
#define _GEN_TYPES_S16_T signed _GEN_TYPES_I16_T
#endif
#ifndef _GEN_TYPES_S32_T
#define _GEN_TYPES_S32_T signed _GEN_TYPES_I32_T
#endif
#ifndef _GEN_TYPES_S64_T
#define _GEN_TYPES_S64_T signed _GEN_TYPES_I64_T
#endif
#ifndef _GEN_TYPES_U8_T
#define _GEN_TYPES_U8_T unsigned _GEN_TYPES_I8_T
#endif
#ifndef _GEN_TYPES_U16_T
#define _GEN_TYPES_U16_T unsigned _GEN_TYPES_I16_T
#endif
#ifndef _GEN_TYPES_U32_T
#define _GEN_TYPES_U32_T unsigned _GEN_TYPES_I32_T
#endif
#ifndef _GEN_TYPES_U64_T
#define _GEN_TYPES_U64_T unsigned _GEN_TYPES_I64_T
#endif
#ifndef _GEN_TYPES_ADDR_T
#define _GEN_TYPES_ADDR_T void *
#endif
 
typedef _GEN_TYPES_I8_T i8_t;
typedef _GEN_TYPES_I16_T i16_t;
typedef _GEN_TYPES_I32_T i32_t;
typedef _GEN_TYPES_I64_T i64_t;
typedef _GEN_TYPES_S8_T s8_t;
typedef _GEN_TYPES_S16_T s16_t;
typedef _GEN_TYPES_S32_T s32_t;
typedef _GEN_TYPES_S64_T s64_t;
typedef _GEN_TYPES_U8_T u8_t;
typedef _GEN_TYPES_U16_T u16_t;
typedef _GEN_TYPES_U32_T u32_t;
typedef _GEN_TYPES_U64_T u64_t;
typedef _GEN_TYPES_ADDR_T addr_t;
 
// Use int_t and uint_t for fast counter variables. The size of these
// types depends on the architecture but it will always be at least 16 bits.
// For example, 16-bit numbers are faster on the 68000 but 32-bit numbers are
// faster on the mcf5200. If you need to assume the size of the variable use
// u16_t or u32_t instead.
 
#ifndef _GEN_TYPES_INT_T
#define _GEN_TYPES_INT_T i32_t
#endif
#ifndef _GEN_TYPES_SINT_T
#define _GEN_TYPES_SINT_T s32_t
#endif
#ifndef _GEN_TYPES_UINT_T
#define _GEN_TYPES_UINT_T u32_t
#endif
 
typedef _GEN_TYPES_INT_T int_t;
typedef _GEN_TYPES_SINT_T sint_t;
typedef _GEN_TYPES_UINT_T uint_t;
 
#endif // _GEN_TYPES_H
 
/arch/v2_0/include/hal_intr.h
0,0 → 1,259
#ifndef CYGONCE_HAL_HAL_INTR_H
#define CYGONCE_HAL_HAL_INTR_H
 
//==========================================================================
//
// hal_intr.h
//
// m68k Interrupt and clock support
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
 
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>
#include <cyg/hal/hal_arch.h>
 
#include <cyg/hal/var_intr.h>
 
//--------------------------------------------------------------------------
// m68k exception vectors. These correspond to VSRs and are the values
// to use for HAL_VSR_GET/SET
#define CYGNUM_HAL_VECTOR_SSP 0
#define CYGNUM_HAL_VECTOR_RESET 1
#define CYGNUM_HAL_VECTOR_BUSERR 2
#define CYGNUM_HAL_VECTOR_ADDERR 3
#define CYGNUM_HAL_VECTOR_ILLINST 4
#define CYGNUM_HAL_VECTOR_ZERODIV 5
#define CYGNUM_HAL_VECTOR_CHKINST 6
#define CYGNUM_HAL_VECTOR_TRAPVINST 7
#define CYGNUM_HAL_VECTOR_PRIVVIOLATION 8
#define CYGNUM_HAL_VECTOR_TRACE 9
#define CYGNUM_HAL_VECTOR_L1010 10
#define CYGNUM_HAL_VECTOR_L1111 11
#define CYGNUM_HAL_VECTOR_UNINITINT 15
#define CYGNUM_HAL_VECTOR_SPURINT 24
#define CYGNUM_HAL_VECTOR_AUTOVEC1 25
#define CYGNUM_HAL_VECTOR_AUTOVEC2 26
#define CYGNUM_HAL_VECTOR_AUTOVEC3 27
#define CYGNUM_HAL_VECTOR_AUTOVEC4 28
#define CYGNUM_HAL_VECTOR_AUTOVEC5 29
#define CYGNUM_HAL_VECTOR_AUTOVEC6 30
#define CYGNUM_HAL_VECTOR_AUTOVEC7 31
#define CYGNUM_HAL_VECTOR_NMI CYGNUM_HAL_VECTOR_AUTOVEC7
#define CYGNUM_HAL_VECTOR_TRAPFIRST 32
#define CYGNUM_HAL_VECTOR_NUMTRAPS 16
#define CYGNUM_HAL_VECTOR_TRAPLAST (CYGNUM_HAL_VECTOR_TRAPFIRST+CYGNUM_HAL_VECTOR_NUMTRAPS-1)
#define CYGNUM_HAL_VECTOR_INTRFIRST 64
#define CYGNUM_HAL_VECTOR_NUMINTRS 192
#define CYGNUM_HAL_VECTOR_INTRLAST (CYGNUM_HAL_VECTOR_INTRFIRST+CYGNUM_HAL_VECTOR_NUMINTRS-1)
 
#define CYGNUM_HAL_VSR_MIN CYGNUM_HAL_VECTOR_SSP
#define CYGNUM_HAL_VSR_MAX CYGNUM_HAL_VECTOR_INTRLAST
#define CYGNUM_HAL_VSR_COUNT (CYGNUM_HAL_VSR_MAX+1)
 
//--------------------------------------------------------------------------
// Interrupt vectors.
 
#ifndef CYGNUM_HAL_ISR_MAX
#define CYGNUM_HAL_ISR_MIN 0
#define CYGNUM_HAL_ISR_MAX 255
#define CYGNUM_HAL_ISR_COUNT (7+CYGNUM_HAL_VECTOR_NUMINTRS)
#endif /* CYGNUM_HAL_ISR_MAX */
 
#ifndef CYGNUM_HAL_EXCEPTION_COUNT
#define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_VECTOR_BUSERR
#define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_VECTOR_SPURINT
#define CYGNUM_HAL_EXCEPTION_COUNT ((CYGNUM_HAL_EXCEPTION_MAX-CYGNUM_HAL_EXCEPTION_MIN)+1)
#endif /* CYGNUM_HAL_EXCEPTION_COUNT */
 
//--------------------------------------------------------------------------
// Static data used by HAL
 
// ISR tables
externC volatile CYG_ADDRESS cyg_hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
externC volatile CYG_ADDRWORD cyg_hal_interrupt_data[CYGNUM_HAL_ISR_COUNT];
externC volatile CYG_ADDRESS cyg_hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT];
 
// VSR table
externC volatile CYG_ADDRESS cyg_hal_vsr_table[CYGNUM_HAL_VSR_COUNT];
 
//---------------------------------------------------------------------------
// Translate a vector number into an ISR table index.
 
#define HAL_TRANSLATE_VECTOR(_vector_,_index_) \
CYG_MACRO_START \
switch ((_vector_)) \
{ \
case CYGNUM_HAL_VECTOR_AUTOVEC1 ... CYGNUM_HAL_VECTOR_AUTOVEC7: \
(_index_) = ((_vector_) - CYGNUM_HAL_VECTOR_AUTOVEC1); \
break; \
case CYGNUM_HAL_VECTOR_INTRFIRST ... CYGNUM_HAL_VECTOR_INTRLAST: \
(_index_) = ((_vector_) \
- CYGNUM_HAL_VECTOR_INTRFIRST \
+ (CYGNUM_HAL_VECTOR_AUTOVEC7 \
- CYGNUM_HAL_VECTOR_AUTOVEC1 \
+ 1)); \
break; \
default: \
CYG_FAIL("Unknown Interrupt!!!"); \
(_index_) = (typeof(_index_))-1; \
} \
CYG_MACRO_END
 
//--------------------------------------------------------------------------
// Interrupt state storage
 
typedef cyg_uint16 CYG_INTERRUPT_STATE;
 
//---------------------------------------------------------------------------
// Interrupt and VSR attachment macros
 
externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);
externC void hal_default_exception_handler(CYG_WORD vector,
HAL_SavedRegisters *regs);
 
#define HAL_INTERRUPT_IN_USE( _vector_, _state_) \
CYG_MACRO_START \
cyg_uint32 _index_; \
HAL_TRANSLATE_VECTOR ((_vector_), _index_); \
\
if (cyg_hal_interrupt_handlers[_index_] \
==(CYG_ADDRESS)&hal_default_isr) \
(_state_) = 0; \
else \
(_state_) = 1; \
CYG_MACRO_END
 
#define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \
CYG_MACRO_START \
cyg_uint32 _index_; \
HAL_TRANSLATE_VECTOR((_vector_), _index_); \
\
if (cyg_hal_interrupt_handlers[_index_] \
==(CYG_ADDRESS)&hal_default_isr) \
{ \
cyg_hal_interrupt_handlers[_index_] = (CYG_ADDRESS)(_isr_); \
cyg_hal_interrupt_data[_index_] = (CYG_ADDRWORD)(_data_); \
cyg_hal_interrupt_objects[_index_] = (CYG_ADDRESS)(_object_); \
} \
CYG_MACRO_END
 
#define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \
CYG_MACRO_START \
cyg_uint32 _index_; \
HAL_INTERRUPT_MASK(_vector_); \
HAL_TRANSLATE_VECTOR((_vector_), _index_); \
if (cyg_hal_interrupt_handlers[_index_] \
== (CYG_ADDRESS)(_isr_)) \
{ \
cyg_hal_interrupt_handlers[_index_] = \
(CYG_ADDRESS)&hal_default_isr; \
cyg_hal_interrupt_data[_index_] = 0; \
cyg_hal_interrupt_objects[_index_] = 0; \
} \
CYG_MACRO_END
 
#define HAL_VSR_GET( _vector_, _pvsr_ ) \
*((CYG_ADDRESS *)(_pvsr_)) = cyg_hal_vsr_table[(_vector_)];
 
 
#define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) \
CYG_MACRO_START \
if( (_poldvsr_) != NULL ) \
*(CYG_ADDRESS *)(_poldvsr_) = cyg_hal_vsr_table[(_vector_)]; \
cyg_hal_vsr_table[(_vector_)] = (CYG_ADDRESS)(_vsr_); \
CYG_MACRO_END
 
//--------------------------------------------------------------------------
// Interrupt control macros
 
// The following interrupt control macros are the default for the 68k
// architecture. Some architectures will override these definitions by
// defining them in their var_intr.h file. Some architectures support
// instructions like andi.w #xxxx,%sr but others (Coldfire) do not.
// Architectures that support these other instructions will want to define
// their own macros.
 
#define HAL_M68K_SET_SR(__newsr__) \
CYG_MACRO_START \
asm volatile ("move.w %0,%%sr\n" \
: \
: "g" ((CYG_INTERRUPT_STATE)(__newsr__))); \
CYG_MACRO_END
 
#ifndef HAL_ENABLE_INTERRUPTS
#define HAL_ENABLE_INTERRUPTS() \
CYG_MACRO_START \
CYG_INTERRUPT_STATE _msk_; \
HAL_QUERY_INTERRUPTS(_msk_); \
HAL_M68K_SET_SR((_msk_ & (CYG_INTERRUPT_STATE)0xf8ff)); \
CYG_MACRO_END
#endif // HAL_ENABLE_INTERRUPTS
 
#ifndef HAL_DISABLE_INTERRUPTS
#define HAL_DISABLE_INTERRUPTS(_old_) \
CYG_MACRO_START \
HAL_QUERY_INTERRUPTS(_old_); \
HAL_M68K_SET_SR((_old_ | (CYG_INTERRUPT_STATE)0x0700)); \
CYG_MACRO_END
#endif //HAL_DISABLE_INTERRUPTS
 
#define HAL_RESTORE_INTERRUPTS(_prev_) \
CYG_MACRO_START \
CYG_INTERRUPT_STATE _msk_; \
HAL_QUERY_INTERRUPTS(_msk_); \
_msk_ &= (CYG_INTERRUPT_STATE)0xf8ff; \
_msk_ |= (((CYG_INTERRUPT_STATE)(_prev_)) \
& (CYG_INTERRUPT_STATE)0x0700); \
asm volatile ("move.w %0,%%sr\n" \
: \
: "g" (_msk_)); \
CYG_MACRO_END
 
// Use the extra assignment to avoid warnings.
// The compiler should optimize it out.
#define HAL_QUERY_INTERRUPTS(__oldmask__) \
CYG_MACRO_START \
CYG_INTERRUPT_STATE _omsk_ = (CYG_INTERRUPT_STATE)(__oldmask__); \
asm volatile ("move.w %%sr,%0\n" \
: "=g" (_omsk_) \
: ); \
(__oldmask__) = (typeof(__oldmask__))_omsk_; \
CYG_MACRO_END
 
//---------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_HAL_INTR_H
 
/arch/v2_0/include/hal_arch.h
0,0 → 1,390
#ifndef CYGONCE_HAL_ARCH_H
#define CYGONCE_HAL_ARCH_H
 
//=============================================================================
//
// hal_arch.h
//
// Architecture specific abstractions
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
 
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>
 
// Include some variant specific architectural defines.
#include <cyg/hal/var_arch.h>
 
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
#include <cyg/hal/m68k_stub.h>
#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 
#ifndef HAL_NORMAL_SAVED_CONTEXT
/*****************************************************************************
HAL_NORMAL_SAVED_CONTEXT -- Saved by a normal context switch
 
Define a generic structure to save a thread context. Some
architecture variants will want to redefine this.
 
*****************************************************************************/
typedef struct
{
 
// Data regs D0-D7
 
#define HAL_NORMAL_SAVED_NUM_D_REGS 8
CYG_WORD32 d[HAL_NORMAL_SAVED_NUM_D_REGS];
 
// Address regs A0-A6
 
#define HAL_NORMAL_SAVED_NUM_A_REGS 7
CYG_ADDRESS a[HAL_NORMAL_SAVED_NUM_A_REGS];
 
// Program Counter
 
CYG_ADDRESS pc;
 
} __attribute__ ((aligned, packed)) HAL_SavedRegisters_normal;
#endif // HAL_NORMAL_SAVED_CONTEXT
 
#ifndef HAL_GENERIC_SAVED_CONTEXT
/*****************************************************************************
HAL_GENERIC_SAVED_CONTEXT -- Generic saved context structure
 
This is a generic structure that should describe various saved
processor contexts on this platform.
 
If the variant HAL does not define this, just define a saved register
structure with a normal context.
 
*****************************************************************************/
#define HAL_GENERIC_SAVED_CONTEXT \
typedef union \
{ \
HAL_SavedRegisters_normal normal; \
} __attribute__ ((aligned, packed)) HAL_SavedRegisters;
#endif // HAL_GENERIC_SAVED_CONTEXT
HAL_GENERIC_SAVED_CONTEXT;
 
#ifndef HAL_THREAD_SWITCH_CONTEXT
/*****************************************************************************
HAL_THREAD_SWITCH_CONTEXT
 
This macro saves the state of the currently running thread and writes
its stack pointer to *(_fspptr_).
 
It then switches to the thread context that *(_tspptr_) points to.
 
INPUT:
 
_fspptr_: A pointer to the location to save the current thread's stack
pointer to.
 
_tspptr_: A pointer to the location containing the stack pointer of
the thread context to switch to.
 
OUTPUT:
 
*(_fspptr_): Contains the stack pointer of the previous thread's
context.
 
*****************************************************************************/
#define HAL_THREAD_SWITCH_CONTEXT(_fspptr_,_tspptr_) \
CYG_MACRO_START \
asm volatile (" pea 1f(%%pc)\n" \
" lea -(8+7)*4(%%sp),%%sp\n" \
" movem.l %%d0-%%d7/%%a0-%%a6,(%%sp)\n" \
" move.l %%sp,%0\n" \
" move.l %1,%%sp\n" \
" movem.l (%%sp),%%d0-%%d7/%%a0-%%a6\n" \
" lea (8+7)*4(%%sp),%%sp\n" \
" rts\n" \
"1:\n" \
: "=g" (*(_fspptr_)) \
: "g" (*(_tspptr_)) \
: "memory"); \
CYG_MACRO_END
#if HAL_NORMAL_SAVED_NUM_D_REGS != 8
#error
#endif
#if HAL_NORMAL_SAVED_NUM_A_REGS != 7
#error
#endif
#endif // HAL_THREAD_SWITCH_CONTEXT
 
#ifndef HAL_THREAD_LOAD_CONTEXT
/*****************************************************************************
HAL_THREAD_LOAD_CONTEXT
 
This macro loads the thread context that *(_tspptr_) points to.
 
This macro does not return.
 
INPUT:
 
_tspptr_: A pointer to the location containing the stack pointer of
the thread context to switch to.
 
*****************************************************************************/
#define HAL_THREAD_LOAD_CONTEXT(_tspptr_) \
CYG_MACRO_START \
asm volatile (" move.l %0,%%sp\n" \
" movem.l (%%sp),%%d0-%%d7/%%a0-%%a6\n" \
" lea (8+7)*4(%%sp),%%sp\n" \
" rts\n" \
: \
: "g" (*(_tspptr_)) \
: "memory"); \
CYG_MACRO_END
#if HAL_NORMAL_SAVED_NUM_D_REGS != 8
#error
#endif
#if HAL_NORMAL_SAVED_NUM_A_REGS != 7
#error
#endif
#endif // HAL_THREAD_LOAD_CONTEXT
 
#ifndef HAL_THREAD_INIT_CONTEXT
/*****************************************************************************
HAL_THREAD_INIT_CONTEXT -- Context Initialization
 
Initialize the context of a thread.
 
INPUT:
 
_sparg_: The name of the variable containing the current sp. This
will be written with the new sp.
 
_thread_: The thread object address, passed as argument to entry
point.
 
_entry_: The thread's entry point address.
 
_id_: A bit pattern used in initializing registers, for debugging.
 
OUTPUT:
 
_sparg_: Updated with the value of the new sp.
 
*****************************************************************************/
#define HAL_THREAD_INIT_CONTEXT(_sparg_, _thread_, _entry_, _id_) \
CYG_MACRO_START \
CYG_WORD32 * _sp_ = ((CYG_WORD32*)((CYG_WORD32)(_sparg_) & ~15)); \
HAL_SavedRegisters_normal * _regs_; \
int _i_; \
\
*(--_sp_) = (CYG_WORD32)(_thread_); /* Thread's parameter. */ \
*(--_sp_) = (CYG_WORD32)0xDEADC0DE; /* Thread's return addr. */ \
\
_regs_ = (HAL_SavedRegisters_normal*) \
((CYG_WORD32)_sp_ - sizeof(HAL_SavedRegisters_normal)); \
\
for (_i_=0; _i_ < HAL_NORMAL_SAVED_NUM_A_REGS; _i_++) \
_regs_->a[_i_] = _regs_->d[_i_] = (_id_); \
_regs_->d[_i_] = (_id_); /* D7 */ \
/* A6, initial frame pointer should be null */ \
_regs_->a[HAL_NORMAL_SAVED_NUM_A_REGS-1] = (CYG_ADDRESS)0; \
/* Thread's starting PC */ \
_regs_->pc = (CYG_ADDRESS)(_entry_); \
\
(_sparg_) = (CYG_ADDRESS)_regs_; \
CYG_MACRO_END
#endif // HAL_THREAD_INIT_CONTEXT
 
//-----------------------------------------------------------------------------
// Bit manipulation routines
 
externC cyg_uint32 hal_lsbit_index(cyg_uint32 mask);
externC cyg_uint32 hal_msbit_index(cyg_uint32 mask);
 
#define HAL_LSBIT_INDEX(index, mask) (index) = hal_lsbit_index(mask);
 
#define HAL_MSBIT_INDEX(index, mask) (index) = hal_msbit_index(mask);
 
//-----------------------------------------------------------------------------
// Idle thread code.
// This macro is called in the idle thread loop, and gives the HAL the
// chance to insert code. Typical idle thread behaviour might be to halt the
// processor.
 
externC void hal_idle_thread_action(cyg_uint32 loop_count);
 
#define HAL_IDLE_THREAD_ACTION(_count_) hal_idle_thread_action(_count_)
 
//-----------------------------------------------------------------------------
// Execution reorder barrier.
// When optimizing the compiler can reorder code. In multithreaded systems
// where the order of actions is vital, this can sometimes cause problems.
// This macro may be inserted into places where reordering should not happen.
 
#define HAL_REORDER_BARRIER() asm volatile ( "" : : : "memory" )
 
//-----------------------------------------------------------------------------
// Breakpoint support
// HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to happen
// if executed.
// HAL_BREAKINST is the value of the breakpoint instruction and
// HAL_BREAKINST_SIZE is its size in bytes.
 
#define HAL_BREAKPOINT(_label_) \
asm volatile (" .globl " #_label_ ";" \
#_label_":" \
" trap #1" \
);
 
#define HAL_BREAKINST 0x4E41
 
#define HAL_BREAKINST_SIZE 2
 
#if defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \
defined(CYGPKG_HAL_EXCEPTIONS)
 
//-----------------------------------------------------------------------------
// Exception handling function.
// This function is defined by the kernel according to this prototype. It is
// invoked from the HAL to deal with any CPU exceptions that the HAL does
// not want to deal with itself. It usually invokes the kernel's exception
// delivery mechanism.
 
externC void cyg_hal_deliver_exception( CYG_WORD code, CYG_ADDRWORD data );
 
#endif /* defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) */
 
//-----------------------------------------------------------------------------
// Minimal and sensible stack sizes: the intention is that applications
// will use these to provide a stack size in the first instance prior to
// proper analysis. Idle thread stack should be this big.
 
// THESE ARE NOT INTENDED TO BE MICROMETRICALLY ACCURATE FIGURES.
// THEY ARE HOWEVER ENOUGH TO START PROGRAMMING.
// YOU MUST MAKE YOUR STACKS LARGER IF YOU HAVE LARGE "AUTO" VARIABLES!
 
// This is not a config option because it should not be adjusted except
// under "enough rope" sort of disclaimers.
 
// Stack frame overhead per call. 6 data registers, 5 address registers,
// frame pointer, and return address. We can't guess the local variables so
// just assume that using all of the registers averages out.
 
#define CYGNUM_HAL_STACK_FRAME_SIZE ((6 + 5 + 1 + 1) * 4)
 
// Stack needed for a context switch.
// All registers + pc + sr + vector
 
#ifndef CYGNUM_HAL_STACK_CONTEXT_SIZE
#define CYGNUM_HAL_STACK_CONTEXT_SIZE ((8+8+1+1+1)*4)
#endif // CYGNUM_HAL_STACK_CONTEXT_SIZE
 
// Interrupt + call to ISR, interrupt_end() and the DSR
 
#define CYGNUM_HAL_STACK_INTERRUPT_SIZE \
((CYGNUM_HAL_STACK_CONTEXT_SIZE) + (8*CYGNUM_HAL_STACK_FRAME_SIZE))
 
// We define a minimum stack size as the minimum any thread could ever
// legitimately get away with. We can throw asserts if users ask for less
// than this. Allow enough for four interrupt sources - clock, serial,
// nic, and one other
 
// No separate interrupt stack exists. Make sure all threads contain
// a stack sufficiently large
 
#define CYGNUM_HAL_STACK_SIZE_MINIMUM \
((4*CYGNUM_HAL_STACK_INTERRUPT_SIZE) \
+ (16*CYGNUM_HAL_STACK_FRAME_SIZE))
 
// Now make a reasonable choice for a typical thread size. Pluck figures
// from thin air and say 30 call frames with an average of 16 words of
// automatic variables per call frame
 
#define CYGNUM_HAL_STACK_SIZE_TYPICAL \
(CYGNUM_HAL_STACK_SIZE_MINIMUM + \
(30 * (CYGNUM_HAL_STACK_FRAME_SIZE+(16*4))))
 
//--------------------------------------------------------------------------
// Macros for switching context between two eCos instances (jump from
// code in ROM to code in RAM or vice versa).
#define CYGARC_HAL_SAVE_GP()
#define CYGARC_HAL_RESTORE_GP()
 
#ifndef HAL_SETJMP
#define HAL_SETJMP
/*****************************************************************************
hal_setjmp/hal_longjmp
 
We do the best we can to define generic setjmp and longjmp routines
for the m68k architecture. Some architectures will need to override this.
 
*****************************************************************************/
 
// We must save all of the registers that are preserved across routine
// calls. The assembly code assumes that this structure is defined in the
// following format. Any changes to this structure will result in changes to
// the assembly code!!
 
typedef struct {
cyg_uint32 d2;
cyg_uint32 d3;
cyg_uint32 d4;
cyg_uint32 d5;
cyg_uint32 d6;
cyg_uint32 d7;
cyg_uint32 a2;
cyg_uint32 a3;
cyg_uint32 a4;
cyg_uint32 a5;
cyg_uint32 a6;
cyg_uint32 sp;
cyg_uint32 pc;
} hal_jmp_buf_t;
 
// This type is used by normal routines to pass the address of the
// structure into our routines without having to explicitly take the address
// of the structure.
 
typedef cyg_uint32 hal_jmp_buf[sizeof(hal_jmp_buf_t) / sizeof(cyg_uint32)];
 
// Define the generic setjmp and longjmp routines.
 
externC int hal_m68k_setjmp(hal_jmp_buf env);
externC void hal_m68k_longjmp(hal_jmp_buf env, int val);
#define hal_setjmp(_env) hal_m68k_setjmp(_env)
#define hal_longjmp(_env, _val) hal_m68k_longjmp(_env, _val)
#endif // HAL_SETJMP
 
//-----------------------------------------------------------------------------
#endif // CYGONCE_HAL_ARCH_H
// End of hal_arch.h
 
/arch/v2_0/include/m68k_stub.h
0,0 → 1,129
#ifndef CYGONCE_HAL_M68K_STUB_H
#define CYGONCE_HAL_M68K_STUB_H
//========================================================================
//
// m68k_stub.h
//
// M68K-specific definitions for generic stub
//
//========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//========================================================================
 
#include <pkgconf/system.h>
#include <pkgconf/hal.h>
 
 
 
#ifdef CYGPKG_IO_SERIAL
#include <pkgconf/io_serial.h>
#endif
 
#include <cyg/hal/hal_diag.h>
 
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 
#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM, externC
 
#define HAL_STUB_PLATFORM_INIT_SERIAL() HAL_DIAG_INIT()
 
#define HAL_STUB_PLATFORM_GET_CHAR() \
((cyg_int8)({ \
cyg_int8 _ch_; \
HAL_DIAG_READ_CHAR(_ch_); \
_ch_; \
}))
 
#define HAL_STUB_PLATFORM_PUT_CHAR(c) HAL_DIAG_WRITE_CHAR((c))
 
#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int,(baud))
 
#define HAL_STUB_PLATFORM_RESET() HAL_DIAG_INIT()
 
#define HAL_STUB_PLATFORM_INIT() HAL_DIAG_INIT()
 
#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 
 
 
#define NUMREGS 18
 
#define REGSIZE( _x_ ) (4)
 
typedef unsigned long target_register_t;
 
enum regnames {
D0, D1, D2, D3, D4, D5, D6, D7,
A0, A1, A2, A3, A4, A5, FP, SP,
PS, PC,
};
 
typedef enum regnames regnames_t;
 
/* Given a trap value TRAP, return the corresponding signal. */
externC int __computeSignal (unsigned int trap_number);
 
/* Return the SPARC trap number corresponding to the last-taken trap. */
externC int __get_trap_number (void);
 
/* Return the currently-saved value corresponding to register REG. */
externC target_register_t get_register (regnames_t reg);
 
/* Store VALUE in the register corresponding to WHICH. */
externC void put_register (regnames_t which, target_register_t value);
 
/* Set the currently-saved pc register value to PC. This also updates NPC
as needed. */
externC void set_pc (target_register_t pc);
 
/* Set things up so that the next user resume will execute one instruction.
This may be done by setting breakpoints or setting a single step flag
in the saved user registers, for example. */
externC void __single_step (void);
 
/* Clear the single-step state. */
externC void __clear_single_step (void);
 
/* If the breakpoint we hit is in the breakpoint() instruction, return a
non-zero value. */
externC int __is_breakpoint_function (void);
 
/* Skip the current instruction. */
externC void __skipinst (void);
 
externC void __install_breakpoints (void);
 
externC void __clear_breakpoints (void);
 
#endif // ifndef CYGONCE_HAL_M68K_STUB_H
/arch/v2_0/include/hal_startup.h
0,0 → 1,15
#ifndef _HAL_STARTUP_H
#define _HAL_STARTUP_H
 
#include <cyg/infra/cyg_type.h>
 
// Include the variant-specific startup header.
 
#include <cyg/hal/var_startup.h>
 
// Declare the routine to call to simulate a hardware reset.
 
externC void hal_hw_reset(void);
 
#endif // _HAL_STARTUP_H
 
/arch/v2_0/include/hal_cache.h
0,0 → 1,52
#ifndef CYGONCE_HAL_CACHE_H
#define CYGONCE_HAL_CACHE_H
 
//=============================================================================
//
// hal_cache.h
//
// HAL cache control API
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
 
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>
 
#include <cyg/hal/var_cache.h>
 
//-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_CACHE_H
// End of hal_cache.h
/arch/v2_0/include/hal_diag.h
0,0 → 1,89
#ifndef CYGONCE_HAL_HAL_DIAG_H
#define CYGONCE_HAL_HAL_DIAG_H
 
//=============================================================================
//
// hal_diag.h
//
// HAL Support for Kernel Diagnostic Routines
//
//=============================================================================
//####UNSUPPORTEDBEGIN####
//
// -------------------------------------------
// This source file has been contributed to eCos/Red Hat. It may have been
// changed slightly to provide an interface consistent with those of other
// files.
//
// The functionality and contents of this file is supplied "AS IS"
// without any form of support and will not necessarily be kept up
// to date by Red Hat.
//
// All inquiries about this file, or the functionality provided by it,
// should be directed to the 'ecos-discuss' mailing list (see
// http://sourceware.cygnus.com/ecos/intouch.html for details).
//
// Maintained by: <Unmaintained>
// -------------------------------------------
//
//####UNSUPPORTEDEND####
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h>
 
//-----------------------------------------------------------------------------
// functions implemented in hal_diag.c
 
externC void hal_diag_init(void);
 
externC void hal_diag_write_char(cyg_int8 c);
 
externC cyg_int8 hal_diag_read_char(void);
 
//-----------------------------------------------------------------------------
 
#define HAL_DIAG_INIT() hal_diag_init()
 
#define HAL_DIAG_WRITE_CHAR(_c_) hal_diag_write_char(_c_)
 
#define HAL_DIAG_READ_CHAR(_c_) ((_c_) = hal_diag_read_char())
 
//-----------------------------------------------------------------------------
// end of hal_diag.h
#endif // CYGONCE_HAL_HAL_DIAG_H
 
/arch/v2_0/src/hal_misc.c
0,0 → 1,195
//==========================================================================
//
// hal_misc.c
//
// HAL miscellaneous functions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h>
#include <cyg/infra/cyg_trac.h> // tracing macros
#include <cyg/infra/cyg_ass.h> // assertion macros
#include <cyg/infra/diag.h> // diag_printf
 
#include <cyg/hal/hal_arch.h> // HAL header
 
#include <cyg/hal/hal_intr.h> // VSR/ISR defines
 
//--------------------------------------------------------------------------
// ISR tables
volatile CYG_ADDRESS cyg_hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
volatile CYG_ADDRWORD cyg_hal_interrupt_data[CYGNUM_HAL_ISR_COUNT];
volatile CYG_ADDRESS cyg_hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT];
 
//--------------------------------------------------------------------------
// VSR table
 
// The cyg_hal_vsr_table table is variant-specific. Some processors must
// have the VSR table at specific locations.
 
/*****************************************************************************
hal_default_exception_handler -- First level C exception handler
 
The assembly default VSR handler calls this routine to handler the
exception. When this routine returns, the state is restored to the state
pointed to by regs.
 
We declare this routine as weak so that other handlers can easily
become the default exception handler.
 
INPUT:
 
vector: The exception vector number.
 
regs: A pointer to the saved state.
 
OUTPUT:
 
RETURN VALUE:
 
None
 
*****************************************************************************/
 
externC void
hal_default_exception_handler(CYG_WORD vector, HAL_SavedRegisters *regs)
__attribute__ ((weak));
 
void hal_default_exception_handler(CYG_WORD vector, HAL_SavedRegisters *regs)
{
 
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
externC void __handle_exception(void);
externC HAL_SavedRegisters * _hal_registers;
 
// Set the pointer to the registers of the current exception
// context. At entry the GDB stub will expand the
// HAL_SavedRegisters structure into a (bigger) register array.
_hal_registers = regs;
 
__handle_exception();
 
#elif defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \
defined(CYGPKG_HAL_EXCEPTIONS)
 
// We should decode the vector and pass a more appropriate
// value as the second argument. For now we simply pass a
// pointer to the saved registers. We should also divert
// breakpoint and other debug vectors into the debug stubs.
 
cyg_hal_deliver_exception(vector, (CYG_ADDRWORD)regs);
 
#else
 
CYG_FAIL("Exception!!!");
 
#endif
 
return;
}
 
//---------------------------------------------------------------------------
// Default ISRs
 
externC cyg_uint32
hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data)
{
diag_printf("Spurious Interrupt: %d\n", vector);
 
// CYG_FAIL("Spurious Interrupt!!!");
return 0;
}
 
//---------------------------------------------------------------------------
// Idle thread action
 
void
hal_idle_thread_action( cyg_uint32 count )
{
}
 
//---------------------------------------------------------------------------
// Determine the index of the ls bit of the supplied mask.
 
cyg_uint32
hal_lsbit_index(cyg_uint32 mask)
{
cyg_uint32 n = mask;
 
static const signed char tab[64] =
{ -1, 0, 1, 12, 2, 6, 0, 13, 3, 0, 7, 0, 0, 0, 0, 14, 10,
4, 0, 0, 8, 0, 0, 25, 0, 0, 0, 0, 0, 21, 27 , 15, 31, 11,
5, 0, 0, 0, 0, 0, 9, 0, 0, 24, 0, 0 , 20, 26, 30, 0, 0, 0,
0, 23, 0, 19, 29, 0, 22, 18, 28, 17, 16, 0
};
 
n &= ~(n-1UL);
n = (n<<16)-n;
n = (n<<6)+n;
n = (n<<4)+n;
 
return tab[n>>26];
}
 
//---------------------------------------------------------------------------
// Determine the index of the ms bit of the supplied mask.
 
cyg_uint32
hal_msbit_index(cyg_uint32 mask)
{
cyg_uint32 x = mask;
cyg_uint32 w;
 
// Phase 1: make word with all ones from that one to the right.
x |= x >> 16;
x |= x >> 8;
x |= x >> 4;
x |= x >> 2;
x |= x >> 1;
 
// Phase 2: calculate number of "1" bits in the word.
w = (x & 0x55555555) + ((x >> 1) & 0x55555555);
w = (w & 0x33333333) + ((w >> 2) & 0x33333333);
w = w + (w >> 4);
w = (w & 0x000F000F) + ((w >> 8) & 0x000F000F);
return (cyg_uint32)((w + (w >> 16)) & 0xFF);
 
}
 
//---------------------------------------------------------------------------
 
/arch/v2_0/src/hal_arch.S
0,0 → 1,156
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
##=============================================================================
/*****************************************************************************
hal_arch.S -- m68k architecture code
*****************************************************************************/
 
#include <pkgconf/hal.h>
 
/*****************************************************************************
FUNC_START -- Function declaration macro
*****************************************************************************/
#define FUNC_START(name) \
.text; \
.even; \
.globl name; \
name:
 
/*****************************************************************************
The following routines assume the hal_jmp_buf structure is defined as
shown below.
 
typedef struct {
cyg_uint32 d2;
cyg_uint32 d3;
cyg_uint32 d4;
cyg_uint32 d5;
cyg_uint32 d6;
cyg_uint32 d7;
cyg_uint32 a2;
cyg_uint32 a3;
cyg_uint32 a4;
cyg_uint32 a5;
cyg_uint32 a6;
cyg_uint32 sp;
cyg_uint32 pc;
} hal_jmp_buf_t;
typedef cyg_uint32 hal_jmp_buf[sizeof(hal_jmp_buf_t) / sizeof(cyg_uint32)];
*****************************************************************************/
 
/*****************************************************************************
hal_m68k_setjmp -- Generic setjmp for the m68k architecture
 
externC int hal_m68k_setjmp(hal_jmp_buf env);
 
INPUT:
 
0(%sp): return address
 
4(%sp): env - address of a hal_jmp_buf structure
 
OUTPUT:
 
d0, d1, a0, a1 are ours to abuse.
 
RETURN VALUE:
 
This routine always returns zero in d0.l.
 
*****************************************************************************/
FUNC_START(hal_m68k_setjmp)
 
lea.l 4(%sp),%a1 /* Get a pointer to the position */
/* of the stack pointer before this */
/* call was made. IMPORTANT: The */
/* longjmp routine and the */
/* exception handler assume that */
/* saved stack pointers point to */
/* the location of the stack before */
/* the routine/exception occurred. */
 
move.l (%a1),%a0 /* Get a pointer to the buffer to */
/* save our state into. */
 
movem.l %d2-%d7/%a2-%a6,(%a0) /* Write all of the preserved */
lea (11*4)(%a0),%a0 /* registers, the stack pointer, */
move.l %a1,(%a0)+ /* and the return address into the */
move.l (%sp),(%a0) /* structure. */
 
moveq.l #0,%d0 /* Load a zero return value and */
rts /* return. */
 
/*****************************************************************************
hal_m68k_longjmp -- Generic longjmp for the m68k architecture
 
externC void hal_m68k_longjmp(hal_jmp_buf env, int val);
 
INPUT:
 
0(%sp): return address
 
4(%sp): env - address of a hal_jmp_buf structure
 
8(%sp): val - the non-zero value to return
 
OUTPUT:
 
d0, d1, a0, a1 are ours to abuse.
 
RETURN VALUE:
 
This routine always returns the value from the val parameter in d0.l
and to the location of the PC in the env structure.
 
*****************************************************************************/
FUNC_START(hal_m68k_longjmp)
 
move.l 8(%sp),%d0 /* Load the return value */
/* parameter. */
 
move.l 4(%sp),%a0 /* Get a pointer to the buffer to */
/* read our state from. */
 
movem.l (%a0),%d2-%d7/%a2-%a6 /* Load our preserved registers, */
lea (11*4)(%a0),%a0 /* stack pointer and return address */
move.l (%a0)+,%d1 /* from the structure. */
move.l (%a0),%a1
 
move.l %d1,%sp /* Set the stack pointer from the */
jmp (%a1) /* structure as out current stack */
/* pointer and jump to the return */
/* address from the structure. */
 
 
 
/arch/v2_0/src/m68k.ld
0,0 → 1,205
/*==========================================================================
//
// m68k.ld
//
// Linker script
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
*/
 
STARTUP(vectors.o)
ENTRY(__exception_reset)
#ifdef EXTRAS
INPUT(extras.o)
#endif
#if (__GNUC__ >= 3)
GROUP(libtarget.a libgcc.a libsupc++.a)
#else
GROUP(libtarget.a libgcc.a)
#endif
 
#define ALIGN_LMA 4
#define FOLLOWING(_section_) AT ((LOADADDR (_section_) + SIZEOF (_section_) + ALIGN_LMA - 1) & ~ (ALIGN_LMA - 1))
#define LMA_EQ_VMA
#define FORCE_OUTPUT . = .
 
#ifndef CYG_LABEL_DEFN
# define CYG_LABEL_DEFN(_label) _label
#endif
 
#define SECTIONS_BEGIN
 
#define SECTION_text(_region_, _vma_, _lma_) \
.text _vma_ : _lma_ \
{ _stext = .; \
*(.text*) *(.gnu.warning) *(.gnu.linkonce*) *(.init) } \
> _region_ \
_etext = .; PROVIDE (etext = .);
 
#define SECTION_fini(_region_, _vma_, _lma_) \
.fini _vma_ : _lma_ \
{ FORCE_OUTPUT; *(.fini) } \
> _region_
 
#define SECTION_rodata1(_region_, _vma_, _lma_) \
.rodata1 _vma_ : _lma_ \
{ FORCE_OUTPUT; *(.rodata1) } \
> _region_
 
#define SECTION_rodata(_region_, _vma_, _lma_) \
.rodata _vma_ : _lma_ \
{ FORCE_OUTPUT; *(.rodata*) } \
> _region_
 
#define SECTION_fixup(_region_, _vma_, _lma_) \
.fixup _vma_ : _lma_ \
{ __FIXUP_START__ = ABSOLUTE(.); *(.fixup) __FIXUP_END__ = ABSOLUTE(.);}\
> _region_
 
#define SECTION_gcc_except_table(_region_, _vma_, _lma_) \
.gcc_except_table _vma_ : _lma_ \
{ __EXCEPT_START__ = ABSOLUTE(.); *(.gcc_except_table) \
__EXCEPT_END__ = ABSOLUTE(.);} \
> _region_
 
#define SECTION_data(_region_, _vma_, _lma_, _rom_data_addr_) \
.data _vma_ : _lma_ \
{ \
__ram_data_start = ABSOLUTE(.); \
*(.data*) \
__GOT1_START__ = ABSOLUTE(.); *(.got1) __GOT1_END__ = ABSOLUTE(.); \
. = ALIGN (4); \
KEEP(*( SORT (.ecos.table.*))); \
. = ALIGN (4); \
__CTOR_LIST__ = ABSOLUTE(.); \
KEEP(*(SORT(.ctors*))); \
__CTOR_END__ = ABSOLUTE(.); \
__DTOR_LIST__ = ABSOLUTE(.); \
KEEP(*(SORT(.dtors*))) \
__DTOR_END__ = ABSOLUTE(.); \
. = ALIGN(8); \
__GOT2_START__ = ABSOLUTE(.); *(.got2) __GOT2_END__ = ABSOLUTE(.); \
__GOT_START = ABSOLUTE(.); _GLOBAL_OFFSET_TABLE_ = ABSOLUTE(. + 32768); \
_SDA_BASE_ = ABSOLUTE(.); *(.got.plt) *(.got) \
__GOT_END__ = ABSOLUTE(.); *(.dynamic) \
*(.eh_frame) \
/* We want the small data sections together, so single-instruction */ \
/* offsets can access them all, and initialized data all before */ \
/* uninitialized, so we can shorten the on-disk segment size. */ \
__SDATA_START__ = ABSOLUTE(.); *(.sdata) \
__ram_data_end = ABSOLUTE(.); \
__ram_data_size = ABSOLUTE (.) - ABSOLUTE(__ram_data_start); \
} \
> _region_ \
__rom_data_start = ABSOLUTE(_rom_data_addr_); \
__rom_data_size = SIZEOF(.data); \
__rom_data_end = __rom_data_start + __rom_data_size;
 
#define SECTION_sbss(_region_, _vma_, _lma_) \
.sbss _vma_ : _lma_ \
{ __sbss_start = ABSOLUTE (.); \
__SBSS_START__ = ABSOLUTE(.); *(.sbss) __SBSS_END__ = ABSOLUTE(.); \
*(.scommon) \
__sbss_end = ABSOLUTE (.); \
__sbss_size = ABSOLUTE (.) - ABSOLUTE(__sbss_start); \
} \
> _region_
 
#define SECTION_bss(_region_, _vma_, _lma_) \
.bss _vma_ : _lma_ \
{ __bss_start = ABSOLUTE (.); \
FORCE_OUTPUT; *(.dynbss) *(.bss) *(COMMON) \
__bss_end = ABSOLUTE (.); \
__bss_size = ABSOLUTE (.) - ABSOLUTE(__bss_start); \
} \
> _region_
 
#define SECTION_stab \
.stab 0 (NOLOAD) : \
{ \
*(.stab) \
}
 
#define SECTION_stabstr \
.stabstr 0 (NOLOAD) : \
{ \
*(.stabstr) \
}
 
#define SECTION_comment \
.comment 0 (NOLOAD) : \
{ \
*(.comment) \
}
 
#define SECTION_heap1(_region_, _vma_, _lma_, _minsize_) \
.heap1 _vma_ : _lma_ \
{ __heap1_start = ABSOLUTE (.); \
. += (_minsize_); \
__heap1_end = ABSOLUTE (.); \
__heap1_size = ABSOLUTE (.) - ABSOLUTE(__heap1_start); \
} \
> _region_
 
#define SECTION_uninvar(_region_, _vma_, _lma_) \
.uninvar _vma_ : _lma_ \
{ __uninvar_start = ABSOLUTE (.); \
FORCE_OUTPUT; *(.uninvar) \
__uninvar_end = ABSOLUTE (.); \
__uninvar_size = ABSOLUTE (.) - ABSOLUTE(__uninvar_start); \
} \
> _region_
 
#define GENERIC_SECTION(_name_, _region_, _vma_, _lma_, _minsize_) \
. ## _name_ _vma_ : _lma_ \
{ __ ## _name_ ## _start = ABSOLUTE (.); \
FORCE_OUTPUT; *(. ## _name_ ## ) \
__ ## _name_ ## _datasize = (ABSOLUTE (.) - ABSOLUTE(__ ## _name_ ## _start)); \
. += (_minsize_) > (__ ## _name_ ## _datasize) ? (_minsize_) - (__ ## _name_ ## _datasize) : 0; \
__ ## _name_ ## _end = ABSOLUTE (.); \
__ ## _name_ ## _size = (ABSOLUTE (.) - ABSOLUTE(__ ## _name_ ## _start)); \
} \
> _region_
 
#define SECTIONS_END \
SECTION_stab \
SECTION_stabstr \
SECTION_comment \
. = ALIGN(4); _end = .; PROVIDE (end = .);
 
#include <pkgconf/system.h>
#include CYGHWR_MEMORY_LAYOUT_LDI
 
/arch/v2_0/src/m68k_stub.c
0,0 → 1,191
//========================================================================
//
// m68k_stub.c
//
// Helper functions for stub
//
//========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//========================================================================
 
#include <stddef.h>
 
#include <pkgconf/hal.h>
 
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
#include <cyg/hal/hal_stub.h>
 
#include <cyg/hal/hal_stub.h>
#include <cyg/hal/hal_arch.h>
#include <cyg/hal/hal_intr.h>
 
#ifdef CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
#include <cyg/hal/dbg-threads-api.h> // dbg_currthread_id
#endif
 
/* Given a trap value TRAP, return the corresponding signal. */
 
int __computeSignal (unsigned int trap_number)
{
switch (trap_number)
{
 
case CYGNUM_HAL_VECTOR_BUSERR:
case CYGNUM_HAL_VECTOR_ADDERR:
return SIGBUS;
 
case CYGNUM_HAL_VECTOR_ILLINST:
return SIGILL;
 
case CYGNUM_HAL_VECTOR_ZERODIV:
/* This isn't quite accurate: this is integer division only. */
return SIGFPE;
 
case CYGNUM_HAL_VECTOR_CHKINST:
case CYGNUM_HAL_VECTOR_TRAPVINST:
return SIGTRAP;
 
case CYGNUM_HAL_VECTOR_PRIVVIOLATION:
return SIGILL;
case CYGNUM_HAL_VECTOR_TRACE:
/* Instruction trace */
return SIGTRAP;
 
case CYGNUM_HAL_VECTOR_L1010:
case CYGNUM_HAL_VECTOR_L1111:
case CYGNUM_HAL_VECTOR_UNINITINT:
case CYGNUM_HAL_VECTOR_SPURINT:
return SIGTRAP;
 
case CYGNUM_HAL_VECTOR_TRAPFIRST ... CYGNUM_HAL_VECTOR_TRAPLAST:
return SIGTRAP;
 
case CYGNUM_HAL_VECTOR_AUTOVEC1 ... CYGNUM_HAL_VECTOR_AUTOVEC7:
case CYGNUM_HAL_VECTOR_INTRFIRST ... CYGNUM_HAL_VECTOR_INTRLAST:
/* External interrupt */
return SIGINT;
 
default:
return SIGTERM;
}
}
 
 
/* Return the trap number corresponding to the last-taken trap. */
 
int __get_trap_number (void)
{
//extern int hal_m68k_trap_number;
 
// The vector is not not part of the GDB register set so get it
// directly from the save context.
//return hal_m68k_trap_number;
 
return 1;
}
 
/* Set the currently-saved pc register value to PC. This also updates NPC
as needed. */
 
void set_pc (target_register_t pc)
{
put_register (PC, pc);
}
 
 
/*----------------------------------------------------------------------
* Single-step support
*/
 
/* Set things up so that the next user resume will execute one instruction.
This may be done by setting breakpoints or setting a single step flag
in the saved user registers, for example. */
 
#define SR_TRACE 0x8000
 
void __single_step (void)
{
target_register_t sr = get_register (PS);
 
// Set trace flag in the exception context.
sr |= SR_TRACE;
 
put_register (PS, sr);
}
 
/* Clear the single-step state. */
 
void __clear_single_step (void)
{
target_register_t sr = get_register (PS);
 
// Clear single-step flag in the exception context.
sr &= ~SR_TRACE;
 
put_register (PS, sr);
}
 
 
void __install_breakpoints (void)
{
/* NOP since single-step HW exceptions are used instead of
breakpoints. */
}
 
void __clear_breakpoints (void)
{
}
 
 
/* If the breakpoint we hit is in the breakpoint() instruction, return a
non-zero value. */
 
int
__is_breakpoint_function ()
{
return get_register (PC) == (target_register_t)&CYG_LABEL_NAME(breakinst);
}
 
 
/* Skip the current instruction. Since this is only called by the
stub when the PC points to a breakpoint or trap instruction,
we can safely just skip 4. */
 
void __skipinst (void)
{
put_register (PC, get_register (PC) + 4);
}
 
#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 
/arch/v2_0/src/hal_startup.c
0,0 → 1,262
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
 
#include <pkgconf/hal.h>
#include <cyg/hal/hal_startup.h>
#include <cyg/hal/hal_memmap.h>
#include <cyg/hal/hal_intr.h>
#include <cyg/hal/hal_diag.h> // hal_diag_init
#include <cyg/infra/diag.h> // diag_printf
#include <string.h> // memcpy, memset
 
externC void cyg_start(void);
externC void hw_vsr_reset(void);
 
#define CYG_HAL_RESET_DEBUG_ENABLE
#ifdef CYG_HAL_RESET_DEBUG_ENABLE
#define CYG_HAL_RESET_DEBUG diag_printf
#else
#define CYG_HAL_RESET_DEBUG()
#endif // CYG_HAL_RESET_DEBUG_ENABLE
 
/*****************************************************************************
hal_vsr_init -- Initialize the vector table
 
INPUT:
 
OUTPUT:
 
RETURN VALUE:
 
None
 
*****************************************************************************/
static void hal_vsr_init(void)
{
 
/* Initialize the HAL's vector table with the ROM vector table. */
 
memcpy((void*)cyg_hal_vsr_table, __romvec_start,
(size_t)sizeof(cyg_hal_vsr_table));
 
}
 
/*****************************************************************************
hal_vsr_init -- Initialize the ISRs
 
INPUT:
 
OUTPUT:
 
RETURN VALUE:
 
None
 
*****************************************************************************/
static void hal_isr_init(void)
{
int_t i;
 
// Initialize all ISR entries to default.
 
for (i = 0; i < CYGNUM_HAL_ISR_COUNT; i++)
{
cyg_hal_interrupt_handlers[i] = (CYG_ADDRESS) &hal_default_isr;
cyg_hal_interrupt_data[i] = (CYG_ADDRWORD)0;
cyg_hal_interrupt_objects[i] = (CYG_ADDRESS)0;
}
}
 
/*****************************************************************************
hal_init_ram_sections -- Initialize the RAM sections
 
Initialize all RAM sections that the C code relies on. data, bss,
sbss.
 
INPUT:
 
OUTPUT:
 
RETURN VALUE:
 
None
 
*****************************************************************************/
static void hal_init_ram_sections(void)
{
 
// Initialize the RAM data section from the ROM image of the data
// section.
 
memcpy(__ram_data_start, __rom_data_start, (size_t)__ram_data_size);
 
// Initialize the bss and sbss sections to zero.
 
memset(__bss_start, 0, (size_t)__bss_size);
memset(__sbss_start, 0, (size_t)__sbss_size);
}
 
/*****************************************************************************
cyg_hal_invoke_constructors -- Call static constructors
 
INPUT:
 
OUTPUT:
 
RETURN VALUE:
 
None
 
*****************************************************************************/
#ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG
cyg_bool cyg_hal_stop_constructors;
#endif
 
typedef void (*pfunc) (void);
extern pfunc __CTOR_LIST__[];
extern pfunc __CTOR_END__[];
 
static void cyg_hal_invoke_constructors(void)
{
#ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG
static pfunc *p = &__CTOR_END__[-1];
 
cyg_hal_stop_constructors = 0;
for (; p >= __CTOR_LIST__; p--) {
(*p) ();
if (cyg_hal_stop_constructors) {
p--;
break;
}
}
#else
pfunc *p;
 
for (p = &__CTOR_END__[-1]; p >= __CTOR_LIST__; p--)
(*p) ();
#endif
}
 
/*****************************************************************************
hal_reset -- Reset vector routine
 
This routine must be called with interrupts disabled and will never
return.
 
Only the assembly reset vector routine should call this routine.
 
INPUT:
 
OUTPUT:
 
RETURN VALUE:
 
None
 
*****************************************************************************/
void hal_reset(void) CYGBLD_ATTRIB_NORET;
void hal_reset(void)
{
const char * fname;
 
fname = __FUNCTION__;
 
// Initialize the RAM sections that the rest of the C code requires.
 
hal_init_ram_sections();
 
// It is now safe to call C functions which may rely on initialized
// data.
 
// Initialize the ISR and VSR tables.
 
hal_isr_init();
hal_vsr_init();
 
// Do any variant-specific reset initialization.
 
var_reset();
 
// Initialize the diagnostics IO.
 
HAL_DIAG_INIT();
CYG_HAL_RESET_DEBUG("%s: RESET\r\n", fname);
 
// Call C++ constructors.
 
CYG_HAL_RESET_DEBUG("%s: calling cyg_hal_invoke_constructors\r\n", fname);
cyg_hal_invoke_constructors();
 
// It should be safe to enable interrupts now.
 
CYG_HAL_RESET_DEBUG("%s: lowering interrupt mask\r\n", fname);
HAL_ENABLE_INTERRUPTS();
 
// Call cyg_start. This routine should not return.
 
CYG_HAL_RESET_DEBUG("%s: calling cyg_start\r\n", fname);
cyg_start();
 
// If we return, loop and print out a message.
 
HAL_DIAG_INIT();
for (;;)
{
CYG_HAL_RESET_DEBUG("%s: cyg_start returned!\r\n", fname);
}
}
 
/*****************************************************************************
hal_hw_reset -- Simulate a hardware reset
 
This routine will never return.
 
INPUT:
 
OUTPUT:
 
RETURN VALUE:
 
None
 
*****************************************************************************/
void hal_hw_reset(void)
{
 
// Give control to the reset vector handler.
 
hw_vsr_reset();
}
 

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