URL
https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
Subversion Repositories openrisc_me
Compare Revisions
- This comparison shows the changes necessary to convert path
/openrisc/trunk/rtos/ecos-2.0/packages/hal/mips/atlas
- from Rev 27 to Rev 174
- ↔ Reverse comparison
Rev 27 → Rev 174
/v2_0/cdl/hal_mips_atlas.cdl
0,0 → 1,345
# ==================================================================== |
# |
# hal_mips_atlas.cdl |
# |
# MIPS Atlas board HAL package configuration data |
# |
# ==================================================================== |
#####ECOSGPLCOPYRIGHTBEGIN#### |
## ------------------------------------------- |
## This file is part of eCos, the Embedded Configurable Operating System. |
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
## |
## eCos is free software; you can redistribute it and/or modify it under |
## the terms of the GNU General Public License as published by the Free |
## Software Foundation; either version 2 or (at your option) any later version. |
## |
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
## WARRANTY; without even the implied warranty of MERCHANTABILITY or |
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
## for more details. |
## |
## You should have received a copy of the GNU General Public License along |
## with eCos; if not, write to the Free Software Foundation, Inc., |
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
## |
## As a special exception, if other files instantiate templates or use macros |
## or inline functions from this file, or you compile this file and link it |
## with other works to produce a work based on this file, this file does not |
## by itself cause the resulting work to be covered by the GNU General Public |
## License. However the source code for this file must still be made available |
## in accordance with section (3) of the GNU General Public License. |
## |
## This exception does not invalidate any other reasons why a work based on |
## this file might be covered by the GNU General Public License. |
## |
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
## at http://sources.redhat.com/ecos/ecos-license/ |
## ------------------------------------------- |
#####ECOSGPLCOPYRIGHTEND#### |
# ==================================================================== |
######DESCRIPTIONBEGIN#### |
# |
# Author(s): dmoseley |
# Original data: bartv |
# Contributors: |
# Date: 2000-06-06 |
# |
#####DESCRIPTIONEND#### |
# |
# ==================================================================== |
|
cdl_package CYGPKG_HAL_MIPS_ATLAS { |
display "Atlas evaluation board" |
parent CYGPKG_HAL_MIPS |
requires { ((((CYGHWR_HAL_MIPS_MIPS32_CORE == "4Kc") || \ |
(CYGHWR_HAL_MIPS_MIPS32_CORE == "4Kp") || \ |
(CYGHWR_HAL_MIPS_MIPS32_CORE == "4Km")) && CYGPKG_HAL_MIPS_MIPS32) || \ |
(((CYGHWR_HAL_MIPS_MIPS64_CORE == "5K") || \ |
(CYGHWR_HAL_MIPS_MIPS64_CORE == "20K")) && CYGPKG_HAL_MIPS_MIPS64)) \ |
} |
include_dir cyg/hal |
description " |
The Atlas HAL package should be used when targetting the |
actual hardware." |
|
compile hal_diag.c platform.S plf_misc.c ser16c550c.c |
|
implements CYGINT_HAL_DEBUG_GDB_STUBS |
implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK |
implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT |
implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT |
|
cdl_option CYGBLD_HAL_TARGET_H { |
display "Variant header" |
flavor data |
no_define |
calculated { CYGPKG_HAL_MIPS_MIPS32 ? "<pkgconf/hal_mips_mips32.h>" : \ |
"<pkgconf/hal_mips_mips64.h>" } |
define -file system.h CYGBLD_HAL_TARGET_H |
description "Variant header." |
|
define_proc { |
puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_mips_atlas.h>" |
puts $::cdl_system_header "" |
puts $::cdl_system_header "/* Make sure we get the CORE type definitions for HAL_PLATFORM_CPU */" |
puts $::cdl_system_header "#include CYGBLD_HAL_TARGET_H" |
puts $::cdl_system_header "#define HAL_PLATFORM_BOARD \"Atlas\"" |
puts $::cdl_system_header "#define HAL_PLATFORM_EXTRA \"\"" |
puts $::cdl_system_header "" |
puts $::cdl_system_header "#if defined(CYGHWR_HAL_MIPS_MIPS32_CORE_4Kc)" |
puts $::cdl_system_header "# define HAL_PLATFORM_CPU \"MIPS32 4Kc\"" |
puts $::cdl_system_header "#elif defined(CYGHWR_HAL_MIPS_MIPS32_CORE_4Kp)" |
puts $::cdl_system_header "# define HAL_PLATFORM_CPU \"MIPS32 4Kp\"" |
puts $::cdl_system_header "#elif defined(CYGHWR_HAL_MIPS_MIPS32_CORE_4Km)" |
puts $::cdl_system_header "# define HAL_PLATFORM_CPU \"MIPS32 4Km\"" |
puts $::cdl_system_header "#elif defined(CYGHWR_HAL_MIPS_MIPS64_CORE_5K)" |
puts $::cdl_system_header "# define HAL_PLATFORM_CPU \"MIPS64 5K\"" |
puts $::cdl_system_header "#elif defined(CYGHWR_HAL_MIPS_MIPS64_CORE_20K)" |
puts $::cdl_system_header "# define HAL_PLATFORM_CPU \"MIPS64 20K\"" |
puts $::cdl_system_header "#else" |
puts $::cdl_system_header "# error Unknown Core" |
puts $::cdl_system_header "#endif" |
puts $::cdl_system_header "" |
} |
|
} |
|
cdl_component CYG_HAL_STARTUP { |
display "Startup type" |
flavor data |
legal_values {"RAM" "ROM"} |
default_value {"RAM"} |
no_define |
define -file system.h CYG_HAL_STARTUP |
description " |
Currently RAM and ROM startup types are supported." |
} |
|
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD { |
display "Diagnostic serial port baud rate" |
flavor data |
legal_values 9600 19200 38400 57600 115200 |
default_value 115200 |
description " |
This option selects the baud rate used for the diagnostic port. |
Note: this should match the value chosen for the GDB port if the |
diagnostic and GDB port are the same." |
} |
|
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD { |
display "GDB serial port baud rate" |
flavor data |
legal_values 9600 19200 38400 57600 115200 |
default_value 115200 |
description " |
This option controls the baud rate used for the GDB connection." |
} |
|
# Real-time clock/counter specifics |
cdl_component CYGNUM_HAL_RTC_CONSTANTS { |
display "Real-time clock constants." |
flavor none |
|
cdl_option CYGNUM_HAL_RTC_NUMERATOR { |
display "Real-time clock numerator" |
flavor data |
calculated 1000000000 |
} |
cdl_option CYGNUM_HAL_RTC_DENOMINATOR { |
display "Real-time clock denominator" |
flavor data |
calculated 100 |
} |
cdl_option CYGNUM_HAL_RTC_PERIOD { |
display "Real-time clock period" |
flavor data |
calculated { 40000000 / CYGNUM_HAL_RTC_DENOMINATOR } |
description " |
The count and compare registers of the Atlas are used |
to drive the eCos kernel RTC. The count register |
increments at the CPU clock speed." |
} |
} |
|
cdl_option CYGBLD_BUILD_GDB_STUBS { |
display "Build GDB stub ROM image" |
default_value 0 |
parent CYGBLD_GLOBAL_OPTIONS |
requires { CYG_HAL_STARTUP == "ROM" } |
requires CYGSEM_HAL_ROM_MONITOR |
requires CYGBLD_BUILD_COMMON_GDB_STUBS |
requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS |
requires ! CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT |
requires ! CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT |
requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT |
requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM |
no_define |
description " |
This option enables the building of the GDB stubs for the |
board. The common HAL controls takes care of most of the |
build process, but the final conversion from ELF image to |
binary data is handled by the platform CDL, allowing |
relocation of the data if necessary." |
|
make -priority 320 { |
<PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img |
$(OBJCOPY) -O binary $< $@ |
} |
} |
|
|
cdl_option CYGNUM_HAL_BREAKPOINT_LIST_SIZE { |
display "Number of breakpoints supported by the HAL." |
flavor data |
default_value 25 |
description " |
This option determines the number of breakpoints supported by the HAL." |
} |
|
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { |
display "Number of communication channels on the board" |
flavor data |
calculated 1 |
} |
|
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { |
display "Debug serial port" |
active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE |
flavor data |
legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 |
default_value 0 |
description " |
The Atlas board has only one serial port. This option |
chooses which port will be used to connect to a host |
running GDB." |
} |
|
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { |
display "Diagnostic serial port" |
active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE |
flavor data |
legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 |
default_value 0 |
description " |
The Atlas board has only one serial port. This option |
chooses which port will be used for diagnostic output." |
} |
|
cdl_component CYGHWR_MEMORY_LAYOUT { |
display "Memory layout" |
flavor data |
no_define |
calculated { CYG_HAL_STARTUP == "RAM" ? "mips_atlas_ram" : \ |
"mips_atlas_rom" } |
|
cdl_option CYGHWR_MEMORY_LAYOUT_LDI { |
display "Memory layout linker script fragment" |
flavor data |
no_define |
define -file system.h CYGHWR_MEMORY_LAYOUT_LDI |
calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_mips_atlas_ram.ldi>" : \ |
"<pkgconf/mlt_mips_atlas_rom.ldi>" } |
} |
|
cdl_option CYGHWR_MEMORY_LAYOUT_H { |
display "Memory layout header file" |
flavor data |
no_define |
define -file system.h CYGHWR_MEMORY_LAYOUT_H |
calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_mips_atlas_ram.h>" : \ |
"<pkgconf/mlt_mips_atlas_rom.h>" } |
} |
} |
|
cdl_option CYGSEM_HAL_USE_ROM_MONITOR { |
display "Work with a ROM monitor" |
flavor booldata |
legal_values { "Generic" "CygMon" "GDB_stubs" } |
default_value { CYG_HAL_STARTUP == "RAM" ? "CygMon" : 0 } |
parent CYGPKG_HAL_ROM_MONITOR |
requires { CYG_HAL_STARTUP == "RAM" } |
description " |
Support can be enabled for three different varieties of ROM monitor. |
This support changes various eCos semantics such as the encoding |
of diagnostic output, or the overriding of hardware interrupt |
vectors. |
Firstly there is \"Generic\" support which prevents the HAL |
from overriding the hardware vectors that it does not use, to |
instead allow an installed ROM monitor to handle them. This is |
the most basic support which is likely to be common to most |
implementations of ROM monitor. |
\"CygMon\" provides support for the Cygnus ROM Monitor. |
And finally, \"GDB_stubs\" provides support when GDB stubs are |
included in the ROM monitor or boot ROM." |
} |
|
cdl_option CYGSEM_HAL_ROM_MONITOR { |
display "Behave as a ROM monitor" |
flavor bool |
default_value 0 |
parent CYGPKG_HAL_ROM_MONITOR |
requires { CYG_HAL_STARTUP == "ROM" } |
description " |
Enable this option if this program is to be used as a ROM monitor, |
i.e. applications will be loaded into RAM on the board, and this |
ROM monitor may process exceptions or interrupts generated from the |
application. This enables features such as utilizing a separate |
interrupt stack when exceptions are generated." |
} |
|
cdl_component CYGPKG_CYGMON_HAL_OPTIONS { |
display "CygMon HAL options" |
flavor none |
no_define |
parent CYGPKG_CYGMON |
active_if CYGPKG_CYGMON |
description " |
This option also lists the target's requirements for a valid CygMon |
configuration." |
|
cdl_option CYGBLD_BUILD_CYGMON_BIN { |
display "Build CygMon ROM binary image" |
active_if CYGBLD_BUILD_CYGMON |
default_value 1 |
no_define |
description "This option enables the conversion of the CygMon ELF |
image to a binary image suitable for ROM programming." |
|
make -priority 325 { |
<PREFIX>/bin/cygmon.srec : <PREFIX>/bin/cygmon.elf |
$(OBJCOPY) --strip-debug $< $(@:.bin=.img) |
$(OBJCOPY) -O srec $< $@ |
} |
} |
} |
|
cdl_component CYGPKG_REDBOOT_HAL_OPTIONS { |
display "Redboot HAL options" |
flavor none |
no_define |
parent CYGPKG_REDBOOT |
active_if CYGPKG_REDBOOT |
description " |
This option lists the target's requirements for a valid Redboot |
configuration." |
|
cdl_option CYGBLD_BUILD_REDBOOT_BIN { |
display "Build Redboot ROM binary image" |
active_if CYGBLD_BUILD_REDBOOT |
default_value 1 |
no_define |
description "This option enables the conversion of the Redboot ELF |
image to a binary image suitable for ROM programming." |
|
compile -library=libextras.a |
|
make -priority 325 { |
<PREFIX>/bin/redboot.srec : <PREFIX>/bin/redboot.elf |
$(OBJCOPY) --strip-all $< $(@:.srec=.img) |
$(OBJCOPY) -O srec $< $@ |
} |
} |
} |
|
} |
/v2_0/include/plf_intr.h
0,0 → 1,238
#ifndef CYGONCE_HAL_PLF_INTR_H |
#define CYGONCE_HAL_PLF_INTR_H |
|
//========================================================================== |
// |
// plf_intr.h |
// |
// Atlas Interrupt and clock support |
// |
//========================================================================== |
//####ECOSGPLCOPYRIGHTBEGIN#### |
// ------------------------------------------- |
// This file is part of eCos, the Embedded Configurable Operating System. |
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
// |
// eCos is free software; you can redistribute it and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
// Software Foundation; either version 2 or (at your option) any later version. |
// |
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
// WARRANTY; without even the implied warranty of MERCHANTABILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with eCos; if not, write to the Free Software Foundation, Inc., |
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
// |
// As a special exception, if other files instantiate templates or use macros |
// or inline functions from this file, or you compile this file and link it |
// with other works to produce a work based on this file, this file does not |
// by itself cause the resulting work to be covered by the GNU General Public |
// License. However the source code for this file must still be made available |
// in accordance with section (3) of the GNU General Public License. |
// |
// This exception does not invalidate any other reasons why a work based on |
// this file might be covered by the GNU General Public License. |
// |
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
// at http://sources.redhat.com/ecos/ecos-license/ |
// ------------------------------------------- |
//####ECOSGPLCOPYRIGHTEND#### |
//========================================================================== |
//#####DESCRIPTIONBEGIN#### |
// |
// Author(s): nickg |
// Contributors: nickg, jskov, |
// gthomas, jlarmour, dmoseley |
// Date: 2000-06-06 |
// Purpose: Define Interrupt support |
// Description: The macros defined here provide the HAL APIs for handling |
// interrupts and the clock for the Atlas board. |
// |
// Usage: |
// #include <cyg/hal/plf_intr.h> |
// ... |
// |
// |
//####DESCRIPTIONEND#### |
// |
//========================================================================== |
|
#include <pkgconf/hal.h> |
|
#include <cyg/infra/cyg_type.h> |
#include <cyg/hal/plf_io.h> |
|
//-------------------------------------------------------------------------- |
// Interrupt vectors. |
|
#ifndef CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED |
|
// These are decoded via the IP bits of the cause |
// register when an external interrupt is delivered. |
|
#define CYGNUM_HAL_INTERRUPT_SER 0 |
#define CYGNUM_HAL_INTERRUPT_TIM0 1 |
#define CYGNUM_HAL_INTERRUPT_2 2 |
#define CYGNUM_HAL_INTERRUPT_3 3 |
#define CYGNUM_HAL_INTERRUPT_FPGA_RTC 4 |
#define CYGNUM_HAL_INTERRUPT_COREHI 5 |
#define CYGNUM_HAL_INTERRUPT_CORELO 6 |
#define CYGNUM_HAL_INTERRUPT_7 7 |
#define CYGNUM_HAL_INTERRUPT_PCIA 8 |
#define CYGNUM_HAL_INTERRUPT_PCIB 9 |
#define CYGNUM_HAL_INTERRUPT_PCIC 10 |
#define CYGNUM_HAL_INTERRUPT_PCID 11 |
#define CYGNUM_HAL_INTERRUPT_ENUM 12 |
#define CYGNUM_HAL_INTERRUPT_DEG 13 |
#define CYGNUM_HAL_INTERRUPT_ATXFAIL 14 |
#define CYGNUM_HAL_INTERRUPT_INTA 15 |
#define CYGNUM_HAL_INTERRUPT_INTB 16 |
#define CYGNUM_HAL_INTERRUPT_INTC 17 |
#define CYGNUM_HAL_INTERRUPT_INTD 18 |
#define CYGNUM_HAL_INTERRUPT_SERR 19 |
#define CYGNUM_HAL_INTERRUPT_HW1 20 |
#define CYGNUM_HAL_INTERRUPT_HW2 21 |
#define CYGNUM_HAL_INTERRUPT_HW3 22 |
#define CYGNUM_HAL_INTERRUPT_HW4 23 |
#define CYGNUM_HAL_INTERRUPT_HW5 24 |
|
// Min/Max ISR numbers and how many there are |
#define CYGNUM_HAL_ISR_MIN 0 |
#define CYGNUM_HAL_ISR_MAX 24 |
#define CYGNUM_HAL_ISR_COUNT 25 |
|
#define CYGNUM_HAL_INTERRUPT_DEBUG_UART CYGNUM_HAL_INTERRUPT_SER |
|
#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_HW5 |
|
#define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED |
|
#endif |
|
//-------------------------------------------------------------------------- |
// Interrupt controller access. |
|
#ifndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED |
|
// Array which stores the configured priority levels for the configured |
// interrupts. |
externC volatile CYG_BYTE hal_interrupt_level[CYGNUM_HAL_ISR_COUNT]; |
|
#define HAL_INTERRUPT_MASK( _vector_ ) \ |
{ \ |
cyg_uint32 __vector = _vector_; \ |
\ |
if( (_vector_) < CYGNUM_HAL_INTERRUPT_HW1 ) \ |
HAL_WRITE_UINT32( HAL_ATLAS_INTRSTEN, (1<<(_vector_)) ); \ |
else \ |
{ \ |
__vector -= (CYGNUM_HAL_INTERRUPT_HW1-1); \ |
\ |
asm volatile ( \ |
"mfc0 $3,$12\n" \ |
"la $2,0x00000400\n" \ |
"sllv $2,$2,%0\n" \ |
"nor $2,$2,$0\n" \ |
"and $3,$3,$2\n" \ |
"mtc0 $3,$12\n" \ |
"nop; nop; nop\n" \ |
: \ |
: "r"(__vector) \ |
: "$2", "$3" \ |
); \ |
} \ |
} |
|
#define HAL_INTERRUPT_UNMASK( _vector_ ) \ |
{ \ |
cyg_uint32 __vector = _vector_; \ |
\ |
if( (__vector) < CYGNUM_HAL_INTERRUPT_HW1 ) \ |
{ \ |
HAL_WRITE_UINT32( HAL_ATLAS_INTSETEN, (1<<(__vector)) ); \ |
__vector = 0; \ |
} \ |
else \ |
__vector -= (CYGNUM_HAL_INTERRUPT_HW1-1); \ |
\ |
asm volatile ( \ |
"mfc0 $3,$12\n" \ |
"la $2,0x00000400\n" \ |
"sllv $2,$2,%0\n" \ |
"or $3,$3,$2\n" \ |
"mtc0 $3,$12\n" \ |
"nop; nop; nop\n" \ |
: \ |
: "r"(__vector) \ |
: "$2", "$3" \ |
); \ |
} |
|
#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \ |
{ \ |
cyg_uint32 __vector = _vector_; \ |
\ |
if( __vector >= CYGNUM_HAL_INTERRUPT_HW1 ) \ |
__vector -= (CYGNUM_HAL_INTERRUPT_HW1-1); \ |
else \ |
__vector = 0; \ |
\ |
asm volatile ( \ |
"mfc0 $3,$13\n" \ |
"la $2,0x00000400\n" \ |
"sllv $2,$2,%0\n" \ |
"nor $2,$2,$0\n" \ |
"and $3,$3,$2\n" \ |
"mtc0 $3,$13\n" \ |
"nop; nop; nop\n" \ |
: \ |
: "r"(__vector) \ |
: "$2", "$3" \ |
); \ |
\ |
} |
|
#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \ |
{ \ |
} |
|
#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \ |
{ \ |
} |
|
#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED |
|
#endif |
|
|
//-------------------------------------------------------------------------- |
// Control-C support. |
|
#if defined(CYGDBG_HAL_MIPS_DEBUG_GDB_CTRLC_SUPPORT) |
|
# define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_SER |
|
externC cyg_uint32 hal_ctrlc_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data); |
|
# define HAL_CTRLC_ISR hal_ctrlc_isr |
|
#endif |
|
|
//---------------------------------------------------------------------------- |
// Reset. |
#ifndef CYGHWR_HAL_RESET_DEFINED |
extern void hal_atlas_reset( void ); |
#define CYGHWR_HAL_RESET_DEFINED |
#define HAL_PLATFORM_RESET() hal_atlas_reset() |
|
#define HAL_PLATFORM_RESET_ENTRY 0xbfc00000 |
|
#endif // CYGHWR_HAL_RESET_DEFINED |
|
//-------------------------------------------------------------------------- |
#endif // ifndef CYGONCE_HAL_PLF_INTR_H |
// End of plf_intr.h |
/v2_0/include/plf_stub.h
0,0 → 1,92
#ifndef CYGONCE_HAL_PLF_STUB_H |
#define CYGONCE_HAL_PLF_STUB_H |
|
//============================================================================= |
// |
// plf_stub.h |
// |
// Platform header for GDB stub support. |
// |
//============================================================================= |
//####ECOSGPLCOPYRIGHTBEGIN#### |
// ------------------------------------------- |
// This file is part of eCos, the Embedded Configurable Operating System. |
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
// |
// eCos is free software; you can redistribute it and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
// Software Foundation; either version 2 or (at your option) any later version. |
// |
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
// WARRANTY; without even the implied warranty of MERCHANTABILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with eCos; if not, write to the Free Software Foundation, Inc., |
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
// |
// As a special exception, if other files instantiate templates or use macros |
// or inline functions from this file, or you compile this file and link it |
// with other works to produce a work based on this file, this file does not |
// by itself cause the resulting work to be covered by the GNU General Public |
// License. However the source code for this file must still be made available |
// in accordance with section (3) of the GNU General Public License. |
// |
// This exception does not invalidate any other reasons why a work based on |
// this file might be covered by the GNU General Public License. |
// |
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
// at http://sources.redhat.com/ecos/ecos-license/ |
// ------------------------------------------- |
//####ECOSGPLCOPYRIGHTEND#### |
//============================================================================= |
//#####DESCRIPTIONBEGIN#### |
// |
// Author(s): jskov |
// Contributors:jskov, dmoseley |
// Date: 2000-06-06 |
// Purpose: Platform HAL stub support for MIPS Atlas boards. |
// Usage: #include <cyg/hal/plf_stub.h> |
// |
//####DESCRIPTIONEND#### |
// |
//============================================================================= |
#include <pkgconf/hal.h> |
|
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS |
|
#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM |
|
#include <cyg/hal/mips-stub.h> // architecture stub support |
|
//---------------------------------------------------------------------------- |
// Define some platform specific communication details. This is mostly |
// handled by hal_if now, but we need to make sure the comms tables are |
// properly initialized. |
|
externC void cyg_hal_plf_comms_init(void); |
|
#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init() |
|
#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud)) |
#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0 |
#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT |
|
//---------------------------------------------------------------------------- |
// Stub initializer. |
#define HAL_STUB_PLATFORM_INIT() CYG_EMPTY_STATEMENT |
|
#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS |
|
//----------------------------------------------------------------------------- |
// Syscall support. |
#ifdef CYGPKG_CYGMON |
// Cygmon provides syscall handling for this board |
#define SIGSYSCALL SIGSYS |
extern int __get_syscall_num (void); |
#endif |
|
//----------------------------------------------------------------------------- |
#endif // CYGONCE_HAL_PLF_STUB_H |
// End of plf_stub.h |
/v2_0/include/pkgconf/mlt_mips_atlas_rom.mlt
0,0 → 1,26
version 0 |
region ram 80000400 fffc00 0 ! |
region rom 9fc00000 80000 1 ! |
section data 0 40 1 1 1 1 0 1 80000400 data1 data1 ! |
section data1 0 40 1 1 0 1 0 1 eh_frame eh_frame ! |
section eh_frame 0 40 1 1 0 1 0 1 gcc_except_table gcc_except_table ! |
section gcc_except_table 0 40 1 1 0 1 0 1 ctors ctors ! |
section ctors 0 40 1 1 0 1 0 1 dtors dtors ! |
section dtors 0 40 1 1 0 1 0 1 devtab devtab ! |
section devtab 0 40 1 1 0 1 0 1 got got ! |
section got 0 40 1 1 0 1 0 1 dynamic dynamic ! |
section dynamic 0 40 1 1 0 1 0 1 sdata sdata ! |
section sdata 0 40 1 1 0 1 0 1 lit8 lit8 ! |
section lit8 0 40 1 1 0 1 0 1 lit4 lit4 ! |
section lit4 0 40 1 1 0 1 0 0 sbss ! |
section sbss 0 40 0 1 0 1 0 1 bss bss ! |
section bss 0 40 0 1 0 1 0 1 heap1 heap1 ! |
section heap1 0 8 0 0 0 0 0 0 ! |
section rom_vectors 0 1 0 1 1 1 1 1 9fc00000 9fc00000 ROMISC ROMISC ! |
section ROMISC 0 40 0 1 0 1 0 1 RELOCS RELOCS ! |
section RELOCS 0 40 0 1 0 1 0 1 init init ! |
section init 0 40 0 1 0 1 0 1 text text ! |
section text 0 40 0 1 0 1 0 1 fini fini ! |
section fini 0 40 0 1 0 1 0 1 rodata rodata ! |
section rodata 0 40 0 1 0 1 0 1 rodata1 rodata1 ! |
section rodata1 0 40 0 1 0 0 0 1 data ! |
/v2_0/include/pkgconf/mlt_mips_atlas_ram.mlt
0,0 → 1,25
version 0 |
region ram 80020000 fe0000 0 ! |
section rom_vectors 0 1 0 1 1 1 1 1 80020000 80020000 ROMISC ROMISC ! |
section ROMISC 0 4 0 1 0 1 0 1 RELOCS RELOCS ! |
section RELOCS 0 4 0 1 0 1 0 1 init init ! |
section init 0 4 0 1 0 1 0 1 text text ! |
section text 0 4 0 1 0 1 0 1 fini fini ! |
section fini 0 4 0 1 0 1 0 1 rodata rodata ! |
section rodata 0 8 0 1 0 1 0 1 rodata1 rodata1 ! |
section rodata1 0 8 0 1 0 1 0 1 data data ! |
section data 0 8 0 1 0 1 0 1 data1 data1 ! |
section data1 0 8 0 1 0 1 0 1 eh_frame eh_frame ! |
section eh_frame 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table ! |
section gcc_except_table 0 4 0 1 0 1 0 1 ctors ctors ! |
section ctors 0 4 0 1 0 1 0 1 dtors dtors ! |
section dtors 0 4 0 1 0 1 0 1 devtab devtab ! |
section devtab 0 4 0 1 0 1 0 1 got got ! |
section got 0 4 0 1 0 1 0 1 dynamic dynamic ! |
section dynamic 0 4 0 1 0 1 0 1 sdata sdata ! |
section sdata 0 4 0 1 0 1 0 1 lit8 lit8 ! |
section lit8 0 8 0 1 0 1 0 1 lit4 lit4 ! |
section lit4 0 8 0 1 0 1 0 1 sbss sbss ! |
section sbss 0 8 0 1 0 1 0 1 bss bss ! |
section bss 0 8 0 1 0 1 0 1 heap1 heap1 ! |
section heap1 0 8 0 0 0 0 0 0 ! |
/v2_0/include/pkgconf/mlt_mips_atlas_rom.h
0,0 → 1,20
// eCos memory layout - Fri Oct 20 06:10:29 2000 |
|
// This is a generated file - do not edit |
|
#ifndef __ASSEMBLER__ |
#include <cyg/infra/cyg_type.h> |
#include <stddef.h> |
|
#endif |
#define CYGMEM_REGION_ram (0x80000400) |
#define CYGMEM_REGION_ram_SIZE (0xfffc00) |
#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) |
#define CYGMEM_REGION_rom (0x9fc00000) |
#define CYGMEM_REGION_rom_SIZE (0x80000) |
#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R) |
#ifndef __ASSEMBLER__ |
extern char CYG_LABEL_NAME (__heap1) []; |
#endif |
#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) |
#define CYGMEM_SECTION_heap1_SIZE (0x81000000 - (size_t) CYG_LABEL_NAME (__heap1)) |
/v2_0/include/pkgconf/mlt_mips_atlas_rom.ldi
0,0 → 1,40
// eCos memory layout - Fri Oct 20 06:10:29 2000 |
|
// This is a generated file - do not edit |
|
#include <cyg/infra/cyg_type.inc> |
|
MEMORY |
{ |
ram : ORIGIN = 0x80000400, LENGTH = 0xfffc00 |
rom : ORIGIN = 0x9fc00000, LENGTH = 0x80000 |
} |
|
SECTIONS |
{ |
SECTIONS_BEGIN |
SECTION_rom_vectors (rom, 0x9fc00000, LMA_EQ_VMA) |
SECTION_ROMISC (rom, ALIGN (0x40), LMA_EQ_VMA) |
SECTION_RELOCS (rom, ALIGN (0x40), LMA_EQ_VMA) |
SECTION_init (rom, ALIGN (0x40), LMA_EQ_VMA) |
SECTION_text (rom, ALIGN (0x40), LMA_EQ_VMA) |
SECTION_fini (rom, ALIGN (0x40), LMA_EQ_VMA) |
SECTION_rodata (rom, ALIGN (0x40), LMA_EQ_VMA) |
SECTION_rodata1 (rom, ALIGN (0x40), LMA_EQ_VMA) |
SECTION_data (ram, 0x80000400, FOLLOWING (.rodata1)) |
SECTION_data1 (ram, ALIGN (0x40), FOLLOWING (.data)) |
SECTION_eh_frame (ram, ALIGN (0x40), FOLLOWING (.data1)) |
SECTION_gcc_except_table (ram, ALIGN (0x40), FOLLOWING (.eh_frame)) |
SECTION_ctors (ram, ALIGN (0x40), FOLLOWING (.gcc_except_table)) |
SECTION_dtors (ram, ALIGN (0x40), FOLLOWING (.ctors)) |
SECTION_devtab (ram, ALIGN (0x40), FOLLOWING (.dtors)) |
SECTION_got (ram, ALIGN (0x40), FOLLOWING (.devtab)) |
SECTION_dynamic (ram, ALIGN (0x40), FOLLOWING (.got)) |
SECTION_sdata (ram, ALIGN (0x40), FOLLOWING (.dynamic)) |
SECTION_lit8 (ram, ALIGN (0x40), FOLLOWING (.sdata)) |
SECTION_lit4 (ram, ALIGN (0x40), FOLLOWING (.lit8)) |
SECTION_sbss (ram, ALIGN (0x40), LMA_EQ_VMA) |
SECTION_bss (ram, ALIGN (0x40), LMA_EQ_VMA) |
CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); |
SECTIONS_END |
} |
/v2_0/include/pkgconf/mlt_mips_atlas_ram.h
0,0 → 1,17
// eCos memory layout - Fri Oct 20 06:11:28 2000 |
|
// This is a generated file - do not edit |
|
#ifndef __ASSEMBLER__ |
#include <cyg/infra/cyg_type.h> |
#include <stddef.h> |
|
#endif |
#define CYGMEM_REGION_ram (0x80020000) |
#define CYGMEM_REGION_ram_SIZE (0xfe0000) |
#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) |
#ifndef __ASSEMBLER__ |
extern char CYG_LABEL_NAME (__heap1) []; |
#endif |
#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) |
#define CYGMEM_SECTION_heap1_SIZE (0x81000000 - (size_t) CYG_LABEL_NAME (__heap1)) |
/v2_0/include/pkgconf/mlt_mips_atlas_ram.ldi
0,0 → 1,39
// eCos memory layout - Fri Oct 20 06:11:28 2000 |
|
// This is a generated file - do not edit |
|
#include <cyg/infra/cyg_type.inc> |
|
MEMORY |
{ |
ram : ORIGIN = 0x80020000, LENGTH = 0xfe0000 |
} |
|
SECTIONS |
{ |
SECTIONS_BEGIN |
SECTION_rom_vectors (ram, 0x80020000, LMA_EQ_VMA) |
SECTION_ROMISC (ram, ALIGN (0x4), LMA_EQ_VMA) |
SECTION_RELOCS (ram, ALIGN (0x4), LMA_EQ_VMA) |
SECTION_init (ram, ALIGN (0x4), LMA_EQ_VMA) |
SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA) |
SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA) |
SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA) |
SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA) |
SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA) |
SECTION_data1 (ram, ALIGN (0x8), LMA_EQ_VMA) |
SECTION_eh_frame (ram, ALIGN (0x4), LMA_EQ_VMA) |
SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA) |
SECTION_ctors (ram, ALIGN (0x4), LMA_EQ_VMA) |
SECTION_dtors (ram, ALIGN (0x4), LMA_EQ_VMA) |
SECTION_devtab (ram, ALIGN (0x4), LMA_EQ_VMA) |
SECTION_got (ram, ALIGN (0x4), LMA_EQ_VMA) |
SECTION_dynamic (ram, ALIGN (0x4), LMA_EQ_VMA) |
SECTION_sdata (ram, ALIGN (0x4), LMA_EQ_VMA) |
SECTION_lit8 (ram, ALIGN (0x8), LMA_EQ_VMA) |
SECTION_lit4 (ram, ALIGN (0x8), LMA_EQ_VMA) |
SECTION_sbss (ram, ALIGN (0x8), LMA_EQ_VMA) |
SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA) |
CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); |
SECTIONS_END |
} |
/v2_0/include/plf_cache.h
0,0 → 1,73
#ifndef CYGONCE_PLF_CACHE_H |
#define CYGONCE_PLF_CACHE_H |
|
//============================================================================= |
// |
// plf_cache.h |
// |
// HAL cache control API |
// |
//============================================================================= |
//####ECOSGPLCOPYRIGHTBEGIN#### |
// ------------------------------------------- |
// This file is part of eCos, the Embedded Configurable Operating System. |
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
// |
// eCos is free software; you can redistribute it and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
// Software Foundation; either version 2 or (at your option) any later version. |
// |
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
// WARRANTY; without even the implied warranty of MERCHANTABILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with eCos; if not, write to the Free Software Foundation, Inc., |
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
// |
// As a special exception, if other files instantiate templates or use macros |
// or inline functions from this file, or you compile this file and link it |
// with other works to produce a work based on this file, this file does not |
// by itself cause the resulting work to be covered by the GNU General Public |
// License. However the source code for this file must still be made available |
// in accordance with section (3) of the GNU General Public License. |
// |
// This exception does not invalidate any other reasons why a work based on |
// this file might be covered by the GNU General Public License. |
// |
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
// at http://sources.redhat.com/ecos/ecos-license/ |
// ------------------------------------------- |
//####ECOSGPLCOPYRIGHTEND#### |
//============================================================================= |
//#####DESCRIPTIONBEGIN#### |
// |
// Author(s): nickg |
// Contributors: nickg |
// Date: 1998-02-17 |
// Purpose: Cache control API |
// Description: The macros defined here provide the HAL APIs for handling |
// cache control operations. |
// Usage: |
// #include <cyg/hal/plf_cache.h> |
// ... |
// |
// |
//####DESCRIPTIONEND#### |
// |
//============================================================================= |
|
#include <pkgconf/hal.h> |
#include <cyg/infra/cyg_type.h> |
|
#include <cyg/hal/plf_cache.h> |
|
//============================================================================= |
|
// Nothing here at present. |
|
//----------------------------------------------------------------------------- |
#endif // ifndef CYGONCE_PLF_CACHE_H |
// End of plf_cache.h |
|
/v2_0/include/platform.inc
0,0 → 1,312
#ifndef CYGONCE_HAL_PLATFORM_INC |
#define CYGONCE_HAL_PLATFORM_INC |
##============================================================================= |
## |
## platform.inc |
## |
## Atlas board assembler header file |
## |
##============================================================================= |
#####ECOSGPLCOPYRIGHTBEGIN#### |
## ------------------------------------------- |
## This file is part of eCos, the Embedded Configurable Operating System. |
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
## |
## eCos is free software; you can redistribute it and/or modify it under |
## the terms of the GNU General Public License as published by the Free |
## Software Foundation; either version 2 or (at your option) any later version. |
## |
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
## WARRANTY; without even the implied warranty of MERCHANTABILITY or |
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
## for more details. |
## |
## You should have received a copy of the GNU General Public License along |
## with eCos; if not, write to the Free Software Foundation, Inc., |
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
## |
## As a special exception, if other files instantiate templates or use macros |
## or inline functions from this file, or you compile this file and link it |
## with other works to produce a work based on this file, this file does not |
## by itself cause the resulting work to be covered by the GNU General Public |
## License. However the source code for this file must still be made available |
## in accordance with section (3) of the GNU General Public License. |
## |
## This exception does not invalidate any other reasons why a work based on |
## this file might be covered by the GNU General Public License. |
## |
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
## at http://sources.redhat.com/ecos/ecos-license/ |
## ------------------------------------------- |
#####ECOSGPLCOPYRIGHTEND#### |
##============================================================================= |
#######DESCRIPTIONBEGIN#### |
## |
## Author(s): dmoseley |
## Contributors: dmoseley |
## Date: 2000-06-06 |
## Purpose: Atlas board definitions. |
## Description: This file contains various definitions and macros that are |
## useful for writing assembly code for the Atlas board. |
## Usage: |
## #include <cyg/hal/platform.inc> |
## ... |
## |
## |
######DESCRIPTIONEND#### |
## |
##============================================================================= |
|
#include <cyg/hal/mips.inc> |
|
#include <cyg/hal/hal_arch.h> |
#include <cyg/hal/plf_io.h> |
|
#------------------------------------------------------------------------------ |
# Additional bits for status register. |
# We set the IM[0] bit to accept all interrupts. |
|
#define INITIAL_SR_PLF 0x00000400 |
|
#------------------------------------------------------------------------------ |
|
#define CYGPKG_HAL_RESET_VECTOR_FIRST_CODE |
.macro hal_reset_vector_first_code |
# Branch forward past the board ID register. |
b 1f |
nop |
nop |
nop |
nop |
nop |
1: |
.endm |
|
#define CYGPKG_HAL_EARLY_INIT |
.macro hal_early_init |
# Do these initializations early (rather than in hal_memc_init) so |
# we have access to the LEDs on the board for debugging purposes. |
|
# |
# WARNING: THESE WRITES NEED TO HANDLE BYTE-SWAPPING PROPERLY WHEN DOING BIG-ENDIAN |
# |
|
# |
# Setup Galileo CPU Interface Register |
# |
# Set the WriteRate bit - ie Accept 'DDD' back-to-back transfers (see CoreLV "Users Manual") |
# All other bits stay the same |
# |
li k0, CYGARC_UNCACHED_ADDRESS(HAL_GALILEO_REGISTER_BASE) |
lw k1, HAL_GALILEO_CPU_INTERFACE_CONFIG_OFFSET(k0) |
li k0, HAL_GALILEO_CPU_WRITERATE_MASK |
or k1, k1, k0 |
li k0, CYGARC_UNCACHED_ADDRESS(HAL_GALILEO_REGISTER_BASE) |
sw k1, HAL_GALILEO_CPU_INTERFACE_CONFIG_OFFSET(k0) |
|
# |
# Use BootCS chip-select for the entire device bus region |
# |
li k1, 0 |
sw k1, HAL_GALILEO_CS3_HIGH_DECODE_OFFSET(k0) |
li k1, 0xf0 |
sw k1, HAL_GALILEO_CSBOOT_LOW_DECODE_OFFSET(k0) |
li k1, 0xff |
sw k1, HAL_GALILEO_CSBOOT_HIGH_DECODE_OFFSET(k0) |
.endm |
|
#------------------------------------------------------------------------------ |
# Interrupt decode macros |
|
# Only INTN[0] is connected on the Atlas board. We need to access the |
# interrupt controller to get the actual vector number. |
|
#ifndef CYGPKG_HAL_MIPS_INTC_INIT_DEFINED |
|
.macro hal_intc_init |
mfc0 v0,status |
nop |
lui v1,0xFFFF |
ori v1,v1,0x04FF |
and v0,v0,v1 # Clear the IntMask bits except IM[0] |
mtc0 v0,status |
nop |
nop |
nop |
.endm |
|
#define CYGPKG_HAL_MIPS_INTC_INIT_DEFINED |
|
#endif |
|
|
#ifndef CYGPKG_HAL_MIPS_INTC_DECODE_DEFINED |
.macro hal_intc_decode vnum |
|
mfc0 v1,status # get status register (interrupt mask) |
mfc0 v0,cause # get cause register |
and v0,v0,v1 # apply interrupt mask |
andi v1,v0,0x400 # test FPGA interrupt |
bnez v1,0f |
srl v0,v0,10 # shift interrupt bits down |
andi v0,v0,0x3f # isolate 6 interrupt bits |
la v1,hal_intc_translation_table |
add v0,v0,v1 # index into table |
b 1f |
lb \vnum,0(v0) # pick up vector number |
0: |
lw v0,HAL_ATLAS_INTSTATUS # Get interrupt status reg |
clz v1,v0 # count leading zeros into v1 |
la v0,31 # v0 = 31 |
sub \vnum,v0,v1 # vnum = 31-v1 == vector number |
1: |
.endm |
|
#ifndef CYGPKG_HAL_MIPS_INTC_TRANSLATE_DEFINED |
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN |
.macro hal_intc_translate inum,vnum |
move \vnum,zero # Just vector zero is supported |
.endm |
#else |
.macro hal_intc_translate inum,vnum |
move \vnum,\inum # Vector == interrupt number |
.endm |
#endif |
#endif |
|
.macro hal_intc_decode_data |
hal_intc_translation_table: |
.byte 20, 20, 20, 20 |
.byte 21, 21, 21, 21 |
.byte 22, 22, 22, 22 |
.byte 22, 22, 22, 22 |
.byte 23, 23, 23, 23 |
.byte 23, 23, 23, 23 |
.byte 23, 23, 23, 23 |
.byte 23, 23, 23, 23 |
.byte 24, 24, 24, 24 |
.byte 24, 24, 24, 24 |
.byte 24, 24, 24, 24 |
.byte 24, 24, 24, 24 |
.byte 24, 24, 24, 24 |
.byte 24, 24, 24, 24 |
.byte 24, 24, 24, 24 |
.byte 24, 24, 24, 24 |
.endm |
|
#define CYGPKG_HAL_MIPS_INTC_DECODE_DEFINED |
#define CYGPKG_HAL_MIPS_INTC_DEFINED |
|
// We also define our own interrupt tables in platform.S... |
#define CYG_HAL_MIPS_ISR_TABLES_DEFINED |
|
#endif |
|
#------------------------------------------------------------------------------ |
# Diagnostic macros |
|
#ifndef CYGPKG_HAL_MIPS_DIAG_DEFINED |
|
.macro hal_diag_init |
.endm |
|
.macro hal_diag_excpt_start |
.endm |
|
.macro hal_diag_intr_start |
.endm |
|
.macro hal_diag_restore |
.endm |
|
#define CYGPKG_HAL_MIPS_DIAG_DEFINED |
|
#endif // ifndef CYGPKG_HAL_MIPS_DIAG_DEFINED |
|
#------------------------------------------------------------------------------ |
# MEMC macros. |
# |
|
#if defined(CYG_HAL_STARTUP_ROM) |
|
#------------------------------------------------------------------------------ |
# Make sure the jump to _start in vectors.S is done uncached |
# |
|
#define CYGARC_START_FUNC_UNCACHED |
|
.macro hal_memc_init |
.extern hal_atlas_init_sdram |
|
lar k0,hal_atlas_init_sdram |
CYGARC_ADDRESS_REG_UNCACHED(k0) |
jalr k0 |
nop |
|
beqz v0, 2f |
nop |
|
# Error in sizing memory |
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS0, 'M') |
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS1, 'E') |
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS2, 'M') |
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS3, 'E') |
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS4, 'R') |
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS5, 'R') |
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS6, 'O') |
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS7, 'R') |
1: b 1b |
nop |
|
2: # No error in sizing memory |
|
# Store the memory size at the base of RAM for later |
la k0, 0x80000000 |
move k1, k0 |
CYGARC_ADDRESS_REG_UNCACHED(k1) |
sw v1, 0(k1) |
nop |
nop |
nop |
.endm |
|
#define CYGPKG_HAL_MIPS_MEMC_DEFINED |
|
#elif defined(CYG_HAL_STARTUP_ROMRAM) |
#error ROMRAM STARTUP NOT YET IMPLEMENTED |
.macro hal_memc_init |
.extern hal_memc_setup |
|
lar k0,hal_memc_setup |
jalr k0 |
nop |
|
# Having got the RAM working, we must now relocate the Entire |
# ROM into it and then continue execution from RAM. |
|
la t0,0x88000000 # dest addr |
la t1,0x80000000 # source addr |
la t3,__ram_data_end # end dest addr |
1: |
lw v0,0(t1) # get word |
addi t1,t1,4 |
sw v0,0(t0) # write word |
addi t0,t0,4 |
bne t0,t3,1b |
nop |
|
la v0,2f # RAM address to go to |
jr v0 |
nop |
2: |
# We are now executing out of RAM! |
|
.endm |
|
#define CYGPKG_HAL_MIPS_MEMC_DEFINED |
|
#endif |
|
#------------------------------------------------------------------------------ |
#endif // ifndef CYGONCE_HAL_PLATFORM_INC |
# end of platform.inc |
/v2_0/include/plf_io.h
0,0 → 1,472
#ifndef CYGONCE_PLF_IO_H |
#define CYGONCE_PLF_IO_H |
|
//============================================================================= |
// |
// plf_io.h |
// |
// Platform specific IO support |
// |
//============================================================================= |
//####ECOSGPLCOPYRIGHTBEGIN#### |
// ------------------------------------------- |
// This file is part of eCos, the Embedded Configurable Operating System. |
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
// |
// eCos is free software; you can redistribute it and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
// Software Foundation; either version 2 or (at your option) any later version. |
// |
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
// WARRANTY; without even the implied warranty of MERCHANTABILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with eCos; if not, write to the Free Software Foundation, Inc., |
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
// |
// As a special exception, if other files instantiate templates or use macros |
// or inline functions from this file, or you compile this file and link it |
// with other works to produce a work based on this file, this file does not |
// by itself cause the resulting work to be covered by the GNU General Public |
// License. However the source code for this file must still be made available |
// in accordance with section (3) of the GNU General Public License. |
// |
// This exception does not invalidate any other reasons why a work based on |
// this file might be covered by the GNU General Public License. |
// |
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
// at http://sources.redhat.com/ecos/ecos-license/ |
// ------------------------------------------- |
//####ECOSGPLCOPYRIGHTEND#### |
//============================================================================= |
//#####DESCRIPTIONBEGIN#### |
// |
// Author(s): dmoseley |
// Contributors: dmoseley |
// Date: 2000-06-06 |
// Purpose: Atlas platform IO support |
// Description: |
// Usage: #include <cyg/hal/plf_io.h> |
// |
//####DESCRIPTIONEND#### |
// |
//============================================================================= |
|
#include <pkgconf/hal.h> |
#include <cyg/hal/hal_misc.h> |
|
#ifdef __ASSEMBLER__ |
#define HAL_REG(x) x |
#else |
#define HAL_REG(x) (volatile CYG_WORD *)(x) |
#endif |
|
//----------------------------------------------------------------------------- |
|
/* Atlas Memory Definitions */ |
#define HAL_ATLAS_RAM_BASE 0x00000000 |
#define HAL_ATLAS_PCI_MEM0_BASE 0x08000000 |
#define HAL_ATLAS_PCI_MEM0_SIZE 0x08000000 // 128 MB |
#define HAL_ATLAS_PCI_MEM1_BASE 0x10000000 |
#define HAL_ATLAS_PCI_MEM1_SIZE 0x08000000 // 128 MB |
#define HAL_ATLAS_PCI_IO_BASE 0x18000000 |
#define HAL_ATLAS_PCI_IO_SIZE 0x03E00000 // 62 MB |
#define HAL_ATLAS_CONTROLLER_BASE 0x1BE00000 |
#define HAL_ATLAS_CONTROLLER_BASE_ISD_CONFIG (HAL_ATLAS_CONTROLLER_BASE >> 21) |
#define HAL_ATLAS_FLASH_BASE 0x1C000000 |
#define HAL_ATLAS_FLASH_SIZE SZ_32M |
#define HAL_ATLAS_MAX_BANKSIZE SZ_512M |
|
#define HAL_ATLAS_NULL_DEVNUM 0x0 |
#define HAL_ATLAS_SAA9730_DEVNUM 0x9800 |
#define HAL_ATLAS_MEMERROR 1 |
|
/* Atlas Registers */ |
#define HAL_ATLAS_REGISTER_BASE 0xBF000000 |
|
#define HAL_ATLAS_INTBASE HAL_ATLAS_REGISTER_BASE |
|
#define HAL_ATLAS_INTRAW_OFFSET 0x00000000 |
#define HAL_ATLAS_INTSETEN_OFFSET 0x00000008 |
#define HAL_ATLAS_INTRSTEN_OFFSET 0x00000010 |
#define HAL_ATLAS_INTENABLE_OFFSET 0x00000018 |
#define HAL_ATLAS_INTSTATUS_OFFSET 0x00000020 |
|
#define HAL_ATLAS_INTRAW HAL_REG(HAL_ATLAS_INTBASE + HAL_ATLAS_INTRAW_OFFSET) |
#define HAL_ATLAS_INTSETEN HAL_REG(HAL_ATLAS_INTBASE + HAL_ATLAS_INTSETEN_OFFSET) |
#define HAL_ATLAS_INTRSTEN HAL_REG(HAL_ATLAS_INTBASE + HAL_ATLAS_INTRSTEN_OFFSET) |
#define HAL_ATLAS_INTENABLE HAL_REG(HAL_ATLAS_INTBASE + HAL_ATLAS_INTENABLE_OFFSET) |
#define HAL_ATLAS_INTSTATUS HAL_REG(HAL_ATLAS_INTBASE + HAL_ATLAS_INTSTATUS_OFFSET) |
|
|
#define HAL_ATLAS_NMISTATUS_OFFSET 0x00000024 |
#define HAL_ATLAS_NMIACK_OFFSET 0x00000104 |
#define HAL_ATLAS_SOFTRES_OFFSET 0x00000500 |
#define HAL_ATLAS_BRKRES_OFFSET 0x00000508 |
#define HAL_ATLAS_REVISION_OFFSET 0x00C00010 |
|
#define HAL_ATLAS_NMISTATUS HAL_REG(HAL_ATLAS_REGISTER_BASE + HAL_ATLAS_NMISTATUS_OFFSET) |
#define HAL_ATLAS_NMIACK HAL_REG(HAL_ATLAS_REGISTER_BASE + HAL_ATLAS_NMIACK_OFFSET) |
#define HAL_ATLAS_SOFTRES HAL_REG(HAL_ATLAS_REGISTER_BASE + HAL_ATLAS_SOFTRES_OFFSET) |
#define HAL_ATLAS_BRKRES HAL_REG(HAL_ATLAS_REGISTER_BASE + HAL_ATLAS_BRKRES_OFFSET) |
#define HAL_ATLAS_REVISION HAL_REG(HAL_ATLAS_REGISTER_BASE + HAL_ATLAS_REVISION_OFFSET) |
|
/* Atlas NMI controller fields */ |
#define HAL_ATLAS_NMISTATUS_FLAG 0x00000001 |
#define HAL_ATLAS_NMIACK_FLAG 0x00000001 |
|
/* Atlas softreset fields */ |
#define HAL_ATLAS_GORESET 0x42 |
|
/* Atlas brkreset fields */ |
#define HAL_ATLAS_BRKRES_DEFAULT_VALUE 0xA |
|
/* Galileo Registers */ |
#define HAL_GALILEO_REGISTER_BASE 0xB4000000 |
#define HAL_GALILEO_PCI0_MEM0_BASE 0xB2000000 |
|
#define HAL_GALILEO_CPU_INTERFACE_CONFIG_OFFSET 0x0 |
#define HAL_GALILEO_INT_SPACE_DECODE_OFFSET 0x68 |
#define HAL_GALILEO_CS3_HIGH_DECODE_OFFSET 0x43c |
#define HAL_GALILEO_CSBOOT_LOW_DECODE_OFFSET 0x440 |
#define HAL_GALILEO_CSBOOT_HIGH_DECODE_OFFSET 0x444 |
|
/* Galileo CPU Interface config fields */ |
#define HAL_GALILEO_BYTE_SWAP (BIT16 | BIT0) |
|
#define HAL_GALILEO_CACHEOPMAP_MASK 0x000001FF |
#define HAL_GALILEO_CACHEPRES_MASK 0x00000200 |
#define HAL_GALILEO_WRITEMODE_MASK 0x00000800 |
#define HAL_GALILEO_ENDIAN_MASK 0x00001000 |
#define HAL_GALILEO_R5KL2_MASK 0x00004000 |
#define HAL_GALILEO_EXT_HIT_DELAY_MASK 0x00008000 |
#define HAL_GALILEO_CPU_WRITERATE_MASK 0x00010000 |
#define HAL_GALILEO_STOP_RETRY_MASK 0x00020000 |
#define HAL_GALILEO_MULTI_GT_MASK 0x00040000 |
#define HAL_GALILEO_SYSADCVALID_MASK 0x00080000 |
|
/* Galileo Memory Controller registers */ |
#define HAL_GALILEO_SDRAM_DUPLICATE_BANK_ADDR BIT20 |
#define HAL_GALILEO_SDRAM_BANK_INTERLEAVE_DIS BIT14 |
#define HAL_GALILEO_CPU_DECODE_SHIFT 21 |
#define HAL_GALILEO_DEV_DECODE_SHIFT 20 |
#define HAL_GALILEO_SDRAM_SRAS_TO_SCAS_DELAY_3C BIT10 |
#define HAL_GALILEO_SDRAM_WIDTH_64BIT BIT6 |
#define HAL_GALILEO_SDRAM_SRAS_PRECHARGE_3C BIT3 |
#define HAL_GALILEO_SDRAM_BANK0_CASLAT_2 BIT0 |
#define HAL_GALILEO_SDRAM_BANK0_SZ_64M BIT11 |
#define HAL_GALILEO_SDRAM_NUM_BANKS_4 BIT5 |
#define HAL_GALILEO_SDRAM_BANK0_PARITY BIT8 |
#define HAL_GALILEO_SDRAM_CFG_RAM_WIDTH BIT15 |
#define HAL_GALILEO_PCI0_CONFIG_ADDR_ConfigEn BIT31 |
#define HAL_GALILEO_PCI0_STATUS_COMMAND_REGNUM 0x04 |
#define HAL_GALILEO_PCI0_BIST_REGNUM 0x0C |
#define HAL_GALILEO_PCI0_SCS32_BASE_REGNUM 0x14 |
#define HAL_GALILEO_PCI0_CONFIG_MEMEn 0x2 |
#define HAL_GALILEO_PCI0_CONFIG_MasEn 0x4 |
#define HAL_GALILEO_PCI0_CONFIG_SErrEn 0x100 |
#define HAL_GALILEO_PCI0_LAT_TIMER_VAL 0x800 |
#define HAL_GALILEO_PCI0_TIMEOUT_RETRY_VALUE 0x00ffffff |
|
#define HAL_GALILEO_SDRAM_BANK0_OFFSET 0x44c |
#define HAL_GALILEO_SDRAM_BANK2_OFFSET 0x454 |
#define HAL_GALILEO_SDRAM_CONFIG_OFFSET 0x448 |
|
#define HAL_GALILEO_SCS10_LD_OFFSET 0x008 |
#define HAL_GALILEO_SCS10_HD_OFFSET 0x010 |
#define HAL_GALILEO_SCS32_LD_OFFSET 0x018 |
#define HAL_GALILEO_SCS32_HD_OFFSET 0x020 |
#define HAL_GALILEO_CS20_LD_OFFSET 0x028 |
#define HAL_GALILEO_CS20_HD_OFFSET 0x030 |
#define HAL_GALILEO_PCIIO_LD_OFFSET 0x048 |
#define HAL_GALILEO_PCIIO_HD_OFFSET 0x050 |
#define HAL_GALILEO_PCIMEM0_LD_OFFSET 0x058 |
#define HAL_GALILEO_PCIMEM0_HD_OFFSET 0x060 |
#define HAL_GALILEO_PCIMEM1_LD_OFFSET 0x080 |
#define HAL_GALILEO_PCIMEM1_HD_OFFSET 0x088 |
#define HAL_GALILEO_PCI1IO_LD_OFFSET 0x090 |
#define HAL_GALILEO_PCI1IO_HD_OFFSET 0x098 |
#define HAL_GALILEO_PCI1MEM0_LD_OFFSET 0x0a0 |
#define HAL_GALILEO_PCI1MEM0_HD_OFFSET 0x0a8 |
#define HAL_GALILEO_PCI1MEM1_LD_OFFSET 0x0b0 |
#define HAL_GALILEO_PCI1MEM1_HD_OFFSET 0x0b8 |
#define HAL_GALILEO_SCS0_LD_OFFSET 0x400 |
#define HAL_GALILEO_SCS0_HD_OFFSET 0x404 |
#define HAL_GALILEO_SCS1_LD_OFFSET 0x408 |
#define HAL_GALILEO_SCS1_HD_OFFSET 0x40c |
#define HAL_GALILEO_SCS2_LD_OFFSET 0x410 |
#define HAL_GALILEO_SCS2_HD_OFFSET 0x414 |
#define HAL_GALILEO_SCS3_LD_OFFSET 0x418 |
#define HAL_GALILEO_SCS3_HD_OFFSET 0x41c |
#define HAL_GALILEO_CS0_LD_OFFSET 0x420 |
#define HAL_GALILEO_CS0_HD_OFFSET 0x424 |
#define HAL_GALILEO_CS1_LD_OFFSET 0x428 |
#define HAL_GALILEO_CS1_HD_OFFSET 0x42c |
#define HAL_GALILEO_CS2_LD_OFFSET 0x430 |
#define HAL_GALILEO_CS2_HD_OFFSET 0x434 |
|
// GALILEO PCI Internal |
#define HAL_GALILEO_PCI_INTERNAL_COMMAND_OFFSET 0xC00 |
#define HAL_GALILEO_PCI0_TIMEOUT_RETRY_OFFSET 0xc04 |
#define HAL_GALILEO_PCI0_SCS10_SIZE_OFFSET 0xc08 |
#define HAL_GALILEO_PCI0_SCS32_SIZE_OFFSET 0xc0c |
#define HAL_GALILEO_PCI0_SCS20_SIZE_OFFSET 0xc10 |
#define HAL_GALILEO_PCI0_CS3_SIZE_OFFSET 0xc14 |
#define HAL_GALILEO_BAR_ENA_OFFSET 0xc3c |
# define HAL_GALILEO_BAR_ENA_SWCS3 (1 << 0) |
# define HAL_GALILEO_BAR_ENA_SWCS32 (1 << 1) |
# define HAL_GALILEO_BAR_ENA_SWCS10 (1 << 2) |
# define HAL_GALILEO_BAR_ENA_IO (1 << 3) |
# define HAL_GALILEO_BAR_ENA_MEM (1 << 4) |
# define HAL_GALILEO_BAR_ENA_CS3 (1 << 5) |
# define HAL_GALILEO_BAR_ENA_CS20 (1 << 6) |
# define HAL_GALILEO_BAR_ENA_SCS32 (1 << 7) |
# define HAL_GALILEO_BAR_ENA_SCS10 (1 << 8) |
#define HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET 0xcf8 |
# define HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE (1 << 31) |
#define HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET 0xcfc |
|
// GALILEO Interrupts |
#define HAL_GALILEO_IRQ_CAUSE_OFFSET 0xc18 |
# define HAL_GALILEO_IRQCAUSE_INTSUM (1 << 0) |
# define HAL_GALILEO_IRQCAUSE_MEMOUT (1 << 1) |
# define HAL_GALILEO_IRQCAUSE_DMAOUT (1 << 2) |
# define HAL_GALILEO_IRQCAUSE_CPUOUT (1 << 3) |
# define HAL_GALILEO_IRQCAUSE_DMA0 (1 << 4) |
# define HAL_GALILEO_IRQCAUSE_DMA1 (1 << 5) |
# define HAL_GALILEO_IRQCAUSE_DMA2 (1 << 6) |
# define HAL_GALILEO_IRQCAUSE_DMA3 (1 << 7) |
# define HAL_GALILEO_IRQCAUSE_T0 (1 << 8) |
# define HAL_GALILEO_IRQCAUSE_T1 (1 << 9) |
# define HAL_GALILEO_IRQCAUSE_T2 (1 << 10) |
# define HAL_GALILEO_IRQCAUSE_T3 (1 << 11) |
# define HAL_GALILEO_IRQCAUSE_MASRD (1 << 12) |
# define HAL_GALILEO_IRQCAUSE_SLVWR (1 << 13) |
# define HAL_GALILEO_IRQCAUSE_MASWR (1 << 14) |
# define HAL_GALILEO_IRQCAUSE_SLVRD (1 << 15) |
# define HAL_GALILEO_IRQCAUSE_AERR (1 << 16) |
# define HAL_GALILEO_IRQCAUSE_MERR (1 << 17) |
# define HAL_GALILEO_IRQCAUSE_MASABT (1 << 18) |
# define HAL_GALILEO_IRQCAUSE_TARABT (1 << 19) |
# define HAL_GALILEO_IRQCAUSE_RETRY (1 << 20) |
# define HAL_GALILEO_IRQCAUSE_CPUSUM (1 << 30) |
# define HAL_GALILEO_IRQCAUSE_PCISUM (1 << 31) |
#define HAL_GALILEO_HIRQ_CAUSE_OFFSET 0xc98 |
#define HAL_GALILEO_CPUIRQ_MASK_OFFSET 0xc1c |
#define HAL_GALILEO_CPUHIRQ_MASK_OFFSET 0xc9c |
|
#define HAL_SAA9730_I2CSC_I2CCC_6400 0x500 |
#define HAL_SAA9730_I2CTFR_ATTR0_START 0xC |
#define HAL_SAA9730_I2CTFR_ATTR2_START 0xC0 |
#define HAL_SAA9730_I2CTFR_ATTR2_STOP 0x40 |
#define HAL_SAA9730_I2CTFR_ATTR1_CONT 0x20 |
#define HAL_SAA9730_I2CTFR_OFFSET 0x2400 |
#define HAL_SAA9730_I2CSC_OFFSET 0x2404 |
#define HAL_SAA9730_SYSRESET_OFFSET 0x4020 |
#define HAL_SAA9730_SYSRESET_ALL 0xdeae |
|
#define HAL_SPD_GET_NUM_ROW_BITS 3 |
#define HAL_SPD_GET_NUM_COL_BITS 4 |
#define HAL_SPD_GET_NUM_MODULE_BANKS 5 |
#define HAL_SPD_GET_CONFIG_TYPE 11 |
#define HAL_SPD_GET_REFRESH_RATE 12 |
#define HAL_SPD_GET_SDRAM_WIDTH 13 |
#define HAL_SPD_GET_ERROR_CHECK_WIDTH 14 |
#define HAL_SPD_GET_BURST_LENGTH 16 |
#define HAL_SPD_GET_NUM_DEVICE_BANKS 17 |
#define HAL_SPD_GET_CAS_LAT 18 |
#define HAL_SPD_GET_ROW_DENSITY 31 |
#define HAL_SPD_CONFIG_TYPE_PARITY BIT0 |
#define HAL_SPD_CONFIG_TYPE_ECC BIT1 |
#define HAL_SPD_REFRESH_RATE_125 5 |
#define HAL_SPD_REFRESH_RATE_62_5 4 |
#define HAL_SPD_REFRESH_RATE_31_3 3 |
#define HAL_SPD_REFRESH_RATE_15_625 0 |
#define HAL_SPD_REFRESH_RATE_7_8 2 |
#define HAL_SPD_REFRESH_RATE_3_9 1 |
|
#define HAL_SPD_REFRESH_COUNTER_125 (125*2) |
#define HAL_SPD_REFRESH_COUNTER_62_5 (62*2) |
#define HAL_SPD_REFRESH_COUNTER_31_3 (31*2) |
#define HAL_SPD_REFRESH_COUNTER_15_625 (15*2) |
#define HAL_SPD_REFRESH_COUNTER_7_8 (7*2) |
#define HAL_SPD_REFRESH_COUNTER_3_9 (3*2) |
|
/* Atlas Display Registers */ |
#define HAL_DISPLAY_BASE (HAL_ATLAS_REGISTER_BASE + 0x400) |
|
#define HAL_DISPLAY_LEDGREEN_OFFSET 0x00 |
#define HAL_DISPLAY_LEDBAR_OFFSET 0x08 |
#define HAL_DISPLAY_ASCIIWORD_OFFSET 0x10 |
#define HAL_DISPLAY_ASCIIPOS0_OFFSET 0x18 |
#define HAL_DISPLAY_ASCIIPOS1_OFFSET 0x20 |
#define HAL_DISPLAY_ASCIIPOS2_OFFSET 0x28 |
#define HAL_DISPLAY_ASCIIPOS3_OFFSET 0x30 |
#define HAL_DISPLAY_ASCIIPOS4_OFFSET 0x38 |
#define HAL_DISPLAY_ASCIIPOS5_OFFSET 0x40 |
#define HAL_DISPLAY_ASCIIPOS6_OFFSET 0x48 |
#define HAL_DISPLAY_ASCIIPOS7_OFFSET 0x50 |
|
#define HAL_DISPLAY_LEDGREEN HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_LEDGREEN_OFFSET) |
#define HAL_DISPLAY_LEDBAR HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_LEDBAR_OFFSET) |
#define HAL_DISPLAY_ASCIIWORD HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIWORD_OFFSET) |
#define HAL_DISPLAY_ASCIIPOS0 HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIPOS0_OFFSET) |
#define HAL_DISPLAY_ASCIIPOS1 HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIPOS1_OFFSET) |
#define HAL_DISPLAY_ASCIIPOS2 HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIPOS2_OFFSET) |
#define HAL_DISPLAY_ASCIIPOS3 HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIPOS3_OFFSET) |
#define HAL_DISPLAY_ASCIIPOS4 HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIPOS4_OFFSET) |
#define HAL_DISPLAY_ASCIIPOS5 HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIPOS5_OFFSET) |
#define HAL_DISPLAY_ASCIIPOS6 HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIPOS6_OFFSET) |
#define HAL_DISPLAY_ASCIIPOS7 HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIPOS7_OFFSET) |
|
#ifdef __ASSEMBLER__ |
|
# define DEBUG_ASCII_DISPLAY(register, character) \ |
li k0, CYGARC_UNCACHED_ADDRESS(register); \ |
li k1, character; \ |
sw k1, 0(k0); \ |
nop; \ |
nop; \ |
nop |
|
# define DEBUG_LED_IMM(val) \ |
li k0, HAL_DISPLAY_LEDBAR; \ |
li k1, val; \ |
sw k1, 0(k0) |
|
# define DEBUG_LED_REG(reg) \ |
li k0, HAL_DISPLAY_LEDBAR; \ |
sw reg, 0(k0) |
|
# define DEBUG_HEX_DISPLAY_IMM(val) \ |
li k0, HAL_DISPLAY_ASCIIWORD; \ |
li k1, val; \ |
sw k1, 0(k0) |
|
# define DEBUG_HEX_DISPLAY_REG(reg) \ |
li k0, HAL_DISPLAY_ASCIIWORD; \ |
sw reg, 0(k0) |
|
# define DEBUG_DELAY() \ |
li k0, 0x20000; \ |
0: sub k0, k0, 1; \ |
bnez k0, 0b; \ |
nop |
|
#else |
|
# define DEBUG_ASCII_DISPLAY(register, character) \ |
*(register) = character |
|
# define DEBUG_LED_IMM(val) \ |
*HAL_DISPLAY_LEDBAR = val |
|
# define DEBUG_HEX_DISPLAY_IMM(val) \ |
*HAL_DISPLAY_ASCIIWORD = val |
|
# define DEBUG_DELAY() \ |
{ \ |
volatile int i = 0x20000; \ |
while (--i) ; \ |
} |
|
# define DEBUG_DISPLAY(str) \ |
{ \ |
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS0, str[0]); \ |
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS1, str[1]); \ |
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS2, str[2]); \ |
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS3, str[3]); \ |
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS4, str[4]); \ |
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS5, str[5]); \ |
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS6, str[6]); \ |
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS7, str[7]); \ |
} |
|
|
#define HAL_GALILEO_PUTREG(x,y) \ |
(*((volatile unsigned *)(CYGARC_UNCACHED_ADDRESS(HAL_ATLAS_CONTROLLER_BASE) + (x))) = (y)) |
#define HAL_GALILEO_GETREG(x) \ |
(*((volatile unsigned *)(CYGARC_UNCACHED_ADDRESS(HAL_ATLAS_CONTROLLER_BASE) + (x)))) |
|
|
extern cyg_uint32 cyg_hal_plf_pci_cfg_read_dword (cyg_uint32 bus, |
cyg_uint32 devfn, |
cyg_uint32 offset); |
extern cyg_uint16 cyg_hal_plf_pci_cfg_read_word (cyg_uint32 bus, |
cyg_uint32 devfn, |
cyg_uint32 offset); |
extern cyg_uint8 cyg_hal_plf_pci_cfg_read_byte (cyg_uint32 bus, |
cyg_uint32 devfn, |
cyg_uint32 offset); |
extern void cyg_hal_plf_pci_cfg_write_dword (cyg_uint32 bus, |
cyg_uint32 devfn, |
cyg_uint32 offset, |
cyg_uint32 val); |
extern void cyg_hal_plf_pci_cfg_write_word (cyg_uint32 bus, |
cyg_uint32 devfn, |
cyg_uint32 offset, |
cyg_uint16 val); |
extern void cyg_hal_plf_pci_cfg_write_byte (cyg_uint32 bus, |
cyg_uint32 devfn, |
cyg_uint32 offset, |
cyg_uint8 val); |
|
// Initialize the PCI bus. |
externC void cyg_hal_plf_pci_init(void); |
#define HAL_PCI_INIT() cyg_hal_plf_pci_init() |
|
// Map PCI device resources starting from these addresses in PCI space. |
#define HAL_PCI_ALLOC_BASE_MEMORY 0x08000000 |
#define HAL_PCI_ALLOC_BASE_IO 0x18000000 |
|
// This is where the PCI spaces are mapped in the CPU's address space. |
// |
#define HAL_PCI_PHYSICAL_MEMORY_BASE 0xA0000000 |
#define HAL_PCI_PHYSICAL_IO_BASE 0xA0000000 |
|
// Read a value from the PCI configuration space of the appropriate |
// size at an address composed from the bus, devfn and offset. |
#define HAL_PCI_CFG_READ_UINT8( __bus, __devfn, __offset, __val ) \ |
__val = cyg_hal_plf_pci_cfg_read_byte((__bus), (__devfn), (__offset)) |
|
#define HAL_PCI_CFG_READ_UINT16( __bus, __devfn, __offset, __val ) \ |
__val = cyg_hal_plf_pci_cfg_read_word((__bus), (__devfn), (__offset)) |
|
#define HAL_PCI_CFG_READ_UINT32( __bus, __devfn, __offset, __val ) \ |
__val = cyg_hal_plf_pci_cfg_read_dword((__bus), (__devfn), (__offset)) |
|
// Write a value to the PCI configuration space of the appropriate |
// size at an address composed from the bus, devfn and offset. |
#define HAL_PCI_CFG_WRITE_UINT8( __bus, __devfn, __offset, __val ) \ |
cyg_hal_plf_pci_cfg_write_byte((__bus), (__devfn), (__offset), (__val)) |
|
#define HAL_PCI_CFG_WRITE_UINT16( __bus, __devfn, __offset, __val ) \ |
cyg_hal_plf_pci_cfg_write_word((__bus), (__devfn), (__offset), (__val)) |
|
#define HAL_PCI_CFG_WRITE_UINT32( __bus, __devfn, __offset, __val ) \ |
cyg_hal_plf_pci_cfg_write_dword((__bus), (__devfn), (__offset), (__val)) |
|
|
// Translate the PCI interrupt requested by the device (INTA#, INTB#, |
// INTC# or INTD#) to the associated CPU interrupt (i.e., HAL vector). |
#define HAL_PCI_TRANSLATE_INTERRUPT( __bus, __devfn, __vec, __valid) \ |
CYG_MACRO_START \ |
__valid = false; \ |
CYG_MACRO_END |
|
|
// Galileo GT64120 on MIPS ATLAS requires special processing. |
// First, it will hang when accessing device 31 on the local bus. |
// Second, we need to ignore the GT64120 so we can set it up |
// outside the generic PCI library. |
#define HAL_PCI_IGNORE_DEVICE(__bus, __dev, __fn) \ |
((__bus) == 0 && ((__dev) == 0 || (__dev) == 31)) |
|
#endif |
|
|
//----------------------------------------------------------------------------- |
// end of plf_io.h |
#endif // CYGONCE_PLF_IO_H |
/v2_0/include/hal_diag.h
0,0 → 1,95
#ifndef CYGONCE_HAL_DIAG_H |
#define CYGONCE_HAL_DIAG_H |
|
/*============================================================================= |
// |
// hal_diag.h |
// |
// HAL Support for Kernel Diagnostic Routines |
// |
//============================================================================= |
//####ECOSGPLCOPYRIGHTBEGIN#### |
// ------------------------------------------- |
// This file is part of eCos, the Embedded Configurable Operating System. |
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
// |
// eCos is free software; you can redistribute it and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
// Software Foundation; either version 2 or (at your option) any later version. |
// |
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
// WARRANTY; without even the implied warranty of MERCHANTABILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with eCos; if not, write to the Free Software Foundation, Inc., |
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
// |
// As a special exception, if other files instantiate templates or use macros |
// or inline functions from this file, or you compile this file and link it |
// with other works to produce a work based on this file, this file does not |
// by itself cause the resulting work to be covered by the GNU General Public |
// License. However the source code for this file must still be made available |
// in accordance with section (3) of the GNU General Public License. |
// |
// This exception does not invalidate any other reasons why a work based on |
// this file might be covered by the GNU General Public License. |
// |
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
// at http://sources.redhat.com/ecos/ecos-license/ |
// ------------------------------------------- |
//####ECOSGPLCOPYRIGHTEND#### |
//============================================================================= |
//#####DESCRIPTIONBEGIN#### |
// |
// Author(s): nickg, gthomas |
// Contributors: nickg, gthomas |
// Date: 1998-09-11 |
// Purpose: HAL Support for Kernel Diagnostic Routines |
// Description: Diagnostic routines for use during kernel development. |
// Usage: #include <cyg/hal/hal_diag.h> |
// |
//####DESCRIPTIONEND#### |
// |
//===========================================================================*/ |
|
#include <pkgconf/hal.h> |
|
#include <cyg/infra/cyg_type.h> |
|
#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG) |
|
#include <cyg/hal/hal_if.h> |
|
#define HAL_DIAG_INIT() hal_if_diag_init() |
#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_) |
#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_) |
|
#else // everything by steam |
|
/*---------------------------------------------------------------------------*/ |
/* functions implemented in hal_diag.c */ |
|
externC void hal_diag_init(void); |
externC void hal_diag_write_char(char c); |
externC void hal_diag_read_char(char *c); |
|
/*---------------------------------------------------------------------------*/ |
|
#define HAL_DIAG_INIT() hal_diag_init() |
|
#define HAL_DIAG_WRITE_CHAR(_c_) hal_diag_write_char(_c_) |
|
#define HAL_DIAG_READ_CHAR(_c_) hal_diag_read_char(&_c_) |
|
#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG |
|
/*---------------------------------------------------------------------------*/ |
// LED |
|
externC void hal_diag_led(int n); |
|
/*---------------------------------------------------------------------------*/ |
/* end of hal_diag.h */ |
#endif /* CYGONCE_HAL_DIAG_H */ |
/v2_0/src/ser16c550c.c
0,0 → 1,608
//============================================================================= |
// |
// ser16c550c.c |
// |
// Simple driver for the 16c550c serial controllers on the Atlas board |
// |
//============================================================================= |
//####ECOSGPLCOPYRIGHTBEGIN#### |
// ------------------------------------------- |
// This file is part of eCos, the Embedded Configurable Operating System. |
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
// |
// eCos is free software; you can redistribute it and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
// Software Foundation; either version 2 or (at your option) any later version. |
// |
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
// WARRANTY; without even the implied warranty of MERCHANTABILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with eCos; if not, write to the Free Software Foundation, Inc., |
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
// |
// As a special exception, if other files instantiate templates or use macros |
// or inline functions from this file, or you compile this file and link it |
// with other works to produce a work based on this file, this file does not |
// by itself cause the resulting work to be covered by the GNU General Public |
// License. However the source code for this file must still be made available |
// in accordance with section (3) of the GNU General Public License. |
// |
// This exception does not invalidate any other reasons why a work based on |
// this file might be covered by the GNU General Public License. |
// |
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
// at http://sources.redhat.com/ecos/ecos-license/ |
// ------------------------------------------- |
//####ECOSGPLCOPYRIGHTEND#### |
//============================================================================= |
//#####DESCRIPTIONBEGIN#### |
// |
// Author(s): dmoseley |
// Contributors:dmoseley |
// Date: 2000-07-06 |
// Description: Simple driver for the 16c550c serial controller |
// |
//####DESCRIPTIONEND#### |
// |
//============================================================================= |
|
#include <pkgconf/hal.h> |
#include <pkgconf/system.h> |
#include CYGBLD_HAL_PLATFORM_H |
|
#include <cyg/hal/hal_arch.h> // SAVE/RESTORE GP macros |
#include <cyg/hal/hal_io.h> // IO macros |
#include <cyg/hal/hal_if.h> // interface API |
#include <cyg/hal/hal_intr.h> // HAL_ENABLE/MASK/UNMASK_INTERRUPTS |
#include <cyg/hal/hal_misc.h> // Helper functions |
#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED |
|
//----------------------------------------------------------------------------- |
// There is only one port. |
#define ATLAS_SER_16550_BASE 0xBF000900 |
|
//----------------------------------------------------------------------------- |
// Define the serial registers. The Atlas board is equipped with a 16550C |
// serial chip. |
#define SER_16550_RBR 0x00 // receiver buffer register, read, dlab = 0 |
#define SER_16550_THR 0x00 // transmitter holding register, write, dlab = 0 |
#define SER_16550_DLL 0x00 // divisor latch (LS), read/write, dlab = 1 |
#define SER_16550_IER 0x08 // interrupt enable register, read/write, dlab = 0 |
#define SER_16550_DLM 0x08 // divisor latch (MS), read/write, dlab = 1 |
#define SER_16550_IIR 0x10 // interrupt identification reg, read, dlab = 0 |
#define SER_16550_FCR 0x10 // fifo control register, write, dlab = 0 |
#define SER_16550_AFR 0x10 // alternate function reg, read/write, dlab = 1 |
#define SER_16550_LCR 0x18 // line control register, read/write |
#define SER_16550_MCR 0x20 // modem control register, read/write |
#define SER_16550_LSR 0x28 // line status register, read |
#define SER_16550_MSR 0x30 // modem status register, read |
#define SER_16550_SCR 0x38 // scratch pad register |
|
// The interrupt enable register bits. |
#define SIO_IER_ERDAI 0x01 // enable received data available irq |
#define SIO_IER_ETHREI 0x02 // enable THR empty interrupt |
#define SIO_IER_ELSI 0x04 // enable receiver line status irq |
#define SIO_IER_EMSI 0x08 // enable modem status interrupt |
|
// The interrupt identification register bits. |
#define SIO_IIR_IP 0x01 // 0 if interrupt pending |
#define SIO_IIR_ID_MASK 0x0e // mask for interrupt ID bits |
|
// The line status register bits. |
#define SIO_LSR_DR 0x01 // data ready |
#define SIO_LSR_OE 0x02 // overrun error |
#define SIO_LSR_PE 0x04 // parity error |
#define SIO_LSR_FE 0x08 // framing error |
#define SIO_LSR_BI 0x10 // break interrupt |
#define SIO_LSR_THRE 0x20 // transmitter holding register empty |
#define SIO_LSR_TEMT 0x40 // transmitter register empty |
#define SIO_LSR_ERR 0x80 // any error condition |
|
// The modem status register bits. |
#define SIO_MSR_DCTS 0x01 // delta clear to send |
#define SIO_MSR_DDSR 0x02 // delta data set ready |
#define SIO_MSR_TERI 0x04 // trailing edge ring indicator |
#define SIO_MSR_DDCD 0x08 // delta data carrier detect |
#define SIO_MSR_CTS 0x10 // clear to send |
#define SIO_MSR_DSR 0x20 // data set ready |
#define SIO_MSR_RI 0x40 // ring indicator |
#define SIO_MSR_DCD 0x80 // data carrier detect |
|
// The line control register bits. |
#define SIO_LCR_WLS0 0x01 // word length select bit 0 |
#define SIO_LCR_WLS1 0x02 // word length select bit 1 |
#define SIO_LCR_STB 0x04 // number of stop bits |
#define SIO_LCR_PEN 0x08 // parity enable |
#define SIO_LCR_EPS 0x10 // even parity select |
#define SIO_LCR_SP 0x20 // stick parity |
#define SIO_LCR_SB 0x40 // set break |
#define SIO_LCR_DLAB 0x80 // divisor latch access bit |
|
// The FIFO control register |
#define SIO_FCR_FCR0 0x01 // enable xmit and rcvr fifos |
#define SIO_FCR_FCR1 0x02 // clear RCVR FIFO |
#define SIO_FCR_FCR2 0x04 // clear XMIT FIFO |
|
///////////////////////////////////////// |
// Interrupt Enable Register |
#define IER_RCV 0x01 |
#define IER_XMT 0x02 |
#define IER_LS 0x04 |
#define IER_MS 0x08 |
|
// Line Control Register |
#define LCR_WL5 0x00 // Word length |
#define LCR_WL6 0x01 |
#define LCR_WL7 0x02 |
#define LCR_WL8 0x03 |
#define LCR_SB1 0x00 // Number of stop bits |
#define LCR_SB1_5 0x04 // 1.5 -> only valid with 5 bit words |
#define LCR_SB2 0x04 |
#define LCR_PN 0x00 // Parity mode - none |
#define LCR_PE 0x0C // Parity mode - even |
#define LCR_PO 0x08 // Parity mode - odd |
#define LCR_PM 0x28 // Forced "mark" parity |
#define LCR_PS 0x38 // Forced "space" parity |
#define LCR_DL 0x80 // Enable baud rate latch |
|
// Line Status Register |
#define LSR_RSR 0x01 |
#define LSR_THE 0x20 |
|
// Modem Control Register |
#define MCR_DTR 0x01 |
#define MCR_RTS 0x02 |
#define MCR_INT 0x08 // Enable interrupts |
|
// Interrupt status register |
#define ISR_None 0x01 |
#define ISR_Rx_Line_Status 0x06 |
#define ISR_Rx_Avail 0x04 |
#define ISR_Rx_Char_Timeout 0x0C |
#define ISR_Tx_Empty 0x02 |
#define IRS_Modem_Status 0x00 |
|
// FIFO control register |
#define FCR_ENABLE 0x01 |
#define FCR_CLEAR_RCVR 0x02 |
#define FCR_CLEAR_XMIT 0x04 |
|
// The Atlas board has a 3.6864 MHz crystal |
#define BAUD_110 2094 |
#define BAUD_150 1536 |
#define BAUD_300 768 |
#define BAUD_600 384 |
#define BAUD_1200 192 |
#define BAUD_2400 96 |
#define BAUD_4800 48 |
#define BAUD_7200 32 |
#define BAUD_9600 24 |
#define BAUD_14400 16 |
#define BAUD_19200 12 |
#define BAUD_38400 6 |
#define BAUD_57600 4 |
#define BAUD_115200 2 |
#define BAUD_230400 1 |
|
#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==9600 |
#define CYG_DEV_SERIAL_BAUD_DIVISOR BAUD_9600 |
#endif |
#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==19200 |
#define CYG_DEV_SERIAL_BAUD_DIVISOR BAUD_19200 |
#endif |
#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==38400 |
#define CYG_DEV_SERIAL_BAUD_DIVISOR BAUD_38400 |
#endif |
#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==57600 |
#define CYG_DEV_SERIAL_BAUD_DIVISOR BAUD_57600 |
#endif |
#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==115200 |
#define CYG_DEV_SERIAL_BAUD_DIVISOR BAUD_115200 |
#endif |
|
#ifndef CYG_DEV_SERIAL_BAUD_DIVISOR |
#error Missing/incorrect serial baud rate defined - CDL error? |
#endif |
|
|
//----------------------------------------------------------------------------- |
typedef struct { |
cyg_uint8* base; |
cyg_int32 msec_timeout; |
int isr_vector; |
} channel_data_t; |
|
static channel_data_t channels[1] = { |
{ (cyg_uint8*)ATLAS_SER_16550_BASE, 1000, CYGNUM_HAL_INTERRUPT_DEBUG_UART} |
}; |
|
//----------------------------------------------------------------------------- |
// Set the baud rate |
|
static void |
cyg_hal_plf_serial_set_baud(cyg_uint8* port, cyg_uint16 baud_divisor) |
{ |
cyg_uint8 _lcr; |
|
HAL_READ_UINT8(port+SER_16550_LCR, _lcr); |
_lcr |= LCR_DL; |
HAL_WRITE_UINT8(port+SER_16550_LCR, _lcr); |
|
HAL_WRITE_UINT8(port+SER_16550_DLM, baud_divisor >> 8); |
HAL_WRITE_UINT8(port+SER_16550_DLL, baud_divisor & 0xff); |
|
_lcr &= ~LCR_DL; |
HAL_WRITE_UINT8(port+SER_16550_LCR, _lcr); |
} |
|
//----------------------------------------------------------------------------- |
// The minimal init, get and put functions. All by polling. |
|
void |
cyg_hal_plf_serial_init_channel(void* __ch_data) |
{ |
cyg_uint8* port; |
cyg_uint8 _lcr; |
|
// Some of the diagnostic print code calls through here with no idea what the ch_data is. |
// Go ahead and assume it is channels[0]. |
if (__ch_data == 0) |
__ch_data = (void*)&channels[0]; |
|
port = ((channel_data_t*)__ch_data)->base; |
|
// Disable port interrupts while changing hardware |
HAL_WRITE_UINT8(port+SER_16550_IER, 0); |
|
// Set databits, stopbits and parity. |
_lcr = LCR_WL8 | LCR_SB1 | LCR_PN; |
HAL_WRITE_UINT8(port+SER_16550_LCR, _lcr); |
|
// Set baud rate. |
cyg_hal_plf_serial_set_baud(port, CYG_DEV_SERIAL_BAUD_DIVISOR); |
|
// Enable and clear FIFO |
HAL_WRITE_UINT8(port+SER_16550_FCR, (FCR_ENABLE | FCR_CLEAR_RCVR | FCR_CLEAR_XMIT)); |
|
// enable RTS to keep host side happy |
HAL_WRITE_UINT8( port+SER_16550_MCR, MCR_RTS ); |
|
// Don't allow interrupts. |
HAL_WRITE_UINT8(port+SER_16550_IER, 0); |
} |
|
void |
cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 __ch) |
{ |
cyg_uint8* port; |
cyg_uint8 _lsr; |
|
// Some of the diagnostic print code calls through here with no idea what the ch_data is. |
// Go ahead and assume it is channels[0]. |
if (__ch_data == 0) |
__ch_data = (void*)&channels[0]; |
|
port = ((channel_data_t*)__ch_data)->base; |
|
CYGARC_HAL_SAVE_GP(); |
|
do { |
HAL_READ_UINT8(port+SER_16550_LSR, _lsr); |
} while ((_lsr & SIO_LSR_THRE) == 0); |
|
// Now, the transmit buffer is empty |
HAL_WRITE_UINT8(port+SER_16550_THR, __ch); |
|
// Hang around until the character has been safely sent. |
do { |
HAL_READ_UINT8(port+SER_16550_LSR, _lsr); |
} while ((_lsr & SIO_LSR_THRE) == 0); |
|
CYGARC_HAL_RESTORE_GP(); |
} |
|
static cyg_bool |
cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch) |
{ |
cyg_uint8* port; |
cyg_uint8 _lsr; |
|
// Some of the diagnostic print code calls through here with no idea what the ch_data is. |
// Go ahead and assume it is channels[0]. |
if (__ch_data == 0) |
__ch_data = (void*)&channels[0]; |
|
port = ((channel_data_t*)__ch_data)->base; |
|
HAL_READ_UINT8(port+SER_16550_LSR, _lsr); |
if ((_lsr & SIO_LSR_DR) == 0) |
return false; |
|
HAL_READ_UINT8(port+SER_16550_RBR, *ch); |
|
return true; |
} |
|
cyg_uint8 |
cyg_hal_plf_serial_getc(void* __ch_data) |
{ |
cyg_uint8 ch; |
CYGARC_HAL_SAVE_GP(); |
|
// Some of the diagnostic print code calls through here with no idea what the ch_data is. |
// Go ahead and assume it is channels[0]. |
if (__ch_data == 0) |
__ch_data = (void*)&channels[0]; |
|
while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch)); |
|
CYGARC_HAL_RESTORE_GP(); |
return ch; |
} |
|
static void |
cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf, |
cyg_uint32 __len) |
{ |
CYGARC_HAL_SAVE_GP(); |
|
// Some of the diagnostic print code calls through here with no idea what the ch_data is. |
// Go ahead and assume it is channels[0]. |
if (__ch_data == 0) |
__ch_data = (void*)&channels[0]; |
|
while(__len-- > 0) |
cyg_hal_plf_serial_putc(__ch_data, *__buf++); |
|
CYGARC_HAL_RESTORE_GP(); |
} |
|
static void |
cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len) |
{ |
CYGARC_HAL_SAVE_GP(); |
|
// Some of the diagnostic print code calls through here with no idea what the ch_data is. |
// Go ahead and assume it is channels[0]. |
if (__ch_data == 0) |
__ch_data = (void*)&channels[0]; |
|
while(__len-- > 0) |
*__buf++ = cyg_hal_plf_serial_getc(__ch_data); |
|
CYGARC_HAL_RESTORE_GP(); |
} |
|
|
cyg_bool |
cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch) |
{ |
int delay_count; |
channel_data_t* chan; |
cyg_bool res; |
CYGARC_HAL_SAVE_GP(); |
|
// Some of the diagnostic print code calls through here with no idea what the ch_data is. |
// Go ahead and assume it is channels[0]. |
if (__ch_data == 0) |
__ch_data = (void*)&channels[0]; |
|
chan = (channel_data_t*)__ch_data; |
|
delay_count = chan->msec_timeout * 10; // delay in .1 ms steps |
|
for(;;) { |
res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch); |
if (res || 0 == delay_count--) |
break; |
CYGACC_CALL_IF_DELAY_US(100); |
} |
|
CYGARC_HAL_RESTORE_GP(); |
return res; |
} |
|
static int |
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...) |
{ |
static int irq_state = 0; |
channel_data_t* chan; |
cyg_uint8 ier; |
int ret = 0; |
CYGARC_HAL_SAVE_GP(); |
|
// Some of the diagnostic print code calls through here with no idea what the ch_data is. |
// Go ahead and assume it is channels[0]. |
if (__ch_data == 0) |
__ch_data = (void*)&channels[0]; |
|
chan = (channel_data_t*)__ch_data; |
|
switch (__func) { |
case __COMMCTL_IRQ_ENABLE: |
irq_state = 1; |
|
HAL_READ_UINT8(chan->base + SER_16550_IER, ier); |
ier |= SIO_IER_ERDAI; |
HAL_WRITE_UINT8(chan->base + SER_16550_IER, ier); |
|
HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1); |
HAL_INTERRUPT_UNMASK(chan->isr_vector); |
break; |
case __COMMCTL_IRQ_DISABLE: |
ret = irq_state; |
irq_state = 0; |
|
HAL_READ_UINT8(chan->base + SER_16550_IER, ier); |
ier &= ~SIO_IER_ERDAI; |
HAL_WRITE_UINT8(chan->base + SER_16550_IER, ier); |
|
HAL_INTERRUPT_MASK(chan->isr_vector); |
break; |
case __COMMCTL_DBG_ISR_VECTOR: |
ret = chan->isr_vector; |
break; |
case __COMMCTL_SET_TIMEOUT: |
{ |
va_list ap; |
|
va_start(ap, __func); |
|
ret = chan->msec_timeout; |
chan->msec_timeout = va_arg(ap, cyg_uint32); |
|
va_end(ap); |
} |
break; |
case __COMMCTL_SETBAUD: |
{ |
cyg_uint32 baud_rate; |
cyg_uint16 baud_divisor; |
cyg_uint8* port = chan->base; |
va_list ap; |
|
va_start(ap, __func); |
baud_rate = va_arg(ap, cyg_uint32); |
va_end(ap); |
|
switch (baud_rate) |
{ |
case 110: baud_divisor = BAUD_110; break; |
case 150: baud_divisor = BAUD_150; break; |
case 300: baud_divisor = BAUD_300; break; |
case 600: baud_divisor = BAUD_600; break; |
case 1200: baud_divisor = BAUD_1200; break; |
case 2400: baud_divisor = BAUD_2400; break; |
case 4800: baud_divisor = BAUD_4800; break; |
case 7200: baud_divisor = BAUD_7200; break; |
case 9600: baud_divisor = BAUD_9600; break; |
case 14400: baud_divisor = BAUD_14400; break; |
case 19200: baud_divisor = BAUD_19200; break; |
case 38400: baud_divisor = BAUD_38400; break; |
case 57600: baud_divisor = BAUD_57600; break; |
case 115200: baud_divisor = BAUD_115200; break; |
case 230400: baud_divisor = BAUD_230400; break; |
default: return -1; break; // Invalid baud rate selected |
} |
|
// |
// We may need to increase the timeout before causing a break reset. |
// According to the Atlas Users Manual (Document MD00005) The BRKRES |
// register will need to be programmed with a value larger that 0xA (the default) |
// if we are going to use a baud rate lower than 2400. |
// |
if (baud_rate <= 2400) |
{ |
// For now, just disable the break reset entirely. |
HAL_WRITE_UINT32(HAL_ATLAS_BRKRES, 0); |
} else { |
// Put the break reset state back to the default |
HAL_WRITE_UINT32(HAL_ATLAS_BRKRES, HAL_ATLAS_BRKRES_DEFAULT_VALUE); |
} |
|
// Disable port interrupts while changing hardware |
HAL_READ_UINT8(port+SER_16550_IER, ier); |
HAL_WRITE_UINT8(port+SER_16550_IER, 0); |
|
// Set baud rate. |
cyg_hal_plf_serial_set_baud(port, baud_divisor); |
|
// Reenable interrupts if necessary |
HAL_WRITE_UINT8(port+SER_16550_IER, ier); |
} |
break; |
|
case __COMMCTL_GETBAUD: |
break; |
default: |
break; |
} |
CYGARC_HAL_RESTORE_GP(); |
return ret; |
} |
|
static int |
cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc, |
CYG_ADDRWORD __vector, CYG_ADDRWORD __data) |
{ |
int res = 0; |
cyg_uint8 _iir, c; |
channel_data_t* chan; |
CYGARC_HAL_SAVE_GP(); |
|
// Some of the diagnostic print code calls through here with no idea what the ch_data is. |
// Go ahead and assume it is channels[0]. |
if (__ch_data == 0) |
__ch_data = (void*)&channels[0]; |
|
chan = (channel_data_t*)__ch_data; |
|
HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector); |
|
HAL_READ_UINT8(chan->base + SER_16550_IIR, _iir); |
_iir &= SIO_IIR_ID_MASK; |
|
*__ctrlc = 0; |
if ((_iir == ISR_Rx_Avail) || (_iir == ISR_Rx_Char_Timeout)) { |
|
HAL_READ_UINT8(chan->base + SER_16550_RBR, c); |
|
if( cyg_hal_is_break( &c , 1 ) ) |
*__ctrlc = 1; |
|
res = CYG_ISR_HANDLED; |
} |
|
CYGARC_HAL_RESTORE_GP(); |
return res; |
} |
|
static void |
cyg_hal_plf_serial_init(void) |
{ |
hal_virtual_comm_table_t* comm; |
int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); |
|
// Disable interrupts. |
HAL_INTERRUPT_MASK(channels[0].isr_vector); |
|
// Init channels |
cyg_hal_plf_serial_init_channel((void*)&channels[0]); |
|
// Setup procs in the vector table |
|
// Set channel 0 |
CYGACC_CALL_IF_SET_CONSOLE_COMM(0); |
comm = CYGACC_CALL_IF_CONSOLE_PROCS(); |
CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[0]); |
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write); |
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read); |
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc); |
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc); |
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control); |
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr); |
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout); |
|
// Restore original console |
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur); |
} |
|
void |
cyg_hal_plf_comms_init(void) |
{ |
static int initialized = 0; |
|
if (initialized) |
return; |
|
initialized = 1; |
|
cyg_hal_plf_serial_init(); |
} |
|
//----------------------------------------------------------------------------- |
// end of ser16c550c.c |
|
/v2_0/src/platform.S
0,0 → 1,584
## |
#============================================================================= |
## platform.S |
## |
## MIPS Atlas platform code |
## |
##============================================================================= |
#####ECOSGPLCOPYRIGHTBEGIN#### |
## ------------------------------------------- |
## This file is part of eCos, the Embedded Configurable Operating System. |
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
## |
## eCos is free software; you can redistribute it and/or modify it under |
## the terms of the GNU General Public License as published by the Free |
## Software Foundation; either version 2 or (at your option) any later version. |
## |
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
## WARRANTY; without even the implied warranty of MERCHANTABILITY or |
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
## for more details. |
## |
## You should have received a copy of the GNU General Public License along |
## with eCos; if not, write to the Free Software Foundation, Inc., |
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
## |
## As a special exception, if other files instantiate templates or use macros |
## or inline functions from this file, or you compile this file and link it |
## with other works to produce a work based on this file, this file does not |
## by itself cause the resulting work to be covered by the GNU General Public |
## License. However the source code for this file must still be made available |
## in accordance with section (3) of the GNU General Public License. |
## |
## This exception does not invalidate any other reasons why a work based on |
## this file might be covered by the GNU General Public License. |
## |
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
## at http://sources.redhat.com/ecos/ecos-license/ |
## ------------------------------------------- |
#####ECOSGPLCOPYRIGHTEND#### |
##============================================================================= |
#######DESCRIPTIONBEGIN#### |
## |
## Author(s): dmoseley |
## Contributors: dmoseley |
## Date: 2000-06-06 |
## Purpose: MIPS Atlas platform code |
## Description: Platform specific code for Atlas board. |
## |
## |
## |
## |
######DESCRIPTIONEND#### |
## |
##============================================================================= |
|
#include <pkgconf/system.h> |
#include <pkgconf/hal.h> |
|
#ifdef CYGPKG_KERNEL |
# include <pkgconf/kernel.h> |
#endif |
|
#include <cyg/hal/arch.inc> |
#include <cyg/hal/plf_io.h> |
#include <cyg/hal/hal_arch.h> |
|
##----------------------------------------------------------------------------- |
|
##----------------------------------------------------------------------------- |
# Platform Initialization. |
# This code performs platform specific initialization. |
|
##----------------------------------------------------------------------------- |
## MEMC initialization. |
## |
|
#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) |
|
.text |
.set noreorder |
|
|
.macro MASK_WRITE_PCI_REG regnum, devnum, mask |
.set noreorder |
# First, read the appropriate register |
li t0, HAL_GALILEO_PCI0_CONFIG_ADDR_ConfigEn | \regnum | \devnum |
sw t0, HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET(s7) |
lw t1, HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET(s7) |
|
# Now, mask in the appropriate bits |
li t2, \mask |
or t1, t2 |
|
# Write the updated value |
li t0, HAL_GALILEO_PCI0_CONFIG_ADDR_ConfigEn | \regnum | \devnum |
sw t0, HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET(s7) |
sw t1, HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET(s7) |
.endm |
|
.macro WRITE_PCI_REG regnum, devnum, base |
.set noreorder |
li t0, HAL_GALILEO_PCI0_CONFIG_ADDR_ConfigEn | \regnum | \devnum |
li t1, \base |
sw t0, HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET(s7) |
sw t1, HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET(s7) |
.endm |
|
#define NO_MASK 0 |
#define NO_ERROR_CHECK 0 |
#define ERROR_CHECK 1 |
.macro READ_SPD_VALUE func, mask, ret_reg, err_check |
.set noreorder |
jal read_spd_value |
li a0, \func # delay slot |
.if \err_check |
beq v0, zero, error |
nop |
.endif |
move \ret_reg, v0 |
.if \mask |
and \ret_reg, \mask |
.endif |
.endm |
|
##----------------------------------------------------------------------------- |
## |
## Initialize the RAM. |
## |
## To do that, we need to first initialize the Galileo PCI stuff to gain access |
## to the SAA9730. |
## From there, use the I2C bus of the SAA9730 to read the SPD SDRAM |
## config data. We then setup the Galileo SDRAM configuration |
## |
## Returns |
## v0 = Error Code |
## v1 = SDRAM size |
## |
FUNC_START(hal_atlas_init_sdram) |
|
.set noreorder |
|
# Save the return address |
move s8, ra |
|
# Setup the base address registers |
li s7, CYGARC_UNCACHED_ADDRESS(HAL_GALILEO_REGISTER_BASE) |
|
# Setup the Galileo controller Endian configuration |
li t0, (HAL_GALILEO_BYTE_SWAP) |
sw t0, HAL_GALILEO_PCI_INTERNAL_COMMAND_OFFSET(s7) |
|
# Setup the PCI_0 Timeout and retry configuration |
li t0, HAL_GALILEO_PCI0_TIMEOUT_RETRY_VALUE |
sw t0, HAL_GALILEO_PCI0_TIMEOUT_RETRY_OFFSET(s7) |
|
# Setup Galileo as PCI Master |
MASK_WRITE_PCI_REG HAL_GALILEO_PCI0_STATUS_COMMAND_REGNUM, HAL_ATLAS_NULL_DEVNUM, \ |
(HAL_GALILEO_PCI0_CONFIG_MEMEn | HAL_GALILEO_PCI0_CONFIG_MasEn | HAL_GALILEO_PCI0_CONFIG_SErrEn) |
|
# Setup Galileo PCI latency timer |
MASK_WRITE_PCI_REG HAL_GALILEO_PCI0_BIST_REGNUM, HAL_ATLAS_NULL_DEVNUM, \ |
HAL_GALILEO_PCI0_LAT_TIMER_VAL |
|
# Setup base address for SAA9730 |
WRITE_PCI_REG HAL_GALILEO_PCI0_SCS32_BASE_REGNUM, HAL_ATLAS_SAA9730_DEVNUM, \ |
CYGARC_PHYSICAL_ADDRESS(HAL_GALILEO_PCI0_MEM0_BASE) |
|
# Setup SAA9730 command and status register |
MASK_WRITE_PCI_REG HAL_GALILEO_PCI0_STATUS_COMMAND_REGNUM, HAL_ATLAS_SAA9730_DEVNUM, \ |
(HAL_GALILEO_PCI0_CONFIG_MEMEn | HAL_GALILEO_PCI0_CONFIG_SErrEn) |
|
# Init the I2C controller |
li t0, HAL_SAA9730_I2CSC_I2CCC_6400 |
li t1, CYGARC_UNCACHED_ADDRESS(HAL_GALILEO_PCI0_MEM0_BASE) |
sw t0, HAL_SAA9730_I2CSC_OFFSET(t1) |
|
##===================================================================================== |
## |
## Read the SPD device parameters and determine memory size |
## |
READ_SPD_VALUE HAL_SPD_GET_NUM_ROW_BITS, 0xf, s0, ERROR_CHECK |
READ_SPD_VALUE HAL_SPD_GET_NUM_COL_BITS, 0xf, s1, ERROR_CHECK |
READ_SPD_VALUE HAL_SPD_GET_NUM_DEVICE_BANKS, NO_MASK, s2, ERROR_CHECK |
|
READ_SPD_VALUE HAL_SPD_GET_SDRAM_WIDTH, 0x7f, s3, ERROR_CHECK |
READ_SPD_VALUE HAL_SPD_GET_NUM_MODULE_BANKS, NO_MASK, s4, ERROR_CHECK |
READ_SPD_VALUE HAL_SPD_GET_ROW_DENSITY, NO_MASK, s5, ERROR_CHECK |
|
# |
# Determine Size |
# SIZE = SDRAM_WIDTH * NUM_DEVICE_BANKS * 2 ^ (NUM_ROW_BITS + NUM_COL_BITS) |
# |
addu t0, s0, s1 # t0 = (NUM_ROW_BITS + NUM_COL_BITS) |
li t1, 1 # t1 = 2 ^ 0 |
sll t1, t0 # t1 = 2 ^ (NUM_ROW_BITS + NUM_COL_BITS) |
multu s2, t1 |
mflo s6 # s6 = NUM_DEVICE_BANKS * 2 ^ (NUM_ROW_BITS + NUM_COL_BITS) |
nop |
nop |
nop |
multu s6, s3 |
mflo s6 # s6 = SDRAM_WIDTH * NUM_DEVICE_BANKS * 2 ^ (NUM_ROW_BITS + NUM_COL_BITS) |
nop |
nop |
nop |
|
# |
# Determine size of Bank 0 |
# |
li s0, HAL_ATLAS_MAX_BANKSIZE |
0: |
and t1, s5, BIT7 |
bnez t1, 8f |
sll s5, 1 |
b 0b |
srl s0, 1 |
8: |
|
# |
# Determine if Bank 1 exists |
# |
li t0, 1 |
beq s4, t0, 8f |
move s1, zero |
# |
# Determine if Bank 1 is different than Bank 0 |
# |
and t1, s5, 0xFF |
beq t1, zero, 8f |
move s1, s0 |
# |
# Determine size of Bank 1 |
# |
li s1, HAL_ATLAS_MAX_BANKSIZE |
0: |
and t1, s5, BIT7 |
bnez t1, 8f |
sll s5, 1 |
b 0b |
srl s1, 1 |
8: |
|
# |
# FIXME: We should probably do some validation on the various |
# memory parameters here at some point. |
# |
|
# |
# Set the base SDRAM bank configuration value. |
# All other fields are zero, and the proper value is masked |
# in when they are known |
# |
li s5, HAL_GALILEO_SDRAM_SRAS_TO_SCAS_DELAY_3C | \ |
HAL_GALILEO_SDRAM_WIDTH_64BIT | \ |
HAL_GALILEO_SDRAM_SRAS_PRECHARGE_3C |
|
# |
# Setup the CASLAT value. |
# Support only CASLAT = 2 |
# |
READ_SPD_VALUE HAL_SPD_GET_CAS_LAT, NO_MASK, v0, NO_ERROR_CHECK |
and t0, v0, 2 |
beqz t0, error |
nop |
ori s5, HAL_GALILEO_SDRAM_BANK0_CASLAT_2 |
|
# |
# Setup SDRAM device size |
# |
li t0, SZ_16M |
beq s6, t0, 8f |
nop |
ori s5, HAL_GALILEO_SDRAM_BANK0_SZ_64M |
8: |
|
# |
# Setup burst length: Support only 8 |
# |
READ_SPD_VALUE HAL_SPD_GET_BURST_LENGTH, NO_MASK, v0, NO_ERROR_CHECK |
and t0, v0, 8 |
beqz t0, error |
nop |
|
# |
# Setup Parity. |
# Only support Parity/Noparity. Don't support ECC. |
# |
READ_SPD_VALUE HAL_SPD_GET_CONFIG_TYPE, NO_MASK, v0, NO_ERROR_CHECK |
li t0, HAL_SPD_CONFIG_TYPE_PARITY |
beq t0, v0, 0f |
nop |
li t0, HAL_SPD_CONFIG_TYPE_ECC |
beq t0, v0, error |
nop |
b 8f |
li v1, 0 |
0: |
ori s5, HAL_GALILEO_SDRAM_BANK0_PARITY |
li v1, 1 |
8: |
|
# |
# Setup number of device banks |
# Only support 2 or 4 banks |
# |
li t0, 2 |
beq s2, t0, 8f |
nop |
li t0, 4 |
beq s2, t0, 0f |
nop |
b error |
nop |
0: |
ori s5, HAL_GALILEO_SDRAM_NUM_BANKS_4 |
8: |
|
# |
# Now actually store the bank config register |
# |
sw s5, HAL_GALILEO_SDRAM_BANK0_OFFSET(s7) |
sw s5, HAL_GALILEO_SDRAM_BANK2_OFFSET(s7) |
|
# |
# Setup the SDRAM configuration register |
# All other fields are zero, and the proper value is masked |
# in when they are known |
# |
li s5, HAL_GALILEO_SDRAM_DUPLICATE_BANK_ADDR | HAL_GALILEO_SDRAM_BANK_INTERLEAVE_DIS |
|
# |
# Setup the Refresh Rate |
# |
READ_SPD_VALUE HAL_SPD_GET_REFRESH_RATE, 0x7f, v0, NO_ERROR_CHECK |
|
li t0, HAL_SPD_REFRESH_RATE_125 |
beq t0, v0, 8f |
li t0, HAL_SPD_REFRESH_COUNTER_125 |
|
li t0, HAL_SPD_REFRESH_RATE_62_5 |
beq t0, v0, 8f |
li t0, HAL_SPD_REFRESH_COUNTER_62_5 |
|
li t0, HAL_SPD_REFRESH_RATE_31_3 |
beq t0, v0, 8f |
li t0, HAL_SPD_REFRESH_COUNTER_31_3 |
|
li t0, HAL_SPD_REFRESH_RATE_15_625 |
beq t0, v0, 8f |
li t0, HAL_SPD_REFRESH_COUNTER_15_625 |
|
li t0, HAL_SPD_REFRESH_RATE_7_8 |
beq t0, v0, 8f |
li t0, HAL_SPD_REFRESH_COUNTER_7_8 |
|
# Unknown: assume 3.9 microseconds |
li t0, HAL_SPD_REFRESH_COUNTER_3_9 |
8: |
|
or s5, t0 |
|
# |
# Setup RAM_WIDTH |
# |
beqz v1, 8f |
nop |
READ_SPD_VALUE HAL_SPD_GET_ERROR_CHECK_WIDTH, 0x7f, v0, NO_ERROR_CHECK |
beq v0, zero, 8f |
nop |
ori s5, HAL_GALILEO_SDRAM_CFG_RAM_WIDTH |
8: |
|
# |
# Store the SDRAM configuration register |
# |
sw s5, HAL_GALILEO_SDRAM_CONFIG_OFFSET(s7) |
|
# |
# Reset SAA9730 now that we are done with the I2C unit. |
# This allows the generic PCI library to start with a clean |
# slate of devices on the PCI bus. |
# |
li a0, CYGARC_UNCACHED_ADDRESS(HAL_GALILEO_PCI0_MEM0_BASE) |
li t0, HAL_SAA9730_SYSRESET_ALL |
sw t0, HAL_SAA9730_SYSRESET_OFFSET(a0) |
|
# |
# Change the Galileo Base address to HAL_ATLAS_CONTROLLER_BASE |
# |
li t0, HAL_ATLAS_CONTROLLER_BASE_ISD_CONFIG |
sw t0, HAL_GALILEO_INT_SPACE_DECODE_OFFSET(s7) |
li s7, CYGARC_UNCACHED_ADDRESS(HAL_ATLAS_CONTROLLER_BASE) |
|
# |
# Setup SDRAM Bank 0 Address Decoding |
# |
li a0, CYGARC_PHYSICAL_ADDRESS(HAL_ATLAS_RAM_BASE) # Physical bottom of Bank 0 |
add a1, s0, a0 |
subu a1, 1 # Physical top of Bank 0 |
|
srl t0, a0, HAL_GALILEO_CPU_DECODE_SHIFT # Setup SCS[1:0] |
srl t1, a1, HAL_GALILEO_CPU_DECODE_SHIFT # First level decoding |
sw t0, HAL_GALILEO_SCS10_LD_OFFSET(s7) # (ie Processor Decode Region) |
sw t1, HAL_GALILEO_SCS10_HD_OFFSET(s7) # |
|
srl t0, a0, HAL_GALILEO_DEV_DECODE_SHIFT # Setup SCS0 |
srl t1, a1, HAL_GALILEO_DEV_DECODE_SHIFT # Second level decoding |
sw t0, HAL_GALILEO_SCS0_LD_OFFSET(s7) # (ie Device Sub-decode Region) |
sw t1, HAL_GALILEO_SCS0_HD_OFFSET(s7) # |
|
# |
# Setup SDRAM Bank 1 Address Decoding |
# |
add a0, s0, CYGARC_PHYSICAL_ADDRESS(HAL_ATLAS_RAM_BASE) # Physical bottom of Bank 1 |
add a1, a0, s1 |
subu a1, 1 # Physical top of Bank 1 |
|
srl t0, a0, HAL_GALILEO_CPU_DECODE_SHIFT # Setup SCS[3:2] |
srl t1, a1, HAL_GALILEO_CPU_DECODE_SHIFT # First level decoding |
sw t0, HAL_GALILEO_SCS32_LD_OFFSET(s7) # (ie Processor Decode Region) |
sw t1, HAL_GALILEO_SCS32_HD_OFFSET(s7) # |
|
srl t0, a0, HAL_GALILEO_DEV_DECODE_SHIFT # Setup SCS2 |
srl t1, a1, HAL_GALILEO_DEV_DECODE_SHIFT # Second level decoding |
sw t0, HAL_GALILEO_SCS2_LD_OFFSET(s7) # (ie Device Sub-decode Region) |
sw t1, HAL_GALILEO_SCS2_HD_OFFSET(s7) # |
|
# |
# Setup PCI windows |
# |
li a0, CYGARC_PHYSICAL_ADDRESS(HAL_ATLAS_PCI_MEM0_BASE) |
add a1, a0, HAL_ATLAS_PCI_MEM0_SIZE |
subu a1, 1 # Physical top of Bank 1 |
srl t0, a0, HAL_GALILEO_CPU_DECODE_SHIFT |
srl t1, a1, HAL_GALILEO_CPU_DECODE_SHIFT |
sw t0, HAL_GALILEO_PCIMEM0_LD_OFFSET(s7) |
sw t1, HAL_GALILEO_PCIMEM0_HD_OFFSET(s7) |
|
li a0, CYGARC_PHYSICAL_ADDRESS(HAL_ATLAS_PCI_MEM1_BASE) |
add a1, a0, HAL_ATLAS_PCI_MEM1_SIZE |
subu a1, 1 # Physical top of Bank 1 |
srl t0, a0, HAL_GALILEO_CPU_DECODE_SHIFT |
srl t1, a1, HAL_GALILEO_CPU_DECODE_SHIFT |
sw t0, HAL_GALILEO_PCIMEM1_LD_OFFSET(s7) |
sw t1, HAL_GALILEO_PCIMEM1_HD_OFFSET(s7) |
|
li a0, CYGARC_PHYSICAL_ADDRESS(HAL_ATLAS_PCI_IO_BASE) |
add a1, a0, HAL_ATLAS_PCI_IO_SIZE |
subu a1, 1 # Physical top of Bank 1 |
srl t0, a0, HAL_GALILEO_CPU_DECODE_SHIFT |
srl t1, a1, HAL_GALILEO_CPU_DECODE_SHIFT |
sw t0, HAL_GALILEO_PCIIO_LD_OFFSET(s7) |
sw t1, HAL_GALILEO_PCIIO_HD_OFFSET(s7) |
|
# |
# Setup FLASH Address Decoding |
# |
li a0, CYGARC_PHYSICAL_ADDRESS(HAL_ATLAS_FLASH_BASE) # Physical bottom of Flash Bank |
add a1, a0, HAL_ATLAS_FLASH_SIZE |
subu a1, 1 # Physical top of Flash Bank |
|
srl t0, a0, HAL_GALILEO_CPU_DECODE_SHIFT # Setup CS[2:0] |
srl t1, a1, HAL_GALILEO_CPU_DECODE_SHIFT # First level decoding |
sw t0, HAL_GALILEO_CS20_LD_OFFSET(s7) # (ie Processor Decode Region) |
sw t1, HAL_GALILEO_CS20_HD_OFFSET(s7) # |
|
srl t0, a0, HAL_GALILEO_DEV_DECODE_SHIFT # Setup CS0 |
srl t1, a1, HAL_GALILEO_DEV_DECODE_SHIFT # Second level decoding |
sw t0, HAL_GALILEO_CS0_LD_OFFSET(s7) # (ie Device Sub-decode Region) |
sw t1, HAL_GALILEO_CS0_HD_OFFSET(s7) # |
|
# |
# Now disable all unused decodes |
# (SCS1, SCS3, PCI1xx, CS1, CS2) |
# |
li t0, 0xffff |
move t1, zero |
sw t0, HAL_GALILEO_SCS1_LD_OFFSET(s7) |
sw t1, HAL_GALILEO_SCS1_HD_OFFSET(s7) |
sw t0, HAL_GALILEO_SCS3_LD_OFFSET(s7) |
sw t1, HAL_GALILEO_SCS3_HD_OFFSET(s7) |
sw t0, HAL_GALILEO_PCI1IO_LD_OFFSET(s7) |
sw t1, HAL_GALILEO_PCI1IO_HD_OFFSET(s7) |
sw t0, HAL_GALILEO_PCI1MEM0_LD_OFFSET(s7) |
sw t1, HAL_GALILEO_PCI1MEM0_HD_OFFSET(s7) |
sw t0, HAL_GALILEO_PCI1MEM1_LD_OFFSET(s7) |
sw t1, HAL_GALILEO_PCI1MEM1_HD_OFFSET(s7) |
sw t0, HAL_GALILEO_CS1_LD_OFFSET(s7) |
sw t1, HAL_GALILEO_CS1_HD_OFFSET(s7) |
sw t0, HAL_GALILEO_CS2_LD_OFFSET(s7) |
sw t1, HAL_GALILEO_CS2_HD_OFFSET(s7) |
|
noerror: |
move v0, zero |
add v1, s0, s1 |
move ra, s8 |
jr ra |
nop |
|
error: |
li v0, HAL_ATLAS_MEMERROR |
move ra, s8 |
jr ra |
nop |
|
FUNC_END(hal_atlas_init_sdram) |
|
## |
## Read a value from the SDRAM SPD device. |
## |
## Parameters: a0 = subaddress |
## Returns: v0 = SPD value read |
## |
FUNC_START(read_spd_value) |
# |
# Setup a base address register |
# |
li a1, CYGARC_UNCACHED_ADDRESS(HAL_GALILEO_PCI0_MEM0_BASE) |
|
# |
# Write the I2C command |
# |
sll a0, 16 |
li t0, (HAL_SAA9730_I2CTFR_ATTR1_CONT | \ |
((0xa0 << 24) | HAL_SAA9730_I2CTFR_ATTR2_START) | \ |
((0xa1 << 8) | HAL_SAA9730_I2CTFR_ATTR0_START)) |
or a0, t0 |
sw a0, HAL_SAA9730_I2CTFR_OFFSET(a1) |
1: lw t0, HAL_SAA9730_I2CTFR_OFFSET(a1) |
and t0, 0x1 |
bnez t0, 1b |
nop |
|
# |
# Read the SPD value |
# |
li a0, HAL_SAA9730_I2CTFR_ATTR2_STOP |
sw a0, HAL_SAA9730_I2CTFR_OFFSET(a1) |
1: lw t0, HAL_SAA9730_I2CTFR_OFFSET(a1) |
and t0, 0x1 |
bnez t0, 1b |
nop |
|
# |
# Setup the return value. |
# |
lw v0, HAL_SAA9730_I2CTFR_OFFSET(a1) |
srl v0, 24 |
|
jr ra |
nop |
FUNC_END(read_spd_value) |
#endif /* defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) */ |
|
##----------------------------------------------------------------------------- |
# Interrupt vector tables. |
# These tables contain the isr, data and object pointers used to deliver |
# interrupts to user code. |
|
.extern hal_default_isr |
|
.data |
|
.globl hal_interrupt_handlers |
hal_interrupt_handlers: |
.rept 25 |
.long hal_default_isr |
.endr |
|
.globl hal_interrupt_data |
hal_interrupt_data: |
.rept 25 |
.long 0 |
.endr |
|
.globl hal_interrupt_objects |
hal_interrupt_objects: |
.rept 25 |
.long 0 |
.endr |
|
|
##----------------------------------------------------------------------------- |
## end of platform.S |
/v2_0/src/hal_diag.c
0,0 → 1,187
/*============================================================================= |
// |
// hal_diag.c |
// |
// HAL diagnostic output code |
// |
//============================================================================= |
//####ECOSGPLCOPYRIGHTBEGIN#### |
// ------------------------------------------- |
// This file is part of eCos, the Embedded Configurable Operating System. |
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
// |
// eCos is free software; you can redistribute it and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
// Software Foundation; either version 2 or (at your option) any later version. |
// |
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
// WARRANTY; without even the implied warranty of MERCHANTABILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with eCos; if not, write to the Free Software Foundation, Inc., |
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
// |
// As a special exception, if other files instantiate templates or use macros |
// or inline functions from this file, or you compile this file and link it |
// with other works to produce a work based on this file, this file does not |
// by itself cause the resulting work to be covered by the GNU General Public |
// License. However the source code for this file must still be made available |
// in accordance with section (3) of the GNU General Public License. |
// |
// This exception does not invalidate any other reasons why a work based on |
// this file might be covered by the GNU General Public License. |
// |
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
// at http://sources.redhat.com/ecos/ecos-license/ |
// ------------------------------------------- |
//####ECOSGPLCOPYRIGHTEND#### |
//============================================================================= |
//#####DESCRIPTIONBEGIN#### |
// |
// Author(s): nickg |
// Contributors: nickg, dmoseley |
// Date: 1998-03-02 |
// Purpose: HAL diagnostic output |
// Description: Implementations of HAL diagnostic output support. |
// |
//####DESCRIPTIONEND#### |
// |
//===========================================================================*/ |
|
#include <pkgconf/hal.h> |
|
#include <cyg/infra/cyg_type.h> // base types |
#include <cyg/infra/cyg_trac.h> // tracing macros |
#include <cyg/infra/cyg_ass.h> // assertion macros |
|
#include <cyg/hal/hal_arch.h> |
#include <cyg/hal/hal_diag.h> |
|
#include <cyg/hal/hal_intr.h> |
|
#include <cyg/hal/hal_io.h> |
|
//----------------------------------------------------------------------------- |
// Select which diag channels to use |
|
//#define CYG_KERNEL_DIAG_LCD |
#define CYG_KERNEL_DIAG_SERIAL |
|
/*---------------------------------------------------------------------------*/ |
|
void hal_diag_led(int x) |
{ |
HAL_WRITE_UINT32(HAL_DISPLAY_LEDBAR, x); |
#if !defined(CYG_KERNEL_DIAG_LCD) |
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIWORD, x); |
#endif |
} |
|
externC void diag_write_string (const char*); |
|
#ifdef CYG_KERNEL_DIAG_SERIAL |
extern void cyg_hal_plf_comms_init(void); |
extern void cyg_hal_plf_serial_putc(void*, cyg_uint8); |
extern cyg_uint8 cyg_hal_plf_serial_getc(void*); |
#endif |
|
void hal_diag_init(void) |
{ |
#if defined(CYGSEM_HAL_ROM_MONITOR) && !defined(CYG_KERNEL_DIAG_SERIAL) |
// It's handy to have the LCD initialized at reset when using it |
// for debugging output. |
// The serial port likely doesn't work yet. Let's wait. |
diag_write_string ("eCos ROM " __TIME__ "\n"); |
diag_write_string (__DATE__ "\n"); |
#endif |
|
#if defined(CYG_KERNEL_DIAG_SERIAL) |
cyg_hal_plf_comms_init(); |
#endif |
} |
|
#if defined(CYG_KERNEL_DIAG_LCD) |
static void hal_diag_clear_lcd(void) |
{ |
volatile int i = 0x20000; |
while (--i) ; |
|
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS0, ' '); |
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS1, ' '); |
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS2, ' '); |
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS3, ' '); |
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS4, ' '); |
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS5, ' '); |
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS6, ' '); |
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS7, ' '); |
} |
#endif /* defined(CYG_KERNEL_DIAG_LCD) */ |
|
void hal_diag_write_char(char c) |
{ |
#if defined(CYG_KERNEL_DIAG_LCD) |
static volatile CYG_WORD* reg = HAL_DISPLAY_ASCIIPOS0; |
#endif |
|
unsigned long __state; |
|
HAL_DISABLE_INTERRUPTS(__state); |
|
if(c == '\n') |
{ |
#if defined(CYG_KERNEL_DIAG_LCD) |
reg = HAL_DISPLAY_ASCIIPOS0; |
hal_diag_clear_lcd(); |
#endif |
#if defined (CYG_KERNEL_DIAG_SERIAL) |
cyg_hal_plf_serial_putc(NULL, '\r'); |
cyg_hal_plf_serial_putc(NULL, '\n'); |
#endif |
} |
else if (c == '\r') |
{ |
// Ignore '\r' |
} |
else |
{ |
#if defined(CYG_KERNEL_DIAG_LCD) |
if (reg == HAL_DISPLAY_ASCIIPOS0) |
hal_diag_clear_lcd(); |
|
HAL_WRITE_UINT32(reg, c); |
|
// Advance to next LED position. |
if (reg == HAL_DISPLAY_ASCIIPOS0) |
reg = HAL_DISPLAY_ASCIIPOS1; |
else if (reg == HAL_DISPLAY_ASCIIPOS1) |
reg = HAL_DISPLAY_ASCIIPOS2; |
else if (reg == HAL_DISPLAY_ASCIIPOS2) |
reg = HAL_DISPLAY_ASCIIPOS3; |
else if (reg == HAL_DISPLAY_ASCIIPOS3) |
reg = HAL_DISPLAY_ASCIIPOS4; |
else if (reg == HAL_DISPLAY_ASCIIPOS4) |
reg = HAL_DISPLAY_ASCIIPOS5; |
else if (reg == HAL_DISPLAY_ASCIIPOS5) |
reg = HAL_DISPLAY_ASCIIPOS6; |
else if (reg == HAL_DISPLAY_ASCIIPOS6) |
reg = HAL_DISPLAY_ASCIIPOS7; |
else // reg == HAL_DISPLAY_ASCIIPOS7 or UNKNOWN |
reg = HAL_DISPLAY_ASCIIPOS0; |
#endif |
#if defined(CYG_KERNEL_DIAG_SERIAL) |
cyg_hal_plf_serial_putc(NULL, c); |
#endif |
} |
|
HAL_RESTORE_INTERRUPTS(__state); |
} |
|
void hal_diag_read_char(char* c) |
{ |
*c = cyg_hal_plf_serial_getc(NULL); |
} |
|
/*---------------------------------------------------------------------------*/ |
/* End of hal_diag.c */ |
/v2_0/src/plf_misc.c
0,0 → 1,412
//========================================================================== |
// |
// plf_misc.c |
// |
// HAL platform miscellaneous functions |
// |
//========================================================================== |
//####ECOSGPLCOPYRIGHTBEGIN#### |
// ------------------------------------------- |
// This file is part of eCos, the Embedded Configurable Operating System. |
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
// |
// eCos is free software; you can redistribute it and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
// Software Foundation; either version 2 or (at your option) any later version. |
// |
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
// WARRANTY; without even the implied warranty of MERCHANTABILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with eCos; if not, write to the Free Software Foundation, Inc., |
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
// |
// As a special exception, if other files instantiate templates or use macros |
// or inline functions from this file, or you compile this file and link it |
// with other works to produce a work based on this file, this file does not |
// by itself cause the resulting work to be covered by the GNU General Public |
// License. However the source code for this file must still be made available |
// in accordance with section (3) of the GNU General Public License. |
// |
// This exception does not invalidate any other reasons why a work based on |
// this file might be covered by the GNU General Public License. |
// |
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
// at http://sources.redhat.com/ecos/ecos-license/ |
// ------------------------------------------- |
//####ECOSGPLCOPYRIGHTEND#### |
//========================================================================== |
//#####DESCRIPTIONBEGIN#### |
// |
// Author(s): nickg |
// Contributors: nickg, jlarmour, dmoseley |
// Date: 2000-06-06 |
// Purpose: HAL miscellaneous functions |
// Description: This file contains miscellaneous functions provided by the |
// HAL. |
// |
//####DESCRIPTIONEND#### |
// |
//========================================================================*/ |
|
#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS |
#include <pkgconf/hal.h> |
|
#include <cyg/infra/cyg_type.h> // Base types |
#include <cyg/infra/cyg_trac.h> // tracing macros |
#include <cyg/infra/cyg_ass.h> // assertion macros |
|
#include <cyg/hal/hal_arch.h> // architectural definitions |
|
#include <cyg/hal/hal_intr.h> // Interrupt handling |
|
#include <cyg/hal/hal_cache.h> // Cache handling |
|
#include <cyg/hal/hal_if.h> |
|
|
#if defined(CYGPKG_IO_PCI) |
#include <cyg/io/pci_hw.h> |
#include <cyg/io/pci.h> |
#endif |
|
/*------------------------------------------------------------------------*/ |
|
#if defined(CYGPKG_CYGMON) |
#include CYGHWR_MEMORY_LAYOUT_H |
extern unsigned long cygmon_memsize; |
#endif |
|
void hal_platform_init(void) |
{ |
HAL_WRITE_UINT32(HAL_DISPLAY_LEDBAR, 0xff); |
#if defined(CYGPKG_CYGMON) |
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS0, ' '); |
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS1, 'C'); |
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS2, 'Y'); |
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS3, 'G'); |
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS4, 'M'); |
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS5, 'O'); |
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS6, 'N'); |
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS7, ' '); |
#elif defined(CYGPKG_REDBOOT) |
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS0, 'R'); |
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS1, 'e'); |
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS2, 'd'); |
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS3, 'B'); |
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS4, 'o'); |
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS5, 'o'); |
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS6, 't'); |
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS7, ' '); |
#else |
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS0, ' '); |
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS1, ' '); |
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS2, 'e'); |
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS3, 'C'); |
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS4, 'o'); |
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS5, 's'); |
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS6, ' '); |
HAL_WRITE_UINT32(HAL_DISPLAY_ASCIIPOS7, ' '); |
#endif |
|
// Set up eCos/ROM interfaces |
hal_if_init(); |
|
HAL_ICACHE_INVALIDATE_ALL(); |
HAL_ICACHE_ENABLE(); |
HAL_DCACHE_INVALIDATE_ALL(); |
HAL_DCACHE_ENABLE(); |
|
#if defined(CYGPKG_CYGMON) |
{ |
// Store the BSP memory info |
unsigned long * ram_real_base = (unsigned long *)0x80000000; |
unsigned long memsize = *ram_real_base; |
// Adjust memsize for the interrupt vectors reserved space |
memsize -= (CYGMEM_REGION_ram - (unsigned long)ram_real_base); |
cygmon_memsize = memsize; |
} |
|
{ |
// |
// Go ahead and enable IM[2] (ie HWInt[0]) so that we get interrupts |
// from the external devices. The device interrupts will still be |
// disabled in the CBUS FPGA interrupt controller, so this will not |
// cause spurious interrupts. |
// It is still up to the device drivers to enable the interrupts in |
// the interrupt controller |
// |
register unsigned long status; |
asm volatile (" mfc0 %0, $12" : "=r" (status) : ); |
status |= SR_IBIT3; |
asm volatile (" mtc0 %0, $12" : : "r" (status)); |
} |
#endif |
} |
|
|
/*------------------------------------------------------------------------*/ |
/* Reset support */ |
|
void hal_atlas_reset(void) |
{ |
*HAL_ATLAS_SOFTRES = HAL_ATLAS_GORESET; |
} |
|
/*------------------------------------------------------------------------*/ |
/* Syscall support */ |
#ifdef CYGPKG_CYGMON |
// Cygmon provides syscall handling for this board |
#include <cyg/hal/hal_stub.h> |
int __get_syscall_num (void) |
{ |
return SIGSYS; |
} |
#endif |
|
|
/*------------------------------------------------------------------------*/ |
/* PCI support */ |
#if defined(CYGPKG_IO_PCI) |
|
#define PCIMEM_START 0x08000000 // PCI memory address |
#define PCIMEM_SIZE 0x10000000 // 256 MByte |
#define PCIIO_START 0x18000000 // PCI io address |
#define PCIIO_SIZE 0x03E00000 // 62 MByte |
|
static int __check_bar(cyg_uint32 addr, cyg_uint32 size) |
{ |
int n; |
|
for (n = 0; n <= 31; n++) |
if (size == (1 << n)) { |
/* Check that address is naturally aligned */ |
if (addr != (addr & ~(size-1))) |
return 0; |
return size - 1; |
} |
return 0; |
} |
|
|
// One-time PCI initialization. |
|
void cyg_hal_plf_pci_init(void) |
{ |
cyg_uint32 bar_ena, start10, start32, end, size; |
cyg_uint8 next_bus; |
|
// Setup for bus mastering |
cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), |
CYG_PCI_CFG_COMMAND, |
CYG_PCI_CFG_COMMAND_IO | |
CYG_PCI_CFG_COMMAND_MEMORY | |
CYG_PCI_CFG_COMMAND_MASTER | |
CYG_PCI_CFG_COMMAND_PARITY | |
CYG_PCI_CFG_COMMAND_SERR); |
|
// Setup latency timer field |
cyg_hal_plf_pci_cfg_write_byte(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), |
CYG_PCI_CFG_LATENCY_TIMER, 6); |
|
// Disable all BARs |
bar_ena = 0x1ff; |
|
// Check for active SCS10 |
start10 = HAL_GALILEO_GETREG(HAL_GALILEO_SCS10_LD_OFFSET) << 21; |
end = ((HAL_GALILEO_GETREG(HAL_GALILEO_SCS10_HD_OFFSET) & 0x7f) + 1) << 21; |
if (end > start10) { |
if ((size = __check_bar(start10, end - start10)) != 0) { |
// Enable BAR |
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_SCS10_SIZE_OFFSET, size); |
bar_ena &= ~HAL_GALILEO_BAR_ENA_SCS10; |
} |
} |
|
// Check for active SCS32 |
start32 = HAL_GALILEO_GETREG(HAL_GALILEO_SCS32_LD_OFFSET) << 21; |
end = ((HAL_GALILEO_GETREG(HAL_GALILEO_SCS32_HD_OFFSET) & 0x7f) + 1) << 21; |
if (end > start32) { |
if ((size = __check_bar(start32, end - start32)) != 0) { |
// Enable BAR |
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_SCS32_SIZE_OFFSET, size); |
bar_ena &= ~HAL_GALILEO_BAR_ENA_SCS32; |
} |
} |
|
bar_ena &= ~HAL_GALILEO_BAR_ENA_SCS10; |
HAL_GALILEO_PUTREG(HAL_GALILEO_BAR_ENA_OFFSET, bar_ena); |
|
|
cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), |
CYG_PCI_CFG_BAR_0, 0xffffffff); |
|
end = cyg_hal_plf_pci_cfg_read_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), |
CYG_PCI_CFG_BAR_0); |
|
cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), |
CYG_PCI_CFG_BAR_0, start10); |
|
|
cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), |
CYG_PCI_CFG_BAR_1, 0xffffffff); |
|
end = cyg_hal_plf_pci_cfg_read_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), |
CYG_PCI_CFG_BAR_1); |
|
cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0), |
CYG_PCI_CFG_BAR_1, start32); |
|
|
#if 0 // FIXME |
|
// SAA9730 was previously initialized just enough to use I2C bus |
// during SDRAM configuration. We reset it here so generic PCI |
// library can deal with it. |
*((volatile unsigned *)(HAL_GALILEO_PCI0_MEM0_BASE + HAL_SAA9730_SYSRESET_OFFSET)) |
= HAL_SAA9730_SYSRESET_ALL; |
#endif |
|
// Configure PCI bus. |
next_bus = 1; |
cyg_pci_set_memory_base(CYGARC_PHYSICAL_ADDRESS(HAL_ATLAS_PCI_MEM0_BASE)); |
cyg_pci_set_io_base(CYGARC_PHYSICAL_ADDRESS(HAL_ATLAS_PCI_IO_BASE)); |
cyg_pci_configure_bus(0, &next_bus); |
} |
|
|
// Check for configuration error. |
static int pci_config_errcheck(void) |
{ |
cyg_uint32 irq; |
|
// Check for master or target abort |
irq = HAL_GALILEO_GETREG(HAL_GALILEO_IRQ_CAUSE_OFFSET); |
|
if (irq & (HAL_GALILEO_IRQCAUSE_MASABT | HAL_GALILEO_IRQCAUSE_TARABT)) { |
// Error. Clear bits. |
HAL_GALILEO_PUTREG(HAL_GALILEO_IRQ_CAUSE_OFFSET, |
~(HAL_GALILEO_IRQCAUSE_MASABT | HAL_GALILEO_IRQCAUSE_TARABT)); |
return 1; |
} |
return 0; |
} |
|
cyg_uint32 cyg_hal_plf_pci_cfg_read_dword (cyg_uint32 bus, |
cyg_uint32 devfn, |
cyg_uint32 offset) |
{ |
cyg_uint32 config_data; |
|
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET, |
HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE | |
(bus << 16) | (devfn << 8) | offset); |
|
config_data = HAL_GALILEO_GETREG(HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET); |
|
if (pci_config_errcheck()) |
return 0xffffffff; |
return config_data; |
} |
|
cyg_uint16 cyg_hal_plf_pci_cfg_read_word (cyg_uint32 bus, |
cyg_uint32 devfn, |
cyg_uint32 offset) |
{ |
cyg_uint32 config_dword; |
|
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET, |
HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE | |
(bus << 16) | (devfn << 8) | (offset & ~3)); |
|
config_dword = HAL_GALILEO_GETREG(HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET); |
|
if (pci_config_errcheck()) |
return 0xffff; |
return (cyg_uint16)((config_dword >> ((offset & 3) * 8)) & 0xffff); |
} |
|
cyg_uint8 cyg_hal_plf_pci_cfg_read_byte (cyg_uint32 bus, |
cyg_uint32 devfn, |
cyg_uint32 offset) |
{ |
cyg_uint32 config_dword; |
|
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET, |
HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE | |
(bus << 16) | (devfn << 8) | (offset & ~3)); |
|
config_dword = HAL_GALILEO_GETREG(HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET); |
|
if (pci_config_errcheck()) |
return 0xff; |
return (cyg_uint8)((config_dword >> ((offset & 3) * 8)) & 0xff); |
} |
|
void cyg_hal_plf_pci_cfg_write_dword (cyg_uint32 bus, |
cyg_uint32 devfn, |
cyg_uint32 offset, |
cyg_uint32 data) |
{ |
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET, |
HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE | |
(bus << 16) | (devfn << 8) | offset); |
|
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET, data); |
|
(void)pci_config_errcheck(); |
} |
|
void cyg_hal_plf_pci_cfg_write_word (cyg_uint32 bus, |
cyg_uint32 devfn, |
cyg_uint32 offset, |
cyg_uint16 data) |
{ |
cyg_uint32 config_dword, shift; |
|
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET, |
HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE | |
(bus << 16) | (devfn << 8) | (offset & ~3)); |
|
config_dword = HAL_GALILEO_GETREG(HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET); |
if (pci_config_errcheck()) |
return; |
|
shift = (offset & 3) * 8; |
config_dword &= ~(0xffff << shift); |
config_dword |= (data << shift); |
|
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET, config_dword); |
|
(void)pci_config_errcheck(); |
} |
|
void cyg_hal_plf_pci_cfg_write_byte (cyg_uint32 bus, |
cyg_uint32 devfn, |
cyg_uint32 offset, |
cyg_uint8 data) |
{ |
cyg_uint32 config_dword, shift; |
|
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET, |
HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE | |
(bus << 16) | (devfn << 8) | (offset & ~3)); |
|
config_dword = HAL_GALILEO_GETREG(HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET); |
if (pci_config_errcheck()) |
return; |
|
shift = (offset & 3) * 8; |
config_dword &= ~(0xff << shift); |
config_dword |= (data << shift); |
|
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET, config_dword); |
|
(void)pci_config_errcheck(); |
} |
#endif // defined(CYGPKG_IO_PCI) |
|
/*------------------------------------------------------------------------*/ |
/* End of plf_misc.c */ |
/v2_0/ChangeLog
0,0 → 1,258
2003-05-08 Nick Garnett <nickg@balti.calivar.com> |
|
* cdl/hal_mips_atlas.cdl: Change default_value of |
CYGSEM_HAL_ROM_MONITOR to zero. |
|
2003-04-29 Nick Garnett <nickg@balti.calivar.com> |
|
* cdl/hal_mips_atlas.cdl: Changed default startup from ROM to |
RAM. |
Also fixed component description. |
|
2003-02-27 Nick Garnett <nickg@calivar.com> |
|
* include/plf_intr.h: Defined CYGNUM_HAL_INTERRUPT_RTC to |
counter/compare register interrupt. Added implementations of |
HAL_INTERRUPT_MASK, HAL_INTERRUPT_UNMASK, and |
HAL_INTERRUPT_ACKNOWLEDGE that will work in eCos rather than just |
RedBoot. |
|
* src/plf_misc.c (hal_platform_init): Changed spelling of eCos for |
the LED to match the official typography. |
|
2002-08-06 Gary Thomas <gary@chez-thomas.org> |
2002-08-06 Motoya Kurotsu <kurotsu@allied-telesis.co.jp> |
|
* src/ser16c550c.c: I/O channel data can't be constant - contains |
timeout information which can be changed. |
|
2001-10-31 Jonathan Larmour <jlarmour@redhat.com> |
|
* cdl/hal_mips_atlas.cdl: Indicate support of variable baud rates. |
|
2001-07-20 David Woodhouse <dwmw2@redhat.com> |
|
* src/redboot_cmds.c: Remove. Obsoleted by generic MIPS version. |
* cdl/hal_mips_atlas.cdl: Remove reference to $1 |
|
2001-04-27 Mark Salter <msalter@redhat.com> |
|
* include/platform.inc (hal_intc_decode): Recognize all external |
interrupts. |
* include/plf_intr.h: Add external interrupts to list of supported |
interrupts. |
* src/platform.S: Allocate space for new interrupt vectors. |
|
2001-03-09 Jesper Skov <jskov@redhat.com> |
|
* src/redboot_cmds.c: Added (linux) exec command. |
* cdl/hal_mips_atlas.cdl: Build redboot cmd file. |
|
2001-03-08 Jesper Skov <jskov@redhat.com> |
|
* cdl/hal_mips_atlas.cdl: Removed |
CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT_GUARANTEED which is now the |
default. |
|
2001-02-23 Gary Thomas <gthomas@redhat.com> |
|
* misc/redboot_ROM.ecm: Renamed from redboot_ROM.cfg |
|
* misc/redboot_RAM.ecm: Renamed from redboot_RAM.cfg |
|
2001-02-19 Nick Garnett <nickg@cygnus.co.uk> |
|
* src/ser16c550c.c (cyg_hal_plf_serial_isr): Removed enable of |
interrupt under RedBoot, apparrently RedBoot already does this |
itself. |
|
2001-02-15 Nick Garnett <nickg@cygnus.co.uk> |
|
* src/ser16c550c.c (cyg_hal_plf_serial_isr): Added code to set up |
ctrl-c interrupt when in RedBoot. |
|
* src/platform.S: |
Added interrupt vector tables. |
|
* include/plf_io.h: |
Moved interrupt controller defines here from plf_intr.h. |
|
* include/plf_intr.h: |
Renumbered interrupts to make them correspond to the bits in the |
interrupt controller registers. Removed _MASK defines and |
CYGNUM_HAL_INTERRUPT_MASK() macro - now done with a shift. |
Moved intc register defines to plf_io.h. |
|
* include/platform.inc: |
Added INITIAL_SR_PLF to permit interrupts for INTN[0]. |
Added local interrupt decode and init macros. |
|
2001-02-08 Jesper Skov <jskov@redhat.com> |
|
* cdl/hal_mips_atlas.cdl: Respect channel configuration |
constraints. |
|
2001-01-31 Nick Garnett <nickg@cygnus.co.uk> |
|
* src/ser16c550c.c (cyg_hal_plf_serial_init_channel): |
Added enable of RTS line so that it is compatible with YAMON, |
which uses hardware flow control. The main effect of this is to |
avoid having to switch flow control on the host during |
development. |
|
* misc/redboot_ROM.cfg: |
* misc/redboot_RAM.cfg: |
Removed requirement for MIPS32 package. |
Enabled CYGSEM_REDBOOT_BSP_SYSCALLS. |
|
* cdl/hal_mips_atlas.cdl: |
Reorganized define_proc so that we can choose the right value for |
CYGBLD_HAL_TARGET_H depending on MIPS32 or MIPS64 target. |
Moved build options out to relevant variant HALs. |
|
2001-01-26 Jesper Skov <jskov@redhat.com> |
|
* src/hal_diag.c: Removed CYGSEM_HAL_VIRTUAL_VECTOR_DIAG check. |
* include/plf_stub.h: Reset macros moved |
* include/plf_intr.h: to this file. |
|
2000-12-22 Bart Veer <bartv@redhat.com> |
(Patch supplied by Mark Salter) |
* include/pkgconf/mlt_mips_atlas_*.h, *.mlt, *.ldi |
More address changes. |
|
2000-12-21 Mark Salter <msalter@redhat.com> |
|
* include/pkgconf/mlt_mips_atlas_ram.mlt: |
Change ram origin and length. |
|
* include/pkgconf/mlt_mips_atlas_ram.ldi: |
* include/pkgconf/mlt_mips_atlas_ram.h: |
Regenerated. |
|
* misc/redboot_RAM.cfg: New file. |
* misc/redboot_ROM.cfg: New file. |
|
* src/ser16c550c.c: Add support for |
CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD |
|
* include/plf_io.h: Add PCI support. |
* src/platform.S: Ditto. |
* src/plf_misc.c: Ditto. |
|
* cdl/hal_mips_atlas.cdl: Add CYGPKG_REDBOOT_HAL_OPTIONS. |
Add -msoft-float flag. Add RTC constants. Change default |
baud to 115200. |
|
2000-12-05 Drew Moseley <dmoseley@redhat.com> |
|
* include/platform.inc: Rewrite the memory controller initialization. |
* include/plf_io.h: Ditto. |
* src/platform.S: Ditto. |
|
* cdl/hal_mips_atlas.cdl: Do not build the binary image. |
|
2000-10-20 Jonathan Larmour <jlarmour@redhat.com> |
|
* include/pkgconf/mlt_mips_atlas_rom.mlt: |
Reinstate padding to 0x40 |
|
* include/pkgconf/mlt_mips_atlas_rom.ldi: |
Regenerated |
|
2000-10-20 Jesper Skov <jskov@redhat.com> |
|
* include/plf_io.h: Move volatile keyword before type. |
* src/hal_diag.c: Same. |
|
2000-10-20 Jonathan Larmour <jlarmour@redhat.com> |
|
* include/pkgconf/mlt_mips_atlas_ram.mlt: |
* include/pkgconf/mlt_mips_atlas_rom.mlt: |
Add heap1 section |
|
* include/pkgconf/mlt_mips_atlas_ram.h: |
* include/pkgconf/mlt_mips_atlas_rom.h: |
* include/pkgconf/mlt_mips_atlas_ram.ldi: |
* include/pkgconf/mlt_mips_atlas_rom.ldi: |
Regenerated |
|
2000-08-14 Drew Moseley <dmoseley@redhat.com> |
|
* src/plf_misc.c (__get_syscall_num): Only define this function if |
CYGPKG_CYGMON is defined since Cygmon is the one providing syscall |
handling in this case. |
|
2000-08-10 Drew Moseley <dmoseley@redhat.com> |
|
* cdl/hal_mips_atlas.cdl: Implement STUBS_BREAK and |
CYGSEM_HAL_ROM_MONITOR. |
|
* src/plf_misc.c: Cleanup. |
|
2000-07-21 Drew Moseley <dmoseley@redhat.com> |
|
* include/platform.inc: Define CYGARC_START_FUNC_UNCACHED so vectors.S |
will jump to _start at the uncached address. |
|
2000-07-21 Drew Moseley <dmoseley@cygnus.com> |
|
* src/plf_misc.c: Rearrange the linkage between Cygmon and HAL so |
that Cygmon needs HAL but not vice-versa. ie HAL no longer calls |
any Cygmon functions. |
|
2000-07-14 Drew Moseley <dmoseley@redhat.com> |
|
* cdl/hal_mips_atlas.cdl: New file. New platform support |
* include/hal_diag.h: Ditto. |
* include/platform.inc: Ditto. |
* include/plf_cache.h: Ditto. |
* include/plf_intr.h: Ditto. |
* include/plf_io.h: Ditto. |
* include/plf_stub.h: Ditto. |
* include/pkgconf/mlt_mips_atlas_ram.h: Ditto. |
* include/pkgconf/mlt_mips_atlas_ram.ldi: Ditto. |
* include/pkgconf/mlt_mips_atlas_ram.mlt: Ditto. |
* include/pkgconf/mlt_mips_atlas_rom.h: Ditto. |
* include/pkgconf/mlt_mips_atlas_rom.ldi: Ditto. |
* include/pkgconf/mlt_mips_atlas_rom.mlt: Ditto. |
* src/hal_diag.c: Ditto. |
* src/makefile: Ditto. |
* src/platform.S: Ditto. |
* src/plf_misc.c: Ditto. |
* src/ser16c550c.c: Ditto. |
|
//=========================================================================== |
//####ECOSGPLCOPYRIGHTBEGIN#### |
// ------------------------------------------- |
// This file is part of eCos, the Embedded Configurable Operating System. |
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
// |
// eCos is free software; you can redistribute it and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
// Software Foundation; either version 2 or (at your option) any later version. |
// |
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
// WARRANTY; without even the implied warranty of MERCHANTABILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with eCos; if not, write to the Free Software Foundation, Inc., |
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
// |
// As a special exception, if other files instantiate templates or use macros |
// or inline functions from this file, or you compile this file and link it |
// with other works to produce a work based on this file, this file does not |
// by itself cause the resulting work to be covered by the GNU General Public |
// License. However the source code for this file must still be made available |
// in accordance with section (3) of the GNU General Public License. |
// |
// This exception does not invalidate any other reasons why a work based on |
// this file might be covered by the GNU General Public License. |
// |
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
// at http://sources.redhat.com/ecos/ecos-license/ |
// ------------------------------------------- |
//####ECOSGPLCOPYRIGHTEND#### |
//=========================================================================== |
/v2_0/misc/redboot_RAM.ecm
0,0 → 1,73
cdl_savefile_version 1; |
cdl_savefile_command cdl_savefile_version {}; |
cdl_savefile_command cdl_savefile_command {}; |
cdl_savefile_command cdl_configuration { description hardware template package }; |
cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; |
cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; |
cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; |
cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; |
|
cdl_configuration eCos { |
description "" ; |
hardware atlas ; |
template redboot ; |
package -hardware CYGPKG_HAL_MIPS v2_0 ; |
package -hardware CYGPKG_HAL_MIPS_ATLAS v2_0 ; |
package -hardware CYGPKG_IO_PCI v2_0 ; |
package -hardware CYGPKG_DEVS_ETH_MIPS_ATLAS v2_0 ; |
package -hardware CYGPKG_IO_SERIAL_MIPS_ATLAS v2_0 ; |
package -hardware CYGPKG_DEVS_FLASH_ATLAS v2_0 ; |
package -template CYGPKG_HAL v2_0 ; |
package -template CYGPKG_INFRA v2_0 ; |
package -template CYGPKG_REDBOOT v2_0 ; |
package CYGPKG_IO_FLASH v2_0 ; |
package CYGPKG_IO_ETH_DRIVERS v2_0 ; |
}; |
|
cdl_option CYGBLD_BUILD_GDB_STUBS { |
user_value 0 |
}; |
|
cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { |
user_value 0 |
}; |
|
cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { |
inferred_value 0 |
}; |
|
cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { |
inferred_value 1 |
}; |
|
cdl_option CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT { |
inferred_value 1 |
}; |
|
cdl_option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT { |
inferred_value 0 |
}; |
|
cdl_option CYGSEM_HAL_USE_ROM_MONITOR { |
inferred_value 0 0 |
}; |
|
cdl_component CYG_HAL_STARTUP { |
user_value RAM |
}; |
|
cdl_option CYGBLD_BUILD_REDBOOT { |
user_value 1 |
}; |
|
#cdl_option CYGSEM_REDBOOT_FLASH_CONFIG { |
# user_value 1 |
#}; |
|
cdl_option CYGSEM_REDBOOT_BSP_SYSCALLS { |
user_value 1 |
}; |
|
cdl_option CYGBLD_REDBOOT_FLASH_BOOT_OFFSET { |
inferred_value 0x1C00000 |
}; |
/v2_0/misc/redboot_ROM.ecm
0,0 → 1,77
cdl_savefile_version 1; |
cdl_savefile_command cdl_savefile_version {}; |
cdl_savefile_command cdl_savefile_command {}; |
cdl_savefile_command cdl_configuration { description hardware template package }; |
cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; |
cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; |
cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; |
cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; |
|
cdl_configuration eCos { |
description "" ; |
hardware atlas ; |
template redboot ; |
package -hardware CYGPKG_HAL_MIPS v2_0 ; |
package -hardware CYGPKG_HAL_MIPS_ATLAS v2_0 ; |
package -hardware CYGPKG_IO_PCI v2_0 ; |
package -hardware CYGPKG_DEVS_ETH_MIPS_ATLAS v2_0 ; |
package -hardware CYGPKG_IO_SERIAL_MIPS_ATLAS v2_0 ; |
package -hardware CYGPKG_DEVS_FLASH_ATLAS v2_0 ; |
package -template CYGPKG_HAL v2_0 ; |
package -template CYGPKG_INFRA v2_0 ; |
package -template CYGPKG_REDBOOT v2_0 ; |
package CYGPKG_IO_FLASH v2_0 ; |
package CYGPKG_IO_ETH_DRIVERS v2_0 ; |
}; |
|
cdl_option CYGBLD_BUILD_GDB_STUBS { |
user_value 0 |
}; |
|
cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { |
user_value 0 |
}; |
|
cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { |
inferred_value 0 |
}; |
|
cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { |
inferred_value 1 |
}; |
|
cdl_option CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT { |
inferred_value 1 |
}; |
|
cdl_option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT { |
inferred_value 0 |
}; |
|
cdl_option CYGSEM_HAL_ROM_MONITOR { |
user_value 1 |
}; |
|
cdl_option CYGSEM_HAL_USE_ROM_MONITOR { |
inferred_value 0 0 |
}; |
|
cdl_component CYG_HAL_STARTUP { |
user_value ROM |
}; |
|
cdl_option CYGBLD_BUILD_REDBOOT { |
user_value 1 |
}; |
|
cdl_option CYGSEM_REDBOOT_FLASH_CONFIG { |
user_value 1 |
}; |
|
cdl_option CYGSEM_REDBOOT_BSP_SYSCALLS { |
user_value 1 |
}; |
|
cdl_option CYGBLD_REDBOOT_FLASH_BOOT_OFFSET { |
inferred_value 0x1C00000 |
}; |