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Rev 27 → Rev 174

/var_cache.h
0,0 → 1,308
#ifndef CYGONCE_VAR_CACHE_H
#define CYGONCE_VAR_CACHE_H
//=============================================================================
//
// var_cache.h
//
// HAL cache control API
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): tmichals
// Contributors: nickg, dmoseley
// Date: 2003-02-13
// Purpose: Cache control API
// Description: The macros defined here provide the HAL APIs for handling
// cache control operations.
// Usage:
// #include <cyg/hal/var_cache.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>
 
#include <cyg/hal/mips-regs.h>
#include <cyg/hal/hal_arch.h>
#include <cyg/hal/plf_cache.h>
#include <cyg/hal/var_arch.h>
 
 
 
//-----------------------------------------------------------------------------
// Cache dimensions
 
// Data cache
#define HAL_DCACHE_SIZE (1024 *8) // Size of data cache in bytes
#define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
#define HAL_DCACHE_WAYS 4 // Associativity of the cache
 
// Instruction cache
#define HAL_ICACHE_SIZE (1024*16) // Size of cache in bytes
#define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
#define HAL_ICACHE_WAYS 4 // Associativity of the cache
 
#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
 
#define HAL_DCACHE_WRITETHRU_MODE 1
#define HAL_DCACHE_WRITEBACK_MODE 0
 
//-----------------------------------------------------------------------------
// General cache defines.
#define HAL_CLEAR_TAGLO() asm volatile (" mtc0 $0, $28;" \
" nop;" \
" nop;" \
" nop;")
#define HAL_CLEAR_TAGHI() asm volatile (" mtc0 $0, $29;" \
" nop;" \
" nop;" \
" nop;")
 
/* Cache instruction opcodes */
#define HAL_CACHE_OP(which, op) (which | (op << 2))
 
#define HAL_WHICH_ICACHE 0x0
#define HAL_WHICH_DCACHE 0x1
 
#define HAL_INDEX_INVALIDATE 0x0
#define HAL_INDEX_LOAD_TAG 0x1
#define HAL_INDEX_STORE_TAG 0x2
#define HAL_HIT_INVALIDATE 0x4
#define HAL_ICACHE_FILL 0x5
#define HAL_DCACHE_HIT_INVALIDATE 0x5
#define HAL_DCACHE_HIT_WRITEBACK 0x6
#define HAL_FETCH_AND_LOCK 0x7
 
//-----------------------------------------------------------------------------
// Global control of data cache
 
// Invalidate the entire cache
#define HAL_DCACHE_INVALIDATE_ALL_DEFINED
#define HAL_DCACHE_INVALIDATE_ALL() \
CYG_MACRO_START \
register volatile CYG_BYTE *addr; \
HAL_CLEAR_TAGLO(); \
HAL_CLEAR_TAGHI(); \
for (addr = (CYG_BYTE *)CYGARC_KSEG_CACHED_BASE; \
addr < (CYG_BYTE *)(CYGARC_KSEG_CACHED_BASE + HAL_DCACHE_SIZE); \
addr += HAL_DCACHE_LINE_SIZE ) \
{ \
asm volatile (" cache %0, 0(%1)" \
: \
: "I" (HAL_CACHE_OP(HAL_WHICH_DCACHE, HAL_INDEX_STORE_TAG)), \
"r"(addr)); \
} \
CYG_MACRO_END
 
// Synchronize the contents of the cache with memory.
__externC void hal_dcache_sync(void);
#define HAL_DCACHE_SYNC_DEFINED
#define HAL_DCACHE_SYNC() hal_dcache_sync()
 
// Set the data cache refill burst size
//#define HAL_DCACHE_BURST_SIZE(_asize_)
 
// Set the data cache write mode
//#define HAL_DCACHE_WRITE_MODE( _mode_ )
 
// Load the contents of the given address range into the data cache
// and then lock the cache so that it stays there.
#define HAL_DCACHE_LOCK_DEFINED
#define HAL_DCACHE_LOCK(_base_, _asize_) \
CYG_MACRO_START \
register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
register CYG_WORD _size_ = (_asize_); \
for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
asm volatile (" cache %0, 0(%1)" \
: \
: "I" (HAL_CACHE_OP(HAL_WHICH_DCACHE, HAL_FETCH_AND_LOCK)), \
"r"(_addr_)); \
CYG_MACRO_END
 
// Undo a previous lock operation
#define HAL_DCACHE_UNLOCK_DEFINED
#define HAL_DCACHE_UNLOCK(_base_, _asize_) \
CYG_MACRO_START \
register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
register CYG_WORD _size_ = (_asize_); \
for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
asm volatile (" cache %0, 0(%1)" \
: \
: "I" (HAL_CACHE_OP(HAL_WHICH_DCACHE, HAL_HIT_INVALIDATE)), \
"r"(_addr_)); \
CYG_MACRO_END
 
// Unlock entire cache
#define HAL_DCACHE_UNLOCK_ALL_DEFINED
#define HAL_DCACHE_UNLOCK_ALL() HAL_DCACHE_UNLOCK(0,HAL_DCACHE_SIZE)
 
 
//-----------------------------------------------------------------------------
// Data cache line control
 
// Allocate cache lines for the given address range without reading its
// contents from memory.
//#define HAL_DCACHE_ALLOCATE( _base_ , _asize_ )
 
// Write dirty cache lines to memory and invalidate the cache entries
// for the given address range.
#define HAL_DCACHE_FLUSH_DEFINED
#if HAL_DCACHE_WRITETHRU_MODE == 1
// No need to flush a writethrough cache
#define HAL_DCACHE_FLUSH( _base_ , _asize_ )
#else
#error HAL_DCACHE_FLUSH undefined for MIPS32 writeback cache
#endif
 
// Write dirty cache lines to memory for the given address range.
#define HAL_DCACHE_STORE_DEFINED
#if HAL_DCACHE_WRITETHRU_MODE == 1
// No need to store a writethrough cache
#define HAL_DCACHE_STORE( _base_ , _asize_ )
#else
#error HAL_DCACHE_STORE undefined for MIPS32 writeback cache
#endif
 
// Invalidate cache lines in the given range without writing to memory.
#define HAL_DCACHE_INVALIDATE_DEFINED
#define HAL_DCACHE_INVALIDATE( _base_ , _asize_ ) \
CYG_MACRO_START \
register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
register CYG_WORD _size_ = (_asize_); \
for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
asm volatile (" cache %0, 0(%1)" \
: \
: "I" (HAL_CACHE_OP(HAL_WHICH_DCACHE, HAL_HIT_INVALIDATE)), \
"r"(_addr_)); \
CYG_MACRO_END
 
 
 
 
 
 
//-----------------------------------------------------------------------------
// Global control of Instruction cache
 
// Invalidate the entire cache
#define HAL_ICACHE_INVALIDATE_ALL_DEFINED
#define HAL_ICACHE_INVALIDATE_ALL() \
CYG_MACRO_START \
register volatile CYG_BYTE *addr; \
HAL_CLEAR_TAGLO(); \
HAL_CLEAR_TAGHI(); \
for (addr = (CYG_BYTE *)CYGARC_KSEG_CACHED_BASE; \
addr < (CYG_BYTE *)(CYGARC_KSEG_CACHED_BASE + HAL_ICACHE_SIZE); \
addr += HAL_ICACHE_LINE_SIZE ) \
{ \
asm volatile (" cache %0, 0(%1)" \
: \
: "I" (HAL_CACHE_OP(HAL_WHICH_ICACHE, HAL_INDEX_STORE_TAG)), \
"r"(addr)); \
} \
CYG_MACRO_END
 
// Synchronize the contents of the cache with memory.
//extern void hal_icache_sync(void);
//#define HAL_ICACHE_SYNC_DEFINED
//#define HAL_ICACHE_SYNC() hal_icache_sync()
 
// Set the instruction cache refill burst size
//#define HAL_ICACHE_BURST_SIZE(_asize_)
 
// Load the contents of the given address range into the data cache
// and then lock the cache so that it stays there.
#define HAL_ICACHE_LOCK_DEFINED
#define HAL_ICACHE_LOCK(_base_, _asize_) \
CYG_MACRO_START \
register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
register CYG_WORD _size_ = (_asize_); \
for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
asm volatile (" cache %0, 0(%1)" \
: \
: "I" (HAL_CACHE_OP(HAL_WHICH_ICACHE, HAL_FETCH_AND_LOCK)), \
"r"(_addr_)); \
CYG_MACRO_END
 
// Undo a previous lock operation
#define HAL_ICACHE_UNLOCK_DEFINED
#define HAL_ICACHE_UNLOCK(_base_, _asize_) \
CYG_MACRO_START \
register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
register CYG_WORD _size_ = (_asize_); \
for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
asm volatile (" cache %0, 0(%1)" \
: \
: "I" (HAL_CACHE_OP(HAL_WHICH_ICACHE, HAL_HIT_INVALIDATE)), \
"r"(_addr_)); \
CYG_MACRO_END
 
// Unlock entire cache
#define HAL_ICACHE_UNLOCK_ALL_DEFINED
#define HAL_ICACHE_UNLOCK_ALL() HAL_ICACHE_UNLOCK(0,HAL_ICACHE_SIZE)
 
//-----------------------------------------------------------------------------
// Instruction cache line control
 
// Invalidate cache lines in the given range without writing to memory.
#define HAL_ICACHE_INVALIDATE_DEFINED
#define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \
CYG_MACRO_START \
register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
register CYG_WORD _size_ = (_asize_); \
for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
asm volatile (" cache %0, 0(%1)" \
: \
: "I" (HAL_CACHE_OP(HAL_WHICH_ICACHE, HAL_HIT_INVALIDATE)), \
"r"(_addr_)); \
CYG_MACRO_END
 
//-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_VAR_CACHE_H
// End of var_cache.h
/var_intr.h
0,0 → 1,69
#ifndef CYGONCE_HAL_VAR_INTR_H
#define CYGONCE_HAL_VAR_INTR_H
//==========================================================================
//
// var_intr.h
//
// IDT 3233x Interrupt and clock support
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): tmichals
// Contributors: tmichals
// Date: 2002-09-20
// Purpose: IDT3233x Interrupt support
// Description: The macros defined here provide the HAL APIs for handling
// interrupts and the clock for variants of the IDT3233x MIPS
// architecture.
//
// Usage:
// #include <cyg/hal/var_intr.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>
#include <cyg/hal/plf_intr.h>
 
 
//--------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_VAR_INTR_H
// End of var_intr.h
/var_arch.h
0,0 → 1,73
#ifndef CYGONCE_HAL_VAR_ARCH_H
#define CYGONCE_HAL_VAR_ARCH_H
 
//==========================================================================
//
// var_arch.h
//
// Architecture specific abstractions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): tmichals
// Contributors:
// Date: 2003-02-13
// Purpose: Define architecture abstractions
// Description: This file contains any extra or modified definitions for
// this variant of the architecture.
// Usage: #include <cyg/hal/var_arch.h>
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>
 
#ifdef CYGSEM_HAL_USE_ROM_MONITOR_CygMon
externC int
hal_diag_irq_check(int vector);
 
#define HAL_DIAG_IRQ_CHECK(_vector_, _ret_) \
CYG_MACRO_START \
_ret_ = hal_diag_irq_check((_vector_)); \
CYG_MACRO_END
#endif
 
//--------------------------------------------------------------------------
#endif // CYGONCE_HAL_VAR_ARCH_H
// End of var_arch.h
/variant.inc
0,0 → 1,249
#ifndef CYGONCE_HAL_VARIANT_INC
#define CYGONCE_HAL_VARIANT_INC
##=============================================================================
##
## variant.inc
##
## IDT32334 family assembler header file
##
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
##=============================================================================
#######DESCRIPTIONBEGIN####
##
## Author(s): tmichals
## Contributors: nickg
## Date: 2003-02-13
## Purpose: MIPS IDT32334 family definitions.
## Description: This file contains various definitions and macros that are
## useful for writing assembly code for the MIPS IDT32334 CPU family.
## Usage:
## #include <cyg/hal/variant.inc>
## ...
##
##
######DESCRIPTIONEND####
##
##=============================================================================
 
#include <pkgconf/hal.h>
#include <cyg/hal/mips.inc>
#include <cyg/hal/platform.inc>
 
#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
#ifndef __ASSEMBLER__
#define __ASSEMBLER__
#endif
//#include <cyg/hal/mips-regs.h>
 
#define CYGARC_ADDRESS_REG_UNCACHED(reg) \
and reg, reg, ~CYGARC_KSEG_MASK; \
or reg, reg, CYGARC_KSEG_UNCACHED
 
#define CYGARC_KSEG_MASK (0xE0000000)
#define CYGARC_KSEG_CACHED (0x80000000)
#define CYGARC_KSEG_UNCACHED (0xA0000000)
#define CYGARC_KSEG_CACHED_BASE (0x80000000)
#define CYGARC_KSEG_UNCACHED_BASE (0xA0000000)
 
 
 
//-----------------------------------------------------------------------------
// Load Address and Relocate. This macro is used in code that may be
// linked to execute out of RAM but is actually executed from ROM. The
// code that initializes the memory controller and copies the ROM
// contents to RAM must work in this way, for example. This macro is used
// in place of an "la" macro instruction when loading code and data
// addresses. There are two versions of the macro here. The first
// assumes that we are executing in the ROM space at 0xbfc00000 and are
// linked to run in the RAM space at 0x80000000. It simply adds the
// difference between the two to the loaded address. The second is more
// code, but will execute correctly at either location since it
// calculates the difference at runtime. The second variant is enabled
// by default.
 
 
#ifdef CYG_HAL_STARTUP_ROMRAM
 
.macro lar reg,addr
.set noat
move $at,ra # save ra
la \reg,\addr # get address into register
la ra,x\@ # get linked address of label
sub \reg,\reg,ra # subtract it from value
bal x\@ # branch and link to label
nop # to get current actual address
x\@:
add \reg,\reg,ra # add actual address
move ra,$at # restore ra
.set at
.endm
#define CYGPKG_HAL_MIPS_LAR_DEFINED
 
#endif
 
 
#------------------------------------------------------------------------------
# Cache macros.
#ifndef CYGPKG_HAL_MIPS_CACHE_DEFINED
 
.macro hal_cache_init
 
# Setup a temporary stack pointer for running C code.
la a0,__interrupt_stack
move sp,a0
CYGARC_ADDRESS_REG_UNCACHED(sp)
# Read the CONFIG1 register into a0
# mfc0 a0, C0_CONFIG
nop
nop
nop
 
# Jump to C-code to initialize caches (uncached)
lar k0, hal_c_cache_init
CYGARC_ADDRESS_REG_UNCACHED(k0)
jalr k0
nop
.endm
 
#define CYGPKG_HAL_MIPS_CACHE_DEFINED
 
#endif
 
 
##-----------------------------------------------------------------------------
## Define CPU variant for architecture HAL.
 
##-----------------------------------------------------------------------------
## Indicate that the ISR tables are defined in variant.S
 
#define CYG_HAL_MIPS_ISR_TABLES_DEFINED
 
##-----------------------------------------------------------------------------
##
 
#ifndef CYGPKG_HAL_MIPS_MEMC_DEFINED
 
## ROM timing characteristics are dependent on the clock speed.
 
.macro hal_memc_init
.endm
 
 
 
#define CYGPKG_HAL_MIPS_MEMC_DEFINED
#endif
##-----------------------------------------------------------------------------
## IDT32334 interrupt handling.
 
#ifndef CYGPKG_HAL_MIPS_INTC_DEFINED
 
 
 
# Set all ILRX registers to 0, masking all external interrupts.
.macro hal_intc_init
.endm
 
.macro hal_intc_decode vnum
mfc0 v1,cause
nop
mfc0 v0,status
nop
and v1,v0,v1
srl v1,v1,11 # shift IP bits to ls bits
andi v1,v1,0x7F # isolate IP bits
la v0,hal_intc_translation_table # address of translation table
add v0,v0,v1 # offset of index byte
lb \vnum,0(v0) # load it
.endm
 
#ifndef CYGPKG_HAL_MIPS_INTC_TRANSLATE_DEFINED
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
.macro hal_intc_translate inum,vnum
move \vnum,zero # Just vector zero is supported
.endm
#else
.macro hal_intc_translate inum,vnum
move \vnum,\inum # Vector == interrupt number
.endm
#endif
#endif
 
# This table translates from the 6 bit value supplied in the IP bits
# of the cause register into a 0..16 offset into the ISR tables.
.macro hal_intc_decode_data
hal_intc_translation_table:
 
.byte 0,1,0,0,3,3,0,0
.byte 0,0,0,0,0,0,0,0
.byte 5,5,0,0,0,5,0,0
.byte 0,0,0,0,0,0,0,0
.byte 0,0,0,0,0,0,0,0
.byte 0,0,0,0,0,0,0,0
.byte 0,0,0,0,0,0,0,0
.byte 0,0,0,0,0,0,0,0
.endm
 
#define CYGPKG_HAL_MIPS_INTC_DEFINED
 
#endif
 
#------------------------------------------------------------------------------
# Diagnostics macros.
#if 0
#ifndef CYGPKG_HAL_MIPS_DIAG_DEFINED
 
# Set up PIO0 for debugging output
.macro hal_diag_init
.endm
 
#define CYGPKG_HAL_MIPS_DIAG_DEFINED
#endif
#endif
 
#------------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_VARIANT_INC
# end of variant.inc

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