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Rev 27 → Rev 174

/var_cache.h
0,0 → 1,314
#ifndef CYGONCE_IMP_CACHE_H
#define CYGONCE_IMP_CACHE_H
 
//=============================================================================
//
// imp_cache.h
//
// HAL cache control API
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors: nickg, dmoseley
// Date: 1998-02-17
// Purpose: Cache control API
// Description: The macros defined here provide the HAL APIs for handling
// cache control operations.
// Usage:
// #include <cyg/hal/imp_cache.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>
 
#include <cyg/hal/mips-regs.h>
#include <cyg/hal/hal_arch.h>
#include <cyg/hal/plf_cache.h>
#include <cyg/hal/var_arch.h>
 
#ifdef CYGHWR_HAL_MIPS_MIPS32_CORE_4Kc
 
//-----------------------------------------------------------------------------
// Cache dimensions
 
// Data cache
#define HAL_DCACHE_SIZE 16384 // Size of data cache in bytes
#define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
#define HAL_DCACHE_WAYS 4 // Associativity of the cache
 
// Instruction cache
#define HAL_ICACHE_SIZE 16384 // Size of cache in bytes
#define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
#define HAL_ICACHE_WAYS 4 // Associativity of the cache
 
#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
 
#define HAL_DCACHE_WRITETHRU_MODE 1
#define HAL_DCACHE_WRITEBACK_MODE 0
 
#else
 
#error Unknown MIPS32 Variant
 
#endif
 
//-----------------------------------------------------------------------------
// General cache defines.
#define HAL_CLEAR_TAGLO() asm volatile (" mtc0 $0, $28;" \
" nop;" \
" nop;" \
" nop;")
#define HAL_CLEAR_TAGHI() asm volatile (" mtc0 $0, $29;" \
" nop;" \
" nop;" \
" nop;")
 
/* Cache instruction opcodes */
#define HAL_CACHE_OP(which, op) (which | (op << 2))
 
#define HAL_WHICH_ICACHE 0x0
#define HAL_WHICH_DCACHE 0x1
 
#define HAL_INDEX_INVALIDATE 0x0
#define HAL_INDEX_LOAD_TAG 0x1
#define HAL_INDEX_STORE_TAG 0x2
#define HAL_HIT_INVALIDATE 0x4
#define HAL_ICACHE_FILL 0x5
#define HAL_DCACHE_HIT_INVALIDATE 0x5
#define HAL_DCACHE_HIT_WRITEBACK 0x6
#define HAL_FETCH_AND_LOCK 0x7
 
//-----------------------------------------------------------------------------
// Global control of data cache
 
// Invalidate the entire cache
#define HAL_DCACHE_INVALIDATE_ALL_DEFINED
#define HAL_DCACHE_INVALIDATE_ALL() \
CYG_MACRO_START \
register volatile CYG_BYTE *addr; \
HAL_CLEAR_TAGLO(); \
HAL_CLEAR_TAGHI(); \
for (addr = (CYG_BYTE *)CYGARC_KSEG_CACHED_BASE; \
addr < (CYG_BYTE *)(CYGARC_KSEG_CACHED_BASE + HAL_DCACHE_SIZE); \
addr += HAL_DCACHE_LINE_SIZE ) \
{ \
asm volatile (" cache %0, 0(%1)" \
: \
: "I" (HAL_CACHE_OP(HAL_WHICH_DCACHE, HAL_INDEX_STORE_TAG)), \
"r"(addr)); \
} \
CYG_MACRO_END
 
// Synchronize the contents of the cache with memory.
extern void hal_dcache_sync(void);
#define HAL_DCACHE_SYNC_DEFINED
#define HAL_DCACHE_SYNC() hal_dcache_sync()
 
// Set the data cache refill burst size
//#define HAL_DCACHE_BURST_SIZE(_asize_)
 
// Set the data cache write mode
//#define HAL_DCACHE_WRITE_MODE( _mode_ )
 
// Load the contents of the given address range into the data cache
// and then lock the cache so that it stays there.
#define HAL_DCACHE_LOCK_DEFINED
#define HAL_DCACHE_LOCK(_base_, _asize_) \
CYG_MACRO_START \
register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
register CYG_WORD _size_ = (_asize_); \
for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
asm volatile (" cache %0, 0(%1)" \
: \
: "I" (HAL_CACHE_OP(HAL_WHICH_DCACHE, HAL_FETCH_AND_LOCK)), \
"r"(_addr_)); \
CYG_MACRO_END
 
// Undo a previous lock operation
#define HAL_DCACHE_UNLOCK_DEFINED
#define HAL_DCACHE_UNLOCK(_base_, _asize_) \
CYG_MACRO_START \
register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
register CYG_WORD _size_ = (_asize_); \
for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
asm volatile (" cache %0, 0(%1)" \
: \
: "I" (HAL_CACHE_OP(HAL_WHICH_DCACHE, HAL_HIT_INVALIDATE)), \
"r"(_addr_)); \
CYG_MACRO_END
 
// Unlock entire cache
#define HAL_DCACHE_UNLOCK_ALL_DEFINED
#define HAL_DCACHE_UNLOCK_ALL() HAL_DCACHE_UNLOCK(0,HAL_DCACHE_SIZE)
 
 
//-----------------------------------------------------------------------------
// Data cache line control
 
// Allocate cache lines for the given address range without reading its
// contents from memory.
//#define HAL_DCACHE_ALLOCATE( _base_ , _asize_ )
 
// Write dirty cache lines to memory and invalidate the cache entries
// for the given address range.
#define HAL_DCACHE_FLUSH_DEFINED
#if HAL_DCACHE_WRITETHRU_MODE == 1
// No need to flush a writethrough cache
#define HAL_DCACHE_FLUSH( _base_ , _asize_ )
#else
#error HAL_DCACHE_FLUSH undefined for MIPS32 writeback cache
#endif
 
// Write dirty cache lines to memory for the given address range.
#define HAL_DCACHE_STORE_DEFINED
#if HAL_DCACHE_WRITETHRU_MODE == 1
// No need to store a writethrough cache
#define HAL_DCACHE_STORE( _base_ , _asize_ )
#else
#error HAL_DCACHE_STORE undefined for MIPS32 writeback cache
#endif
 
// Invalidate cache lines in the given range without writing to memory.
#define HAL_DCACHE_INVALIDATE_DEFINED
#define HAL_DCACHE_INVALIDATE( _base_ , _asize_ ) \
CYG_MACRO_START \
register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
register CYG_WORD _size_ = (_asize_); \
for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \
asm volatile (" cache %0, 0(%1)" \
: \
: "I" (HAL_CACHE_OP(HAL_WHICH_DCACHE, HAL_HIT_INVALIDATE)), \
"r"(_addr_)); \
CYG_MACRO_END
 
 
 
 
 
 
//-----------------------------------------------------------------------------
// Global control of Instruction cache
 
// Invalidate the entire cache
#define HAL_ICACHE_INVALIDATE_ALL_DEFINED
#define HAL_ICACHE_INVALIDATE_ALL() \
CYG_MACRO_START \
register volatile CYG_BYTE *addr; \
HAL_CLEAR_TAGLO(); \
HAL_CLEAR_TAGHI(); \
for (addr = (CYG_BYTE *)CYGARC_KSEG_CACHED_BASE; \
addr < (CYG_BYTE *)(CYGARC_KSEG_CACHED_BASE + HAL_ICACHE_SIZE); \
addr += HAL_ICACHE_LINE_SIZE ) \
{ \
asm volatile (" cache %0, 0(%1)" \
: \
: "I" (HAL_CACHE_OP(HAL_WHICH_ICACHE, HAL_INDEX_STORE_TAG)), \
"r"(addr)); \
} \
CYG_MACRO_END
 
// Synchronize the contents of the cache with memory.
extern void hal_icache_sync(void);
#define HAL_ICACHE_SYNC_DEFINED
#define HAL_ICACHE_SYNC() hal_icache_sync()
 
// Set the instruction cache refill burst size
//#define HAL_ICACHE_BURST_SIZE(_asize_)
 
// Load the contents of the given address range into the data cache
// and then lock the cache so that it stays there.
#define HAL_ICACHE_LOCK_DEFINED
#define HAL_ICACHE_LOCK(_base_, _asize_) \
CYG_MACRO_START \
register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
register CYG_WORD _size_ = (_asize_); \
for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
asm volatile (" cache %0, 0(%1)" \
: \
: "I" (HAL_CACHE_OP(HAL_WHICH_ICACHE, HAL_FETCH_AND_LOCK)), \
"r"(_addr_)); \
CYG_MACRO_END
 
// Undo a previous lock operation
#define HAL_ICACHE_UNLOCK_DEFINED
#define HAL_ICACHE_UNLOCK(_base_, _asize_) \
CYG_MACRO_START \
register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
register CYG_WORD _size_ = (_asize_); \
for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
asm volatile (" cache %0, 0(%1)" \
: \
: "I" (HAL_CACHE_OP(HAL_WHICH_ICACHE, HAL_HIT_INVALIDATE)), \
"r"(_addr_)); \
CYG_MACRO_END
 
// Unlock entire cache
#define HAL_ICACHE_UNLOCK_ALL_DEFINED
#define HAL_ICACHE_UNLOCK_ALL() HAL_ICACHE_UNLOCK(0,HAL_ICACHE_SIZE)
 
//-----------------------------------------------------------------------------
// Instruction cache line control
 
// Invalidate cache lines in the given range without writing to memory.
#define HAL_ICACHE_INVALIDATE_DEFINED
#define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \
CYG_MACRO_START \
register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \
register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
register CYG_WORD _size_ = (_asize_); \
for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
asm volatile (" cache %0, 0(%1)" \
: \
: "I" (HAL_CACHE_OP(HAL_WHICH_ICACHE, HAL_HIT_INVALIDATE)), \
"r"(_addr_)); \
CYG_MACRO_END
 
//-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_IMP_CACHE_H
// End of imp_cache.h
/var_intr.h
0,0 → 1,72
#ifndef CYGONCE_HAL_IMP_INTR_H
#define CYGONCE_HAL_IMP_INTR_H
 
//==========================================================================
//
// imp_intr.h
//
// MIPS32 Interrupt and clock support
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors: nickg, jskov,
// gthomas, jlarmour, dmoseley
// Date: 1999-02-16
// Purpose: MIPS32 Interrupt support
// Description: The macros defined here provide the HAL APIs for handling
// interrupts and the clock for variants of the MIPS32
// architecture.
//
// Usage:
// #include <cyg/hal/imp_intr.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h>
 
#include <cyg/hal/plf_intr.h>
//--------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_IMP_INTR_H
// End of imp_intr.h
/var_arch.h
0,0 → 1,236
#ifndef CYGONCE_HAL_VAR_ARCH_H
#define CYGONCE_HAL_VAR_ARCH_H
 
//==========================================================================
//
// var_arch.h
//
// Architecture specific abstractions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors: nickg, dmoseley
// Date: 1999-02-17
// Purpose: Define architecture abstractions
// Description: This file contains any extra or modified definitions for
// this variant of the architecture.
// Usage: #include <cyg/hal/var_arch.h>
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#ifndef __ASSEMBLER__
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>
#endif
 
//--------------------------------------------------------------------------
// Define macros for accessing CP0 registers
 
#define HAL_GET_CP0_REGISTER_32( _regval_, _cp0_regno_, _cp0_regsel_ ) \
{ \
cyg_uint32 tmp; \
asm volatile ("mfc0 %0,$%1,%2\nnop\n" \
: "=r" (tmp) \
: "i" (_cp0_regno_), "i" (_cp0_regsel_) ); \
_regval_ = tmp; \
}
 
#define HAL_SET_CP0_REGISTER_32( _regval_, _cp0_regno_, _cp0_regsel_ ) \
{ \
cyg_uint32 tmp = _regval_; \
asm volatile ("mtc0 %1,$%2,%3\nnop\n" \
: "=r" (tmp) \
: "r" (tmp), "i" (_cp0_regno_), "i" (_cp0_regsel_) ); \
}
 
#define HAL_GET_CP0_REGISTER_64( _regval_, _cp0_regno_, _cp0_regsel_ ) \
HAL_GET_CP0_REGISTER_32( _regval_, _cp0_regno_, _cp0_regsel_ )
#define HAL_SET_CP0_REGISTER_64( _regval_, _cp0_regno_, _cp0_regsel_ ) \
HAL_SET_CP0_REGISTER_32( _regval_, _cp0_regno_, _cp0_regsel_ )
 
//--------------------------------------------------------------------------
 
#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
/* System Control Coprocessor (CP0) exception processing registers */
/* These supplement the definitions in mips-regs.h */
#define C0_INDEX $0 /* Index into TLB Array - 4Kc core */
#define C0_RANDOM $1 /* Randomly generated index into TLB Array - 4Kc core */
#define C0_ENTRYLO0 $2 /* Low-order portion of the TLB entry for even-numbered virtual pages - 4Kc core */
#define C0_ENTRYLO1 $3 /* Low-order portion of the TLB entry for odd-numbered virtual pages - 4Kc core */
#define CO_PAGEMASK $5 /* Pointer to page table entry in memory - 4Kc core */
#define C0_WIRED $6 /* Number of fixed TLB entries - 4Kc core */
#define C0_ENTRYHI $10 /* High-order portion of the TLB entry - 4Kc core */
#define C0_PRId $15 /* Processor Identification and Revision */
#define C0_CONFIG $16 /* Configuration Register */
#define C0_LLADDR $17 /* Load linked address */
#define C0_LLADDR $17 /* Load linked address */
#define C0_DEBUG $23 /* Debug control and exception status */
#define C0_DEPC $24 /* Program counter at last debug exception */
#define C0_TAGLO $28 /* Low-order portion of cache tag interface */
#define C0_TAGHI $29 /* High-order portion of cache tag interface (not implemented in 4K cores */
#define C0_DESAVE $31 /* Debug handler scratch pad register */
 
/* Coprocessor Register selector field */
#define C0_SELECTOR_0 0x0
#define C0_SELECTOR_1 0x1
 
/* Status register fields */
#define SR_RP 0x08000000 /* Enter reduced-power mode */
#define SR_NMI 0x00080000 /* Reset vector called through assertion of the NMI signal */
 
/* Cause register fields */
#define CAUSE_IV 0x00800000 /* Interrupt vector to use -- Bit=0 -> offset=0x180;
Bit=1 -> offset=0x200; */
#define CAUSE_WP 0x00400000 /* Watch exception deferred due to either Status[EXL] or Status[ERL] */
#define CAUSE_MIPS32IP7 CAUSE_IP8 /* The MIPS32 architecture refers to these bits using a 0 base, */
#define CAUSE_MIPS32IP6 CAUSE_IP7 /* but the generic mips-regs.h refers to them with a 1 base */
#define CAUSE_MIPS32IP5 CAUSE_IP6
#define CAUSE_MIPS32IP4 CAUSE_IP5
#define CAUSE_MIPS32IP3 CAUSE_IP4
#define CAUSE_MIPS32IP2 CAUSE_IP3
#define CAUSE_MIPS32IP1 CAUSE_IP2
#define CAUSE_MIPS32IP0 CAUSE_IP1
 
#define CAUSE_MIPS32HW5 CAUSE_MIPS32IP1
#define CAUSE_MIPS32HW4 CAUSE_MIPS32IP1
#define CAUSE_MIPS32HW3 CAUSE_MIPS32IP1
#define CAUSE_MIPS32HW2 CAUSE_MIPS32IP1
#define CAUSE_MIPS32HW1 CAUSE_MIPS32IP1
#define CAUSE_MIPS32HW0 CAUSE_MIPS32IP1
#define CAUSE_MIPS32SW1 CAUSE_MIPS32IP1
#define CAUSE_MIPS32SW0 CAUSE_MIPS32IP0
 
/* Exception Codes */
#define EXC_WATCH 23 /* Reference to the Watch address */
#define EXC_MCHECK 24 /* Machine Check */
 
/* Processor Identification fields */
#define PRId_COMPANY_ID_MASK 0x00FF0000 /* Which company manufactured this chip */
#define PRId_COMPANY_MIPS_TECHNOLOGIES 0x00010000
#define PRId_PROCESSOR_ID_MASK 0x0000FF00 /* Which processor is this */
#define PRId_PROCESSOR_4Kc 0x00008000
#define PRId_PROCESSOR_4Kp_4Km 0x00008300
#define PRId_REVISION 0x000000FF /* Which revision is this */
 
/* Config register fields */
#define CONFIG_M 0x80000000 /* Hardwired to '1' to indicate presence of Config1 register */
#define CONFIG_K23 0x70000000 /* Controls cacheability of kseg2 and kseg3 in BAT */
#define CONFIG_KU 0x0E000000 /* Controls cacheability of ksegu in BAT */
#define CONFIG_MDU 0x00100000 /* MDU Type: 0 == Fast Multiplier Array; 1 == Iterative */
#define CONFIG_MM 0x00060000 /* Merge mode */
#define CONFIG_BM 0x00010000 /* Burst mode: 0 == Sequential; 1 == SubBlock */
#define CONFIG_BE 0x00008000 /* Endian mode: 0 == Little Endian; 1 == Big Endian */
#define CONFIG_AT 0x00006000 /* Architecture Type */
#define CONFIG_AR 0x00001C00 /* Architecture Revision */
#define CONFIG_MT 0x00000380 /* MMU Type */
#define CONFIG_K0 0x00000007 /* kseg0 coherency algorithm */
 
/* KSEG cache control codes */
#define CONFIG_KSEG2_3_CACHEABLE 0x30000000 /* KSeg2 and KSeg3 are cacheable/noncoherent/write-through/no write-allocate */
#define CONFIG_KSEG2_3_UNCACHEABLE 0x20000000 /* KSeg2 and KSeg3 are cacheable/noncoherent/write-through/no write-allocate */
#define CONFIG_KSEGU_CACHEABLE 0x06000000 /* KSegu is cacheable/noncoherent/write-through/no write-allocate */
#define CONFIG_KSEGU_UNCACHEABLE 0x04000000 /* KSegu is cacheable/noncoherent/write-through/no write-allocate */
#define CONFIG_KSEG0_CACHEABLE 0x00000003 /* KSeg0 is cacheable/noncoherent/write-through/no write-allocate */
#define CONFIG_KSEG0_UNCACHEABLE 0x00000002 /* KSeg0 is cacheable/noncoherent/write-through/no write-allocate */
 
/* Merge mode control codes */
#define CONFIG_NO_MERGING 0x00000000
#define CONFIG_SYSAD_VALID_MERGING 0x00200000
#define CONFIG_FULL_MERGING 0x00400000
 
/* Architecture Type codes */
#define CONFIG_AT_MIPS32 0x00000000
 
/* Architecture Revision codes */
#define CONFIG_AR_REVISION_1 0x00000000
 
/* MMU Type codes */
#define CONFIG_MMU_TYPE_STANDARD_TLB 0x00000080
#define CONFIG_MMU_TYPE_FIXED 0x00000180
 
/* Config1 register fields */
#define CONFIG1_MMU_SIZE_MASK 0x7E000000 /* Number of entries in the TLB minus 1 */
#define CONFIG1_IS 0x01C00000 /* Number of instruction cache sets per way */
#define CONFIG1_IL 0x00380000 /* Instruction cache line size */
#define CONFIG1_IA 0x00030000 /* Level of Instruction cache associativity */
#define CONFIG1_DS 0x0000E000 /* Number of data cache sets per way */
#define CONFIG1_DL 0x00001C00 /* Data cache line size */
#define CONFIG1_DA 0x00000380 /* Level of Data cache associativity */
#define CONFIG1_PC 0x00000010 /* Performance Counter registers implemented */
#define CONFIG1_WR 0x00000008 /* Watch registers implemented */
#define CONFIG1_CA 0x00000004 /* Code compression implemented */
#define CONFIG1_EP 0x00000002 /* EJTAG implemented */
#define CONFIG1_FP 0x00000001 /* FPU implemented */
 
/* Instruction cache sets-per-way codes */
#define CONFIG1_ICACHE_64_SETS_PER_WAY 0x00000000
#define CONFIG1_ICACHE_128_SETS_PER_WAY 0x00400000
#define CONFIG1_ICACHE_256_SETS_PER_WAY 0x00800000
 
/* Instruction cache line size codes */
#define CONFIG1_ICACHE_NOT_PRESET 0x00000000
#define CONFIG1_ICACHE_LINE_SIZE_16_BYTES 0x00180000
 
/* Instruction cache associativity codes */
#define CONFIG1_ICACHE_DIRECT_MAPPED 0x00000000
#define CONFIG1_ICACHE_2_WAY 0x00010000
#define CONFIG1_ICACHE_3_WAY 0x00020000
#define CONFIG1_ICACHE_4_WAY 0x00030000
 
/* Data cache sets-per-way codes */
#define CONFIG1_DCACHE_64_SETS_PER_WAY 0x00000000
#define CONFIG1_DCACHE_128_SETS_PER_WAY 0x00002000
#define CONFIG1_DCACHE_256_SETS_PER_WAY 0x00004000
 
/* Data cache line size codes */
#define CONFIG1_DCACHE_NOT_PRESET 0x00000000
#define CONFIG1_DCACHE_LINE_SIZE_16_BYTES 0x00000C00
 
/* Data cache associativity codes */
#define CONFIG1_DCACHE_DIRECT_MAPPED 0x00000000
#define CONFIG1_DCACHE_2_WAY 0x00000080
#define CONFIG1_DCACHE_3_WAY 0x00000100
#define CONFIG1_DCACHE_4_WAY 0x00000180
 
#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
 
//--------------------------------------------------------------------------
#endif // CYGONCE_HAL_VAR_ARCH_H
// End of var_arch.h
/variant.inc
0,0 → 1,187
#ifndef CYGONCE_HAL_VARIANT_INC
#define CYGONCE_HAL_VARIANT_INC
##=============================================================================
##
## variant.inc
##
## MIPS 32/64 family assembler header file
##
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
##=============================================================================
#######DESCRIPTIONBEGIN####
##
## Author(s): dmoseley
## Contributors: dmoseley
## Date: 2000-06-07
## Purpose: MIPS32 family definitions.
## Description: This file contains various definitions and macros that are
## useful for writing assembly code for the MIPS32 CPU family.
## Usage:
## #include <cyg/hal/variant.inc>
## ...
##
##
######DESCRIPTIONEND####
##
##=============================================================================
 
#include <pkgconf/hal.h>
#include <cyg/hal/mips.inc>
 
#include <cyg/hal/platform.inc>
 
#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
#include <cyg/hal/mips-regs.h>
#include <cyg/hal/var_arch.h>
 
##-----------------------------------------------------------------------------
## Define CPU variant for architecture HAL.
#define CYG_HAL_MIPS_MIPS32
 
#------------------------------------------------------------------------------
# Cache macros.
#ifndef CYGPKG_HAL_MIPS_CACHE_DEFINED
 
.macro hal_cache_init
 
# Setup a temporary stack pointer for running C code.
la a0,__interrupt_stack
move sp,a0
CYGARC_ADDRESS_REG_UNCACHED(sp)
# Read the CONFIG1 register into a0
mfc0 a0, C0_CONFIG, 1
nop
nop
nop
 
# Jump to C-code to initialize caches (uncached)
lar k0, hal_c_cache_init
CYGARC_ADDRESS_REG_UNCACHED(k0)
jalr k0
nop
.endm
 
#define CYGPKG_HAL_MIPS_CACHE_DEFINED
 
#endif
 
#------------------------------------------------------------------------------
# Monitor initialization.
#ifndef CYGPKG_HAL_MIPS_MON_DEFINED
 
#if defined(CYG_HAL_STARTUP_ROM) || \
( defined(CYG_HAL_STARTUP_RAM) && \
!defined(CYGSEM_HAL_USE_ROM_MONITOR))
# If we are starting up from ROM, or we are starting in
# RAM and NOT using a ROM monitor, initialize the VSR table.
 
.macro hal_mon_init
# Set default exception VSR for all vectors
ori a0,zero,16 # CYGNUM_HAL_VSR_COUNT
la a1,__default_exception_vsr
la a2,hal_vsr_table
1: sw a1,0(a2)
addi a2,a2,4
addi a0,a0,-1
bne a0,zero,1b
nop
 
# Now set special VSRs
la a0,hal_vsr_table
# Set interrupt VSR
la a1,__default_interrupt_vsr
sw a1,0*4(a0) # CYGNUM_HAL_VECTOR_INTERRUPT
# Add special handler on breakpoint vector to allow GDB and
# GCC to both use 'break' without conflicts.
la a1,__break_vsr_springboard
sw a1,9*4(a0) # CYGNUM_HAL_VECTOR_BREAKPOINT
# Set exception handler on special vectors
# FIXME: Should use proper definitions
la a1,__default_exception_vsr
sw a1,32*4(a0) # debug
sw a1,33*4(a0) # utlb
sw a1,34*4(a0) # nmi
.endm
#elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR)
 
# Initialize the VSR table entries
# We only take control of the interrupt vector,
# the rest are left to the ROM for now...
 
.macro hal_mon_init
la a0,__default_interrupt_vsr
la a3,hal_vsr_table
sw a0,0(a3)
.endm
 
#else
 
.macro hal_mon_init
.endm
 
#endif
 
#define CYGPKG_HAL_MIPS_MON_DEFINED
 
#endif
 
#------------------------------------------------------------------------------
# Decide whether the VSR table is defined externally, or is to be defined
# here.
 
#if defined(CYGPKG_HAL_MIPS_SIM) || \
( defined(CYGPKG_HAL_MIPS_ATLAS) && \
defined(CYG_HAL_STARTUP_RAM) && \
!defined(CYGSEM_HAL_USE_ROM_MONITOR) \
)
 
## VSR table defined in linker script
 
#else
 
#define CYG_HAL_MIPS_VSR_TABLE_DEFINED
 
#endif
 
#------------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_VARIANT_INC
# end of variant.inc

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