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/openrisc/trunk/rtos/ecos-2.0/packages/hal/mips/mips64/v2_0
- from Rev 27 to Rev 174
- ↔ Reverse comparison
Rev 27 → Rev 174
/cdl/hal_mips_mips64.cdl
0,0 → 1,165
# ==================================================================== |
# |
# hal_mips_mips64.cdl |
# |
# MIPS 64 variant architectural HAL package configuration data |
# |
# ==================================================================== |
#####ECOSGPLCOPYRIGHTBEGIN#### |
## ------------------------------------------- |
## This file is part of eCos, the Embedded Configurable Operating System. |
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
## |
## eCos is free software; you can redistribute it and/or modify it under |
## the terms of the GNU General Public License as published by the Free |
## Software Foundation; either version 2 or (at your option) any later version. |
## |
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
## WARRANTY; without even the implied warranty of MERCHANTABILITY or |
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
## for more details. |
## |
## You should have received a copy of the GNU General Public License along |
## with eCos; if not, write to the Free Software Foundation, Inc., |
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
## |
## As a special exception, if other files instantiate templates or use macros |
## or inline functions from this file, or you compile this file and link it |
## with other works to produce a work based on this file, this file does not |
## by itself cause the resulting work to be covered by the GNU General Public |
## License. However the source code for this file must still be made available |
## in accordance with section (3) of the GNU General Public License. |
## |
## This exception does not invalidate any other reasons why a work based on |
## this file might be covered by the GNU General Public License. |
## |
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
## at http://sources.redhat.com/ecos/ecos-license/ |
## ------------------------------------------- |
#####ECOSGPLCOPYRIGHTEND#### |
# ==================================================================== |
######DESCRIPTIONBEGIN#### |
# |
# Author(s): nickg (after MIPS32 by dmoseley) |
# Original data: bartv, nickg |
# Contributors: |
# Date: 2001-01-30 |
# |
#####DESCRIPTIONEND#### |
# |
# ==================================================================== |
|
cdl_package CYGPKG_HAL_MIPS_MIPS64 { |
display "MIPS64 variant" |
parent CYGPKG_HAL_MIPS |
hardware |
include_dir cyg/hal |
description " |
The MIPS64 architecture HAL package provides generic support |
for this processor architecture. It is also necessary to |
select a specific target platform HAL package." |
|
cdl_option CYGHWR_HAL_MIPS_MIPS64_CORE { |
display "Mips64 processor core used" |
flavor data |
default_value {"5K"} |
legal_values {"5K" "20K" } |
description " |
The MIPS64 cores come in (at least) 2 flavors. The main |
differences being in the MMU" |
} |
|
implements CYGINT_HAL_MIPS_VARIANT |
|
cdl_option CYGHWR_HAL_MIPS_64BIT { |
display "Variant 64 bit architecture support" |
calculated 1 |
} |
|
cdl_option CYGHWR_HAL_MIPS_FPU { |
display "Variant FPU support" |
calculated 0 |
} |
|
cdl_option CYGHWR_HAL_MIPS_FPU_64BIT { |
display "Variant 64 bit FPU support" |
calculated 1 |
} |
|
cdl_option CYGPKG_HAL_MIPS_LSBFIRST { |
display "CPU Variant little-endian" |
calculated 1 |
} |
|
cdl_option CYGPKG_HAL_MIPS_GDB_REPORT_CP0 { |
display "Report contents of CP0 to GDB" |
calculated 1 |
} |
|
define_proc { |
puts $::cdl_header "#include <pkgconf/hal_mips.h>" |
} |
|
compile var_misc.c variant.S |
|
make { |
<PREFIX>/lib/target.ld: <PACKAGE>/src/mips_mips64.ld |
$(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(CFLAGS) -o $@ $< |
@echo $@ ": \\" > $(notdir $@).deps |
@tail +2 target.tmp >> $(notdir $@).deps |
@echo >> $(notdir $@).deps |
@rm target.tmp |
} |
|
cdl_option CYGBLD_LINKER_SCRIPT { |
display "Linker script" |
flavor data |
no_define |
calculated { "src/mips_mips64.ld" } |
} |
|
cdl_component CYGBLD_GLOBAL_OPTIONS { |
display "Global build options" |
flavor none |
parent CYGPKG_NONE |
description " |
Global build options including control over |
compiler flags, linker flags and choice of toolchain." |
|
|
cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { |
display "Global command prefix" |
flavor data |
no_define |
default_value { "mipsisa32-elf" } |
description " |
This option specifies the command prefix used when |
invoking the build tools. Note that both MIPS32 and |
MIPS64 targets use the same toolchain." |
} |
|
cdl_option CYGBLD_GLOBAL_CFLAGS { |
display "Global compiler flags" |
flavor data |
no_define |
default_value { "-mips64 -EL -msoft-float -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority -G0" } |
description " |
This option controls the global compiler flags which |
are used to compile all packages by |
default. Individual packages may define |
options which override these global flags." |
} |
|
cdl_option CYGBLD_GLOBAL_LDFLAGS { |
display "Global linker flags" |
flavor data |
no_define |
default_value { "-EL -msoft-float -g -nostdlib -Wl,--gc-sections -Wl,-static" } |
description " |
This option controls the global linker flags. Individual |
packages may define options which override these global flags." |
} |
|
} |
|
} |
/include/var_cache.h
0,0 → 1,314
#ifndef CYGONCE_IMP_CACHE_H |
#define CYGONCE_IMP_CACHE_H |
|
//============================================================================= |
// |
// imp_cache.h |
// |
// HAL cache control API |
// |
//============================================================================= |
//####ECOSGPLCOPYRIGHTBEGIN#### |
// ------------------------------------------- |
// This file is part of eCos, the Embedded Configurable Operating System. |
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
// |
// eCos is free software; you can redistribute it and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
// Software Foundation; either version 2 or (at your option) any later version. |
// |
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
// WARRANTY; without even the implied warranty of MERCHANTABILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with eCos; if not, write to the Free Software Foundation, Inc., |
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
// |
// As a special exception, if other files instantiate templates or use macros |
// or inline functions from this file, or you compile this file and link it |
// with other works to produce a work based on this file, this file does not |
// by itself cause the resulting work to be covered by the GNU General Public |
// License. However the source code for this file must still be made available |
// in accordance with section (3) of the GNU General Public License. |
// |
// This exception does not invalidate any other reasons why a work based on |
// this file might be covered by the GNU General Public License. |
// |
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
// at http://sources.redhat.com/ecos/ecos-license/ |
// ------------------------------------------- |
//####ECOSGPLCOPYRIGHTEND#### |
//============================================================================= |
//#####DESCRIPTIONBEGIN#### |
// |
// Author(s): nickg |
// Contributors: nickg, dmoseley |
// Date: 1998-02-17 |
// Purpose: Cache control API |
// Description: The macros defined here provide the HAL APIs for handling |
// cache control operations. |
// Usage: |
// #include <cyg/hal/imp_cache.h> |
// ... |
// |
// |
//####DESCRIPTIONEND#### |
// |
//============================================================================= |
|
#include <pkgconf/hal.h> |
#include <cyg/infra/cyg_type.h> |
|
#include <cyg/hal/mips-regs.h> |
#include <cyg/hal/hal_arch.h> |
#include <cyg/hal/plf_cache.h> |
#include <cyg/hal/var_arch.h> |
|
#ifdef CYGHWR_HAL_MIPS_MIPS64_CORE_5K |
|
//----------------------------------------------------------------------------- |
// Cache dimensions |
|
// Data cache |
#define HAL_DCACHE_SIZE 8192 // Size of data cache in bytes |
#define HAL_DCACHE_LINE_SIZE 32 // Size of a data cache line |
#define HAL_DCACHE_WAYS 2 // Associativity of the cache |
|
// Instruction cache |
#define HAL_ICACHE_SIZE 8192 // Size of cache in bytes |
#define HAL_ICACHE_LINE_SIZE 32 // Size of a cache line |
#define HAL_ICACHE_WAYS 2 // Associativity of the cache |
|
#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) |
#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) |
|
#define HAL_DCACHE_WRITETHRU_MODE 1 |
#define HAL_DCACHE_WRITEBACK_MODE 0 |
|
#else |
|
#error Unknown MIPS32 Variant |
|
#endif |
|
//----------------------------------------------------------------------------- |
// General cache defines. |
#define HAL_CLEAR_TAGLO() asm volatile (" mtc0 $0, $28;" \ |
" nop;" \ |
" nop;" \ |
" nop;") |
#define HAL_CLEAR_TAGHI() asm volatile (" mtc0 $0, $29;" \ |
" nop;" \ |
" nop;" \ |
" nop;") |
|
/* Cache instruction opcodes */ |
#define HAL_CACHE_OP(which, op) (which | (op << 2)) |
|
#define HAL_WHICH_ICACHE 0x0 |
#define HAL_WHICH_DCACHE 0x1 |
|
#define HAL_INDEX_INVALIDATE 0x0 |
#define HAL_INDEX_LOAD_TAG 0x1 |
#define HAL_INDEX_STORE_TAG 0x2 |
#define HAL_HIT_INVALIDATE 0x4 |
#define HAL_ICACHE_FILL 0x5 |
#define HAL_DCACHE_HIT_INVALIDATE 0x5 |
#define HAL_DCACHE_HIT_WRITEBACK 0x6 |
#define HAL_FETCH_AND_LOCK 0x7 |
|
//----------------------------------------------------------------------------- |
// Global control of data cache |
|
// Invalidate the entire cache |
#define HAL_DCACHE_INVALIDATE_ALL_DEFINED |
#define HAL_DCACHE_INVALIDATE_ALL() \ |
CYG_MACRO_START \ |
register volatile CYG_BYTE *addr; \ |
HAL_CLEAR_TAGLO(); \ |
HAL_CLEAR_TAGHI(); \ |
for (addr = (CYG_BYTE *)CYGARC_KSEG_CACHED_BASE; \ |
addr < (CYG_BYTE *)(CYGARC_KSEG_CACHED_BASE + HAL_DCACHE_SIZE); \ |
addr += HAL_DCACHE_LINE_SIZE ) \ |
{ \ |
asm volatile (" cache %0, 0(%1)" \ |
: \ |
: "I" (HAL_CACHE_OP(HAL_WHICH_DCACHE, HAL_INDEX_STORE_TAG)), \ |
"r"(addr)); \ |
} \ |
CYG_MACRO_END |
|
// Synchronize the contents of the cache with memory. |
extern void hal_dcache_sync(void); |
#define HAL_DCACHE_SYNC_DEFINED |
#define HAL_DCACHE_SYNC() hal_dcache_sync() |
|
// Set the data cache refill burst size |
//#define HAL_DCACHE_BURST_SIZE(_asize_) |
|
// Set the data cache write mode |
//#define HAL_DCACHE_WRITE_MODE( _mode_ ) |
|
// Load the contents of the given address range into the data cache |
// and then lock the cache so that it stays there. |
#define HAL_DCACHE_LOCK_DEFINED |
#define HAL_DCACHE_LOCK(_base_, _asize_) \ |
CYG_MACRO_START \ |
register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ |
register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ |
register CYG_WORD _size_ = (_asize_); \ |
for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ |
asm volatile (" cache %0, 0(%1)" \ |
: \ |
: "I" (HAL_CACHE_OP(HAL_WHICH_DCACHE, HAL_FETCH_AND_LOCK)), \ |
"r"(_addr_)); \ |
CYG_MACRO_END |
|
// Undo a previous lock operation |
#define HAL_DCACHE_UNLOCK_DEFINED |
#define HAL_DCACHE_UNLOCK(_base_, _asize_) \ |
CYG_MACRO_START \ |
register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ |
register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ |
register CYG_WORD _size_ = (_asize_); \ |
for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ |
asm volatile (" cache %0, 0(%1)" \ |
: \ |
: "I" (HAL_CACHE_OP(HAL_WHICH_DCACHE, HAL_HIT_INVALIDATE)), \ |
"r"(_addr_)); \ |
CYG_MACRO_END |
|
// Unlock entire cache |
#define HAL_DCACHE_UNLOCK_ALL_DEFINED |
#define HAL_DCACHE_UNLOCK_ALL() HAL_DCACHE_UNLOCK(0,HAL_DCACHE_SIZE) |
|
|
//----------------------------------------------------------------------------- |
// Data cache line control |
|
// Allocate cache lines for the given address range without reading its |
// contents from memory. |
//#define HAL_DCACHE_ALLOCATE( _base_ , _asize_ ) |
|
// Write dirty cache lines to memory and invalidate the cache entries |
// for the given address range. |
#define HAL_DCACHE_FLUSH_DEFINED |
#if HAL_DCACHE_WRITETHRU_MODE == 1 |
// No need to flush a writethrough cache |
#define HAL_DCACHE_FLUSH( _base_ , _asize_ ) |
#else |
#error HAL_DCACHE_FLUSH undefined for MIPS32 writeback cache |
#endif |
|
// Write dirty cache lines to memory for the given address range. |
#define HAL_DCACHE_STORE_DEFINED |
#if HAL_DCACHE_WRITETHRU_MODE == 1 |
// No need to store a writethrough cache |
#define HAL_DCACHE_STORE( _base_ , _asize_ ) |
#else |
#error HAL_DCACHE_STORE undefined for MIPS32 writeback cache |
#endif |
|
// Invalidate cache lines in the given range without writing to memory. |
#define HAL_DCACHE_INVALIDATE_DEFINED |
#define HAL_DCACHE_INVALIDATE( _base_ , _asize_ ) \ |
CYG_MACRO_START \ |
register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ |
register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ |
register CYG_WORD _size_ = (_asize_); \ |
for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE ) \ |
asm volatile (" cache %0, 0(%1)" \ |
: \ |
: "I" (HAL_CACHE_OP(HAL_WHICH_DCACHE, HAL_HIT_INVALIDATE)), \ |
"r"(_addr_)); \ |
CYG_MACRO_END |
|
|
|
|
|
|
//----------------------------------------------------------------------------- |
// Global control of Instruction cache |
|
// Invalidate the entire cache |
#define HAL_ICACHE_INVALIDATE_ALL_DEFINED |
#define HAL_ICACHE_INVALIDATE_ALL() \ |
CYG_MACRO_START \ |
register volatile CYG_BYTE *addr; \ |
HAL_CLEAR_TAGLO(); \ |
HAL_CLEAR_TAGHI(); \ |
for (addr = (CYG_BYTE *)CYGARC_KSEG_CACHED_BASE; \ |
addr < (CYG_BYTE *)(CYGARC_KSEG_CACHED_BASE + HAL_ICACHE_SIZE); \ |
addr += HAL_ICACHE_LINE_SIZE ) \ |
{ \ |
asm volatile (" cache %0, 0(%1)" \ |
: \ |
: "I" (HAL_CACHE_OP(HAL_WHICH_ICACHE, HAL_INDEX_STORE_TAG)), \ |
"r"(addr)); \ |
} \ |
CYG_MACRO_END |
|
// Synchronize the contents of the cache with memory. |
extern void hal_icache_sync(void); |
#define HAL_ICACHE_SYNC_DEFINED |
#define HAL_ICACHE_SYNC() hal_icache_sync() |
|
// Set the instruction cache refill burst size |
//#define HAL_ICACHE_BURST_SIZE(_asize_) |
|
// Load the contents of the given address range into the data cache |
// and then lock the cache so that it stays there. |
#define HAL_ICACHE_LOCK_DEFINED |
#define HAL_ICACHE_LOCK(_base_, _asize_) \ |
CYG_MACRO_START \ |
register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ |
register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ |
register CYG_WORD _size_ = (_asize_); \ |
for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \ |
asm volatile (" cache %0, 0(%1)" \ |
: \ |
: "I" (HAL_CACHE_OP(HAL_WHICH_ICACHE, HAL_FETCH_AND_LOCK)), \ |
"r"(_addr_)); \ |
CYG_MACRO_END |
|
// Undo a previous lock operation |
#define HAL_ICACHE_UNLOCK_DEFINED |
#define HAL_ICACHE_UNLOCK(_base_, _asize_) \ |
CYG_MACRO_START \ |
register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ |
register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ |
register CYG_WORD _size_ = (_asize_); \ |
for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \ |
asm volatile (" cache %0, 0(%1)" \ |
: \ |
: "I" (HAL_CACHE_OP(HAL_WHICH_ICACHE, HAL_HIT_INVALIDATE)), \ |
"r"(_addr_)); \ |
CYG_MACRO_END |
|
// Unlock entire cache |
#define HAL_ICACHE_UNLOCK_ALL_DEFINED |
#define HAL_ICACHE_UNLOCK_ALL() HAL_ICACHE_UNLOCK(0,HAL_ICACHE_SIZE) |
|
//----------------------------------------------------------------------------- |
// Instruction cache line control |
|
// Invalidate cache lines in the given range without writing to memory. |
#define HAL_ICACHE_INVALIDATE_DEFINED |
#define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \ |
CYG_MACRO_START \ |
register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_); \ |
register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \ |
register CYG_WORD _size_ = (_asize_); \ |
for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \ |
asm volatile (" cache %0, 0(%1)" \ |
: \ |
: "I" (HAL_CACHE_OP(HAL_WHICH_ICACHE, HAL_HIT_INVALIDATE)), \ |
"r"(_addr_)); \ |
CYG_MACRO_END |
|
//----------------------------------------------------------------------------- |
#endif // ifndef CYGONCE_IMP_CACHE_H |
// End of imp_cache.h |
/include/var_intr.h
0,0 → 1,72
#ifndef CYGONCE_HAL_IMP_INTR_H |
#define CYGONCE_HAL_IMP_INTR_H |
|
//========================================================================== |
// |
// imp_intr.h |
// |
// MIPS64 Interrupt and clock support |
// |
//========================================================================== |
//####ECOSGPLCOPYRIGHTBEGIN#### |
// ------------------------------------------- |
// This file is part of eCos, the Embedded Configurable Operating System. |
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
// |
// eCos is free software; you can redistribute it and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
// Software Foundation; either version 2 or (at your option) any later version. |
// |
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
// WARRANTY; without even the implied warranty of MERCHANTABILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with eCos; if not, write to the Free Software Foundation, Inc., |
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
// |
// As a special exception, if other files instantiate templates or use macros |
// or inline functions from this file, or you compile this file and link it |
// with other works to produce a work based on this file, this file does not |
// by itself cause the resulting work to be covered by the GNU General Public |
// License. However the source code for this file must still be made available |
// in accordance with section (3) of the GNU General Public License. |
// |
// This exception does not invalidate any other reasons why a work based on |
// this file might be covered by the GNU General Public License. |
// |
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
// at http://sources.redhat.com/ecos/ecos-license/ |
// ------------------------------------------- |
//####ECOSGPLCOPYRIGHTEND#### |
//========================================================================== |
//#####DESCRIPTIONBEGIN#### |
// |
// Author(s): nickg |
// Contributors: nickg, jskov, |
// gthomas, jlarmour, dmoseley |
// Date: 1999-02-16 |
// Purpose: MIPS64 Interrupt support |
// Description: The macros defined here provide the HAL APIs for handling |
// interrupts and the clock for variants of the MIPS64 |
// architecture. |
// |
// Usage: |
// #include <cyg/hal/imp_intr.h> |
// ... |
// |
// |
//####DESCRIPTIONEND#### |
// |
//========================================================================== |
|
#include <pkgconf/hal.h> |
|
#include <cyg/infra/cyg_type.h> |
|
#include <cyg/hal/plf_intr.h> |
|
//-------------------------------------------------------------------------- |
#endif // ifndef CYGONCE_HAL_IMP_INTR_H |
// End of imp_intr.h |
/include/var_arch.h
0,0 → 1,253
#ifndef CYGONCE_HAL_VAR_ARCH_H |
#define CYGONCE_HAL_VAR_ARCH_H |
|
//========================================================================== |
// |
// var_arch.h |
// |
// Architecture specific abstractions |
// |
//========================================================================== |
//####ECOSGPLCOPYRIGHTBEGIN#### |
// ------------------------------------------- |
// This file is part of eCos, the Embedded Configurable Operating System. |
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
// |
// eCos is free software; you can redistribute it and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
// Software Foundation; either version 2 or (at your option) any later version. |
// |
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
// WARRANTY; without even the implied warranty of MERCHANTABILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with eCos; if not, write to the Free Software Foundation, Inc., |
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
// |
// As a special exception, if other files instantiate templates or use macros |
// or inline functions from this file, or you compile this file and link it |
// with other works to produce a work based on this file, this file does not |
// by itself cause the resulting work to be covered by the GNU General Public |
// License. However the source code for this file must still be made available |
// in accordance with section (3) of the GNU General Public License. |
// |
// This exception does not invalidate any other reasons why a work based on |
// this file might be covered by the GNU General Public License. |
// |
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
// at http://sources.redhat.com/ecos/ecos-license/ |
// ------------------------------------------- |
//####ECOSGPLCOPYRIGHTEND#### |
//========================================================================== |
//#####DESCRIPTIONBEGIN#### |
// |
// Author(s): nickg |
// Contributors: nickg, dmoseley |
// Date: 2001-01-30 |
// Purpose: Define architecture abstractions |
// Description: This file contains any extra or modified definitions for |
// this variant of the architecture. |
// Usage: #include <cyg/hal/var_arch.h> |
// |
//####DESCRIPTIONEND#### |
// |
//========================================================================== |
|
#ifndef __ASSEMBLER__ |
#include <pkgconf/hal.h> |
#include <cyg/infra/cyg_type.h> |
#endif |
|
//-------------------------------------------------------------------------- |
// Define register size used for GDB |
|
#define CYG_HAL_GDB_REG CYG_WORD64 |
|
//-------------------------------------------------------------------------- |
// define macros for accessing CP0 registers |
|
#define HAL_GET_CP0_REGISTER_32( _regval_, _cp0_regno_, _cp0_regsel_ ) \ |
{ \ |
cyg_uint32 tmp; \ |
asm volatile ("mfc0 %0,$%1,%2\nnop;nop;nop\n" \ |
: "=r" (tmp) \ |
: "i" (_cp0_regno_), "i" (_cp0_regsel_) ); \ |
_regval_ = tmp; \ |
} |
|
#define HAL_SET_CP0_REGISTER_32( _regval_, _cp0_regno_, _cp0_regsel_ ) \ |
{ \ |
cyg_uint32 tmp = _regval_; \ |
asm volatile ("mtc0 %1,$%2,%3\nnop\n" \ |
: "=r" (tmp) \ |
: "r" (tmp), "i" (_cp0_regno_), "i" (_cp0_regsel_) ); \ |
} |
|
#define HAL_GET_CP0_REGISTER_64( _regval_, _cp0_regno_, _cp0_regsel_ ) \ |
{ \ |
cyg_uint64 tmp; \ |
asm volatile ("dmfc0 %0,$%1,%2\nnop\n" \ |
: "=r" (tmp) \ |
: "i" (_cp0_regno_), "i" (_cp0_regsel_) ); \ |
_regval_ = tmp; \ |
} |
|
#define HAL_SET_CP0_REGISTER_64( _regval_, _cp0_regno_, _cp0_regsel_ ) \ |
{ \ |
cyg_uint64 tmp = _regval_; \ |
asm volatile ("dmtc0 %1,$%2,%3\nnop\n" \ |
: "=r" (tmp) \ |
: "r" (tmp), "i" (_cp0_regno_), "i" (_cp0_regsel_) ); \ |
} |
|
//-------------------------------------------------------------------------- |
|
#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS |
/* System Control Coprocessor (CP0) exception processing registers */ |
/* These supplement the definitions in mips-regs.h */ |
#define C0_INDEX $0 /* Index into TLB Array - 4Kc core */ |
#define C0_RANDOM $1 /* Randomly generated index into TLB Array - 4Kc core */ |
#define C0_ENTRYLO0 $2 /* Low-order portion of the TLB entry for even-numbered virtual pages - 4Kc core */ |
#define C0_ENTRYLO1 $3 /* Low-order portion of the TLB entry for odd-numbered virtual pages - 4Kc core */ |
#define CO_PAGEMASK $5 /* Pointer to page table entry in memory - 4Kc core */ |
#define C0_WIRED $6 /* Number of fixed TLB entries - 4Kc core */ |
#define C0_ENTRYHI $10 /* High-order portion of the TLB entry - 4Kc core */ |
#define C0_PRId $15 /* Processor Identification and Revision */ |
#define C0_CONFIG $16 /* Configuration Register */ |
#define C0_LLADDR $17 /* Load linked address */ |
#define C0_LLADDR $17 /* Load linked address */ |
#define C0_DEBUG $23 /* Debug control and exception status */ |
#define C0_DEPC $24 /* Program counter at last debug exception */ |
#define C0_TAGLO $28 /* Low-order portion of cache tag interface */ |
#define C0_TAGHI $29 /* High-order portion of cache tag interface (not implemented in 4K cores */ |
#define C0_DESAVE $31 /* Debug handler scratch pad register */ |
|
/* Coprocessor Register selector field */ |
#define C0_SELECTOR_0 0x0 |
#define C0_SELECTOR_1 0x1 |
|
/* Status register fields */ |
#define SR_RP 0x08000000 /* Enter reduced-power mode */ |
#define SR_NMI 0x00080000 /* Reset vector called through assertion of the NMI signal */ |
|
/* Cause register fields */ |
#define CAUSE_IV 0x00800000 /* Interrupt vector to use -- Bit=0 -> offset=0x180; |
Bit=1 -> offset=0x200; */ |
#define CAUSE_WP 0x00400000 /* Watch exception deferred due to either Status[EXL] or Status[ERL] */ |
#define CAUSE_MIPS32IP7 CAUSE_IP8 /* The MIPS32 architecture refers to these bits using a 0 base, */ |
#define CAUSE_MIPS32IP6 CAUSE_IP7 /* but the generic mips-regs.h refers to them with a 1 base */ |
#define CAUSE_MIPS32IP5 CAUSE_IP6 |
#define CAUSE_MIPS32IP4 CAUSE_IP5 |
#define CAUSE_MIPS32IP3 CAUSE_IP4 |
#define CAUSE_MIPS32IP2 CAUSE_IP3 |
#define CAUSE_MIPS32IP1 CAUSE_IP2 |
#define CAUSE_MIPS32IP0 CAUSE_IP1 |
|
#define CAUSE_MIPS32HW5 CAUSE_MIPS32IP1 |
#define CAUSE_MIPS32HW4 CAUSE_MIPS32IP1 |
#define CAUSE_MIPS32HW3 CAUSE_MIPS32IP1 |
#define CAUSE_MIPS32HW2 CAUSE_MIPS32IP1 |
#define CAUSE_MIPS32HW1 CAUSE_MIPS32IP1 |
#define CAUSE_MIPS32HW0 CAUSE_MIPS32IP1 |
#define CAUSE_MIPS32SW1 CAUSE_MIPS32IP1 |
#define CAUSE_MIPS32SW0 CAUSE_MIPS32IP0 |
|
/* Exception Codes */ |
#define EXC_WATCH 23 /* Reference to the Watch address */ |
#define EXC_MCHECK 24 /* Machine Check */ |
|
/* Processor Identification fields */ |
#define PRId_COMPANY_ID_MASK 0x00FF0000 /* Which company manufactured this chip */ |
#define PRId_COMPANY_MIPS_TECHNOLOGIES 0x00010000 |
#define PRId_PROCESSOR_ID_MASK 0x0000FF00 /* Which processor is this */ |
#define PRId_PROCESSOR_4Kc 0x00008000 |
#define PRId_PROCESSOR_4Kp_4Km 0x00008300 |
#define PRId_REVISION 0x000000FF /* Which revision is this */ |
|
/* Config register fields */ |
#define CONFIG_M 0x80000000 /* Hardwired to '1' to indicate presence of Config1 register */ |
#define CONFIG_K23 0x70000000 /* Controls cacheability of kseg2 and kseg3 in BAT */ |
#define CONFIG_KU 0x0E000000 /* Controls cacheability of ksegu in BAT */ |
#define CONFIG_MDU 0x00100000 /* MDU Type: 0 == Fast Multiplier Array; 1 == Iterative */ |
#define CONFIG_MM 0x00060000 /* Merge mode */ |
#define CONFIG_BM 0x00010000 /* Burst mode: 0 == Sequential; 1 == SubBlock */ |
#define CONFIG_BE 0x00008000 /* Endian mode: 0 == Little Endian; 1 == Big Endian */ |
#define CONFIG_AT 0x00006000 /* Architecture Type */ |
#define CONFIG_AR 0x00001C00 /* Architecture Revision */ |
#define CONFIG_MT 0x00000380 /* MMU Type */ |
#define CONFIG_K0 0x00000007 /* kseg0 coherency algorithm */ |
|
/* KSEG cache control codes */ |
#define CONFIG_KSEG2_3_CACHEABLE 0x30000000 /* KSeg2 and KSeg3 are cacheable/noncoherent/write-through/no write-allocate */ |
#define CONFIG_KSEG2_3_UNCACHEABLE 0x20000000 /* KSeg2 and KSeg3 are cacheable/noncoherent/write-through/no write-allocate */ |
#define CONFIG_KSEGU_CACHEABLE 0x06000000 /* KSegu is cacheable/noncoherent/write-through/no write-allocate */ |
#define CONFIG_KSEGU_UNCACHEABLE 0x04000000 /* KSegu is cacheable/noncoherent/write-through/no write-allocate */ |
#define CONFIG_KSEG0_CACHEABLE 0x00000003 /* KSeg0 is cacheable/noncoherent/write-through/no write-allocate */ |
#define CONFIG_KSEG0_UNCACHEABLE 0x00000002 /* KSeg0 is cacheable/noncoherent/write-through/no write-allocate */ |
|
/* Merge mode control codes */ |
#define CONFIG_NO_MERGING 0x00000000 |
#define CONFIG_SYSAD_VALID_MERGING 0x00200000 |
#define CONFIG_FULL_MERGING 0x00400000 |
|
/* Architecture Type codes */ |
#define CONFIG_AT_MIPS32 0x00000000 |
|
/* Architecture Revision codes */ |
#define CONFIG_AR_REVISION_1 0x00000000 |
|
/* MMU Type codes */ |
#define CONFIG_MMU_TYPE_STANDARD_TLB 0x00000080 |
#define CONFIG_MMU_TYPE_FIXED 0x00000180 |
|
/* Config1 register fields */ |
#define CONFIG1_MMU_SIZE_MASK 0x7E000000 /* Number of entries in the TLB minus 1 */ |
#define CONFIG1_IS 0x01C00000 /* Number of instruction cache sets per way */ |
#define CONFIG1_IL 0x00380000 /* Instruction cache line size */ |
#define CONFIG1_IA 0x00030000 /* Level of Instruction cache associativity */ |
#define CONFIG1_DS 0x0000E000 /* Number of data cache sets per way */ |
#define CONFIG1_DL 0x00001C00 /* Data cache line size */ |
#define CONFIG1_DA 0x00000380 /* Level of Data cache associativity */ |
#define CONFIG1_PC 0x00000010 /* Performance Counter registers implemented */ |
#define CONFIG1_WR 0x00000008 /* Watch registers implemented */ |
#define CONFIG1_CA 0x00000004 /* Code compression implemented */ |
#define CONFIG1_EP 0x00000002 /* EJTAG implemented */ |
#define CONFIG1_FP 0x00000001 /* FPU implemented */ |
|
/* Instruction cache sets-per-way codes */ |
#define CONFIG1_ICACHE_64_SETS_PER_WAY 0x00000000 |
#define CONFIG1_ICACHE_128_SETS_PER_WAY 0x00400000 |
#define CONFIG1_ICACHE_256_SETS_PER_WAY 0x00800000 |
|
/* Instruction cache line size codes */ |
#define CONFIG1_ICACHE_NOT_PRESET 0x00000000 |
#define CONFIG1_ICACHE_LINE_SIZE_32_BYTES 0x00200000 |
|
/* Instruction cache associativity codes */ |
#define CONFIG1_ICACHE_DIRECT_MAPPED 0x00000000 |
#define CONFIG1_ICACHE_2_WAY 0x00010000 |
#define CONFIG1_ICACHE_3_WAY 0x00020000 |
#define CONFIG1_ICACHE_4_WAY 0x00030000 |
|
/* Data cache sets-per-way codes */ |
#define CONFIG1_DCACHE_64_SETS_PER_WAY 0x00000000 |
#define CONFIG1_DCACHE_128_SETS_PER_WAY 0x00002000 |
#define CONFIG1_DCACHE_256_SETS_PER_WAY 0x00004000 |
|
/* Data cache line size codes */ |
#define CONFIG1_DCACHE_NOT_PRESET 0x00000000 |
#define CONFIG1_DCACHE_LINE_SIZE_32_BYTES 0x00001000 |
|
/* Data cache associativity codes */ |
#define CONFIG1_DCACHE_DIRECT_MAPPED 0x00000000 |
#define CONFIG1_DCACHE_2_WAY 0x00000080 |
#define CONFIG1_DCACHE_3_WAY 0x00000100 |
#define CONFIG1_DCACHE_4_WAY 0x00000180 |
|
#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS |
|
//-------------------------------------------------------------------------- |
#endif // CYGONCE_HAL_VAR_ARCH_H |
// End of var_arch.h |
/include/variant.inc
0,0 → 1,189
#ifndef CYGONCE_HAL_VARIANT_INC |
#define CYGONCE_HAL_VARIANT_INC |
##============================================================================= |
## |
## variant.inc |
## |
## MIPS 32 family assembler header file |
## |
##============================================================================= |
#####ECOSGPLCOPYRIGHTBEGIN#### |
## ------------------------------------------- |
## This file is part of eCos, the Embedded Configurable Operating System. |
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
## |
## eCos is free software; you can redistribute it and/or modify it under |
## the terms of the GNU General Public License as published by the Free |
## Software Foundation; either version 2 or (at your option) any later version. |
## |
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
## WARRANTY; without even the implied warranty of MERCHANTABILITY or |
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
## for more details. |
## |
## You should have received a copy of the GNU General Public License along |
## with eCos; if not, write to the Free Software Foundation, Inc., |
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
## |
## As a special exception, if other files instantiate templates or use macros |
## or inline functions from this file, or you compile this file and link it |
## with other works to produce a work based on this file, this file does not |
## by itself cause the resulting work to be covered by the GNU General Public |
## License. However the source code for this file must still be made available |
## in accordance with section (3) of the GNU General Public License. |
## |
## This exception does not invalidate any other reasons why a work based on |
## this file might be covered by the GNU General Public License. |
## |
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
## at http://sources.redhat.com/ecos/ecos-license/ |
## ------------------------------------------- |
#####ECOSGPLCOPYRIGHTEND#### |
##============================================================================= |
#######DESCRIPTIONBEGIN#### |
## |
## Author(s): dmoseley |
## Contributors: dmoseley |
## Date: 2001-01-30 |
## Purpose: MIPS64 family definitions. |
## Description: This file contains various definitions and macros that are |
## useful for writing assembly code for the MIPS64 CPU family. |
## Usage: |
## #include <cyg/hal/variant.inc> |
## ... |
## |
## |
######DESCRIPTIONEND#### |
## |
##============================================================================= |
|
#include <pkgconf/hal.h> |
|
#include <cyg/hal/mips.inc> |
|
#include <cyg/hal/platform.inc> |
|
#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS |
#include <cyg/hal/mips-regs.h> |
#include <cyg/hal/var_arch.h> |
|
##----------------------------------------------------------------------------- |
## Define CPU variant for architecture HAL. |
|
#define CYG_HAL_MIPS_MIPS64 |
|
# Set the KX bit to use 64 bit addressing in kernel mode. |
|
#define INITIAL_SR_VAR 0x00000080 |
|
#------------------------------------------------------------------------------ |
# Cache macros. |
|
#ifndef CYGPKG_HAL_MIPS_CACHE_DEFINED |
|
.macro hal_cache_init |
|
# Setup a temporary stack pointer for running C code. |
la a0,__interrupt_stack |
move sp,a0 |
CYGARC_ADDRESS_REG_UNCACHED(sp) |
|
# Read the CONFIG1 register into a0 |
mfc0 a0, C0_CONFIG, 1 |
nop |
nop |
nop |
|
# Jump to C-code to initialize caches (uncached) |
lar k0, hal_c_cache_init |
CYGARC_ADDRESS_REG_UNCACHED(k0) |
jalr k0 |
nop |
.endm |
|
#define CYGPKG_HAL_MIPS_CACHE_DEFINED |
|
#endif |
|
#------------------------------------------------------------------------------ |
# Monitor initialization. |
|
#ifndef CYGPKG_HAL_MIPS_MON_DEFINED |
|
#if defined(CYG_HAL_STARTUP_ROM) || \ |
( defined(CYG_HAL_STARTUP_RAM) && \ |
!defined(CYGSEM_HAL_USE_ROM_MONITOR)) |
# If we are starting up from ROM, or we are starting in |
# RAM and NOT using a ROM monitor, initialize the VSR table. |
|
.macro hal_mon_init |
la a0,__default_interrupt_vsr |
la a1,__default_exception_vsr |
la a3,hal_vsr_table |
|
sw a0,0(a3) |
sw a1,1*4(a3) |
sw a1,2*4(a3) |
sw a1,3*4(a3) |
sw a1,4*4(a3) |
sw a1,5*4(a3) |
sw a1,6*4(a3) |
sw a1,7*4(a3) |
sw a1,8*4(a3) |
sw a1,9*4(a3) |
sw a1,10*4(a3) |
sw a1,11*4(a3) |
sw a1,12*4(a3) |
sw a1,13*4(a3) |
sw a1,14*4(a3) |
sw a1,15*4(a3) |
|
sw a1,32*4(a3) |
sw a1,33*4(a3) |
.endm |
|
#elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR) |
|
# Initialize the VSR table entries |
# We only take control of the interrupt vector, |
# the rest are left to the ROM for now... |
|
.macro hal_mon_init |
la a0,__default_interrupt_vsr |
la a3,hal_vsr_table |
sw a0,0(a3) |
.endm |
|
#else |
|
.macro hal_mon_init |
.endm |
|
#endif |
|
|
#define CYGPKG_HAL_MIPS_MON_DEFINED |
|
#endif |
|
#------------------------------------------------------------------------------ |
# Decide whether the VSR table is defined externally, or is to be defined |
# here. |
|
#if defined(CYGPKG_HAL_MIPS_SIM) || \ |
( defined(CYGPKG_HAL_MIPS_ATLAS) && \ |
defined(CYG_HAL_STARTUP_RAM) && \ |
!defined(CYGSEM_HAL_USE_ROM_MONITOR) \ |
) |
|
## VSR table defined in linker script |
|
#else |
|
#define CYG_HAL_MIPS_VSR_TABLE_DEFINED |
|
#endif |
|
#------------------------------------------------------------------------------ |
#endif // ifndef CYGONCE_HAL_VARIANT_INC |
# end of variant.inc |
/src/var_misc.c
0,0 → 1,225
//========================================================================== |
// |
// var_misc.c |
// |
// HAL implementation miscellaneous functions |
// |
//========================================================================== |
//####ECOSGPLCOPYRIGHTBEGIN#### |
// ------------------------------------------- |
// This file is part of eCos, the Embedded Configurable Operating System. |
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
// |
// eCos is free software; you can redistribute it and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
// Software Foundation; either version 2 or (at your option) any later version. |
// |
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
// WARRANTY; without even the implied warranty of MERCHANTABILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with eCos; if not, write to the Free Software Foundation, Inc., |
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
// |
// As a special exception, if other files instantiate templates or use macros |
// or inline functions from this file, or you compile this file and link it |
// with other works to produce a work based on this file, this file does not |
// by itself cause the resulting work to be covered by the GNU General Public |
// License. However the source code for this file must still be made available |
// in accordance with section (3) of the GNU General Public License. |
// |
// This exception does not invalidate any other reasons why a work based on |
// this file might be covered by the GNU General Public License. |
// |
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
// at http://sources.redhat.com/ecos/ecos-license/ |
// ------------------------------------------- |
//####ECOSGPLCOPYRIGHTEND#### |
//========================================================================== |
//#####DESCRIPTIONBEGIN#### |
// |
// Author(s): nickg |
// Contributors: nickg, jlarmour, dmoseley |
// Date: 2000-07-14 |
// Purpose: HAL miscellaneous functions |
// Description: This file contains miscellaneous functions provided by the |
// HAL. |
// |
//####DESCRIPTIONEND#### |
// |
//========================================================================*/ |
|
#include <pkgconf/hal.h> |
|
#include <cyg/infra/cyg_type.h> // Base types |
#include <cyg/infra/cyg_trac.h> // tracing macros |
#include <cyg/infra/cyg_ass.h> // assertion macros |
|
#include <cyg/hal/hal_intr.h> |
|
#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS |
#include <cyg/hal/hal_arch.h> |
#include <cyg/hal/var_arch.h> |
#include <cyg/hal/plf_io.h> |
#include <cyg/hal/hal_cache.h> |
|
/*------------------------------------------------------------------------*/ |
// Array which stores the configured priority levels for the configured |
// interrupts. |
|
volatile CYG_BYTE hal_interrupt_level[CYGNUM_HAL_ISR_COUNT]; |
|
/*------------------------------------------------------------------------*/ |
|
void hal_variant_init(void) |
{ |
} |
|
/* |
* Uncomment the following to allow for dynamic cache sizing. |
* Currently we are going to assume the exact part specified in the ecosconfig stuff. |
* Perhaps in the near future this can all be done dynamically. |
*/ |
/* define DYNAMIC_CACHE_SIZING */ |
|
#if 0 |
#ifndef DYNAMIC_CACHE_SIZING |
#warning " \n\ |
STILL NEED TO IMPLEMENT DYNAMIC_CACHE_SIZING. \n\ |
ALSO, the HAL_PLATFORM_CPU/etc defines need to be dynamic. \n\ |
ALSO, need to do big endian stuff as well. \n\ |
Determine if network debug is necessary. \n\ |
Remove MIPS memc_init code" |
#endif |
#endif |
|
/*------------------------------------------------------------------------*/ |
// Initialize the caches |
|
int hal_init_icache(unsigned long config1_val) |
{ |
#ifdef DYNAMIC_CACHE_SIZING |
int icache_linesize, icache_assoc, icache_sets, icache_lines, icache_size; |
unsigned long cache_addr; |
|
switch (config1_val & CONFIG1_IL) |
{ |
case CONFIG1_ICACHE_LINE_SIZE_32_BYTES: icache_linesize = 32; break; |
case CONFIG1_ICACHE_NOT_PRESET: return -1; break; |
default: /* Error */ return -1; break; |
} |
|
switch (config1_val & CONFIG1_IA) |
{ |
case CONFIG1_ICACHE_DIRECT_MAPPED: icache_assoc = 1; break; |
case CONFIG1_ICACHE_2_WAY: icache_assoc = 2; break; |
case CONFIG1_ICACHE_3_WAY: icache_assoc = 3; break; |
case CONFIG1_ICACHE_4_WAY: icache_assoc = 4; break; |
default: /* Error */ return -1; break; |
} |
|
switch (config1_val & CONFIG1_IS) |
{ |
case CONFIG1_ICACHE_64_SETS_PER_WAY: icache_sets = 64; break; |
case CONFIG1_ICACHE_128_SETS_PER_WAY: icache_sets = 128; break; |
case CONFIG1_ICACHE_256_SETS_PER_WAY: icache_sets = 256; break; |
default: /* Error */ return -1; break; |
} |
|
icache_lines = icache_sets * icache_assoc; |
icache_size = icache_lines * icache_linesize; |
#endif /* DYNAMIC_CACHE_SIZING */ |
|
/* |
* Reset does not invalidate the cache so let's do so now. |
*/ |
HAL_ICACHE_INVALIDATE_ALL(); |
|
#ifdef DYNAMIC_CACHE_SIZING |
return icache_size; |
#else |
return HAL_ICACHE_SIZE; |
#endif |
} |
|
int hal_init_dcache(unsigned long config1_val) |
{ |
#ifdef DYNAMIC_CACHE_SIZING |
int dcache_linesize, dcache_assoc, dcache_sets, dcache_lines, dcache_size; |
|
switch (config1_val & CONFIG1_DL) |
{ |
case CONFIG1_DCACHE_LINE_SIZE_32_BYTES: dcache_linesize = 32; break; |
case CONFIG1_DCACHE_NOT_PRESET: return -1; break; |
default: /* Error */ return -1; break; |
} |
|
switch (config1_val & CONFIG1_DA) |
{ |
case CONFIG1_DCACHE_DIRECT_MAPPED: dcache_assoc = 1; break; |
case CONFIG1_DCACHE_2_WAY: dcache_assoc = 2; break; |
case CONFIG1_DCACHE_3_WAY: dcache_assoc = 3; break; |
case CONFIG1_DCACHE_4_WAY: dcache_assoc = 4; break; |
default: /* Error */ return -1; break; |
} |
|
switch (config1_val & CONFIG1_DS) |
{ |
case CONFIG1_DCACHE_64_SETS_PER_WAY: dcache_sets = 64; break; |
case CONFIG1_DCACHE_128_SETS_PER_WAY: dcache_sets = 128; break; |
case CONFIG1_DCACHE_256_SETS_PER_WAY: dcache_sets = 256; break; |
default: /* Error */ return -1; break; |
} |
|
dcache_lines = dcache_sets * dcache_assoc; |
dcache_size = dcache_lines * dcache_linesize; |
#endif /* DYNAMIC_CACHE_SIZING */ |
|
/* |
* Reset does not invalidate the cache so let's do so now. |
*/ |
HAL_DCACHE_INVALIDATE_ALL(); |
|
#ifdef DYNAMIC_CACHE_SIZING |
return dcache_size; |
#else |
return HAL_DCACHE_SIZE; |
#endif |
} |
|
void hal_c_cache_init(unsigned long config1_val) |
{ |
volatile unsigned val; |
|
if (hal_init_icache(config1_val) == -1) |
{ |
/* Error */ |
; |
} |
|
if (hal_init_dcache(config1_val) == -1) |
{ |
/* Error */ |
; |
} |
|
// enable cached KSEG0 |
asm volatile("mfc0 %0,$16;" : "=r"(val)); |
val &= ~3; |
asm volatile("mtc0 %0,$16;" : : "r"(val)); |
} |
|
void hal_icache_sync(void) |
{ |
HAL_ICACHE_INVALIDATE_ALL(); |
} |
|
void hal_dcache_sync(void) |
{ |
HAL_DCACHE_INVALIDATE_ALL(); |
} |
|
/*------------------------------------------------------------------------*/ |
/* End of var_misc.c */ |
/src/variant.S
0,0 → 1,77
##============================================================================= |
## |
## variant.S |
## |
## MIPS 64 variant code |
## |
##============================================================================= |
#####ECOSGPLCOPYRIGHTBEGIN#### |
## ------------------------------------------- |
## This file is part of eCos, the Embedded Configurable Operating System. |
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
## |
## eCos is free software; you can redistribute it and/or modify it under |
## the terms of the GNU General Public License as published by the Free |
## Software Foundation; either version 2 or (at your option) any later version. |
## |
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
## WARRANTY; without even the implied warranty of MERCHANTABILITY or |
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
## for more details. |
## |
## You should have received a copy of the GNU General Public License along |
## with eCos; if not, write to the Free Software Foundation, Inc., |
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
## |
## As a special exception, if other files instantiate templates or use macros |
## or inline functions from this file, or you compile this file and link it |
## with other works to produce a work based on this file, this file does not |
## by itself cause the resulting work to be covered by the GNU General Public |
## License. However the source code for this file must still be made available |
## in accordance with section (3) of the GNU General Public License. |
## |
## This exception does not invalidate any other reasons why a work based on |
## this file might be covered by the GNU General Public License. |
## |
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
## at http://sources.redhat.com/ecos/ecos-license/ |
## ------------------------------------------- |
#####ECOSGPLCOPYRIGHTEND#### |
##============================================================================= |
#######DESCRIPTIONBEGIN#### |
## |
## Author(s): dmoseley |
## Contributors: dmoseley |
## Date: 2000-06-07 |
## Purpose: MIPS 64 variant code |
## Description: Variant specific code for MIPS64 architecture. |
## |
## |
## |
## |
######DESCRIPTIONEND#### |
## |
##============================================================================= |
|
#include <pkgconf/system.h> |
#include <pkgconf/hal.h> |
|
#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS |
#include <cyg/hal/mips-regs.h> |
|
#ifdef CYGPKG_KERNEL |
# include <pkgconf/kernel.h> |
#endif |
|
#include <cyg/hal/arch.inc> |
|
#include <cyg/hal/var_arch.h> |
#include <cyg/hal/hal_arch.h> |
|
##----------------------------------------------------------------------------- |
# Variant Initialization. |
# This code performs variant specific initialization. |
|
##----------------------------------------------------------------------------- |
## end of variant.S |
|
/src/mips_mips64.ld
0,0 → 1,386
//=========================================================================== |
// |
// MLT linker script for MIPS64 |
// |
//=========================================================================== |
//####ECOSGPLCOPYRIGHTBEGIN#### |
// ------------------------------------------- |
// This file is part of eCos, the Embedded Configurable Operating System. |
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
// |
// eCos is free software; you can redistribute it and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
// Software Foundation; either version 2 or (at your option) any later version. |
// |
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
// WARRANTY; without even the implied warranty of MERCHANTABILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with eCos; if not, write to the Free Software Foundation, Inc., |
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
// |
// As a special exception, if other files instantiate templates or use macros |
// or inline functions from this file, or you compile this file and link it |
// with other works to produce a work based on this file, this file does not |
// by itself cause the resulting work to be covered by the GNU General Public |
// License. However the source code for this file must still be made available |
// in accordance with section (3) of the GNU General Public License. |
// |
// This exception does not invalidate any other reasons why a work based on |
// this file might be covered by the GNU General Public License. |
// |
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
// at http://sources.redhat.com/ecos/ecos-license/ |
// ------------------------------------------- |
//####ECOSGPLCOPYRIGHTEND#### |
//=========================================================================== |
|
#include <pkgconf/system.h> |
|
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", |
"elf32-littlemips") |
/* The preprocessor defines mips, but we know we're mips :-) */ |
#undef mips |
OUTPUT_ARCH(mips:isa64) |
|
STARTUP(vectors.o) |
ENTRY(reset_vector) |
#ifdef EXTRAS |
INPUT(extras.o) |
#endif |
#if (__GNUC__ >= 3) |
GROUP(libtarget.a libgcc.a libsupc++.a) |
#else |
GROUP(libtarget.a libgcc.a) |
#endif |
|
/* FIXME: The MLT should pass in the required alignment since it must be |
* the same as the VMA's alignment. As a result of this bug, all the MIPS64 |
* ROM mlt files have alignment 8, when some should have alignment 4 |
* (902557-CR) |
*/ |
#define ALIGN_LMA 0x40 |
#define FOLLOWING(_section_) AT ((LOADADDR (_section_) + SIZEOF (_section_) + ALIGN_LMA - 1) & ~ (ALIGN_LMA - 1)) |
#define LMA_EQ_VMA |
#define FORCE_OUTPUT . = . |
|
#define SECTIONS_BEGIN |
|
#if defined(CYG_HAL_STARTUP_RAM) |
|
/* this version for RAM startup */ |
#define SECTION_rom_vectors(_region_, _vma_, _lma_) \ |
.rom_vectors _vma_ : _lma_ \ |
{ KEEP (*(.utlb_vector)) \ |
. = ALIGN(0x80); KEEP(*(.other_vector)) \ |
/* debug and reset vector not used in RAM version */ \ |
KEEP(*(.debug_vector)) \ |
KEEP (*(.reset_vector)) } \ |
> _region_ |
|
#elif defined(CYG_HAL_STARTUP_ROM) |
|
/* this version for ROM startup */ |
#define SECTION_rom_vectors(_region_, _vma_, _lma_) \ |
.rom_vectors _vma_ : _lma_ \ |
{ KEEP (*(.reset_vector)) \ |
. = ALIGN(0x200); KEEP (*(.utlb_vector)) \ |
. = . + 0x100; \ |
. = ALIGN(0x80); KEEP(*(.other_vector)) \ |
. = . + 0x80; \ |
. = ALIGN(0x80); KEEP(*(.debug_vector)) } \ |
> _region_ |
|
#endif /* ROM startup version of ROM vectors */ |
|
#define SECTION_ROMISC(_region_, _vma_, _lma_) \ |
.interp _vma_ : _lma_ { *(.interp) } > _region_ \ |
.hash : FOLLOWING(.interp) { *(.hash) } > _region_ \ |
.dynsym : FOLLOWING(.hash) { *(.dynsym) } > _region_ \ |
.dynstr : FOLLOWING(.dynsym) { *(.dynstr) } > _region_ \ |
.gnu.version : FOLLOWING(.dynstr) { *(.gnu.version) } > _region_ \ |
.gnu.version_d : FOLLOWING(.gnu.version) { *(.gnu.version_d) } > _region_ \ |
.gnu.version_r : FOLLOWING(.gnu.version_d) { *(.gnu.version_r) } > _region_ \ |
.plt : FOLLOWING(.gnu.version_r) { *(.plt) } > _region_ |
|
#define SECTION_RELOCS(_region_, _vma_, _lma_) \ |
.rel.text : \ |
{ \ |
*(.rel.text) \ |
*(.rel.text.*) \ |
*(.rel.gnu.linkonce.t*) \ |
} > _region_ \ |
.rela.text : \ |
{ \ |
*(.rela.text) \ |
*(.rela.text.*) \ |
*(.rela.gnu.linkonce.t*) \ |
} > _region_ \ |
.rel.data : \ |
{ \ |
*(.rel.data) \ |
*(.rel.data.*) \ |
*(.rel.gnu.linkonce.d*) \ |
} > _region_ \ |
.rela.data : \ |
{ \ |
*(.rela.data) \ |
*(.rela.data.*) \ |
*(.rela.gnu.linkonce.d*) \ |
} > _region_ \ |
.rel.rodata : \ |
{ \ |
*(.rel.rodata) \ |
*(.rel.rodata.*) \ |
*(.rel.gnu.linkonce.r*) \ |
} > _region_ \ |
.rela.rodata : \ |
{ \ |
*(.rela.rodata) \ |
*(.rela.rodata.*) \ |
*(.rela.gnu.linkonce.r*) \ |
} > _region_ \ |
.rel.got : { *(.rel.got) } > _region_ \ |
.rela.got : { *(.rela.got) } > _region_ \ |
.rel.ctors : { *(.rel.ctors) } > _region_ \ |
.rela.ctors : { *(.rela.ctors) } > _region_ \ |
.rel.dtors : { *(.rel.dtors) } > _region_ \ |
.rela.dtors : { *(.rela.dtors) } > _region_ \ |
.rel.init : { *(.rel.init) } > _region_ \ |
.rela.init : { *(.rela.init) } > _region_ \ |
.rel.fini : { *(.rel.fini) } > _region_ \ |
.rela.fini : { *(.rela.fini) } > _region_ \ |
.rel.bss : { *(.rel.bss) } > _region_ \ |
.rela.bss : { *(.rela.bss) } > _region_ \ |
.rel.plt : { *(.rel.plt) } > _region_ \ |
.rela.plt : { *(.rela.plt) } > _region_ \ |
.rel.dyn : { *(.rel.dyn) } > _region_ |
|
#define SECTION_init(_region_, _vma_, _lma_) \ |
.init _vma_ : _lma_ \ |
{ \ |
FORCE_OUTPUT; KEEP (*(.init)) \ |
} > _region_ =0 |
|
#define SECTION_text(_region_, _vma_, _lma_) \ |
.text _vma_ : _lma_ \ |
{ \ |
_stext = .; _ftext = . ; \ |
*(.text) \ |
*(.text.*) \ |
*(.stub) \ |
*(.gnu.warning) \ |
*(.gnu.linkonce.t*) \ |
*(.mips16.fn.*) *(.mips16.call.*) \ |
} > _region_ =0 \ |
_etext = .; PROVIDE (etext = .); |
|
#define SECTION_fini(_region_, _vma_, _lma_) \ |
.fini _vma_ : _lma_ \ |
{ \ |
FORCE_OUTPUT; KEEP (*(.fini)) \ |
} > _region_ =0 |
|
#define SECTION_rodata(_region_, _vma_, _lma_) \ |
.rodata _vma_ : _lma_ \ |
{ \ |
FORCE_OUTPUT; *(.rodata) *(.rodata.*) *(.gnu.linkonce.r*) \ |
} > _region_ |
|
#define SECTION_rodata1(_region_, _vma_, _lma_) \ |
.rodata1 _vma_ : _lma_ \ |
{ \ |
FORCE_OUTPUT; *(.rodata1) *(.rodata1.*) \ |
} > _region_ |
|
#define SECTION_vsr_table(_region_, _vma_, _lma_) \ |
.vsr_table _vma_ : _lma_ \ |
{ \ |
FORCE_OUTPUT; *(.vsr_table) \ |
} > _region_ |
|
#define SECTION_data(_region_, _vma_, _lma_) \ |
.data _vma_ : _lma_ \ |
{ \ |
__ram_data_start = ABSOLUTE (.); _fdata = . ; \ |
*(.data) *(.data.*) *(.gnu.linkonce.d*) \ |
*( .2ram.*) \ |
. = ALIGN (8); \ |
SORT(CONSTRUCTORS) \ |
} > _region_ \ |
__rom_data_start = LOADADDR(.data); |
|
#define SECTION_data1(_region_, _vma_, _lma_) \ |
.data1 _vma_ : _lma_ \ |
{ \ |
FORCE_OUTPUT; *(.data1) *(.data1.*) \ |
} > _region_ |
|
#define SECTION_eh_frame(_region_, _vma_, _lma_) \ |
.eh_frame _vma_ : _lma_ \ |
{ \ |
FORCE_OUTPUT; *(.eh_frame) \ |
} > _region_ |
|
#define SECTION_gcc_except_table(_region_, _vma_, _lma_) \ |
.gcc_except_table _vma_ : _lma_ \ |
{ \ |
FORCE_OUTPUT; *(.gcc_except_table) \ |
} > _region_ |
|
|
/* gcc uses crtbegin.o to find the start of |
the constructors, so we make sure it is |
first. Because this is a wildcard, it |
doesn't matter if the user does not |
actually link against crtbegin.o; the |
linker won't look for a file to match a |
wildcard. The wildcard also means that it |
doesn't matter which directory crtbegin.o |
is in. */ |
|
/* We don't want to include the .ctors section from |
the crtend.o file until after the sorted ctors. |
The .ctor section from the crtend file contains the |
end of ctors marker and it must be last */ |
|
/* FIXME: We shouldn't need to define __CTOR_LIST__/__CTOR_END__ |
and __DTOR_LIST__/__DTOR_END__ except by the PROVIDE lines. |
However this doesn't work for old (99r1-era) toolchains, so |
leave it for now. */ |
|
#define SECTION_ctors(_region_, _vma_, _lma_) \ |
.ctors _vma_ : _lma_ \ |
{ \ |
FORCE_OUTPUT; \ |
KEEP (*crtbegin.o(.ctors)) \ |
__CTOR_LIST__ = .; \ |
PROVIDE (__CTOR_LIST__ = .); \ |
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) \ |
KEEP (*(SORT(.ctors.*))) \ |
KEEP (*(.ctors)) \ |
__CTOR_END__ = .; \ |
PROVIDE (__CTOR_END__ = .); \ |
} > _region_ |
|
#define SECTION_dtors(_region_, _vma_, _lma_) \ |
.dtors _vma_ : _lma_ \ |
{ \ |
FORCE_OUTPUT; \ |
KEEP (*crtbegin.o(.dtors)) \ |
__DTOR_LIST__ = .; \ |
PROVIDE (__DTOR_LIST__ = .); \ |
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) \ |
KEEP (*(SORT(.dtors.*))) \ |
KEEP (*(.dtors)) \ |
__DTOR_END__ = .; \ |
PROVIDE (__DTOR_END__ = .); \ |
} > _region_ |
|
#define SECTION_devtab(_region_, _vma_, _lma_) \ |
.devtab _vma_ : _lma_ \ |
{ \ |
FORCE_OUTPUT; \ |
KEEP(*( SORT (.ecos.table.*))) ; \ |
} > _region_ |
|
#define SECTION_got(_region_, _vma_, _lma_) \ |
_gp = ALIGN(16) + 0x7ff0; \ |
.got _vma_ : _lma_ \ |
{ \ |
FORCE_OUTPUT; *(.got.plt) *(.got) \ |
} > _region_ |
|
#define SECTION_dynamic(_region_, _vma_, _lma_) \ |
.dynamic _vma_ : _lma_ \ |
{ \ |
FORCE_OUTPUT; *(.dynamic) \ |
} > _region_ |
|
/* We want the small data sections together, so single-instruction offsets |
can access them all, and initialized data all before uninitialized, so |
we can shorten the on-disk segment size. */ |
|
#define SECTION_sdata(_region_, _vma_, _lma_) \ |
.sdata _vma_ : _lma_ \ |
{ \ |
FORCE_OUTPUT; *(.sdata) *(.sdata.*) *(.gnu.linkonce.s*) \ |
} > _region_ |
|
#define SECTION_lit8(_region_, _vma_, _lma_) \ |
.lit8 _vma_ : _lma_ \ |
{ \ |
FORCE_OUTPUT; *(.lit8) \ |
} > _region_ |
|
#define SECTION_lit4(_region_, _vma_, _lma_) \ |
.lit4 : FOLLOWING(.lit8) \ |
{ \ |
FORCE_OUTPUT; *(.lit4) \ |
} > _region_ \ |
__ram_data_end = .; _edata = . ; \ |
PROVIDE (edata = .); |
|
#define SECTION_sbss(_region_, _vma_, _lma_) \ |
__bss_start = .; _fbss = .; \ |
.sbss _vma_ : _lma_ \ |
{ \ |
FORCE_OUTPUT; *(.dynsbss) *(.sbss) *(.sbss.*) *(.scommon) \ |
} > _region_ |
|
#define SECTION_bss(_region_, _vma_, _lma_) \ |
.bss _vma_ : _lma_ \ |
{ \ |
*(.dynbss) *(.bss) *(.bss.*) *(COMMON) \ |
} > _region_ \ |
__bss_end = .; |
|
/* The /DISCARD/ section ensures that the output will not contain a |
* .mdebug section as it confuses GDB. This is a workaround for CR 100804. |
*/ |
|
#define SECTIONS_END . = ALIGN(4); _end = .; PROVIDE (end = .); \ |
/* Stabs debugging sections. */ \ |
.stab 0 : { *(.stab) } \ |
.stabstr 0 : { *(.stabstr) } \ |
.stab.excl 0 : { *(.stab.excl) } \ |
.stab.exclstr 0 : { *(.stab.exclstr) } \ |
.stab.index 0 : { *(.stab.index) } \ |
.stab.indexstr 0 : { *(.stab.indexstr) } \ |
.comment 0 : { *(.comment) } \ |
/* DWARF debug sections. \ |
Symbols in the DWARF debugging sections are relative to \ |
the beginning of the section so we begin them at 0. */ \ |
/* DWARF 1 */ \ |
.debug 0 : { *(.debug) } \ |
.line 0 : { *(.line) } \ |
/* GNU DWARF 1 extensions */ \ |
.debug_srcinfo 0 : { *(.debug_srcinfo) } \ |
.debug_sfnames 0 : { *(.debug_sfnames) } \ |
/* DWARF 1.1 and DWARF 2 */ \ |
.debug_aranges 0 : { *(.debug_aranges) } \ |
.debug_pubnames 0 : { *(.debug_pubnames) } \ |
/* DWARF 2 */ \ |
.debug_info 0 : { *(.debug_info) } \ |
.debug_abbrev 0 : { *(.debug_abbrev) } \ |
.debug_line 0 : { *(.debug_line) } \ |
.debug_frame 0 : { *(.debug_frame) } \ |
.debug_str 0 : { *(.debug_str) } \ |
.debug_loc 0 : { *(.debug_loc) } \ |
.debug_macinfo 0 : { *(.debug_macinfo) } \ |
/* SGI/MIPS DWARF 2 extensions */ \ |
.debug_weaknames 0 : { *(.debug_weaknames) } \ |
.debug_funcnames 0 : { *(.debug_funcnames) } \ |
.debug_typenames 0 : { *(.debug_typenames) } \ |
.debug_varnames 0 : { *(.debug_varnames) } \ |
/* These must appear regardless of . */ \ |
.gptab.sdata : { *(.gptab.data) *(.gptab.sdata) } \ |
.gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) } \ |
/DISCARD/ 0 : { *(.mdebug) } |
|
#include CYGHWR_MEMORY_LAYOUT_LDI |
|
hal_vsr_table = 0x80000200; |
hal_virtual_vector_table = 0x80000300; |
/ChangeLog
0,0 → 1,86
2003-04-10 Nick Garnett <nickg@balti.calivar.com> |
|
* src/mips_mips64.ld: |
Added libsupc++.a to GROUP() directive for GCC versions later than |
3.0. |
|
2003-04-09 Jonathan Larmour <jifl@eCosCentric.com> |
|
* src/mips_mips64.ld: |
Fix .gnulinkonce.s -> .gnu.linkonce.s typo. |
|
2002-05-24 Jesper Skov <jskov@redhat.com> |
|
* include/var_arch.h: Removed HAL_DIAG_IRQ_CHECK. It's not |
implemented. |
|
2002-05-22 Jesper Skov <jskov@redhat.com> |
|
* include/var_arch.h: Added __ASSEMBLER__ protection. |
|
2001-12-04 Nick Garnett <nickg@redhat.com> |
|
* include/var_arch.h: Added macros to read/write CP0 registers. |
|
* cdl/hal_mips_mips64.cdl: Added CYGPKG_HAL_MIPS_GDB_REPORT_CP0 |
option to enable reporting of CP0 registers to GDB. |
|
2001-11-06 Mark Salter <msalter@redhat.com> |
|
* src/mips_mips64.ld: Add .2ram section. |
|
2001-02-23 Jesper Skov <jskov@redhat.com> |
|
* include/var_cache.h: Removed HAL_FLASH_CACHES_WANT_OPTIMAL. It |
is now the default. |
|
2001-02-15 Nick Garnett <nickg@cygnus.co.uk> |
|
* src/variant.S: Removed ISR tables. |
|
2001-01-30 Nick Garnett <nickg@cygnus.co.uk> |
|
* cdl/hal_mips_mips64.cdl: New variant support - just a 64 bit |
version of the MIPS32 variant. |
* include/var_arch.h: Ditto. |
* include/var_cache.h: Ditto. |
* include/var_intr.h: Ditto. |
* include/variant.inc: Ditto. |
* src/mips_mips64.ld: Ditto. |
* src/var_misc.c: Ditto. |
* src/variant.S: Ditto. |
|
//=========================================================================== |
//####ECOSGPLCOPYRIGHTBEGIN#### |
// ------------------------------------------- |
// This file is part of eCos, the Embedded Configurable Operating System. |
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
// |
// eCos is free software; you can redistribute it and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
// Software Foundation; either version 2 or (at your option) any later version. |
// |
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
// WARRANTY; without even the implied warranty of MERCHANTABILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with eCos; if not, write to the Free Software Foundation, Inc., |
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
// |
// As a special exception, if other files instantiate templates or use macros |
// or inline functions from this file, or you compile this file and link it |
// with other works to produce a work based on this file, this file does not |
// by itself cause the resulting work to be covered by the GNU General Public |
// License. However the source code for this file must still be made available |
// in accordance with section (3) of the GNU General Public License. |
// |
// This exception does not invalidate any other reasons why a work based on |
// this file might be covered by the GNU General Public License. |
// |
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
// at http://sources.redhat.com/ecos/ecos-license/ |
// ------------------------------------------- |
//####ECOSGPLCOPYRIGHTEND#### |
//=========================================================================== |