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URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

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    /openrisc/trunk/rtos/ecos-2.0/packages/hal/mips/ref4955/v2_0/src
    from Rev 27 to Rev 174
    ↔ Reverse comparison
  •

Rev 27 → Rev 174

/plf_stub.c
0,0 → 1,70
//=============================================================================
//
// plf_stub.c
//
// Platform specific code for GDB stub support.
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
// Contributors:jskov
// Date: 2000-05-15
// Purpose: Platform specific code for GDB stub support.
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
 
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 
#include <cyg/hal/hal_stub.h>
 
#include <cyg/hal/hal_io.h> // HAL IO macros
 
//-----------------------------------------------------------------------------
// Stub init
 
void
hal_plf_stub_init(void)
{
}
 
#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
//-----------------------------------------------------------------------------
// End of plf_stub.c
/pc87338.c
0,0 → 1,418
#ifndef CYGONCE_HAL_PC_SER_H
#define CYGONCE_HAL_PC_SER_H
//=============================================================================
//
// pc87338.c
//
// Simple driver for the serial controllers in the PC87338 SuperIO chip
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
// Contributors:jskov
// Date: 2000-06-20
// Description: Simple driver for the PC87338 serial controllers
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/hal/hal_arch.h> // SAVE/RESTORE GP macros
#include <cyg/hal/hal_io.h> // IO macros
#include <cyg/hal/hal_if.h> // interface API
#include <cyg/hal/hal_intr.h> // HAL_ENABLE/MASK/UNMASK_INTERRUPTS
#include <cyg/hal/hal_misc.h> // Helper functions
#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED
 
//-----------------------------------------------------------------------------
// Controller definitions.
 
//-----------------------------------------------------------------------------
// There are two serial ports.
#define CYG_DEVICE_SERIAL_SCC1 0xb40003f8 // port 1
#define CYG_DEVICE_SERIAL_SCC2 0xb40002f8 // port 2
 
//-----------------------------------------------------------------------------
// Serial registers (shared by all banks)
#define CYG_DEVICE_BSR (0x03)
#define CYG_DEVICE_LCR (0x03)
 
#define CYG_DEVICE_BSR_BANK0 0x00
#define CYG_DEVICE_BSR_BANK2 0xe0
 
#define CYG_DEVICE_LCR_LEN_5BIT 0x00
#define CYG_DEVICE_LCR_LEN_6BIT 0x01
#define CYG_DEVICE_LCR_LEN_7BIT 0x02
#define CYG_DEVICE_LCR_LEN_8BIT 0x03
#define CYG_DEVICE_LCR_STOP_1 0x00
#define CYG_DEVICE_LCR_STOP_2 0x04
#define CYG_DEVICE_LCR_PARITY_NONE 0x00
#define CYG_DEVICE_LCR_PARITY_ODD 0x08
#define CYG_DEVICE_LCR_PARITY_EVEN 0x18
#define CYG_DEVICE_LCR_PARITY_LOGIC1 0x28
#define CYG_DEVICE_LCR_PARITY_LOGIC0 0x38
#define CYG_DEVICE_LCR_SBRK 0x40
 
// Bank 0 (control/status)
#define CYG_DEVICE_BK0_TXD (0x00)
#define CYG_DEVICE_BK0_RXD (0x00)
#define CYG_DEVICE_BK0_IER (0x01)
#define CYG_DEVICE_BK0_EIR (0x02)
#define CYG_DEVICE_BK0_FCR (0x02)
#define CYG_DEVICE_BK0_MCR (0x04)
#define CYG_DEVICE_BK0_LSR (0x05)
#define CYG_DEVICE_BK0_MSR (0x06)
#define CYG_DEVICE_BK0_SPR (0x07)
#define CYG_DEVICE_BK0_ASCR (0x07)
 
#define CYG_DEVICE_BK0_LSR_RXDA 0x01
#define CYG_DEVICE_BK0_LSR_OE 0x02
#define CYG_DEVICE_BK0_LSR_PE 0x04
#define CYG_DEVICE_BK0_LSR_FE 0x08
#define CYG_DEVICE_BK0_LSR_BRK 0x10
#define CYG_DEVICE_BK0_LSR_TXRDY 0x20
#define CYG_DEVICE_BK0_LSR_TXEMP 0x40
#define CYG_DEVICE_BK0_LSR_ER_INF 0x80
 
#define CYG_DEVICE_BK0_IER_TMR_IE 0x80
#define CYG_DEVICE_BK0_IER_SFIF_IE 0x40
#define CYG_DEVICE_BK0_IER_TXEMP_IE 0x20
#define CYG_DEVICE_BK0_IER_DMA_IE 0x10
#define CYG_DEVICE_BK0_IER_MS_IE 0x08
#define CYG_DEVICE_BK0_IER_LS_IE 0x04
#define CYG_DEVICE_BK0_IER_TXLDL_IE 0x02
#define CYG_DEVICE_BK0_IER_RXHDL_IE 0x01
 
#define CYG_DEVICE_BK0_EIR_FEN1 0x80
#define CYG_DEVICE_BK0_EIR_FEN0 0x40
#define CYG_DEVICE_BK0_EIR_RXFT 0x08
#define CYG_DEVICE_BK0_EIR_IPR1 0x04
#define CYG_DEVICE_BK0_EIR_IPR0 0x02
#define CYG_DEVICE_BK0_EIR_IPF 0x01
 
#define CYG_DEVICE_BK0_EIR_mask 0x07
#define CYG_DEVICE_BK0_EIR_IRQ_ERR 0x06
#define CYG_DEVICE_BK0_EIR_IRQ_RX 0x04
#define CYG_DEVICE_BK0_EIR_IRQ_TX 0x02
 
#define CYG_DEVICE_BK0_MCR_ISEN 0x08 // interrupt signal enable
 
 
// Bank 2 (baud generator)
#define CYG_DEVICE_BK2_BGDL (0x00)
#define CYG_DEVICE_BK2_BGDH (0x01)
#define CYG_DEVICE_BK2_EXCR1 (0x02)
#define CYG_DEVICE_BK2_EXCR2 (0x04)
#define CYG_DEVICE_BK2_TXFLV (0x06)
#define CYG_DEVICE_BK2_RXFLV (0x07)
 
 
//-----------------------------------------------------------------------------
typedef struct {
cyg_uint8* base;
cyg_int32 msec_timeout;
int isr_vector;
} channel_data_t;
 
//-----------------------------------------------------------------------------
// The minimal init, get and put functions. All by polling.
 
void
cyg_hal_plf_serial_init_channel(void* __ch_data)
{
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
cyg_uint8 lcr;
 
HAL_WRITE_UINT8(base+CYG_DEVICE_BSR, CYG_DEVICE_BSR_BANK0);
HAL_WRITE_UINT8(base+CYG_DEVICE_BK0_IER, 0);
HAL_WRITE_UINT8(base+CYG_DEVICE_BK0_MCR, CYG_DEVICE_BK0_MCR_ISEN);
 
// Disable FIFOs
HAL_WRITE_UINT8(base+CYG_DEVICE_BK0_FCR, 0);
 
// 8-1-no parity.
HAL_WRITE_UINT8(base+CYG_DEVICE_LCR,
CYG_DEVICE_LCR_LEN_8BIT | CYG_DEVICE_LCR_STOP_1 | CYG_DEVICE_LCR_PARITY_NONE);
 
// Set speed to 38400 (switch bank, remember old LCR setting)
HAL_READ_UINT8(base+CYG_DEVICE_LCR, lcr);
HAL_WRITE_UINT8(base+CYG_DEVICE_BSR, CYG_DEVICE_BSR_BANK2);
HAL_WRITE_UINT8(base+CYG_DEVICE_BK2_BGDL, 3);
HAL_WRITE_UINT8(base+CYG_DEVICE_BK2_BGDH, 0);
HAL_WRITE_UINT8(base+CYG_DEVICE_LCR, lcr);
}
 
void
cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 __ch)
{
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
cyg_uint8 lsr;
CYGARC_HAL_SAVE_GP();
 
do {
HAL_READ_UINT8(base+CYG_DEVICE_BK0_LSR, lsr);
} while ((lsr & CYG_DEVICE_BK0_LSR_TXRDY) == 0);
 
HAL_WRITE_UINT8(base+CYG_DEVICE_BK0_TXD, __ch);
 
// Hang around until the character has been safely sent.
do {
HAL_READ_UINT8(base+CYG_DEVICE_BK0_LSR, lsr);
} while ((lsr & CYG_DEVICE_BK0_LSR_TXRDY) == 0);
 
CYGARC_HAL_RESTORE_GP();
}
 
static cyg_bool
cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
{
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
cyg_uint8 lsr;
 
HAL_READ_UINT8(base+CYG_DEVICE_BK0_LSR, lsr);
if ((lsr & CYG_DEVICE_BK0_LSR_RXDA) == 0)
return false;
 
HAL_READ_UINT8 (base+CYG_DEVICE_BK0_RXD, *ch);
 
return true;
}
 
cyg_uint8
cyg_hal_plf_serial_getc(void* __ch_data)
{
cyg_uint8 ch;
CYGARC_HAL_SAVE_GP();
 
while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
 
CYGARC_HAL_RESTORE_GP();
return ch;
}
 
static channel_data_t channels[2] = {
{ (cyg_uint8*)CYG_DEVICE_SERIAL_SCC1, 1000, CYGNUM_HAL_INTERRUPT_DEBUG_UART},
{ (cyg_uint8*)CYG_DEVICE_SERIAL_SCC2, 1000, CYGNUM_HAL_INTERRUPT_USER_UART}
};
 
static void
cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
cyg_uint32 __len)
{
CYGARC_HAL_SAVE_GP();
 
while(__len-- > 0)
cyg_hal_plf_serial_putc(__ch_data, *__buf++);
 
CYGARC_HAL_RESTORE_GP();
}
 
static void
cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
{
CYGARC_HAL_SAVE_GP();
 
while(__len-- > 0)
*__buf++ = cyg_hal_plf_serial_getc(__ch_data);
 
CYGARC_HAL_RESTORE_GP();
}
 
 
cyg_bool
cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
{
int delay_count;
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_bool res;
CYGARC_HAL_SAVE_GP();
 
delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
 
for(;;) {
res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
if (res || 0 == delay_count--)
break;
CYGACC_CALL_IF_DELAY_US(100);
}
 
CYGARC_HAL_RESTORE_GP();
return res;
}
 
static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_uint8 ier;
int ret = 0;
CYGARC_HAL_SAVE_GP();
 
switch (__func) {
case __COMMCTL_IRQ_ENABLE:
irq_state = 1;
 
HAL_READ_UINT8(chan->base+CYG_DEVICE_BK0_IER, ier);
ier |= CYG_DEVICE_BK0_IER_RXHDL_IE;
HAL_WRITE_UINT8(chan->base+CYG_DEVICE_BK0_IER, ier);
 
HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1);
HAL_INTERRUPT_UNMASK(chan->isr_vector);
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
 
HAL_READ_UINT8(chan->base+CYG_DEVICE_BK0_IER, ier);
ier &= ~CYG_DEVICE_BK0_IER_RXHDL_IE;
HAL_WRITE_UINT8(chan->base+CYG_DEVICE_BK0_IER, ier);
 
HAL_INTERRUPT_MASK(chan->isr_vector);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
 
va_start(ap, __func);
 
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
 
va_end(ap);
}
default:
break;
}
CYGARC_HAL_RESTORE_GP();
return ret;
}
 
static int
cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
int res = 0;
cyg_uint8 eir, c;
channel_data_t* chan = (channel_data_t*)__ch_data;
CYGARC_HAL_SAVE_GP();
 
HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
 
HAL_READ_UINT8(chan->base+CYG_DEVICE_BK0_EIR, eir);
 
*__ctrlc = 0;
if( (eir & CYG_DEVICE_BK0_EIR_mask) == CYG_DEVICE_BK0_EIR_IRQ_RX ) {
 
HAL_READ_UINT8(chan->base+CYG_DEVICE_BK0_RXD, c);
if( cyg_hal_is_break( &c , 1 ) )
*__ctrlc = 1;
 
res = CYG_ISR_HANDLED;
}
 
CYGARC_HAL_RESTORE_GP();
return res;
}
 
static void
cyg_hal_plf_serial_init(void)
{
hal_virtual_comm_table_t* comm;
int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
 
// Disable interrupts.
HAL_INTERRUPT_MASK(channels[0].isr_vector);
HAL_INTERRUPT_MASK(channels[1].isr_vector);
 
// Init channels
cyg_hal_plf_serial_init_channel((void*)&channels[0]);
cyg_hal_plf_serial_init_channel((void*)&channels[1]);
// Setup procs in the vector table
 
// Set channel 0
CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[0]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
 
// Set channel 1
CYGACC_CALL_IF_SET_CONSOLE_COMM(1);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[1]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
// Restore original console
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
}
 
void
cyg_hal_plf_comms_init(void)
{
static int initialized = 0;
 
if (initialized)
return;
 
initialized = 1;
 
cyg_hal_plf_serial_init();
}
 
//-----------------------------------------------------------------------------
// end of pc87338.c
#endif // CYGONCE_HAL_PC_SER_INL
/platform.S
0,0 → 1,347
##=============================================================================
##
## platform.S
##
## MIPS REF4955-TX4955 platform code
##
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
##=============================================================================
#######DESCRIPTIONBEGIN####
##
## Author(s): nickg
## Contributors:nickg, jskov
## Date: 2000-05-09
## Purpose: MIPS REF4955-TX4955 platform code
## Description: Platform specific code for REF4955-TX4955 board.
##
######DESCRIPTIONEND####
##
##=============================================================================
 
.set noreorder
 
#include <pkgconf/system.h>
#include <pkgconf/hal.h>
 
#ifdef CYGPKG_KERNEL
# include <pkgconf/kernel.h>
#endif
#include <cyg/hal/arch.inc>
#include <cyg/hal/plf_defs.inc>
 
##-----------------------------------------------------------------------------
## ISR springboard.
## This routine decodes the interrupt from the various interrupt controllers
## and vectors to it.
 
# On entry:
# a0 = MIPS status register interrupt number (1,2 or 3)
# a1 = ISR data value (= interrupt controller reg address)
# a2 = saved reg dump ptr
# s0 = saved reg dump ptr
# s1 = vector table offset
# s2 = interrupt number
# a3,v0,v1 etc available for use
 
.text
FUNC_START(hal_isr_springboard_pci)
lbu v0,0(a1)
nor v0,v0,v0
la a1,CYGARC_REG_PCI_MASK
lbu a2,0(a1)
and v0,v0,a2
addi a2,$0,CYGNUM_HAL_INTERRUPT_INTC_PCI_base
b hal_isr_springboard
nop
FUNC_END(hal_isr_springboard_pci)
FUNC_START(hal_isr_springboard_io)
lbu v0,0(a1)
nor v0,v0,v0
la a1,CYGARC_REG_IO_MASK
lbu a2,0(a1)
and v0,v0,a2
addi a2,$0,CYGNUM_HAL_INTERRUPT_INTC_IO_base
b hal_isr_springboard
nop
FUNC_END(hal_isr_springboard_io)
hal_isr_springboard_v320usc:
lw v0,0(a1)
la a1,CYGARC_REG_INT_CFG0
lw v1,0(a1)
lw a2,4(a1) # CFG1
or v1,v1,a2
lw a2,8(a1) # CFG2
or v1,v1,a2
la a1,CYGARC_REG_INT_CFG3
lw a2,0(a1)
or v1,v1,a2
and v0,v0,v1
addi a2,$0,CYGNUM_HAL_INTERRUPT_INTC_V320USC_base
FUNC_START(hal_isr_springboard)
# The following code implements an ls bit index algorithm similar
# to that in hal_lsbit_index() in hal_misc.c.
negu v1,v0 # v1 = -v0
and v1,v1,v0 # v1 &= v0 [isolate ls bit]
sll v0,v1,16 # v0 = v1<<16
subu v1,v0,v1 # v1 = v0 - v1
sll a0,v1,6 # a0 = v1<<6
addu v1,v1,a0 # v1 += a0
sll a1,v1,4 # a1 = v1<<4
addu v1,v1,a1 # v1 += a1
la v0,hal_isr_springboard_table # v0 = table address
srl v1,v1,26 # v1 = v1>>26
addu v1,v1,v0 # v1 = table entry address
lb a0,0(v1) # a0 = intc isr number
add s2,a0,a2 # s2 = eCos isr number
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
hal_isr_springboard_chaining:
# This serves as the __default_interrupt_isr entry-point in
# chaning mode, thus ensuring that all interrupts from
# vectors 0-5 eventually end up on the special CHAINING vector.
# (See the hal_interrupt_handlers table)
ori s1,zero,CYGNUM_HAL_INTERRUPT_CHAINING*4 # s1 = chaining isr ix
#else
sll s1,s2,2 # s1 = isr table index
#endif
 
la v1,hal_interrupt_handlers
add v1,v1,s1 # v1 = isr handler address
lw v1,0(v1) # v1 = isr handler
 
la a1,hal_interrupt_data
add a1,a1,s1 # a1 = address of data ptr
lw a1,0(a1) # a1 = data pointer
 
move a0,s2 # pass interrupt number
 
jr v1 # jump to handler, return is to
# default vsr already in ra
nop
 
FUNC_END(hal_isr_springboard)
 
hal_isr_springboard_table:
.byte -1, 0, 1, 12, 2, 6, 0, 13
.byte 3, 0, 7, 0, 0, 0, 0, 14
.byte 10, 4, 0, 0, 8, 0, 0, 25
.byte 0, 0, 0, 0, 0, 21, 27, 15
.byte 31, 11, 5, 0, 0, 0, 0, 0
.byte 9, 0, 0, 24, 0, 0, 20, 26
.byte 30, 0, 0, 0, 0, 23, 0, 19
.byte 29, 0, 22, 18, 28, 17, 16, 0
 
##-----------------------------------------------------------------------------
## MEMC initialization.
## This also initializes the PCI bus and ISA bus bridge, so at the end of this
## we should have full access to all the memory and devices we need.
## This code is table driven, which is somewhat more compact that coding it all.
## Table entries consist of an address and a value to store in that address.
## A zero address terminates the table. Two special address values modify the
## behaviour:
## DELAY_LOOP loops for the number of iterations in the value field.
## WRITE16 treats the next 2 words as an address and value to be written
## with a 16 bit write cycle.
#if !defined(CYG_HAL_STARTUP_RAM)
#define DELAY_LOOP 1
#define WRITE16 2
 
FUNC_START(hal_memc_setup)
 
lar t0,hal_memc_setup_table
la t1,0xbfc00000
la t2,DELAY_LOOP
la t3,WRITE16
1:
lw a0,0(t0) # next table entry
lw a1,4(t0) # value to write
addiu t0,8 # go to next entry
beq a0,t2,2f # Check for delay
nop
beq a0,t3,3f # Check for 16 bit write
nop
beqz a0,9f # zero terminates loop
nop
sw a1,0(a0) # write it
lw zero,0(t1) # uncached read to flush write buffer
b 1b
nop
2:
lw zero,0(t1) # uncached read to flush write buffer
bnez a1,2b # count down by value in a1
addiu a1,-1 # decrement in delay slot
b 1b # go back to loop
nop
3:
lw a3,0(t0) # get next word
addiu t0,4 # skip it
sh a3,0(a1) # store halfword
lw zero,0(t1) # uncached read to flush write buffer
b 1b
nop
9:
jr ra
nop
 
FUNC_END(hal_memc_setup)
 
##-----------------------------------------------------------------------------
## The initialization table
 
#define USC_LB_BUS_CFG 0xb800007c
#define USC_SDRAM_MA_CMD 0xb8000088
hal_memc_setup_table:
 
.long DELAY_LOOP, 10000 # Wait for HW to settle
 
#ifdef CYGPKG_HAL_MIPS_MSBFIRST
# V320SC : big-endian, max bus watch timer
.long USC_LB_BUS_CFG, 0x04010ff0
#else
.long USC_LB_BUS_CFG, 0x04000ff0
#endif
.long USC_SDRAM_MA_CMD, 0x00a70000
.long USC_SDRAM_MA_CMD, 0x00e70220
 
.long 0, 0
#endif // !CYG_HAL_STARTUP_RAM
##-----------------------------------------------------------------------------
## ISR tables.
.extern hal_default_isr
.data
 
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
.globl hal_interrupt_handlers
hal_interrupt_handlers:
# These first 6 vectors all go through a springboard for further
# interrupt controller vector decoding before ending up on the
# special chaining vector below.
.long hal_isr_springboard_v320usc
.long hal_isr_springboard_pci
.long hal_isr_springboard_chaining
.long hal_isr_springboard_chaining
.long hal_isr_springboard_io
.long hal_isr_springboard_chaining
 
.long hal_default_isr # chaining vector
.globl hal_interrupt_data
hal_interrupt_data:
.long CYGARC_REG_INT_STAT
.long CYGARC_REG_PCI_STAT
.long 0
.long 0
.long CYGARC_REG_IO_STAT
.long 0
 
.long 0 # chaining vector data
 
.globl hal_interrupt_objects
hal_interrupt_objects:
.long 0
.long 0
.long 0
.long 0
.long 0
.long 0
 
.long 0 # chaining vector object
 
.globl cyg_hal_interrupt_level
cyg_hal_interrupt_level:
.rept CYGNUM_HAL_ISR_COUNT
.byte 0
.endr
 
#else // CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
.globl hal_interrupt_handlers
hal_interrupt_handlers:
.long hal_isr_springboard_v320usc
.long hal_isr_springboard_pci
.long hal_default_isr
.long hal_default_isr
.long hal_isr_springboard_io
.long hal_default_isr
 
.rept CYGNUM_HAL_ISR_COUNT-6
.long hal_default_isr
.endr
.globl hal_interrupt_data
hal_interrupt_data:
.long CYGARC_REG_INT_STAT
.long CYGARC_REG_PCI_STAT
.long 0
.long 0
.long CYGARC_REG_IO_STAT
.long 0
 
.rept CYGNUM_HAL_ISR_COUNT-6
.long 0
.endr
 
.globl hal_interrupt_objects
hal_interrupt_objects:
.rept CYGNUM_HAL_ISR_COUNT
.long 0
.endr
 
.globl cyg_hal_interrupt_level
cyg_hal_interrupt_level:
.rept CYGNUM_HAL_ISR_COUNT
.byte 0
.endr
 
#endif // CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
 
##-----------------------------------------------------------------------------
## end of platform.S
/hal_diag.c
0,0 → 1,218
//=============================================================================
//
// hal_diag.c
//
// HAL diagnostic output code
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
// Contributors:nickg, jskov
// Date: 2000-05-10
// Purpose: HAL diagnostic output
// Description: Implementations of HAL diagnostic output support.
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
 
#if !defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
 
#include <cyg/infra/cyg_type.h> // base types
#include <cyg/infra/cyg_trac.h> // tracing macros
#include <cyg/infra/cyg_ass.h> // assertion macros
 
#include <cyg/hal/hal_arch.h>
#include <cyg/hal/hal_diag.h>
 
#include <cyg/hal/hal_intr.h>
#include <cyg/hal/hal_misc.h> // Helper functions
 
#include <cyg/hal/hal_io.h>
 
#include <cyg/hal/hal_if.h> // ROM calling interface
 
#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
#include <cyg/hal/hal_stub.h> // CYG_HAL_GDB_x_CRITICAL_IO_REGION
#endif
 
externC void cyg_hal_plf_serial_init_channel(void* __ch_data);
externC void cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 __ch);
externC cyg_uint8 cyg_hal_plf_serial_getc(void* __ch_data);
 
//-----------------------------------------------------------------------------
// Hit the hardware directly. Either wrap in GDB O-packets, or write
// data raw to device.
 
// Decide when to wrap text output as GDB O-packets
#if (CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL \
== CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL)
 
#if defined(CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs) \
|| defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
 
#define CYG_DIAG_GDB
 
#endif
 
#endif
 
//-----------------------------------------------------------------------------
// There are two serial ports. Hardwire to use one of them.
#define CYG_DEVICE_SERIAL_SCC1 0xb40003f8 // port 1
#define CYG_DEVICE_SERIAL_SCC2 0xb40002f8 // port 2
 
typedef struct {
cyg_uint8* base;
cyg_int32 msec_timeout;
int isr_vector;
} channel_data_t;
 
#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 0)
#define BASE ((cyg_uint8*)CYG_DEVICE_SERIAL_SCC1)
#else
#define BASE ((cyg_uint8*)CYG_DEVICE_SERIAL_SCC2)
#endif
 
static channel_data_t channel = { BASE, 0, 0};
 
#ifdef CYG_DIAG_GDB
 
void
hal_diag_write_char(char c)
{
static char line[100];
static int pos = 0;
 
// No need to send CRs
if( c == '\r' ) return;
 
line[pos++] = c;
 
if( c == '\n' || pos == sizeof(line) )
{
CYG_INTERRUPT_STATE old;
 
// Disable interrupts. This prevents GDB trying to interrupt us
// while we are in the middle of sending a packet. The serial
// receive interrupt will be seen when we re-enable interrupts
// later.
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
#else
HAL_DISABLE_INTERRUPTS(old);
#endif
while(1)
{
static char hex[] = "0123456789ABCDEF";
cyg_uint8 csum = 0;
int i;
char c1;
cyg_hal_plf_serial_putc(&channel, '$');
cyg_hal_plf_serial_putc(&channel, 'O');
csum += 'O';
for( i = 0; i < pos; i++ )
{
char ch = line[i];
char h = hex[(ch>>4)&0xF];
char l = hex[ch&0xF];
cyg_hal_plf_serial_putc(&channel, h);
cyg_hal_plf_serial_putc(&channel, l);
csum += h;
csum += l;
}
cyg_hal_plf_serial_putc(&channel, '#');
cyg_hal_plf_serial_putc(&channel, hex[(csum>>4)&0xF]);
cyg_hal_plf_serial_putc(&channel, hex[csum&0xF]);
 
c1 = cyg_hal_plf_serial_getc(&channel);
 
if( c1 == '+' ) break;
}
pos = 0;
// And re-enable interrupts
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
#else
HAL_RESTORE_INTERRUPTS(old);
#endif
}
}
 
void
hal_diag_read_char(char *c)
{
*c = cyg_hal_plf_serial_getc(&channel);
}
 
#else // CYG_DIAG_GDB
 
// Hit the hardware directly, no GDB translation
 
void
hal_diag_read_char(char *c)
{
*c = cyg_hal_plf_serial_getc(&channel);
}
 
void
hal_diag_write_char(char c)
{
cyg_hal_plf_serial_putc(&channel, c);
}
 
 
#endif
 
// Reagardless whether encoding or not we alway initialize the device.
 
void
hal_diag_init(void)
{
// Init serial device
cyg_hal_plf_serial_init_channel((void*)&channel);
}
 
#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
 
//-----------------------------------------------------------------------------
// End of hal_diag.c
/plf_mk_defs.c
0,0 → 1,106
//==========================================================================
//
// plf_mk_defs.c
//
// HAL (platform) "make defs" program
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): gthomas
// Contributors: gthomas, jskov
// Date: 2000-05-11
// Purpose: Platform dependent definition generator
// Description: This file contains code that can be compiled by the target
// compiler and used to generate machine specific definitions
// suitable for use in assembly code.
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/hal/hal_arch.h> // HAL header
#include <cyg/hal/hal_intr.h> // HAL header
#include <cyg/hal/hal_cache.h> // HAL header
#ifdef CYGPKG_KERNEL
# include <pkgconf/kernel.h>
# include <cyg/kernel/instrmnt.h>
#endif
 
/*
* This program is used to generate definitions needed by
* assembly language modules.
*
* This technique was first used in the OSF Mach kernel code:
* generate asm statements containing #defines,
* compile this file to assembler, and then extract the
* #defines from the assembly-language output.
*/
 
#define DEFINE(sym, val) \
asm volatile("\n\t.equ\t" #sym ",%0" : : "i" (val))
 
int
main(void)
{
// Some other exception related definitions
DEFINE(CYGNUM_HAL_ISR_COUNT, CYGNUM_HAL_ISR_COUNT);
DEFINE(CYGNUM_HAL_VSR_COUNT, CYGNUM_HAL_VSR_COUNT);
DEFINE(CYGNUM_HAL_VECTOR_INTERRUPT, CYGNUM_HAL_VECTOR_INTERRUPT);
DEFINE(CYGNUM_HAL_VECTOR_BREAKPOINT, CYGNUM_HAL_VECTOR_BREAKPOINT);
 
// Interrupt details
DEFINE(CYGNUM_HAL_INTERRUPT_INTC_V320USC_base, CYGNUM_HAL_INTERRUPT_INTC_V320USC_base);
DEFINE(CYGNUM_HAL_INTERRUPT_INTC_PCI_base, CYGNUM_HAL_INTERRUPT_INTC_PCI_base);
DEFINE(CYGNUM_HAL_INTERRUPT_INTC_IO_base, CYGNUM_HAL_INTERRUPT_INTC_IO_base);
DEFINE(CYGARC_REG_INT_STAT, CYGARC_REG_INT_STAT);
DEFINE(CYGARC_REG_PCI_STAT, CYGARC_REG_PCI_STAT);
DEFINE(CYGARC_REG_IO_STAT, CYGARC_REG_IO_STAT);
DEFINE(CYGARC_REG_PCI_MASK, CYGARC_REG_PCI_MASK);
DEFINE(CYGARC_REG_IO_MASK, CYGARC_REG_IO_MASK);
DEFINE(CYGARC_REG_INT_CFG0, CYGARC_REG_INT_CFG0);
DEFINE(CYGARC_REG_INT_CFG3, CYGARC_REG_INT_CFG3);
#if defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN)
DEFINE(CYGNUM_HAL_INTERRUPT_CHAINING, CYGNUM_HAL_INTERRUPT_CHAINING);
#endif
 
return 0;
}
 
//--------------------------------------------------------------------------
// EOF plf_mk_defs.c
/plf_misc.c
0,0 → 1,123
//==========================================================================
//
// plf_misc.c
//
// HAL platform miscellaneous functions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors: nickg, jlarmour, jskov
// Date: 2000-05-15
// Purpose: HAL miscellaneous functions
// Description: This file contains miscellaneous functions provided by the
// HAL.
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h> // Base types
#include <cyg/infra/cyg_trac.h> // tracing macros
#include <cyg/infra/cyg_ass.h> // assertion macros
 
#include <cyg/hal/hal_arch.h> // architectural definitions
 
#include <cyg/hal/hal_intr.h> // Interrupt handling
 
#include <cyg/hal/hal_cache.h> // Cache handling
#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED
 
#include <cyg/hal/hal_if.h> // Calling interface definitions
#include <cyg/hal/hal_misc.h> // Helper functions
 
//--------------------------------------------------------------------------
 
#define CYGARC_REG_SUPERIO_IREG 0xb4000398
#define CYGARC_REG_SUPERIO_DREG 0xb4000399
 
#define CYGARC_REG_SUPERIO_FER 0x00 // function enable
#define CYGARC_REG_SUPERIO_FAR 0x01 // function address
#define CYGARC_REG_SUPERIO_PTR 0x02 // power and test
#define CYGARC_REG_SUPERIO_CLK 0x51 // clock controller
 
 
#define CYGARC_REG_SUPERIO_FER_PAR 0x01
#define CYGARC_REG_SUPERIO_FER_SCC1 0x02
#define CYGARC_REG_SUPERIO_FER_SCC2 0x04
 
#define CYGARC_REG_SUPERIO_CLK_14M 0x00 // 14MHz source
#define CYGARC_REG_SUPERIO_CLK_CME 0x04 // clock multiplier enabled
 
#define CYGARC_REG_SUPERIO_PTR_PPEXT 0x80 // extended
 
 
 
 
static void write_super_io(cyg_uint8 offset, cyg_uint8 data)
{
HAL_WRITE_UINT8(CYGARC_REG_SUPERIO_IREG, offset);
HAL_WRITE_UINT8(CYGARC_REG_SUPERIO_DREG, data);
HAL_WRITE_UINT8(CYGARC_REG_SUPERIO_DREG, data);
}
 
void hal_platform_init(void)
{
hal_if_init();
 
// Configure the SuperIO chip
write_super_io(CYGARC_REG_SUPERIO_FER,
CYGARC_REG_SUPERIO_FER_SCC1|CYGARC_REG_SUPERIO_FER_SCC2);
write_super_io(CYGARC_REG_SUPERIO_FAR, 0x10);
write_super_io(CYGARC_REG_SUPERIO_CLK,
CYGARC_REG_SUPERIO_CLK_14M|CYGARC_REG_SUPERIO_CLK_CME);
 
// Set up VSC320 interrupt controller. INT1 must merge INT2 and
// INT3 according to the platform specification.
HAL_WRITE_UINT32(CYGARC_REG_INT_CFG1,
CYGARC_REG_INT_CFG_INT2|CYGARC_REG_INT_CFG_INT3);
 
// Unmask vectors which are entry points for interrupt controllers
HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_V320USC_INT0);
HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_V320USC_INT1);
HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_IO);
}
 
//--------------------------------------------------------------------------
// End of plf_misc.c

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