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Rev 27 → Rev 174

/cdl/hal_mips_tx49_ref4955.cdl
0,0 → 1,309
# ====================================================================
#
# hal_mips_tx49_ref4955.cdl
#
# TX49/REF4955 board HAL package configuration data
#
# ====================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
# ====================================================================
######DESCRIPTIONBEGIN####
#
# Author(s): jskov
# Original data: bartv
# Contributors:
# Date: 2000-05-15
#
#####DESCRIPTIONEND####
#
# ====================================================================
 
cdl_package CYGPKG_HAL_MIPS_TX49_REF4955 {
display "REF4955 evaluation board"
parent CYGPKG_HAL_MIPS
requires CYGPKG_HAL_MIPS_TX49
define_header hal_mips_tx49_ref4955.h
include_dir cyg/hal
description "
The REF4955 HAL package should be used when targetting the
actual hardware."
 
compile hal_diag.c platform.S plf_misc.c plf_stub.c pc87338.c
 
implements CYGINT_HAL_DEBUG_GDB_STUBS
implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
 
define_proc {
puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_mips_tx49.h>"
puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_mips_tx49_ref4955.h>"
 
puts $::cdl_header "#define CYGHWR_HAL_MIPS_WARMSTART_COLDSTART"
 
puts $::cdl_header "#define CYGPRI_KERNEL_TESTS_DHRYSTONE_PASSES 1000000"
}
 
cdl_component CYG_HAL_STARTUP {
display "Startup type"
flavor data
legal_values {"RAM" "ROM"}
default_value {"RAM"}
no_define
define -file system.h CYG_HAL_STARTUP
description "
When targetting the REF4955 board it is possible to build
the system for either RAM bootstrap or ROM bootstrap. RAM
bootstrap generally requires that the board
is equipped with ROMs containing a suitable ROM monitor or
equivalent software that allows GDB to download the eCos
application on to the board. The ROM bootstrap typically
requires that the eCos application be blown into EPROMs or
equivalent technology."
}
 
cdl_option CYGHWR_HAL_MIPS_TX49_REF4955_ENDIAN {
display "Board endian mode"
flavor data
legal_values {"big" "little"}
default_value {"big"}
no_define
description "
The TX4955 Reference Platform can be used in either big or
little endian mode. This option select which. The board
will also need to be reconfigured if this option changes."
}
cdl_option CYGHWR_HAL_MIPS_TX49_REF4955_ENDIAN_SET {
display "Communicate endian setting to variant HAL"
active_if {CYGHWR_HAL_MIPS_TX49_REF4955_ENDIAN == "big"}
calculated 1
implements CYGINT_HAL_MIPS_MSBFIRST
}
 
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
display "Number of communication channels on the board"
flavor data
calculated 2
}
 
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
display "Debug serial port"
active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
flavor data
legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
default_value 0
description "
The REF4955 board has two separate serial ports. This option
chooses which of these ports will be used to connect to a host
running GDB."
}
 
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
display "Diagnostic serial port"
active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
flavor data
legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
default_value 0
description "
The REF4955 board has two separate serial ports. This option
chooses which of these ports will be used for diagnostic output."
}
 
# The "-o file" is a workaround for CR100958 - without it the
# output file would end up in the source directory under CygWin.
# n.b. grep does not behave itself under win32
make -priority 1 {
<PREFIX>/include/cyg/hal/plf_defs.inc : <PACKAGE>/src/plf_mk_defs.c
$(CC) $(CFLAGS) $(INCLUDE_PATH) -Wp,-MD,plf_defs.tmp -o plf_mk_defs.tmp -S $<
fgrep .equ plf_mk_defs.tmp | sed s/#// > $@
@echo $@ ": \\" > $(notdir $@).deps
@tail +2 plf_defs.tmp >> $(notdir $@).deps
@echo >> $(notdir $@).deps
@rm plf_defs.tmp plf_mk_defs.tmp
}
 
# Real-time clock/counter specifics
cdl_component CYGNUM_HAL_RTC_CONSTANTS {
display "Real-time clock constants."
flavor none
cdl_option CYGNUM_HAL_RTC_NUMERATOR {
display "Real-time clock numerator"
flavor data
calculated 1000000000
}
cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
display "Real-time clock denominator"
flavor data
calculated 100
}
cdl_option CYGNUM_HAL_RTC_PERIOD {
display "Real-time clock period"
flavor data
calculated { 660000 }
description "
The count and compare registers of the TX49 are used
to drive the eCos kernel RTC. The count register
increments at 66MHz on the REF4955."
}
}
 
cdl_component CYGBLD_GLOBAL_OPTIONS {
display "Global build options"
flavor none
parent CYGPKG_NONE
description "
Global build options including control over
compiler flags, linker flags and choice of toolchain."
 
 
cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
display "Global command prefix"
flavor data
no_define
default_value { "mips-tx49-elf" }
description "
This option specifies the command prefix used when
invoking the build tools."
}
 
cdl_option CYGBLD_GLOBAL_CFLAGS {
display "Global compiler flags"
flavor data
no_define
default_value { CYGPKG_HAL_MIPS_MSBFIRST ? "-mips2 -EB -mabi=eabi -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" : "-mips2 -EL -mabi=eabi -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
description "
This option controls the global compiler flags which
are used to compile all packages by
default. Individual packages may define
options which override these global flags."
}
 
cdl_option CYGBLD_GLOBAL_LDFLAGS {
display "Global linker flags"
flavor data
no_define
default_value { CYGPKG_HAL_MIPS_MSBFIRST ? "-g -mips2 -EB -mabi=eabi -nostdlib -Wl,--gc-sections -Wl,-static" : "-g -mips2 -EL -mabi=eabi -nostdlib -Wl,--gc-sections -Wl,-static" }
description "
This option controls the global linker flags. Individual
packages may define options which override these global flags."
}
 
cdl_option CYGBLD_BUILD_GDB_STUBS {
display "Build GDB stub ROM image"
default_value 0
requires { CYG_HAL_STARTUP == "ROM" }
requires CYGSEM_HAL_ROM_MONITOR
requires CYGBLD_BUILD_COMMON_GDB_STUBS
requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
requires ! CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
no_define
description "
This option enables the building of the GDB stubs for the
board. The common HAL controls takes care of most of the
build process, but the final conversion from ELF image to
SREC data is handled by the platform CDL, allowing
relocation of the data if necessary."
 
make -priority 320 {
<PREFIX>/bin/gdb_module.srec : <PREFIX>/bin/gdb_module.img
$(OBJCOPY) --strip-unneeded -O srec $< pre-swap.srec
$(OBJCOPY) --strip-unneeded --change-addresses 0x40400000 $< be-swap.img
$(OBJCOPY) -O binary be-swap.img be-swap.bin
$(REPOSITORY)/$(PACKAGE)/misc/swap4.tcl be-swap.bin be.bin
$(OBJCOPY) --change-address 0xbfc00000 -I binary -O srec be.bin $@
}
}
}
 
cdl_component CYGHWR_MEMORY_LAYOUT {
display "Memory layout"
flavor data
no_define
calculated { CYG_HAL_STARTUP == "RAM" ? "mips_tx49_ref4955_ram" : \
"mips_tx49_ref4955_rom" }
 
cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
display "Memory layout linker script fragment"
flavor data
no_define
define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_mips_tx49_ref4955_ram.ldi>" : \
"<pkgconf/mlt_mips_tx49_ref4955_rom.ldi>" }
}
 
cdl_option CYGHWR_MEMORY_LAYOUT_H {
display "Memory layout header file"
flavor data
no_define
define -file system.h CYGHWR_MEMORY_LAYOUT_H
calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_mips_tx49_ref4955_ram.h>" : \
"<pkgconf/mlt_mips_tx49_ref4955_rom.h>" }
}
}
 
cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
display "Work with a ROM monitor"
flavor booldata
legal_values { "GDB_stubs" }
default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
parent CYGPKG_HAL_ROM_MONITOR
requires { CYG_HAL_STARTUP == "RAM" }
description "
Support can be enabled for GDB stubs.
This support changes various eCos semantics such as the encoding
of diagnostic output, or the overriding of hardware interrupt
vectors.
\"GDB_stubs\" provides support when GDB stubs are
included in the ROM monitor or boot ROM, allowing debugging
via GDB."
}
 
cdl_option CYGSEM_HAL_ROM_MONITOR {
display "Behave as a ROM monitor"
flavor bool
default_value 0
parent CYGPKG_HAL_ROM_MONITOR
requires { CYG_HAL_STARTUP == "ROM" }
description "
Enable this option if this program is to be used as a ROM monitor,
i.e. applications will be loaded into RAM on the board, and this
ROM monitor may process exceptions or interrupts generated from the
application. This enables features such as utilizing a separate
interrupt stack when exceptions are generated."
}
}
/include/plf_intr.h
0,0 → 1,320
#ifndef CYGONCE_HAL_PLF_INTR_H
#define CYGONCE_HAL_PLF_INTR_H
 
//==========================================================================
//
// plf_intr.h
//
// REF4955 Interrupt and clock support
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
// Contributors: jskov, nickg
// Date: 2000-05-09
// Purpose: Define Interrupt support
// Description: The macros defined here provide the HAL APIs for handling
// interrupts and the clock for the REF4955 board.
//
// Usage:
// #include <cyg/hal/plf_intr.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h>
 
//--------------------------------------------------------------------------
// Interrupt vectors.
 
#ifndef CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
 
 
// The first 6 correspond to the interrupt lines in the status/cause regs
#define CYGNUM_HAL_INTERRUPT_V320USC_INT0 0
#define CYGNUM_HAL_INTERRUPT_V320USC_INT1 1
#define CYGNUM_HAL_INTERRUPT_EXT 2
#define CYGNUM_HAL_INTERRUPT_LAN 3
#define CYGNUM_HAL_INTERRUPT_IO 4
#define CYGNUM_HAL_INTERRUPT_COMPARE 5
 
 
#if defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN)
 
// This overlaps with LB_MBI below but it doesn't matter. It's only used
// by the HAL to access the special chaining entry in the ISR tables.
// All other attempted access to the ISR table will be redirected to this
// entry (curtsey of HAL_TRANSLATE_VECTOR). The other vector definitions
// are still valid, but only for enable/disable/config etc. (i.e., in
// chaining mode they have associated entries in the ISR tables).
#define CYGNUM_HAL_INTERRUPT_CHAINING 6
 
#define HAL_TRANSLATE_VECTOR(_vector_,_index_) \
(_index_) = CYGNUM_HAL_INTERRUPT_CHAINING
 
#endif
 
 
// The next 32 correspond to the interrupt lines in the V320USC's interrupt
// controller. These are decoded from the controller when an interrupt
// enters via CYGNUM_HAL_INTERRUPT_V320USC_INT0.
#define CYGNUM_HAL_INTERRUPT_INTC_V320USC_base 6
#define CYGNUM_HAL_INTERRUPT_LB_MBI 6
#define CYGNUM_HAL_INTERRUPT_PCI_MBI 7
#define CYGNUM_HAL_INTERRUPT_RESERVED_2 8
#define CYGNUM_HAL_INTERRUPT_I2O_OP_NE 9
#define CYGNUM_HAL_INTERRUPT_I2O_IF_NF 10
#define CYGNUM_HAL_INTERRUPT_I2O_IP_NE 11
#define CYGNUM_HAL_INTERRUPT_I2O_OP_NF 12
#define CYGNUM_HAL_INTERRUPT_I2O_OF_NE 13
#define CYGNUM_HAL_INTERRUPT_RESERVED_8 14
#define CYGNUM_HAL_INTERRUPT_RESERVED_9 15
#define CYGNUM_HAL_INTERRUPT_RESERVED_10 16
#define CYGNUM_HAL_INTERRUPT_RESERVED_11 17
#define CYGNUM_HAL_INTERRUPT_TIMER0 18
#define CYGNUM_HAL_INTERRUPT_TIMER1 19
#define CYGNUM_HAL_INTERRUPT_RESERVED_14 20
#define CYGNUM_HAL_INTERRUPT_ENUM 21
#define CYGNUM_HAL_INTERRUPT_DMA0 22
#define CYGNUM_HAL_INTERRUPT_DMA1 23
#define CYGNUM_HAL_INTERRUPT_RESERVED_18 24
#define CYGNUM_HAL_INTERRUPT_RESERVED_19 25
#define CYGNUM_HAL_INTERRUPT_PWR_STATE 26
#define CYGNUM_HAL_INTERRUPT_HBI 27
#define CYGNUM_HAL_INTERRUPT_WDI 28
#define CYGNUM_HAL_INTERRUPT_BWI 29
#define CYGNUM_HAL_INTERRUPT_PSLAVE_PI 30
#define CYGNUM_HAL_INTERRUPT_PMASTER_PI 31
#define CYGNUM_HAL_INTERRUPT_PCI_T_ABORT 32
#define CYGNUM_HAL_INTERRUPT_PCI_M_ABORT 33
#define CYGNUM_HAL_INTERRUPT_DRAM_PI 34
#define CYGNUM_HAL_INTERRUPT_RESERVED_29 35
#define CYGNUM_HAL_INTERRUPT_DI0 36
#define CYGNUM_HAL_INTERRUPT_DI1 37
 
// The next 6 correspond to the interrupt lines specific to the PCI
// connector (decoded from CYGNUM_HAL_INTERRUPT_V320USC_INT1)
#define CYGNUM_HAL_INTERRUPT_INTC_PCI_base 38
#define CYGNUM_HAL_INTERRUPT_SERR 38
#define CYGNUM_HAL_INTERRUPT_PERR 39
#define CYGNUM_HAL_INTERRUPT_INTD 40
#define CYGNUM_HAL_INTERRUPT_INTC 41
#define CYGNUM_HAL_INTERRUPT_INTB 42
#define CYGNUM_HAL_INTERRUPT_INTA 43
 
// The next 5 correspond to the interrupt lines specific to the REF4955
// board (decoded from CYGNUM_HAL_INTERRUPT_IO)
#define CYGNUM_HAL_INTERRUPT_INTC_IO_base 44
#define CYGNUM_HAL_INTERRUPT_SOFTWARE 44
#define CYGNUM_HAL_INTERRUPT_INT_SWITCH 45
#define CYGNUM_HAL_INTERRUPT_PARALLEL 46
#define CYGNUM_HAL_INTERRUPT_DEBUG_UART 47
#define CYGNUM_HAL_INTERRUPT_USER_UART 48
 
 
// Min/Max ISR numbers and how many there are
#define CYGNUM_HAL_ISR_MIN CYGNUM_HAL_INTERRUPT_V320USC_INT0
#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_USER_UART
#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX - CYGNUM_HAL_ISR_MIN + 1)
 
// The vector used by the Real time clock
#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_COMPARE
 
#define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
 
#endif
 
//--------------------------------------------------------------------------
// Interrupt controler information
 
// V320USC
#define CYGARC_REG_INT_STAT 0xb80000ec
 
#define CYGARC_REG_INT_CFG0 0xb80000e0
#define CYGARC_REG_INT_CFG1 0xb80000e4
#define CYGARC_REG_INT_CFG2 0xb80000e8
#define CYGARC_REG_INT_CFG3 0xb8000158
 
#define CYGARC_REG_INT_CFG_INT0 0x00000100
#define CYGARC_REG_INT_CFG_INT1 0x00000200
#define CYGARC_REG_INT_CFG_INT2 0x00000400
#define CYGARC_REG_INT_CFG_INT3 0x00000800
 
 
// FPGA
#define CYGARC_REG_PCI_STAT 0xb5300000
#define CYGARC_REG_PCI_MASK 0xb5300030
 
#define CYGARC_REG_IO_STAT 0xb5300010
#define CYGARC_REG_IO_MASK 0xb5300040
 
 
#define HAL_INTERRUPT_MASK( _vector_ ) \
CYG_MACRO_START \
if( (_vector_) <= CYGNUM_HAL_INTERRUPT_COMPARE ) \
{ \
asm volatile ( \
"mfc0 $3,$12\n" \
"la $2,0x00000400\n" \
"sllv $2,$2,%0\n" \
"nor $2,$2,$0\n" \
"and $3,$3,$2\n" \
"mtc0 $3,$12\n" \
"nop; nop; nop\n" \
: \
: "r"(_vector_) \
: "$2", "$3" \
); \
} \
else if ((_vector_) >= CYGNUM_HAL_INTERRUPT_INTC_IO_base) \
{ \
cyg_uint8 _mask_; \
cyg_uint32 _shift_ = (_vector_)-CYGNUM_HAL_INTERRUPT_INTC_IO_base; \
HAL_READ_UINT8(CYGARC_REG_IO_MASK, _mask_ ); \
_mask_ &= ~(1<<_shift_); \
HAL_WRITE_UINT8(CYGARC_REG_IO_MASK, _mask_ ); \
} \
else if (_vector_ >= CYGNUM_HAL_INTERRUPT_INTC_PCI_base) \
{ \
cyg_uint8 _mask_; \
cyg_uint32 _shift_ = (_vector_)-CYGNUM_HAL_INTERRUPT_INTC_PCI_base; \
HAL_READ_UINT8(CYGARC_REG_PCI_MASK, _mask_ ); \
_mask_ &= ~(1<<_shift_); \
HAL_WRITE_UINT8(CYGARC_REG_PCI_MASK, _mask_ ); \
} else { /* V320USC */ \
cyg_uint32 _mask_; \
cyg_uint32 _shift_ = \
(_vector_)-CYGNUM_HAL_INTERRUPT_INTC_V320USC_base; \
HAL_READ_UINT32(CYGARC_REG_INT_CFG0, _mask_ ); \
_mask_ &= !(1<<_shift_); \
HAL_WRITE_UINT32(CYGARC_REG_INT_CFG0, _mask_ ); \
} \
CYG_MACRO_END
 
#define HAL_INTERRUPT_UNMASK( _vector_ ) \
CYG_MACRO_START \
if( (_vector_) <= CYGNUM_HAL_INTERRUPT_COMPARE ) \
{ \
asm volatile ( \
"mfc0 $3,$12\n" \
"la $2,0x00000400\n" \
"sllv $2,$2,%0\n" \
"or $3,$3,$2\n" \
"mtc0 $3,$12\n" \
"nop; nop; nop\n" \
: \
: "r"(_vector_) \
: "$2", "$3" \
); \
} \
else if ((_vector_) >= CYGNUM_HAL_INTERRUPT_INTC_IO_base) \
{ \
cyg_uint8 _mask_; \
cyg_uint32 _shift_ = (_vector_)-CYGNUM_HAL_INTERRUPT_INTC_IO_base; \
HAL_READ_UINT8(CYGARC_REG_IO_MASK, _mask_ ); \
_mask_ |= (1<<_shift_); \
HAL_WRITE_UINT8(CYGARC_REG_IO_MASK, _mask_ ); \
} \
else if (_vector_ >= CYGNUM_HAL_INTERRUPT_INTC_PCI_base) \
{ \
cyg_uint8 _mask_; \
cyg_uint32 _shift_ = (_vector_)-CYGNUM_HAL_INTERRUPT_INTC_PCI_base; \
HAL_READ_UINT8(CYGARC_REG_PCI_MASK, _mask_ ); \
_mask_ |= (1<<_shift_); \
HAL_WRITE_UINT8(CYGARC_REG_PCI_MASK, _mask_ ); \
} else { /* V320USC */ \
cyg_uint32 _mask_; \
cyg_uint32 _shift_ = \
(_vector_)-CYGNUM_HAL_INTERRUPT_INTC_V320USC_base; \
HAL_READ_UINT32(CYGARC_REG_INT_CFG0, _mask_ ); \
_mask_ |= (1<<_shift_); \
HAL_WRITE_UINT32(CYGARC_REG_INT_CFG0, _mask_ ); \
} \
CYG_MACRO_END
 
#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
CYG_MACRO_START \
cyg_uint32 _srvector_ = _vector_; \
if ((_vector_) >= CYGNUM_HAL_INTERRUPT_INTC_IO_base) { \
_srvector_ = CYGNUM_HAL_INTERRUPT_IO; \
} else if (_vector_ >= CYGNUM_HAL_INTERRUPT_INTC_PCI_base) { \
_srvector_ = CYGNUM_HAL_INTERRUPT_V320USC_INT1; \
} else if (_vector_ >= CYGNUM_HAL_INTERRUPT_INTC_V320USC_base) { \
cyg_uint32 _mask_; \
cyg_uint32 _shift_ = \
(_vector_)-CYGNUM_HAL_INTERRUPT_INTC_V320USC_base; \
_mask_ = (1<<_shift_); \
HAL_WRITE_UINT32(CYGARC_REG_INT_STAT, _mask_ ); \
_srvector_ = CYGNUM_HAL_INTERRUPT_V320USC_INT0; \
} \
asm volatile ( \
"mfc0 $3,$13\n" \
"la $2,0x00000400\n" \
"sllv $2,$2,%0\n" \
"nor $2,$2,$0\n" \
"and $3,$3,$2\n" \
"mtc0 $3,$13\n" \
"nop; nop; nop\n" \
: \
: "r"(_srvector_) \
: "$2", "$3" \
); \
CYG_MACRO_END
 
#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ )
 
#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ )
 
#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
 
 
//----------------------------------------------------------------------------
// Reset.
#define CYGARC_REG_BOARD_RESET 0xb5400000
 
#define HAL_PLATFORM_RESET() HAL_WRITE_UINT8(CYGARC_REG_BOARD_RESET,0)
 
#define HAL_PLATFORM_RESET_ENTRY 0xbfc00000
 
//--------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_PLF_INTR_H
// End of plf_intr.h
/include/plf_stub.h
0,0 → 1,85
#ifndef CYGONCE_HAL_PLF_STUB_H
#define CYGONCE_HAL_PLF_STUB_H
 
//=============================================================================
//
// plf_stub.h
//
// Platform header for GDB stub support.
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
// Contributors:jskov
// Date: 2000-05-15
// Purpose: Platform HAL stub support for MIPS/REF4955 boards.
// Usage: #include <cyg/hal/plf_stub.h>
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
 
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 
#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM
 
#include <cyg/hal/mips-stub.h> // architecture stub support
 
//----------------------------------------------------------------------------
// Define some platform specific communication details. This is mostly
// handled by hal_if now, but we need to make sure the comms tables are
// properly initialized.
 
externC void cyg_hal_plf_comms_init(void);
 
#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init()
 
#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud))
#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0
#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT
 
//----------------------------------------------------------------------------
// Stub initializer.
extern void hal_plf_stub_init( void );
#define HAL_STUB_PLATFORM_INIT() hal_plf_stub_init();
 
#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
//-----------------------------------------------------------------------------
#endif // CYGONCE_HAL_PLF_STUB_H
// End of plf_stub.h
/include/pkgconf/mlt_mips_tx49_ref4955_rom.h
0,0 → 1,35
// eCos memory layout - Fri Oct 20 06:22:57 2000
 
// This is a generated file - do not edit
 
#ifndef __ASSEMBLER__
#include <cyg/infra/cyg_type.h>
#include <stddef.h>
 
#endif
#define CYGMEM_REGION_ram (0x80000000)
#define CYGMEM_REGION_ram_SIZE (0x4000000)
#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
#define CYGMEM_REGION_rom (0xbfc00000)
#define CYGMEM_REGION_rom_SIZE (0x1000000)
#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__reserved_vectors) [];
#endif
#define CYGMEM_SECTION_reserved_vectors (CYG_LABEL_NAME (__reserved_vectors))
#define CYGMEM_SECTION_reserved_vectors_SIZE (0x200)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__reserved_vsr_table) [];
#endif
#define CYGMEM_SECTION_reserved_vsr_table (CYG_LABEL_NAME (__reserved_vsr_table))
#define CYGMEM_SECTION_reserved_vsr_table_SIZE (0x100)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__reserved_virtual_table) [];
#endif
#define CYGMEM_SECTION_reserved_virtual_table (CYG_LABEL_NAME (__reserved_virtual_table))
#define CYGMEM_SECTION_reserved_virtual_table_SIZE (0x100)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__heap1) [];
#endif
#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
#define CYGMEM_SECTION_heap1_SIZE (0x84000000 - (size_t) CYG_LABEL_NAME (__heap1))
/include/pkgconf/mlt_mips_tx49_ref4955_rom.ldi
0,0 → 1,43
// eCos memory layout - Fri Oct 20 06:22:57 2000
 
// This is a generated file - do not edit
 
#include <cyg/infra/cyg_type.inc>
 
MEMORY
{
ram : ORIGIN = 0x80000000, LENGTH = 0x4000000
rom : ORIGIN = 0xbfc00000, LENGTH = 0x1000000
}
 
SECTIONS
{
SECTIONS_BEGIN
SECTION_rom_vectors (rom, 0xbfc00000, LMA_EQ_VMA)
SECTION_ROMISC (rom, ALIGN (0x8), LMA_EQ_VMA)
SECTION_RELOCS (rom, ALIGN (0x8), LMA_EQ_VMA)
SECTION_init (rom, ALIGN (0x8), LMA_EQ_VMA)
SECTION_text (rom, ALIGN (0x8), LMA_EQ_VMA)
SECTION_fini (rom, ALIGN (0x8), LMA_EQ_VMA)
SECTION_rodata (rom, ALIGN (0x8), LMA_EQ_VMA)
SECTION_rodata1 (rom, ALIGN (0x8), LMA_EQ_VMA)
CYG_LABEL_DEFN(__reserved_vectors) = 0x80000000; . = CYG_LABEL_DEFN(__reserved_vectors) + 0x200;
CYG_LABEL_DEFN(__reserved_vsr_table) = ALIGN (0x10); . = CYG_LABEL_DEFN(__reserved_vsr_table) + 0x100;
CYG_LABEL_DEFN(__reserved_virtual_table) = ALIGN (0x10); . = CYG_LABEL_DEFN(__reserved_virtual_table) + 0x100;
SECTION_data (ram, ALIGN (0x10), FOLLOWING (.rodata1))
SECTION_data1 (ram, ALIGN (0x8), FOLLOWING (.data))
SECTION_eh_frame (ram, ALIGN (0x8), FOLLOWING (.data1))
SECTION_gcc_except_table (ram, ALIGN (0x8), FOLLOWING (.eh_frame))
SECTION_ctors (ram, ALIGN (0x8), FOLLOWING (.gcc_except_table))
SECTION_dtors (ram, ALIGN (0x8), FOLLOWING (.ctors))
SECTION_devtab (ram, ALIGN (0x8), FOLLOWING (.dtors))
SECTION_got (ram, ALIGN (0x8), FOLLOWING (.devtab))
SECTION_dynamic (ram, ALIGN (0x8), FOLLOWING (.got))
SECTION_sdata (ram, ALIGN (0x8), FOLLOWING (.dynamic))
SECTION_lit8 (ram, ALIGN (0x8), FOLLOWING (.sdata))
SECTION_lit4 (ram, ALIGN (0x8), FOLLOWING (.lit8))
SECTION_sbss (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
SECTIONS_END
}
/include/pkgconf/mlt_mips_tx49_ref4955_ram.h
0,0 → 1,37
// eCos memory layout - Fri Oct 20 06:22:02 2000
 
// This is a generated file - do not edit
 
#ifndef __ASSEMBLER__
#include <cyg/infra/cyg_type.h>
#include <stddef.h>
 
#endif
#define CYGMEM_REGION_ram (0x80000000)
#define CYGMEM_REGION_ram_SIZE (0x4000000)
#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__reserved_vectors) [];
#endif
#define CYGMEM_SECTION_reserved_vectors (CYG_LABEL_NAME (__reserved_vectors))
#define CYGMEM_SECTION_reserved_vectors_SIZE (0x200)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__reserved_vsr_table) [];
#endif
#define CYGMEM_SECTION_reserved_vsr_table (CYG_LABEL_NAME (__reserved_vsr_table))
#define CYGMEM_SECTION_reserved_vsr_table_SIZE (0x100)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__reserved_virtual_table) [];
#endif
#define CYGMEM_SECTION_reserved_virtual_table (CYG_LABEL_NAME (__reserved_virtual_table))
#define CYGMEM_SECTION_reserved_virtual_table_SIZE (0x100)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__reserved_for_rom) [];
#endif
#define CYGMEM_SECTION_reserved_for_rom (CYG_LABEL_NAME (__reserved_for_rom))
#define CYGMEM_SECTION_reserved_for_rom_SIZE (0x7c00)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__heap1) [];
#endif
#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
#define CYGMEM_SECTION_heap1_SIZE (0x84000000 - (size_t) CYG_LABEL_NAME (__heap1))
/include/pkgconf/mlt_mips_tx49_ref4955_ram.ldi
0,0 → 1,43
// eCos memory layout - Fri Oct 20 06:22:02 2000
 
// This is a generated file - do not edit
 
#include <cyg/infra/cyg_type.inc>
 
MEMORY
{
ram : ORIGIN = 0x80000000, LENGTH = 0x4000000
}
 
SECTIONS
{
SECTIONS_BEGIN
CYG_LABEL_DEFN(__reserved_vectors) = 0x80000000; . = CYG_LABEL_DEFN(__reserved_vectors) + 0x200;
CYG_LABEL_DEFN(__reserved_vsr_table) = ALIGN (0x10); . = CYG_LABEL_DEFN(__reserved_vsr_table) + 0x100;
CYG_LABEL_DEFN(__reserved_virtual_table) = ALIGN (0x10); . = CYG_LABEL_DEFN(__reserved_virtual_table) + 0x100;
CYG_LABEL_DEFN(__reserved_for_rom) = ALIGN (0x10); . = CYG_LABEL_DEFN(__reserved_for_rom) + 0x7c00;
SECTION_rom_vectors (ram, ALIGN (0x10), LMA_EQ_VMA)
SECTION_ROMISC (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_RELOCS (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_init (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_data1 (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_eh_frame (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_ctors (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_dtors (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_devtab (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_got (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_dynamic (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_sdata (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_lit8 (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_lit4 (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_sbss (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
SECTIONS_END
}
/include/pkgconf/mlt_mips_tx49_ref4955_rom.mlt
0,0 → 1,29
version 0
region ram 80000000 4000000 0 !
region rom bfc00000 1000000 1 !
section reserved_vectors 200 1 0 0 1 1 1 1 80000000 80000000 reserved_vsr_table reserved_vsr_table !
section reserved_vsr_table 100 10 0 0 0 1 0 1 reserved_virtual_table reserved_virtual_table !
section reserved_virtual_table 100 10 0 0 0 1 0 0 data !
section data 0 10 1 1 0 1 0 1 data1 data1 !
section data1 0 8 1 1 0 1 0 1 eh_frame eh_frame !
section eh_frame 0 8 1 1 0 1 0 1 gcc_except_table gcc_except_table !
section gcc_except_table 0 8 1 1 0 1 0 1 ctors ctors !
section ctors 0 8 1 1 0 1 0 1 dtors dtors !
section dtors 0 8 1 1 0 1 0 1 devtab devtab !
section devtab 0 8 1 1 0 1 0 1 got got !
section got 0 8 1 1 0 1 0 1 dynamic dynamic !
section dynamic 0 8 1 1 0 1 0 1 sdata sdata !
section sdata 0 8 1 1 0 1 0 1 lit8 lit8 !
section lit8 0 8 1 1 0 1 0 1 lit4 lit4 !
section lit4 0 8 1 1 0 1 0 0 sbss !
section sbss 0 8 0 1 0 1 0 1 bss bss !
section bss 0 8 0 1 0 1 0 1 heap1 heap1 !
section heap1 0 8 0 0 0 0 0 0 !
section rom_vectors 0 1 0 1 1 1 1 1 bfc00000 bfc00000 ROMISC ROMISC !
section ROMISC 0 8 0 1 0 1 0 1 RELOCS RELOCS !
section RELOCS 0 8 0 1 0 1 0 1 init init !
section init 0 8 0 1 0 1 0 1 text text !
section text 0 8 0 1 0 1 0 1 fini fini !
section fini 0 8 0 1 0 1 0 1 rodata rodata !
section rodata 0 8 0 1 0 1 0 1 rodata1 rodata1 !
section rodata1 0 8 0 1 0 0 0 1 data !
/include/pkgconf/mlt_mips_tx49_ref4955_ram.mlt
0,0 → 1,29
version 0
region ram 80000000 4000000 0 !
section reserved_vectors 200 1 0 0 1 1 1 1 80000000 80000000 reserved_vsr_table reserved_vsr_table !
section reserved_vsr_table 100 10 0 0 0 1 0 1 reserved_virtual_table reserved_virtual_table !
section reserved_virtual_table 100 10 0 0 0 1 0 1 reserved_for_rom reserved_for_rom !
section reserved_for_rom 7c00 10 0 0 0 1 0 1 rom_vectors rom_vectors !
section rom_vectors 0 10 0 1 0 1 0 1 ROMISC ROMISC !
section ROMISC 0 4 0 1 0 1 0 1 RELOCS RELOCS !
section RELOCS 0 4 0 1 0 1 0 1 init init !
section init 0 4 0 1 0 1 0 1 text text !
section text 0 4 0 1 0 1 0 1 fini fini !
section fini 0 4 0 1 0 1 0 1 rodata rodata !
section rodata 0 8 0 1 0 1 0 1 rodata1 rodata1 !
section rodata1 0 8 0 1 0 1 0 1 data data !
section data 0 8 0 1 0 1 0 1 data1 data1 !
section data1 0 8 0 1 0 1 0 1 eh_frame eh_frame !
section eh_frame 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
section gcc_except_table 0 4 0 1 0 1 0 1 ctors ctors !
section ctors 0 4 0 1 0 1 0 1 dtors dtors !
section dtors 0 4 0 1 0 1 0 1 devtab devtab !
section devtab 0 4 0 1 0 1 0 1 got got !
section got 0 4 0 1 0 1 0 1 dynamic dynamic !
section dynamic 0 4 0 1 0 1 0 1 sdata sdata !
section sdata 0 4 0 1 0 1 0 1 lit8 lit8 !
section lit8 0 8 0 1 0 1 0 1 lit4 lit4 !
section lit4 0 8 0 1 0 1 0 1 sbss sbss !
section sbss 0 8 0 1 0 1 0 1 bss bss !
section bss 0 8 0 1 0 1 0 1 heap1 heap1 !
section heap1 0 8 0 0 0 0 0 0 !
/include/plf_cache.h
0,0 → 1,68
#ifndef CYGONCE_PLF_CACHE_H
#define CYGONCE_PLF_CACHE_H
 
//=============================================================================
//
// plf_cache.h
//
// HAL cache control API
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors: nickg
// Date: 1998-02-17
// Purpose: Cache control API
// Description: The macros defined here provide the HAL APIs for handling
// cache control operations.
// Usage:
// #include <cyg/hal/plf_cache.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
//=============================================================================
 
// Nothing here at present.
 
//-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_PLF_CACHE_H
// End of plf_cache.h
 
/include/platform.inc
0,0 → 1,243
#ifndef CYGONCE_HAL_PLATFORM_INC
#define CYGONCE_HAL_PLATFORM_INC
##=============================================================================
##
## platform.inc
##
## REF4955/TX4955 board assembler header file
##
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
##=============================================================================
#######DESCRIPTIONBEGIN####
##
## Author(s): nickg
## Contributors:nickg,jskov
## Date: 2000-05-15
## Purpose: REF4955/TX4955 board definitions.
## Description: This file contains various definitions and macros that are
## useful for writing assembly code for the REF4955/TX4955 board.
## Usage:
## #include <cyg/hal/platform.inc>
## ...
##
##
######DESCRIPTIONEND####
##
##=============================================================================
 
#include <cyg/hal/mips.inc>
#include <cyg/hal/plf_defs.inc>
 
 
#------------------------------------------------------------------------------
# Macro for copying vectors to RAM if necessary.
#if !defined(CYGSEM_HAL_USE_ROM_MONITOR)
 
.macro hal_vectors_init
# If we don~t play nice with a ROM monitor, copy the required
# vectors into the proper location.
la t0,0x80000000 # dest addr
la t1,utlb_vector # source addr
la t3,utlb_vector_end # end dest addr
1:
lw v0,0(t1) # get word
addi t1,t1,4
sw v0,0(t0) # write word
addi t0,t0,4
bne t1,t3,1b
nop
 
la t0,0x80000180 # dest addr
la t1,other_vector # source addr
la t3,other_vector_end # end dest addr
1:
lw v0,0(t1) # get word
addi t1,t1,4
sw v0,0(t0) # write word
addi t0,t0,4
bne t1,t3,1b
nop
 
.set mips3 # Set ISA to MIPS 3 to allow cache insns
# Now clear the region in the caches
la t0,0x80000000 # dest addr
ori t1,t0,0x200 # source addr
1: cache 0x01,0(t0) # Flush word from data cache
cache 0x01,1(t0)
cache 0x01,2(t0)
cache 0x01,3(t0)
nop
cache 0x00,0(t0) # Invalidate icache for word
cache 0x00,1(t0)
cache 0x00,2(t0)
cache 0x00,3(t0)
nop
addi t0,t0,0x20
bne t0,t1,1b
nop
.set mips0 # reset ISA to default
 
.endm
 
#else
 
.macro hal_vectors_init
.endm
 
#endif
 
#------------------------------------------------------------------------------
# Monitor initialization.
#ifndef CYGPKG_HAL_MIPS_MON_DEFINED
 
#if defined(CYG_HAL_STARTUP_ROM) || \
( defined(CYG_HAL_STARTUP_RAM) && \
!defined(CYGSEM_HAL_USE_ROM_MONITOR))
# If we are starting up from ROM, or we are starting in
# RAM and NOT using a ROM monitor, initialize the VSR table.
 
.macro hal_mon_init
hal_vectors_init
# Set default exception VSR for all vectors
ori a0,zero,CYGNUM_HAL_VSR_COUNT
la a1,__default_exception_vsr
la a2,hal_vsr_table
1: sw a1,0(a2)
addi a2,a2,4
addi a0,a0,-1
bne a0,zero,1b
nop
 
# Now set special VSRs
la a0,hal_vsr_table
# Set interrupt VSR
la a1,__default_interrupt_vsr
sw a1,CYGNUM_HAL_VECTOR_INTERRUPT*4(a0)
# Add special handler on breakpoint vector to allow GDB and
# GCC to both use 'break' without conflicts.
la a1,__break_vsr_springboard
sw a1,CYGNUM_HAL_VECTOR_BREAKPOINT*4(a0)
# Set exception handler on special vectors
# FIXME: Should use proper definitions
la a1,__default_exception_vsr
sw a1,32*4(a0) # debug
sw a1,33*4(a0) # utlb
sw a1,34*4(a0) # nmi
.endm
#elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR)
 
# Initialize the VSR table entries
# We only take control of the interrupt vector,
# the rest are left to the ROM for now...
 
.macro hal_mon_init
hal_vectors_init
# Set interrupt VSR
la a0,hal_vsr_table
la a1,__default_interrupt_vsr
sw a1,CYGNUM_HAL_VECTOR_INTERRUPT*4(a0)
.endm
 
#else
 
.macro hal_mon_init
hal_vectors_init
.endm
 
#endif
 
#define CYGPKG_HAL_MIPS_MON_DEFINED
#endif
 
#------------------------------------------------------------------------------
 
#if !defined(CYG_HAL_STARTUP_RAM)
.macro hal_memc_init
// Only initialize the SDRAM controller when running in ROM
.extern hal_memc_setup
lar t0,hal_memc_setup
jalr t0
nop
.endm
#define CYGPKG_HAL_MIPS_MEMC_DEFINED
#endif
 
#------------------------------------------------------------------------------
# Decide whether the VSR table is defined externally, or is to be defined
# here.
 
## ISR tables are defined in platform.S
#define CYG_HAL_MIPS_ISR_TABLES_DEFINED
 
## VSR table is at a fixed RAM address defined by the linker script
#define CYG_HAL_MIPS_VSR_TABLE_DEFINED
 
##-----------------------------------------------------------------------------
## For chaining, use the calculated cause vector number.
 
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
.macro hal_intc_translate inum,vnum
move \vnum,\inum # Vector == interrupt number
.endm
#define CYGPKG_HAL_MIPS_INTC_TRANSLATE_DEFINED
#endif
 
##-----------------------------------------------------------------------------
#ifdef CYG_STARTUP_ROM
 
## Initial SR value for use in ROM:
## CP0 usable
## Vectors in RAM
## FP registers are 32 bit
## All hw ints disabled
#define INITIAL_SR 0x30000000
 
#else
 
## Initial SR value for use standalone:
## CP0 usable
## Vectors to RAM
## FP registers are 32 bit
## All hw ints disabled
#define INITIAL_SR 0x30000000
 
#endif
 
#------------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_PLATFORM_INC
# end of platform.inc
/include/hal_diag.h
0,0 → 1,92
#ifndef CYGONCE_HAL_HAL_DIAG_H
#define CYGONCE_HAL_HAL_DIAG_H
 
//=============================================================================
//
// hal_diag.h
//
// HAL Support for Kernel Diagnostic Routines
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
// Contributors:jskov, nickg
// Date: 2000-05-15
// Purpose: HAL Support for Kernel Diagnostic Routines
// Description: Diagnostic routines for use during kernel development.
// Usage: #include <cyg/hal/hal_diag.h>
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h>
 
#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
 
#include <cyg/hal/hal_if.h>
 
#define HAL_DIAG_INIT() hal_if_diag_init()
#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_)
#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_)
 
#else // everything by steam
 
//-----------------------------------------------------------------------------
// functions implemented in hal_diag.c
 
externC void hal_diag_init(void);
 
externC void hal_diag_write_char(char c);
 
externC void hal_diag_read_char(char *c);
 
//-----------------------------------------------------------------------------
 
#define HAL_DIAG_INIT() hal_diag_init()
 
#define HAL_DIAG_WRITE_CHAR(_c_) hal_diag_write_char(_c_)
 
#define HAL_DIAG_READ_CHAR(_c_) hal_diag_read_char(&_c_)
 
#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
 
//-----------------------------------------------------------------------------
// end of hal_diag.h
#endif // CYGONCE_HAL_HAL_DIAG_H
/include/plf_io.h
0,0 → 1,200
#ifndef CYGONCE_PLF_IO_H
#define CYGONCE_PLF_IO_H
 
//=============================================================================
//
// plf_io.h
//
// HAL platform device IO register support.
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors:nickg, jskov
// Date: 2000-05-18
// Purpose: Define IO register support
// Description: The macros defined here provide the HAL APIs for handling
// device IO control registers.
//
// Usage:
// #include <cyg/hal/plf_io.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
 
//-----------------------------------------------------------------------------
// BYTE Register access.
// Individual and vectorized access to 8 bit registers.
 
// Little-endian version
#if (CYG_BYTEORDER == CYG_LSBFIRST)
 
#define HAL_READ_UINT8( _register_, _value_ ) \
((_value_) = *((volatile CYG_BYTE *)(_register_)))
 
#define HAL_WRITE_UINT8( _register_, _value_ ) \
(*((volatile CYG_BYTE *)(_register_)) = (_value_))
 
#define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \
CYG_MACRO_START \
cyg_count32 _i_,_j_; \
for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
(_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_j_]; \
CYG_MACRO_END
 
#define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \
CYG_MACRO_START \
cyg_count32 _i_,_j_; \
for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
((volatile CYG_BYTE *)(_register_))[_j_] = (_buf_)[_i_]; \
CYG_MACRO_END
 
#else // Big-endian version
 
#define HAL_READ_UINT8( _register_, _value_ ) \
((_value_) = *((volatile CYG_BYTE *)((CYG_ADDRWORD)(_register_)^3)))
 
#define HAL_WRITE_UINT8( _register_, _value_ ) \
(*((volatile CYG_BYTE *)((CYG_ADDRWORD)(_register_)^3)) = (_value_))
 
#define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \
CYG_MACRO_START \
cyg_count32 _i_,_j_; \
volatile CYG_BYTE* _r_ = ((CYG_ADDRWORD)(_register_)^3); \
for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
(_buf_)[_i_] = _r_[_j_]; \
CYG_MACRO_END
 
#define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \
CYG_MACRO_START \
cyg_count32 _i_,_j_; \
volatile CYG_BYTE* _r_ = ((CYG_ADDRWORD)(_register_)^3); \
for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
_r_[_j_] = (_buf_)[_i_]; \
CYG_MACRO_END
 
#endif // Big-endian
 
//-----------------------------------------------------------------------------
// 16 bit access.
// Individual and vectorized access to 16 bit registers.
// Little-endian version
#if (CYG_BYTEORDER == CYG_LSBFIRST)
 
#define HAL_READ_UINT16( _register_, _value_ ) \
((_value_) = *((volatile CYG_WORD16 *)(_register_)))
 
#define HAL_WRITE_UINT16( _register_, _value_ ) \
(*((volatile CYG_WORD16 *)(_register_)) = (_value_))
 
#define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \
CYG_MACRO_START \
cyg_count32 _i_,_j_; \
for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
(_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_j_]; \
CYG_MACRO_END
 
#define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \
CYG_MACRO_START \
cyg_count32 _i_,_j_; \
for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
((volatile CYG_WORD16 *)(_register_))[_j_] = (_buf_)[_i_]; \
CYG_MACRO_END
 
#else // Big-endian version
 
#define HAL_READ_UINT16( _register_, _value_ ) \
((_value_) = *((volatile CYG_WORD16 *)((CYG_ADDRWORD)(_register_)^3)))
 
#define HAL_WRITE_UINT16( _register_, _value_ ) \
(*((volatile CYG_WORD16 *)((CYG_ADDRWORD)(_register_)^3)) = (_value_))
 
#define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \
CYG_MACRO_START \
cyg_count32 _i_,_j_; \
volatile CYG_WORD16* _r_ = ((CYG_ADDRWORD)(_register_)^3); \
for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
(_buf_)[_i_] = _r_[_j_]; \
CYG_MACRO_END
 
#define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \
CYG_MACRO_START \
cyg_count32 _i_,_j_; \
volatile CYG_WORD16* _r_ = ((CYG_ADDRWORD)(_register_)^3); \
for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
_r_[_j_] = (_buf_)[_i_]; \
CYG_MACRO_END
 
#endif // Big-endian
 
//-----------------------------------------------------------------------------
// 32 bit access.
// Individual and vectorized access to 32 bit registers.
 
// Note: same macros for little- and big-endian systems.
#define HAL_READ_UINT32( _register_, _value_ ) \
((_value_) = *((volatile CYG_WORD32 *)(_register_)))
 
#define HAL_WRITE_UINT32( _register_, _value_ ) \
(*((volatile CYG_WORD32 *)(_register_)) = (_value_))
 
#define HAL_READ_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \
{ \
cyg_count32 _i_,_j_; \
for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
(_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_j_]; \
}
 
#define HAL_WRITE_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \
{ \
cyg_count32 _i_,_j_; \
for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
((volatile CYG_WORD32 *)(_register_))[_j_] = (_buf_)[_i_]; \
}
 
#define HAL_IO_MACROS_DEFINED
 
//-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_PLF_IO_H
// End of plf_io.h
/src/plf_stub.c
0,0 → 1,70
//=============================================================================
//
// plf_stub.c
//
// Platform specific code for GDB stub support.
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
// Contributors:jskov
// Date: 2000-05-15
// Purpose: Platform specific code for GDB stub support.
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
 
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 
#include <cyg/hal/hal_stub.h>
 
#include <cyg/hal/hal_io.h> // HAL IO macros
 
//-----------------------------------------------------------------------------
// Stub init
 
void
hal_plf_stub_init(void)
{
}
 
#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
//-----------------------------------------------------------------------------
// End of plf_stub.c
/src/pc87338.c
0,0 → 1,418
#ifndef CYGONCE_HAL_PC_SER_H
#define CYGONCE_HAL_PC_SER_H
//=============================================================================
//
// pc87338.c
//
// Simple driver for the serial controllers in the PC87338 SuperIO chip
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
// Contributors:jskov
// Date: 2000-06-20
// Description: Simple driver for the PC87338 serial controllers
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/hal/hal_arch.h> // SAVE/RESTORE GP macros
#include <cyg/hal/hal_io.h> // IO macros
#include <cyg/hal/hal_if.h> // interface API
#include <cyg/hal/hal_intr.h> // HAL_ENABLE/MASK/UNMASK_INTERRUPTS
#include <cyg/hal/hal_misc.h> // Helper functions
#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED
 
//-----------------------------------------------------------------------------
// Controller definitions.
 
//-----------------------------------------------------------------------------
// There are two serial ports.
#define CYG_DEVICE_SERIAL_SCC1 0xb40003f8 // port 1
#define CYG_DEVICE_SERIAL_SCC2 0xb40002f8 // port 2
 
//-----------------------------------------------------------------------------
// Serial registers (shared by all banks)
#define CYG_DEVICE_BSR (0x03)
#define CYG_DEVICE_LCR (0x03)
 
#define CYG_DEVICE_BSR_BANK0 0x00
#define CYG_DEVICE_BSR_BANK2 0xe0
 
#define CYG_DEVICE_LCR_LEN_5BIT 0x00
#define CYG_DEVICE_LCR_LEN_6BIT 0x01
#define CYG_DEVICE_LCR_LEN_7BIT 0x02
#define CYG_DEVICE_LCR_LEN_8BIT 0x03
#define CYG_DEVICE_LCR_STOP_1 0x00
#define CYG_DEVICE_LCR_STOP_2 0x04
#define CYG_DEVICE_LCR_PARITY_NONE 0x00
#define CYG_DEVICE_LCR_PARITY_ODD 0x08
#define CYG_DEVICE_LCR_PARITY_EVEN 0x18
#define CYG_DEVICE_LCR_PARITY_LOGIC1 0x28
#define CYG_DEVICE_LCR_PARITY_LOGIC0 0x38
#define CYG_DEVICE_LCR_SBRK 0x40
 
// Bank 0 (control/status)
#define CYG_DEVICE_BK0_TXD (0x00)
#define CYG_DEVICE_BK0_RXD (0x00)
#define CYG_DEVICE_BK0_IER (0x01)
#define CYG_DEVICE_BK0_EIR (0x02)
#define CYG_DEVICE_BK0_FCR (0x02)
#define CYG_DEVICE_BK0_MCR (0x04)
#define CYG_DEVICE_BK0_LSR (0x05)
#define CYG_DEVICE_BK0_MSR (0x06)
#define CYG_DEVICE_BK0_SPR (0x07)
#define CYG_DEVICE_BK0_ASCR (0x07)
 
#define CYG_DEVICE_BK0_LSR_RXDA 0x01
#define CYG_DEVICE_BK0_LSR_OE 0x02
#define CYG_DEVICE_BK0_LSR_PE 0x04
#define CYG_DEVICE_BK0_LSR_FE 0x08
#define CYG_DEVICE_BK0_LSR_BRK 0x10
#define CYG_DEVICE_BK0_LSR_TXRDY 0x20
#define CYG_DEVICE_BK0_LSR_TXEMP 0x40
#define CYG_DEVICE_BK0_LSR_ER_INF 0x80
 
#define CYG_DEVICE_BK0_IER_TMR_IE 0x80
#define CYG_DEVICE_BK0_IER_SFIF_IE 0x40
#define CYG_DEVICE_BK0_IER_TXEMP_IE 0x20
#define CYG_DEVICE_BK0_IER_DMA_IE 0x10
#define CYG_DEVICE_BK0_IER_MS_IE 0x08
#define CYG_DEVICE_BK0_IER_LS_IE 0x04
#define CYG_DEVICE_BK0_IER_TXLDL_IE 0x02
#define CYG_DEVICE_BK0_IER_RXHDL_IE 0x01
 
#define CYG_DEVICE_BK0_EIR_FEN1 0x80
#define CYG_DEVICE_BK0_EIR_FEN0 0x40
#define CYG_DEVICE_BK0_EIR_RXFT 0x08
#define CYG_DEVICE_BK0_EIR_IPR1 0x04
#define CYG_DEVICE_BK0_EIR_IPR0 0x02
#define CYG_DEVICE_BK0_EIR_IPF 0x01
 
#define CYG_DEVICE_BK0_EIR_mask 0x07
#define CYG_DEVICE_BK0_EIR_IRQ_ERR 0x06
#define CYG_DEVICE_BK0_EIR_IRQ_RX 0x04
#define CYG_DEVICE_BK0_EIR_IRQ_TX 0x02
 
#define CYG_DEVICE_BK0_MCR_ISEN 0x08 // interrupt signal enable
 
 
// Bank 2 (baud generator)
#define CYG_DEVICE_BK2_BGDL (0x00)
#define CYG_DEVICE_BK2_BGDH (0x01)
#define CYG_DEVICE_BK2_EXCR1 (0x02)
#define CYG_DEVICE_BK2_EXCR2 (0x04)
#define CYG_DEVICE_BK2_TXFLV (0x06)
#define CYG_DEVICE_BK2_RXFLV (0x07)
 
 
//-----------------------------------------------------------------------------
typedef struct {
cyg_uint8* base;
cyg_int32 msec_timeout;
int isr_vector;
} channel_data_t;
 
//-----------------------------------------------------------------------------
// The minimal init, get and put functions. All by polling.
 
void
cyg_hal_plf_serial_init_channel(void* __ch_data)
{
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
cyg_uint8 lcr;
 
HAL_WRITE_UINT8(base+CYG_DEVICE_BSR, CYG_DEVICE_BSR_BANK0);
HAL_WRITE_UINT8(base+CYG_DEVICE_BK0_IER, 0);
HAL_WRITE_UINT8(base+CYG_DEVICE_BK0_MCR, CYG_DEVICE_BK0_MCR_ISEN);
 
// Disable FIFOs
HAL_WRITE_UINT8(base+CYG_DEVICE_BK0_FCR, 0);
 
// 8-1-no parity.
HAL_WRITE_UINT8(base+CYG_DEVICE_LCR,
CYG_DEVICE_LCR_LEN_8BIT | CYG_DEVICE_LCR_STOP_1 | CYG_DEVICE_LCR_PARITY_NONE);
 
// Set speed to 38400 (switch bank, remember old LCR setting)
HAL_READ_UINT8(base+CYG_DEVICE_LCR, lcr);
HAL_WRITE_UINT8(base+CYG_DEVICE_BSR, CYG_DEVICE_BSR_BANK2);
HAL_WRITE_UINT8(base+CYG_DEVICE_BK2_BGDL, 3);
HAL_WRITE_UINT8(base+CYG_DEVICE_BK2_BGDH, 0);
HAL_WRITE_UINT8(base+CYG_DEVICE_LCR, lcr);
}
 
void
cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 __ch)
{
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
cyg_uint8 lsr;
CYGARC_HAL_SAVE_GP();
 
do {
HAL_READ_UINT8(base+CYG_DEVICE_BK0_LSR, lsr);
} while ((lsr & CYG_DEVICE_BK0_LSR_TXRDY) == 0);
 
HAL_WRITE_UINT8(base+CYG_DEVICE_BK0_TXD, __ch);
 
// Hang around until the character has been safely sent.
do {
HAL_READ_UINT8(base+CYG_DEVICE_BK0_LSR, lsr);
} while ((lsr & CYG_DEVICE_BK0_LSR_TXRDY) == 0);
 
CYGARC_HAL_RESTORE_GP();
}
 
static cyg_bool
cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
{
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
cyg_uint8 lsr;
 
HAL_READ_UINT8(base+CYG_DEVICE_BK0_LSR, lsr);
if ((lsr & CYG_DEVICE_BK0_LSR_RXDA) == 0)
return false;
 
HAL_READ_UINT8 (base+CYG_DEVICE_BK0_RXD, *ch);
 
return true;
}
 
cyg_uint8
cyg_hal_plf_serial_getc(void* __ch_data)
{
cyg_uint8 ch;
CYGARC_HAL_SAVE_GP();
 
while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
 
CYGARC_HAL_RESTORE_GP();
return ch;
}
 
static channel_data_t channels[2] = {
{ (cyg_uint8*)CYG_DEVICE_SERIAL_SCC1, 1000, CYGNUM_HAL_INTERRUPT_DEBUG_UART},
{ (cyg_uint8*)CYG_DEVICE_SERIAL_SCC2, 1000, CYGNUM_HAL_INTERRUPT_USER_UART}
};
 
static void
cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
cyg_uint32 __len)
{
CYGARC_HAL_SAVE_GP();
 
while(__len-- > 0)
cyg_hal_plf_serial_putc(__ch_data, *__buf++);
 
CYGARC_HAL_RESTORE_GP();
}
 
static void
cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
{
CYGARC_HAL_SAVE_GP();
 
while(__len-- > 0)
*__buf++ = cyg_hal_plf_serial_getc(__ch_data);
 
CYGARC_HAL_RESTORE_GP();
}
 
 
cyg_bool
cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
{
int delay_count;
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_bool res;
CYGARC_HAL_SAVE_GP();
 
delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
 
for(;;) {
res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
if (res || 0 == delay_count--)
break;
CYGACC_CALL_IF_DELAY_US(100);
}
 
CYGARC_HAL_RESTORE_GP();
return res;
}
 
static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_uint8 ier;
int ret = 0;
CYGARC_HAL_SAVE_GP();
 
switch (__func) {
case __COMMCTL_IRQ_ENABLE:
irq_state = 1;
 
HAL_READ_UINT8(chan->base+CYG_DEVICE_BK0_IER, ier);
ier |= CYG_DEVICE_BK0_IER_RXHDL_IE;
HAL_WRITE_UINT8(chan->base+CYG_DEVICE_BK0_IER, ier);
 
HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1);
HAL_INTERRUPT_UNMASK(chan->isr_vector);
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
 
HAL_READ_UINT8(chan->base+CYG_DEVICE_BK0_IER, ier);
ier &= ~CYG_DEVICE_BK0_IER_RXHDL_IE;
HAL_WRITE_UINT8(chan->base+CYG_DEVICE_BK0_IER, ier);
 
HAL_INTERRUPT_MASK(chan->isr_vector);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
 
va_start(ap, __func);
 
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
 
va_end(ap);
}
default:
break;
}
CYGARC_HAL_RESTORE_GP();
return ret;
}
 
static int
cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
int res = 0;
cyg_uint8 eir, c;
channel_data_t* chan = (channel_data_t*)__ch_data;
CYGARC_HAL_SAVE_GP();
 
HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
 
HAL_READ_UINT8(chan->base+CYG_DEVICE_BK0_EIR, eir);
 
*__ctrlc = 0;
if( (eir & CYG_DEVICE_BK0_EIR_mask) == CYG_DEVICE_BK0_EIR_IRQ_RX ) {
 
HAL_READ_UINT8(chan->base+CYG_DEVICE_BK0_RXD, c);
if( cyg_hal_is_break( &c , 1 ) )
*__ctrlc = 1;
 
res = CYG_ISR_HANDLED;
}
 
CYGARC_HAL_RESTORE_GP();
return res;
}
 
static void
cyg_hal_plf_serial_init(void)
{
hal_virtual_comm_table_t* comm;
int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
 
// Disable interrupts.
HAL_INTERRUPT_MASK(channels[0].isr_vector);
HAL_INTERRUPT_MASK(channels[1].isr_vector);
 
// Init channels
cyg_hal_plf_serial_init_channel((void*)&channels[0]);
cyg_hal_plf_serial_init_channel((void*)&channels[1]);
// Setup procs in the vector table
 
// Set channel 0
CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[0]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
 
// Set channel 1
CYGACC_CALL_IF_SET_CONSOLE_COMM(1);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[1]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
// Restore original console
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
}
 
void
cyg_hal_plf_comms_init(void)
{
static int initialized = 0;
 
if (initialized)
return;
 
initialized = 1;
 
cyg_hal_plf_serial_init();
}
 
//-----------------------------------------------------------------------------
// end of pc87338.c
#endif // CYGONCE_HAL_PC_SER_INL
/src/platform.S
0,0 → 1,347
##=============================================================================
##
## platform.S
##
## MIPS REF4955-TX4955 platform code
##
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
##=============================================================================
#######DESCRIPTIONBEGIN####
##
## Author(s): nickg
## Contributors:nickg, jskov
## Date: 2000-05-09
## Purpose: MIPS REF4955-TX4955 platform code
## Description: Platform specific code for REF4955-TX4955 board.
##
######DESCRIPTIONEND####
##
##=============================================================================
 
.set noreorder
 
#include <pkgconf/system.h>
#include <pkgconf/hal.h>
 
#ifdef CYGPKG_KERNEL
# include <pkgconf/kernel.h>
#endif
#include <cyg/hal/arch.inc>
#include <cyg/hal/plf_defs.inc>
 
##-----------------------------------------------------------------------------
## ISR springboard.
## This routine decodes the interrupt from the various interrupt controllers
## and vectors to it.
 
# On entry:
# a0 = MIPS status register interrupt number (1,2 or 3)
# a1 = ISR data value (= interrupt controller reg address)
# a2 = saved reg dump ptr
# s0 = saved reg dump ptr
# s1 = vector table offset
# s2 = interrupt number
# a3,v0,v1 etc available for use
 
.text
FUNC_START(hal_isr_springboard_pci)
lbu v0,0(a1)
nor v0,v0,v0
la a1,CYGARC_REG_PCI_MASK
lbu a2,0(a1)
and v0,v0,a2
addi a2,$0,CYGNUM_HAL_INTERRUPT_INTC_PCI_base
b hal_isr_springboard
nop
FUNC_END(hal_isr_springboard_pci)
FUNC_START(hal_isr_springboard_io)
lbu v0,0(a1)
nor v0,v0,v0
la a1,CYGARC_REG_IO_MASK
lbu a2,0(a1)
and v0,v0,a2
addi a2,$0,CYGNUM_HAL_INTERRUPT_INTC_IO_base
b hal_isr_springboard
nop
FUNC_END(hal_isr_springboard_io)
hal_isr_springboard_v320usc:
lw v0,0(a1)
la a1,CYGARC_REG_INT_CFG0
lw v1,0(a1)
lw a2,4(a1) # CFG1
or v1,v1,a2
lw a2,8(a1) # CFG2
or v1,v1,a2
la a1,CYGARC_REG_INT_CFG3
lw a2,0(a1)
or v1,v1,a2
and v0,v0,v1
addi a2,$0,CYGNUM_HAL_INTERRUPT_INTC_V320USC_base
FUNC_START(hal_isr_springboard)
# The following code implements an ls bit index algorithm similar
# to that in hal_lsbit_index() in hal_misc.c.
negu v1,v0 # v1 = -v0
and v1,v1,v0 # v1 &= v0 [isolate ls bit]
sll v0,v1,16 # v0 = v1<<16
subu v1,v0,v1 # v1 = v0 - v1
sll a0,v1,6 # a0 = v1<<6
addu v1,v1,a0 # v1 += a0
sll a1,v1,4 # a1 = v1<<4
addu v1,v1,a1 # v1 += a1
la v0,hal_isr_springboard_table # v0 = table address
srl v1,v1,26 # v1 = v1>>26
addu v1,v1,v0 # v1 = table entry address
lb a0,0(v1) # a0 = intc isr number
add s2,a0,a2 # s2 = eCos isr number
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
hal_isr_springboard_chaining:
# This serves as the __default_interrupt_isr entry-point in
# chaning mode, thus ensuring that all interrupts from
# vectors 0-5 eventually end up on the special CHAINING vector.
# (See the hal_interrupt_handlers table)
ori s1,zero,CYGNUM_HAL_INTERRUPT_CHAINING*4 # s1 = chaining isr ix
#else
sll s1,s2,2 # s1 = isr table index
#endif
 
la v1,hal_interrupt_handlers
add v1,v1,s1 # v1 = isr handler address
lw v1,0(v1) # v1 = isr handler
 
la a1,hal_interrupt_data
add a1,a1,s1 # a1 = address of data ptr
lw a1,0(a1) # a1 = data pointer
 
move a0,s2 # pass interrupt number
 
jr v1 # jump to handler, return is to
# default vsr already in ra
nop
 
FUNC_END(hal_isr_springboard)
 
hal_isr_springboard_table:
.byte -1, 0, 1, 12, 2, 6, 0, 13
.byte 3, 0, 7, 0, 0, 0, 0, 14
.byte 10, 4, 0, 0, 8, 0, 0, 25
.byte 0, 0, 0, 0, 0, 21, 27, 15
.byte 31, 11, 5, 0, 0, 0, 0, 0
.byte 9, 0, 0, 24, 0, 0, 20, 26
.byte 30, 0, 0, 0, 0, 23, 0, 19
.byte 29, 0, 22, 18, 28, 17, 16, 0
 
##-----------------------------------------------------------------------------
## MEMC initialization.
## This also initializes the PCI bus and ISA bus bridge, so at the end of this
## we should have full access to all the memory and devices we need.
## This code is table driven, which is somewhat more compact that coding it all.
## Table entries consist of an address and a value to store in that address.
## A zero address terminates the table. Two special address values modify the
## behaviour:
## DELAY_LOOP loops for the number of iterations in the value field.
## WRITE16 treats the next 2 words as an address and value to be written
## with a 16 bit write cycle.
#if !defined(CYG_HAL_STARTUP_RAM)
#define DELAY_LOOP 1
#define WRITE16 2
 
FUNC_START(hal_memc_setup)
 
lar t0,hal_memc_setup_table
la t1,0xbfc00000
la t2,DELAY_LOOP
la t3,WRITE16
1:
lw a0,0(t0) # next table entry
lw a1,4(t0) # value to write
addiu t0,8 # go to next entry
beq a0,t2,2f # Check for delay
nop
beq a0,t3,3f # Check for 16 bit write
nop
beqz a0,9f # zero terminates loop
nop
sw a1,0(a0) # write it
lw zero,0(t1) # uncached read to flush write buffer
b 1b
nop
2:
lw zero,0(t1) # uncached read to flush write buffer
bnez a1,2b # count down by value in a1
addiu a1,-1 # decrement in delay slot
b 1b # go back to loop
nop
3:
lw a3,0(t0) # get next word
addiu t0,4 # skip it
sh a3,0(a1) # store halfword
lw zero,0(t1) # uncached read to flush write buffer
b 1b
nop
9:
jr ra
nop
 
FUNC_END(hal_memc_setup)
 
##-----------------------------------------------------------------------------
## The initialization table
 
#define USC_LB_BUS_CFG 0xb800007c
#define USC_SDRAM_MA_CMD 0xb8000088
hal_memc_setup_table:
 
.long DELAY_LOOP, 10000 # Wait for HW to settle
 
#ifdef CYGPKG_HAL_MIPS_MSBFIRST
# V320SC : big-endian, max bus watch timer
.long USC_LB_BUS_CFG, 0x04010ff0
#else
.long USC_LB_BUS_CFG, 0x04000ff0
#endif
.long USC_SDRAM_MA_CMD, 0x00a70000
.long USC_SDRAM_MA_CMD, 0x00e70220
 
.long 0, 0
#endif // !CYG_HAL_STARTUP_RAM
##-----------------------------------------------------------------------------
## ISR tables.
.extern hal_default_isr
.data
 
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
.globl hal_interrupt_handlers
hal_interrupt_handlers:
# These first 6 vectors all go through a springboard for further
# interrupt controller vector decoding before ending up on the
# special chaining vector below.
.long hal_isr_springboard_v320usc
.long hal_isr_springboard_pci
.long hal_isr_springboard_chaining
.long hal_isr_springboard_chaining
.long hal_isr_springboard_io
.long hal_isr_springboard_chaining
 
.long hal_default_isr # chaining vector
.globl hal_interrupt_data
hal_interrupt_data:
.long CYGARC_REG_INT_STAT
.long CYGARC_REG_PCI_STAT
.long 0
.long 0
.long CYGARC_REG_IO_STAT
.long 0
 
.long 0 # chaining vector data
 
.globl hal_interrupt_objects
hal_interrupt_objects:
.long 0
.long 0
.long 0
.long 0
.long 0
.long 0
 
.long 0 # chaining vector object
 
.globl cyg_hal_interrupt_level
cyg_hal_interrupt_level:
.rept CYGNUM_HAL_ISR_COUNT
.byte 0
.endr
 
#else // CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
.globl hal_interrupt_handlers
hal_interrupt_handlers:
.long hal_isr_springboard_v320usc
.long hal_isr_springboard_pci
.long hal_default_isr
.long hal_default_isr
.long hal_isr_springboard_io
.long hal_default_isr
 
.rept CYGNUM_HAL_ISR_COUNT-6
.long hal_default_isr
.endr
.globl hal_interrupt_data
hal_interrupt_data:
.long CYGARC_REG_INT_STAT
.long CYGARC_REG_PCI_STAT
.long 0
.long 0
.long CYGARC_REG_IO_STAT
.long 0
 
.rept CYGNUM_HAL_ISR_COUNT-6
.long 0
.endr
 
.globl hal_interrupt_objects
hal_interrupt_objects:
.rept CYGNUM_HAL_ISR_COUNT
.long 0
.endr
 
.globl cyg_hal_interrupt_level
cyg_hal_interrupt_level:
.rept CYGNUM_HAL_ISR_COUNT
.byte 0
.endr
 
#endif // CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
 
##-----------------------------------------------------------------------------
## end of platform.S
/src/hal_diag.c
0,0 → 1,218
//=============================================================================
//
// hal_diag.c
//
// HAL diagnostic output code
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
// Contributors:nickg, jskov
// Date: 2000-05-10
// Purpose: HAL diagnostic output
// Description: Implementations of HAL diagnostic output support.
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
 
#if !defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
 
#include <cyg/infra/cyg_type.h> // base types
#include <cyg/infra/cyg_trac.h> // tracing macros
#include <cyg/infra/cyg_ass.h> // assertion macros
 
#include <cyg/hal/hal_arch.h>
#include <cyg/hal/hal_diag.h>
 
#include <cyg/hal/hal_intr.h>
#include <cyg/hal/hal_misc.h> // Helper functions
 
#include <cyg/hal/hal_io.h>
 
#include <cyg/hal/hal_if.h> // ROM calling interface
 
#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
#include <cyg/hal/hal_stub.h> // CYG_HAL_GDB_x_CRITICAL_IO_REGION
#endif
 
externC void cyg_hal_plf_serial_init_channel(void* __ch_data);
externC void cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 __ch);
externC cyg_uint8 cyg_hal_plf_serial_getc(void* __ch_data);
 
//-----------------------------------------------------------------------------
// Hit the hardware directly. Either wrap in GDB O-packets, or write
// data raw to device.
 
// Decide when to wrap text output as GDB O-packets
#if (CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL \
== CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL)
 
#if defined(CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs) \
|| defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
 
#define CYG_DIAG_GDB
 
#endif
 
#endif
 
//-----------------------------------------------------------------------------
// There are two serial ports. Hardwire to use one of them.
#define CYG_DEVICE_SERIAL_SCC1 0xb40003f8 // port 1
#define CYG_DEVICE_SERIAL_SCC2 0xb40002f8 // port 2
 
typedef struct {
cyg_uint8* base;
cyg_int32 msec_timeout;
int isr_vector;
} channel_data_t;
 
#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 0)
#define BASE ((cyg_uint8*)CYG_DEVICE_SERIAL_SCC1)
#else
#define BASE ((cyg_uint8*)CYG_DEVICE_SERIAL_SCC2)
#endif
 
static channel_data_t channel = { BASE, 0, 0};
 
#ifdef CYG_DIAG_GDB
 
void
hal_diag_write_char(char c)
{
static char line[100];
static int pos = 0;
 
// No need to send CRs
if( c == '\r' ) return;
 
line[pos++] = c;
 
if( c == '\n' || pos == sizeof(line) )
{
CYG_INTERRUPT_STATE old;
 
// Disable interrupts. This prevents GDB trying to interrupt us
// while we are in the middle of sending a packet. The serial
// receive interrupt will be seen when we re-enable interrupts
// later.
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
#else
HAL_DISABLE_INTERRUPTS(old);
#endif
while(1)
{
static char hex[] = "0123456789ABCDEF";
cyg_uint8 csum = 0;
int i;
char c1;
cyg_hal_plf_serial_putc(&channel, '$');
cyg_hal_plf_serial_putc(&channel, 'O');
csum += 'O';
for( i = 0; i < pos; i++ )
{
char ch = line[i];
char h = hex[(ch>>4)&0xF];
char l = hex[ch&0xF];
cyg_hal_plf_serial_putc(&channel, h);
cyg_hal_plf_serial_putc(&channel, l);
csum += h;
csum += l;
}
cyg_hal_plf_serial_putc(&channel, '#');
cyg_hal_plf_serial_putc(&channel, hex[(csum>>4)&0xF]);
cyg_hal_plf_serial_putc(&channel, hex[csum&0xF]);
 
c1 = cyg_hal_plf_serial_getc(&channel);
 
if( c1 == '+' ) break;
}
pos = 0;
// And re-enable interrupts
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
#else
HAL_RESTORE_INTERRUPTS(old);
#endif
}
}
 
void
hal_diag_read_char(char *c)
{
*c = cyg_hal_plf_serial_getc(&channel);
}
 
#else // CYG_DIAG_GDB
 
// Hit the hardware directly, no GDB translation
 
void
hal_diag_read_char(char *c)
{
*c = cyg_hal_plf_serial_getc(&channel);
}
 
void
hal_diag_write_char(char c)
{
cyg_hal_plf_serial_putc(&channel, c);
}
 
 
#endif
 
// Reagardless whether encoding or not we alway initialize the device.
 
void
hal_diag_init(void)
{
// Init serial device
cyg_hal_plf_serial_init_channel((void*)&channel);
}
 
#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
 
//-----------------------------------------------------------------------------
// End of hal_diag.c
/src/plf_mk_defs.c
0,0 → 1,106
//==========================================================================
//
// plf_mk_defs.c
//
// HAL (platform) "make defs" program
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): gthomas
// Contributors: gthomas, jskov
// Date: 2000-05-11
// Purpose: Platform dependent definition generator
// Description: This file contains code that can be compiled by the target
// compiler and used to generate machine specific definitions
// suitable for use in assembly code.
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/hal/hal_arch.h> // HAL header
#include <cyg/hal/hal_intr.h> // HAL header
#include <cyg/hal/hal_cache.h> // HAL header
#ifdef CYGPKG_KERNEL
# include <pkgconf/kernel.h>
# include <cyg/kernel/instrmnt.h>
#endif
 
/*
* This program is used to generate definitions needed by
* assembly language modules.
*
* This technique was first used in the OSF Mach kernel code:
* generate asm statements containing #defines,
* compile this file to assembler, and then extract the
* #defines from the assembly-language output.
*/
 
#define DEFINE(sym, val) \
asm volatile("\n\t.equ\t" #sym ",%0" : : "i" (val))
 
int
main(void)
{
// Some other exception related definitions
DEFINE(CYGNUM_HAL_ISR_COUNT, CYGNUM_HAL_ISR_COUNT);
DEFINE(CYGNUM_HAL_VSR_COUNT, CYGNUM_HAL_VSR_COUNT);
DEFINE(CYGNUM_HAL_VECTOR_INTERRUPT, CYGNUM_HAL_VECTOR_INTERRUPT);
DEFINE(CYGNUM_HAL_VECTOR_BREAKPOINT, CYGNUM_HAL_VECTOR_BREAKPOINT);
 
// Interrupt details
DEFINE(CYGNUM_HAL_INTERRUPT_INTC_V320USC_base, CYGNUM_HAL_INTERRUPT_INTC_V320USC_base);
DEFINE(CYGNUM_HAL_INTERRUPT_INTC_PCI_base, CYGNUM_HAL_INTERRUPT_INTC_PCI_base);
DEFINE(CYGNUM_HAL_INTERRUPT_INTC_IO_base, CYGNUM_HAL_INTERRUPT_INTC_IO_base);
DEFINE(CYGARC_REG_INT_STAT, CYGARC_REG_INT_STAT);
DEFINE(CYGARC_REG_PCI_STAT, CYGARC_REG_PCI_STAT);
DEFINE(CYGARC_REG_IO_STAT, CYGARC_REG_IO_STAT);
DEFINE(CYGARC_REG_PCI_MASK, CYGARC_REG_PCI_MASK);
DEFINE(CYGARC_REG_IO_MASK, CYGARC_REG_IO_MASK);
DEFINE(CYGARC_REG_INT_CFG0, CYGARC_REG_INT_CFG0);
DEFINE(CYGARC_REG_INT_CFG3, CYGARC_REG_INT_CFG3);
#if defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN)
DEFINE(CYGNUM_HAL_INTERRUPT_CHAINING, CYGNUM_HAL_INTERRUPT_CHAINING);
#endif
 
return 0;
}
 
//--------------------------------------------------------------------------
// EOF plf_mk_defs.c
/src/plf_misc.c
0,0 → 1,123
//==========================================================================
//
// plf_misc.c
//
// HAL platform miscellaneous functions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors: nickg, jlarmour, jskov
// Date: 2000-05-15
// Purpose: HAL miscellaneous functions
// Description: This file contains miscellaneous functions provided by the
// HAL.
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h> // Base types
#include <cyg/infra/cyg_trac.h> // tracing macros
#include <cyg/infra/cyg_ass.h> // assertion macros
 
#include <cyg/hal/hal_arch.h> // architectural definitions
 
#include <cyg/hal/hal_intr.h> // Interrupt handling
 
#include <cyg/hal/hal_cache.h> // Cache handling
#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED
 
#include <cyg/hal/hal_if.h> // Calling interface definitions
#include <cyg/hal/hal_misc.h> // Helper functions
 
//--------------------------------------------------------------------------
 
#define CYGARC_REG_SUPERIO_IREG 0xb4000398
#define CYGARC_REG_SUPERIO_DREG 0xb4000399
 
#define CYGARC_REG_SUPERIO_FER 0x00 // function enable
#define CYGARC_REG_SUPERIO_FAR 0x01 // function address
#define CYGARC_REG_SUPERIO_PTR 0x02 // power and test
#define CYGARC_REG_SUPERIO_CLK 0x51 // clock controller
 
 
#define CYGARC_REG_SUPERIO_FER_PAR 0x01
#define CYGARC_REG_SUPERIO_FER_SCC1 0x02
#define CYGARC_REG_SUPERIO_FER_SCC2 0x04
 
#define CYGARC_REG_SUPERIO_CLK_14M 0x00 // 14MHz source
#define CYGARC_REG_SUPERIO_CLK_CME 0x04 // clock multiplier enabled
 
#define CYGARC_REG_SUPERIO_PTR_PPEXT 0x80 // extended
 
 
 
 
static void write_super_io(cyg_uint8 offset, cyg_uint8 data)
{
HAL_WRITE_UINT8(CYGARC_REG_SUPERIO_IREG, offset);
HAL_WRITE_UINT8(CYGARC_REG_SUPERIO_DREG, data);
HAL_WRITE_UINT8(CYGARC_REG_SUPERIO_DREG, data);
}
 
void hal_platform_init(void)
{
hal_if_init();
 
// Configure the SuperIO chip
write_super_io(CYGARC_REG_SUPERIO_FER,
CYGARC_REG_SUPERIO_FER_SCC1|CYGARC_REG_SUPERIO_FER_SCC2);
write_super_io(CYGARC_REG_SUPERIO_FAR, 0x10);
write_super_io(CYGARC_REG_SUPERIO_CLK,
CYGARC_REG_SUPERIO_CLK_14M|CYGARC_REG_SUPERIO_CLK_CME);
 
// Set up VSC320 interrupt controller. INT1 must merge INT2 and
// INT3 according to the platform specification.
HAL_WRITE_UINT32(CYGARC_REG_INT_CFG1,
CYGARC_REG_INT_CFG_INT2|CYGARC_REG_INT_CFG_INT3);
 
// Unmask vectors which are entry points for interrupt controllers
HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_V320USC_INT0);
HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_V320USC_INT1);
HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_IO);
}
 
//--------------------------------------------------------------------------
// End of plf_misc.c
/ChangeLog
0,0 → 1,366
2003-01-29 John Dallaway <jld@ecoscentric.com>
 
* misc/slow_cat.tcl, misc/swap4.tcl:
Accommodate latest Cygwin Tcl shell (tclsh83.exe)
 
2002-08-06 Gary Thomas <gary@chez-thomas.org>
2002-08-06 Motoya Kurotsu <kurotsu@allied-telesis.co.jp>
 
* src/pc87338.c: I/O channel data can't be constant - contains
timeout information which can be changed.
 
2002-05-13 Jesper Skov <jskov@redhat.com>
 
* cdl/hal_mips_tx49_ref4955.cdl: Removed implemntation of
CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT_NOT_GUARANTEED.
 
2002-04-24 Jesper Skov <jskov@redhat.com>
 
* cdl/hal_mips_tx49_ref4955.cdl:
CYGPRI_KERNEL_TESTS_DHRYSTONE_PASSES defined.
 
2001-03-08 Jesper Skov <jskov@redhat.com>
 
* cdl/hal_mips_tx49_ref4955.cdl: Does not guarantee virtual vector
support.
 
2001-02-08 Jesper Skov <jskov@redhat.com>
 
* cdl/hal_mips_tx49_ref4955.cdl: Respect channel configuration
constraints.
 
2001-01-26 Jesper Skov <jskov@redhat.com>
 
* src/pc87338.c: Removed CYGSEM_HAL_VIRTUAL_VECTOR_DIAG check.
* include/plf_stub.h: Reset macros moved
* include/plf_intr.h: to this file.
 
2000-10-20 Jonathan Larmour <jlarmour@redhat.com>
 
* include/pkgconf/mlt_mips_tx49_ref4955_ram.mlt:
* include/pkgconf/mlt_mips_tx49_ref4955_rom.mlt:
Add heap1 section
 
* include/pkgconf/mlt_mips_tx49_ref4955_ram.h:
* include/pkgconf/mlt_mips_tx49_ref4955_rom.h:
* include/pkgconf/mlt_mips_tx49_ref4955_ram.ldi:
* include/pkgconf/mlt_mips_tx49_ref4955_rom.ldi:
Regenerated
 
2000-09-06 Jesper Skov <jskov@redhat.com>
 
* include/platform.inc: Flush cache after copying vectors.
 
* src/plf_misc.c (hal_platform_init): Removed cache-enabling
code. This is now done earlier in the variant init code.
 
2000-07-21 Jesper Skov <jskov@redhat.com>
 
* include/platform.inc: Moved vector copying code to
hal_mon_init so it comes after cache initialization.
 
2000-06-30 Jesper Skov <jskov@redhat.com>
 
* src/pc87338.c: calling i/f macro changes.
 
* src/hal_diag.c: Fix warning.
 
* cdl/hal_mips_tx49_ref4955.cdl: Endian options next to each
other.
 
* include/platform.inc: Only define hal_memc_setup if it will have
a content - otherwise the assembler emits a (harmless) warning.
 
2000-06-29 Jesper Skov <jskov@redhat.com>
 
* src/hal_diag.c: Changed to match the below.
 
* src/pc87338.c: Use per-channel data struct instead of crufty code.
 
2000-06-28 Jesper Skov <jskov@redhat.com>
 
* src/hal_diag.c: Cleanup.
 
2000-06-26 Jesper Skov <jskov@redhat.com>
 
* src/plf_misc.c:
* src/pc87338.c:
* include/plf_intr.h:
Moved Ctrl-c handling to driver file. Added timeout and proper
channel changing services.
 
* cdl/hal_mips_tx49_ref4955.cdl: Removed ROM_DEBUG_CHANNEL option.
 
2000-06-21 Jonathan Larmour <jlarmour@redhat.co.uk>
 
* misc/slow_cat.tcl: Fix quoting when invoking TCL interpreter
* misc/swap4.tcl: Likewise
 
2000-06-21 Jesper Skov <jskov@redhat.com>
 
* src/plf_stub.c:
* src/pc87338.c: [added]
* src/pc87338.inl: [deleted]
* src/hal_diag.c:
* include/plf_stub.h:
* include/hal_diag.h:
* cdl/hal_mips_tx49_ref4955.cdl:
Whenever a serial driver is included, use it to service both ports
via the vector table, both for diag and stub use. Configurations
which rely on the vector table then do not need any serial driver,
regardless of which port is configured for use.
 
2000-06-15 Jesper Skov <jskov@redhat.com>
 
* include/hal_diag.h: Only define HAL_PLF_DIAG functions when
required.
 
* src/plf_misc.c: Comment fix.
 
* src/plf_stub.c: Config option renamed.
 
* src/hal_diag.c:
* include/hal_diag.h:
Use common HAL console wrappers for virtual vector diag.
 
* cdl/hal_mips_tx49_ref4955.cdl: Added final console/debug comm
config options. Cleaned up USE_ROM_MONITOR option.
 
2000-06-13 Jesper Skov <jskov@redhat.com>
 
* src/plf_misc.c (hal_ctrlc_isr): Only return handled when the irq
was indeed handled.
 
* cdl/hal_mips_tx49_ref4955.cdl: Added some virtual vector config
variables.
 
2000-06-09 Jesper Skov <jskov@redhat.com>
 
* src/hal_diag.c: Only use table diag if so configured.
 
2000-06-08 Jesper Skov <jskov@redhat.com>
 
* src/plf_stub.c: init code moved to common HAL.
 
* src/plf_misc.c: Moved some code and init responsibilities to
common HAL.
 
* src/hal_diag.c: Allow use of ROM interface for diag IO.
 
* include/plf_stub.h (HAL_STUB_PLATFORM_RESET_ENTRY): defined
(mostly for testing, as the board has reset).
 
* include/hal_diag.h: Use diag_init to allow for configuration.
 
* cdl/hal_mips_tx49_ref4955.cdl: Tweaks for
CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT.
 
2000-06-06 Jonathan Larmour <jlarmour@redhat.co.uk>
 
* misc/slow_cat.tcl: Use more correct runes to restart with tclsh
* misc/swap4.tcl: likewise
 
2000-05-30 Jesper Skov <jskov@redhat.com>
 
* include/plf_intr.h:
Handle V320USC sources in mask/unmask/ack macros.
 
* src/plf_misc.c:
* include/plf_intr.h:
Set VSC320 interrupt controller as per spec.
 
* include/plf_stub.h (HAL_STUB_PLATFORM_RESET): Memory access to
reset board.
 
* src/platform.S:
* src/plf_mk_defs.c:
Mask request bits with enable bits on VSC320.
 
2000-05-26 Jesper Skov <jskov@redhat.com>
 
* include/pkgconf/mlt_mips_tx49_ref4955_rom.h:
* include/pkgconf/mlt_mips_tx49_ref4955_rom.ldi:
* include/pkgconf/mlt_mips_tx49_ref4955_rom.mlt:
* include/pkgconf/mlt_mips_tx49_ref4955_ram.h:
* include/pkgconf/mlt_mips_tx49_ref4955_ram.ldi:
* include/pkgconf/mlt_mips_tx49_ref4955_ram.mlt:
Updated MLT files.
 
2000-05-25 Jesper Skov <jskov@redhat.com>
 
* src/plf_misc.c: Set up thread debug ptr.
 
* cdl/hal_mips_tx49_ref4955.cdl: Include thread support in stub.
 
2000-05-24 Jesper Skov <jskov@redhat.com>
 
* include/platform.inc: Don't use k0/k1 in init code (not a
problem per se, but for consistency).
 
2000-05-23 Jesper Skov <jskov@redhat.com>
 
* src/plf_mk_defs.c:
* src/platform.S:
* include/plf_intr.h:
* include/platform.inc (hal_intc_translate): Use vectors 0-5 even
when chaining is enabled.
 
* misc/slow_cat.tcl: Removed the regexp magic. gets handles the
conversion.
 
2000-05-22 Jesper Skov <jskov@redhat.com>
 
* misc/slow_cat.tcl: Comments and minor tweaks.
 
* src/platform.S:
* include/platform.inc:
* src/plf_mk_defs.c:
* cdl/hal_mips_tx49_ref4955.cdl:
Use mk_defs definitions instead of magic constants.
 
* cdl/hal_mips_tx49_ref4955.cdl: Generate swapped srec file.
 
* src/pc87338.inl:
* src/hal_diag.c:
Cleanup.
 
2000-05-18 Jesper Skov <jskov@redhat.com>
 
* include/plf_io.h: Define endian-safe IO macros.
 
* src/plf_stub.c:
* src/hal_diag.c:
Use specified ports.
 
* cdl/hal_mips_tx49_ref4955.cdl: Change default endianess to
big. Add options to control debug/diag ports.
 
* src/platform.S: Set V320SC to big-endian mode when required.
 
2000-05-17 Jesper Skov <jskov@redhat.com>
 
* src/plf_stub.c:
* src/plf_misc.c:
* src/pc87338.inl:
Ctrl-c code uses local stub if available.
 
* src/hal_diag.c: Fixed for running under stub.
 
* include/plf_intr.h: Fix warnings.
 
* include/pkgconf/mlt_mips_tx49_ref4955_ram.ldi:
* include/pkgconf/mlt_mips_tx49_ref4955_rom.ldi:
Leave gap for virtual table.
 
* src/plf_misc.c: Support ctrl-c.
 
* src/platform.S: Springboard code must use mask since sources are
set to interrupt when disabled.
 
* src/pc87338.inl: Added interrupt definitions and interrupt init.
 
* src/plf_stub.c:
* include/plf_stub.h:
Platform stub init of virtual vector table.
 
* include/plf_intr.h: Added control macros. Only handles on-board
interrupt controller, not the V320USC one.
 
* include/platform.inc: Use VSR/break springboard.
 
2000-05-16 Jesper Skov <jskov@redhat.com>
 
* include/platform.inc:
Use FPU in 32 bit mode.
 
2000-05-15 Jesper Skov <jskov@redhat.com>
 
* cdl/hal_mips_tx49_ref4955.cdl: Require warm-starts to be treated
like cold-starts.
 
* src/plf_stub.c:
* include/plf_stub.h:
* include/plf_io.h:
* include/hal_diag.h:
Cleanup.
 
* src/platform.S: Adjust springboard code for the three interrupt
controllers.
* include/plf_intr.h: Change vectors to match decoding.
* include/platform.inc: Cleanup. Enable FPU.
* cdl/hal_mips_tx49_ref4955.cdl: Cleanup. Fix incrementer rate.
 
2000-05-12 Jesper Skov <jskov@redhat.com>
 
* src/plf_misc.c (hal_platform_init): Initialize SuperIO chip.
 
* src/platform.S: Added magic assembler operand.
 
* src/hal_diag.c: Cleaned up.
 
* include/platform.inc (hal_memc_init): Added configury.
 
* cdl/hal_mips_tx49_ref4955.cdl: Default to GDB_stubs ROM monitor.
 
2000-05-11 Jesper Skov <jskov@redhat.com>
 
* include/pkgconf/mlt_mips_tx49_ref4955_rom.ldi:
* include/pkgconf/mlt_mips_tx49_ref4955_ram.ldi:
More space for vectors and VSR table [need to update .h&.ldi]
* include/platform.inc: Move memory setup into a function. Fix
register typos.
 
* include/platform.inc: Re-added the magic debug exception VSR
pointers. Copy VSRs to vector space [needs configury].
 
* include/pkgconf/mlt_mips_tx49_ref4955_ram.h:
* include/pkgconf/mlt_mips_tx49_ref4955_ram.ldi:
* include/pkgconf/mlt_mips_tx49_ref4955_ram.mlt:
* include/pkgconf/mlt_mips_tx49_ref4955_rom.h:
* include/pkgconf/mlt_mips_tx49_ref4955_rom.ldi:
* include/pkgconf/mlt_mips_tx49_ref4955_rom.mlt:
Updated for platform.
 
* include/platform.inc: Some definitions added.
 
* cdl/hal_mips_tx49_ref4955.cdl: don't move srec image.
 
2000-05-10 Jesper Skov <jskov@redhat.com>
 
* Cloned from jmr3904. Still stuff to clean out and stuff to add.
 
//===========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//===========================================================================
/misc/swap4.tcl
0,0 → 1,26
#!/bin/bash
# restart using a Tcl shell \
exec sh -c 'for tclshell in tclsh tclsh83 cygtclsh80 ; do \
( echo | $tclshell ) 2> /dev/null && exec $tclshell "`( cygpath -w \"$0\" ) 2> /dev/null || echo $0`" "$@" ; \
done ; \
echo "swap4.tcl: cannot find Tcl shell" ; exit 1' "$0" "$@"
 
proc filter { input_file output_file } {
set input_fd [open $input_file "r"]
set output_fd [open $output_file "w"]
 
fconfigure $input_fd -translation binary
fconfigure $output_fd -translation binary
while { 1 } {
set data [read $input_fd 4]
if { [eof $input_fd] } {
break
}
binary scan $data "i" var
puts -nonewline $output_fd [binary format "I" $var]
}
close $input_fd
close $output_fd
}
 
filter [lindex $argv 0] [lindex $argv 1]
/misc/slow_cat.tcl
0,0 → 1,21
#!/bin/bash
# restart using a Tcl shell \
exec sh -c 'for tclshell in tclsh tclsh83 cygtclsh80 ; do \
( echo | $tclshell ) 2> /dev/null && exec $tclshell "`( cygpath -w \"$0\" ) 2> /dev/null || echo $0`" "$@" ; \
done ; \
echo "slow_cat.tcl: cannot find Tcl shell" ; exit 1' "$0" "$@"
 
# Can be used like this:
# Get flash ready for programming using Minicom or similar
# [o (Option menu), a (flAsh menu), b (Boot write)]
# Then execute the following
# slow_cat.tcl < install/bin/gdb_module.srec >/dev/ttyS0
 
# Delay lines by 1/10 of a second to allow the flash to recover The
# gets also strips off the broken (DOS) new-lines that objcopy is
# generating. The puts replace them with 0x0a which the firmware
# requires.
while { 0 <= [gets stdin line] } {
puts $line
after 100
}

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