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    /openrisc/trunk/rtos/ecos-2.0/packages/hal/mips/rm7000/var
    from Rev 27 to Rev 174
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Rev 27 → Rev 174

/v2_0/cdl/hal_mips_rm7000.cdl
0,0 → 1,163
# ====================================================================
#
# hal_mips_rm7000.cdl
#
# MIPS/RM7000 variant architectural HAL package configuration data
#
# ====================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
# ====================================================================
######DESCRIPTIONBEGIN####
#
# Author(s): jskov
# Original data: bartv, nickg
# Contributors:
# Date: 2000-05-15
#
#####DESCRIPTIONEND####
#
# ====================================================================
 
cdl_package CYGPKG_HAL_MIPS_RM7000 {
display "RM7000 variant"
parent CYGPKG_HAL_MIPS
hardware
include_dir cyg/hal
define_header hal_mips_rm7000.h
description "
The RM7000 architecture HAL package provides generic support
for this processor architecture. It is also necessary to
select a specific target platform HAL package."
 
cdl_component CYGPKG_HAL_MIPS_RM7000A {
display "RM7000A microprocessor"
default_value 1
implements CYGINT_HAL_MIPS_VARIANT
description "
The RM7000A microprocessor. This is chip which in addition to
the RM7000 processor core has built in second level cache
of 256kB."
 
define_proc {
# Sizes are configurable (on the core). Should be configurable.
puts $::cdl_header "#define CYGHWR_HAL_DCACHE_SIZE 16384"
puts $::cdl_header "#define CYGHWR_HAL_ICACHE_SIZE 16384"
}
 
cdl_option CYGHWR_HAL_MIPS_64BIT {
display "Variant 64 bit architecture support"
description "
While the RM7000 is a 64bit CPU, only its 32bit mode is
currently supported in eCos."
calculated 0
}
 
# This is optional (on the core). Should be configurable.
cdl_option CYGHWR_HAL_MIPS_FPU {
display "Variant FPU support"
calculated 1
}
 
cdl_interface CYGINT_HAL_MIPS_FPU_64BIT {
display "Variant 64 bit FPU support interface"
}
 
cdl_option CYGHWR_HAL_MIPS_FPU_64BIT {
display "Variant 64 bit FPU support"
calculated { CYGINT_HAL_MIPS_FPU_64BIT == 1 ? 1 : 0 }
}
 
cdl_option CYGHWR_HAL_MIPS_FPU_32BIT {
display "Variant 32 bit FPU support"
calculated { CYGINT_HAL_MIPS_FPU_64BIT == 0 ? 1 : 0 }
}
 
# FGRn+1 is most significant part of the FGRn&FGRn+1 pair of FPRn/2
# This is true for BE mips2 mode at least. Not sure about fp64 mode
cdl_option CYGPKG_HAL_MIPS_DOUBLE_LSBFIRST {
active_if CYGHWR_HAL_MIPS_FPU_32BIT
calculated 1
}
 
cdl_interface CYGINT_HAL_MIPS_MSBFIRST {
no_define
display "CPU Variant big-endian interface"
}
 
cdl_option CYGPKG_HAL_MIPS_MSBFIRST {
display "CPU Variant big-endian"
calculated { CYGINT_HAL_MIPS_MSBFIRST == 0 ? 0 : 1 }
}
 
cdl_option CYGPKG_HAL_MIPS_LSBFIRST {
display "CPU Variant little-endian"
calculated { CYGINT_HAL_MIPS_MSBFIRST != 0 ? 0 : 1 }
}
}
 
define_proc {
puts $::cdl_header "#include <pkgconf/hal_mips.h>"
}
 
compile var_misc.c variant.S var_mk_defs.c
 
# The "-o file" is a workaround for CR100958 - without it the
# output file would end up in the source directory under CygWin.
# n.b. grep does not behave itself under win32
make -priority 1 {
<PREFIX>/include/cyg/hal/var_defs.inc : <PACKAGE>/src/var_mk_defs.c
$(CC) $(CFLAGS) $(INCLUDE_PATH) -Wp,-MD,var_defs.tmp -o var_mk_defs.tmp -S $<
fgrep .equ var_mk_defs.tmp | sed s/#// > $@
@echo $@ ": \\" > $(notdir $@).deps
@tail +2 var_defs.tmp >> $(notdir $@).deps
@echo >> $(notdir $@).deps
@rm var_defs.tmp var_mk_defs.tmp
}
 
make {
<PREFIX>/lib/target.ld: <PACKAGE>/src/mips_rm7000.ld
$(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(CFLAGS) -o $@ $<
@echo $@ ": \\" > $(notdir $@).deps
@tail +2 target.tmp >> $(notdir $@).deps
@echo >> $(notdir $@).deps
@rm target.tmp
}
 
cdl_option CYGBLD_LINKER_SCRIPT {
display "Linker script"
flavor data
no_define
calculated { "src/mips_rm7000.ld" }
}
}
/v2_0/include/var_cache.h
0,0 → 1,199
#ifndef CYGONCE_VAR_CACHE_H
#define CYGONCE_VAR_CACHE_H
 
//=============================================================================
//
// var_cache.h
//
// HAL cache control API
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors:nickg, jskov
// Date: 2000-05-09
// Purpose: Cache control API
// Description: The macros defined here provide the HAL APIs for handling
// cache control operations.
// Usage:
// #include <cyg/hal/imp_cache.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
#include CYGHWR_MEMORY_LAYOUT_H
 
#include <cyg/infra/cyg_type.h>
 
#include <cyg/hal/mips-regs.h>
 
#include <cyg/hal/plf_cache.h>
 
 
//=============================================================================
// Area to use for cache scrubbing. This must be a cache sized area in
// cachable space which can be cleared. Defaults to use the area reserved
// for shared PCI memory space.
#ifndef CYGHWR_HAL_MIPS_RM7000_CACHE_SCRUB_BASE
# define CYGHWR_HAL_MIPS_RM7000_CACHE_SCRUB_BASE CYGMEM_SECTION_pci_window
#endif
 
//=============================================================================
// QED RM7000A
 
#ifdef CYGPKG_HAL_MIPS_RM7000A
 
//-----------------------------------------------------------------------------
// Cache dimensions
 
// Data cache
#define HAL_DCACHE_SIZE CYGHWR_HAL_DCACHE_SIZE // size in bytes
#define HAL_DCACHE_LINE_SIZE 32 // Size of a data cache line
#define HAL_DCACHE_WAYS 4 // Associativity of the cache
 
// Instruction cache
#define HAL_ICACHE_SIZE CYGHWR_HAL_ICACHE_SIZE // size in bytes
#define HAL_ICACHE_LINE_SIZE 32 // Size of a cache line
#define HAL_ICACHE_WAYS 4 // Associativity of the cache
 
#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
 
//-----------------------------------------------------------------------------
// Global control of data cache
 
//-----------------------------------------------------------------------------
//The RM7000 mostly uses the default MIPS cache controls defined in
//hal_cache.h Here we define the cache enable and disable macros. The
//only control we appear to have is the kseg0 cache state in
//config0. So all these macros at present manipulate this.
 
#ifndef HAL_DCACHE_ENABLE_DEFINED
#define HAL_DCACHE_ENABLE() \
CYG_MACRO_START \
asm volatile ( "mfc0 $2,$16\n" \
"nop; nop; nop\n" \
"la $3,0xFFFFFFF8\n" \
"and $2,$2,$3\n" \
"ori $2,$2,3\n" \
"mtc0 $2,$16\n" \
"nop; nop; nop;\n" \
: \
: \
: "$2", "$3" \
); \
CYG_MACRO_END
#define HAL_DCACHE_ENABLE_DEFINED
#endif
 
// Disable the data cache
#ifndef HAL_DCACHE_DISABLE_DEFINED
#define HAL_DCACHE_DISABLE() \
CYG_MACRO_START \
asm volatile ( "mfc0 $2,$16\n" \
"nop; nop; nop\n" \
"la $3,0xFFFFFFF8\n" \
"and $2,$2,$3\n" \
"ori $2,$2,2\n" \
"mtc0 $2,$16\n" \
"nop; nop; nop;\n" \
: \
: \
: "$2", "$3" \
); \
CYG_MACRO_END
#define HAL_DCACHE_DISABLE_DEFINED
#endif
 
#ifndef HAL_DCACHE_IS_ENABLED_DEFINED
#define HAL_DCACHE_IS_ENABLED(_state_) \
CYG_MACRO_START \
CYG_WORD32 _cstate_; \
asm volatile ( "mfc0 %0,$16\n" \
: "=r"(_cstate_) \
); \
if( (_cstate_ & 7) == 2 ) _state_ = 0; \
else _state_ = 1; \
CYG_MACRO_END
#define HAL_DCACHE_IS_ENABLED_DEFINED
#endif
 
#ifndef HAL_ICACHE_ENABLE_DEFINED
#define HAL_ICACHE_ENABLE() HAL_DCACHE_ENABLE()
#define HAL_ICACHE_ENABLE_DEFINED
#endif
 
// Disable the instruction cache
#ifndef HAL_ICACHE_DISABLE_DEFINED
#define HAL_ICACHE_DISABLE() HAL_DCACHE_DISABLE()
#define HAL_ICACHE_DISABLE_DEFINED
#endif
 
#ifndef HAL_ICACHE_IS_ENABLED_DEFINED
#define HAL_ICACHE_IS_ENABLED(_state_) HAL_DCACHE_IS_ENABLED(_state_)
#define HAL_ICACHE_IS_ENABLED_DEFINED
#endif
 
#if 0 // FIXME: Need this for RM7000A also?
// TX49 cache instruction must not affect the line it executes out of,
// so disable instruction cache before invalidating it.
#define HAL_ICACHE_INVALIDATE_ALL_DEFINED
#define HAL_ICACHE_INVALIDATE_ALL() \
CYG_MACRO_START \
register CYG_ADDRESS _baddr_ = 0x80000000; \
register CYG_ADDRESS _addr_ = 0x80000000; \
register CYG_WORD _state_; \
_HAL_ASM_SET_MIPS_ISA(3); \
HAL_ICACHE_IS_ENABLED( _state_ ); \
HAL_ICACHE_DISABLE(); \
for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \
{ _HAL_ASM_ICACHE_ALL_WAYS(0x00, _addr_); } \
if( _state_ ) HAL_ICACHE_ENABLE(); \
_HAL_ASM_SET_MIPS_ISA(0); \
CYG_MACRO_END
#endif
 
#endif // CYGPKG_HAL_MIPS_RM7000A
 
 
//-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_VAR_CACHE_H
// End of var_cache.h
/v2_0/include/var_intr.h
0,0 → 1,178
#ifndef CYGONCE_HAL_VAR_INTR_H
#define CYGONCE_HAL_VAR_INTR_H
 
//==========================================================================
//
// imp_intr.h
//
// RM7000 Interrupt and clock support
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
// Contributors: jskov
// Date: 2000-05-09
// Purpose: RM7000 Interrupt support
// Description: The macros defined here provide the HAL APIs for handling
// interrupts and the clock for variants of the RM7000 MIPS
// architecture.
//
// Usage:
// #include <cyg/hal/var_intr.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/hal/plf_intr.h>
 
//--------------------------------------------------------------------------
// Interrupt controller information
 
#ifndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
#define HAL_INTERRUPT_MASK( _vector_ ) \
CYG_MACRO_START \
if( (_vector_) <= CYGNUM_HAL_INTERRUPT_COMPARE ) \
{ \
asm volatile ( \
"mfc0 $3,$12\n" \
"la $2,0x00000400\n" \
"sllv $2,$2,%0\n" \
"nor $2,$2,$0\n" \
"and $3,$3,$2\n" \
"mtc0 $3,$12\n" \
"nop; nop; nop\n" \
: \
: "r"(_vector_) \
: "$2", "$3" \
); \
} \
else \
{ \
/* int 6:9 are masked in the Interrupt Control register */ \
asm volatile ( \
"cfc0 $3,$20\n" \
"la $2,0x00000004\n" \
"sllv $2,$2,%0\n" \
"nor $2,$2,$0\n" \
"and $3,$3,$2\n" \
"ctc0 $3,$20\n" \
"nop; nop; nop\n" \
: \
: "r"((_vector_) ) \
: "$2", "$3" \
); \
} \
CYG_MACRO_END
 
#define HAL_INTERRUPT_UNMASK( _vector_ ) \
CYG_MACRO_START \
if( (_vector_) <= CYGNUM_HAL_INTERRUPT_COMPARE ) \
{ \
asm volatile ( \
"mfc0 $3,$12\n" \
"la $2,0x00000400\n" \
"sllv $2,$2,%0\n" \
"or $3,$3,$2\n" \
"mtc0 $3,$12\n" \
"nop; nop; nop\n" \
: \
: "r"(_vector_) \
: "$2", "$3" \
); \
} \
else \
{ \
/* int 6:9 are masked in the Interrupt Control register */ \
asm volatile ( \
"cfc0 $3,$20\n" \
"la $2,0x00000004\n" \
"sllv $2,$2,%0\n" \
"or $3,$3,$2\n" \
"ctc0 $3,$20\n" \
"nop; nop; nop\n" \
: \
: "r"((_vector_) ) \
: "$2", "$3" \
); \
} \
CYG_MACRO_END
 
#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
CYG_MACRO_START \
/* All 10 interrupts have pending bits in the cause register */ \
cyg_uint32 _srvector_ = _vector_; \
asm volatile ( \
"mfc0 $3,$13\n" \
"la $2,0x00000400\n" \
"sllv $2,$2,%0\n" \
"nor $2,$2,$0\n" \
"and $3,$3,$2\n" \
"mtc0 $3,$13\n" \
"nop; nop; nop\n" \
: \
: "r"(_srvector_) \
: "$2", "$3" \
); \
CYG_MACRO_END
 
#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ )
 
#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ )
 
#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
 
#endif
 
//--------------------------------------------------------------------------
// Interrupt vectors.
 
// Vectors and handling of these are defined in platform HALs since the
// CPU itself does not have a builtin interrupt controller.
 
//--------------------------------------------------------------------------
// Clock control
 
// This is handled by the default code
 
//--------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_VAR_INTR_H
// End of var_intr.h
/v2_0/include/var_arch.h
0,0 → 1,71
#ifndef CYGONCE_HAL_VAR_ARCH_H
#define CYGONCE_HAL_VAR_ARCH_H
 
//==========================================================================
//
// var_arch.h
//
// Architecture specific abstractions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors: nickg, jskov
// Date: 2000-05-15
// Purpose: Define architecture abstractions
// Description: This file contains any extra or modified definitions for
// this variant of the architecture.
// Usage: #include <cyg/hal/var_arch.h>
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>
 
// -------------------------------------------------------------------------
// Although the RM7000 is really a 64 bit CPU, we have defined
// target_register_t elsewhere to be 32-bits because we only support
// 32-bit mode. Registers will still be sent to GDB as 64-bit, but that's
// not relevant for CYG_HAL_GDB_REG.
 
#define CYG_HAL_GDB_REG CYG_WORD32
 
//--------------------------------------------------------------------------
#endif // CYGONCE_HAL_VAR_ARCH_H
// End of var_arch.h
/v2_0/include/variant.inc
0,0 → 1,180
#ifndef CYGONCE_HAL_VARIANT_INC
#define CYGONCE_HAL_VARIANT_INC
##=============================================================================
##
## variant.inc
##
## RM7000 family assembler header file
##
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
##=============================================================================
#######DESCRIPTIONBEGIN####
##
## Author(s): nickg
## Contributors:nickg, jskov
## Date: 2000-05-10
## Purpose: RM7000 family definitions.
## Description: This file contains various definitions and macros that are
## useful for writing assembly code for the RM7000 CPU family.
## Usage:
## #include <cyg/hal/variant.inc>
## ...
##
##
######DESCRIPTIONEND####
##
##=============================================================================
 
#include <pkgconf/hal.h>
#include <cyg/hal/mips.inc>
#include <cyg/hal/platform.inc>
#include <cyg/hal/var_defs.inc>
 
##-----------------------------------------------------------------------------
## Define CPU variant for architecture HAL.
#define CYG_HAL_MIPS_RM7000
 
#------------------------------------------------------------------------------
# Set up initial value for config register. Sets endian mode and
# disables the cache on kseg0.
 
#if defined(CYGPKG_HAL_MIPS_MSBFIRST)
# define INITIAL_CONFIG0 0x00008002
#elif defined(CYGPKG_HAL_MIPS_LSBFIRST)
# define INITIAL_CONFIG0 0x00000002
#else
# error MIPS endianness not set by configuration
#endif
 
#------------------------------------------------------------------------------
# Set up initial value for FPU FCR31 register. We set the FS bit to flush
# denormalized results to zero and enable div-by-zero exceptions.
 
#ifndef CYG_HAL_MIPS_FCSR_INIT
#define CYG_HAL_MIPS_FCSR_INIT 0x01000400
#endif
 
#------------------------------------------------------------------------------
# Cache macros.
#ifndef CYGPKG_HAL_MIPS_CACHE_DEFINED
 
.macro hal_cache_init
 
mfc0 v0,config0 # disable Kseg0 caching in config0 register
nop
nop
la v1,0xfffffff8
and v0,v0,v1
ori v0,v0,2
mtc0 v0,config0
nop
nop
nop
 
.set mips3 # Set ISA to MIPS 3 to allow cache insns
 
# Now ensure the caches are invalidated. The caches are NOT cleared or
# invalidated on non-power-up resets and may come up in a random state
# on power-up. Hence they may contain stale or randomly bogus data.
# Here we use the index-store-tag cache operation to clear all the
# cache tags and states to zero. This will render them all invalid on
# the RM7000.
 
mtc0 zero,taglo
mtc0 zero,taghi
 
# D-cache:
la t0,CYGHWR_HAL_MIPS_RM7000_CACHE_SCRUB_BASE
ori t1,t0,HAL_DCACHE_SIZE
1:
cache 0x09,0x0000(t0)
cache 0x09,0x1000(t0)
cache 0x09,0x2000(t0)
cache 0x09,0x3000(t0)
 
# Clear area so Icache loads below will read valid
# instructions.
sw zero,0x00(t0)
sw zero,0x04(t0)
sw zero,0x08(t0)
sw zero,0x0c(t0)
sw zero,0x10(t0)
sw zero,0x14(t0)
sw zero,0x18(t0)
sw zero,0x1c(t0)
addi t0,t0,0x20
sub v0,t1,t0
bgez v0,1b
nop
 
# I-cache:
la a0,CYGHWR_HAL_MIPS_RM7000_CACHE_SCRUB_BASE
ori a1,a0,HAL_ICACHE_SIZE
1:
cache 0x08,0x0000(a0)
cache 0x08,0x1000(a0)
cache 0x08,0x2000(a0)
cache 0x08,0x3000(a0)
 
# Needs extra scrubbing due to RM7000A erratum #31
cache 0x14,0x0000(a0)
cache 0x14,0x1000(a0)
cache 0x14,0x2000(a0)
cache 0x14,0x3000(a0)
cache 0x08,0x0000(a0)
cache 0x08,0x1000(a0)
cache 0x08,0x2000(a0)
cache 0x08,0x3000(a0)
 
addi a0,a0,0x20
sub v0,a1,a0
bgez v0,1b
nop
 
.set mips0 # reset ISA to default
 
.endm
 
#define CYGPKG_HAL_MIPS_CACHE_DEFINED
 
#endif
 
#------------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_VARIANT_INC
# end of variant.inc
/v2_0/ChangeLog
0,0 → 1,106
2003-04-10 Nick Garnett <nickg@balti.calivar.com>
 
* src/mips_rm7000.ld:
Added libsupc++.a to GROUP() directive for GCC versions later than
3.0.
 
2003-04-09 Jonathan Larmour <jifl@eCosCentric.com>
 
* src/mips_rm7000.ld:
Fix .gnulinkonce.s -> .gnu.linkonce.s typo.
 
2001-08-09 Jonathan Larmour <jlarmour@redhat.com>
 
* include/var_intr.h: Move HAL_INTERRUPT_ interrupt controller
access macros here from Ocelot HAL.
 
2001-06-25 Jesper Skov <jskov@redhat.com>
 
* include/var_cache.h: Default definition for
CYGHWR_HAL_MIPS_RM7000_CACHE_SCRUB_BASE.
* src/var_mk_defs.c: export CYGHWR_HAL_MIPS_RM7000_CACHE_SCRUB_BASE.
* include/variant.inc: Use CYGHWR_HAL_MIPS_RM7000_CACHE_SCRUB_BASE.
 
2001-06-08 Jesper Skov <jskov@redhat.com>
 
* include/variant.inc: Scrub cache according to erratum #31.
 
* src/var_mk_defs.c: Added.
 
* cdl/hal_mips_rm7000.cdl: Make var_defs.inc.
 
2001-05-23 Jesper Skov <jskov@redhat.com>
 
* src/mips_rm7000.ld: Added .2ram handling.
 
2001-01-26 Jesper Skov <jskov@redhat.com>
 
* include/variant.inc: Remove hal_intc_decode macro since it's a
change needed in arch.
 
2001-01-25 Jesper Skov <jskov@redhat.com>
 
* include/variant.inc: Added hal_intc_decode macro which masks the
cause register with the status register. Works around what would
appear to be a HW bug.
2001-01-19 Jesper Skov <jskov@redhat.com>
 
* src/var_misc.c (hal_variant_init): Enable caches.
 
* include/variant.inc: Fixed typos in icache clear code.
 
2001-01-10 Jesper Skov <jskov@redhat.com>
 
* cdl/hal_mips_rm7000.cdl: Fix typo.
 
2000-12-07 Jesper Skov <jskov@redhat.com>
 
* src/var_misc.c (hal_variant_init): Disable caches until flash
stuff is working.
 
2000-12-06 Jesper Skov <jskov@redhat.com>
 
* src/mips_rm7000.ld: Include extras.o regardless of CYGPKG_IO
presence.
 
* src/var_misc.c: Enable caches.
 
2000-11-30 Jesper Skov <jskov@redhat.com>
 
* Cloned from hal/mips/tx49
 
//===========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//===========================================================================
/v2_0/src/var_mk_defs.c
0,0 → 1,90
//==========================================================================
//
// var_mk_defs.c
//
// HAL (variant) "make defs" program
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): gthomas
// Contributors: gthomas, jskov
// Date: 2001-06-08
// Purpose: Variant dependent definition generator
// Description: This file contains code that can be compiled by the target
// compiler and used to generate machine specific definitions
// suitable for use in assembly code.
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/hal/hal_arch.h> // HAL header
#include <cyg/hal/hal_intr.h> // HAL header
#include <cyg/hal/hal_cache.h> // HAL header
#ifdef CYGPKG_KERNEL
# include <pkgconf/kernel.h>
# include <cyg/kernel/instrmnt.h>
#endif
 
/*
* This program is used to generate definitions needed by
* assembly language modules.
*
* This technique was first used in the OSF Mach kernel code:
* generate asm statements containing #defines,
* compile this file to assembler, and then extract the
* #defines from the assembly-language output.
*/
 
#define DEFINE(sym, val) \
asm volatile("\n\t.equ\t" #sym ",%0" : : "i" (val))
 
int
main(void)
{
// Cache stuff
DEFINE(HAL_DCACHE_SIZE, HAL_DCACHE_SIZE);
DEFINE(HAL_ICACHE_SIZE, HAL_ICACHE_SIZE);
DEFINE(CYGHWR_HAL_MIPS_RM7000_CACHE_SCRUB_BASE, CYGHWR_HAL_MIPS_RM7000_CACHE_SCRUB_BASE);
 
return 0;
}
 
//--------------------------------------------------------------------------
// EOF var_mk_defs.c
/v2_0/src/var_misc.c
0,0 → 1,80
//==========================================================================
//
// var_misc.c
//
// HAL implementation miscellaneous functions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors: nickg, jlarmour
// Date: 1999-01-21
// Purpose: HAL miscellaneous functions
// Description: This file contains miscellaneous functions provided by the
// HAL.
//
//####DESCRIPTIONEND####
//
//========================================================================*/
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h> // Base types
#include <cyg/infra/cyg_trac.h> // tracing macros
#include <cyg/infra/cyg_ass.h> // assertion macros
 
#include <cyg/hal/hal_intr.h>
#include <cyg/hal/hal_cache.h>
 
/*------------------------------------------------------------------------*/
// Array which stores the configured priority levels for the configured
// interrupts.
 
volatile CYG_BYTE hal_interrupt_level[CYGNUM_HAL_ISR_COUNT];
 
/*------------------------------------------------------------------------*/
 
void hal_variant_init(void)
{
// The RM7000 only has an enable that works on both caches. So we
// only need to enable one of them for both to work.
//HAL_DCACHE_ENABLE();
HAL_ICACHE_ENABLE();
}
 
/*------------------------------------------------------------------------*/
/* End of var_misc.c */
/v2_0/src/variant.S
0,0 → 1,57
##=============================================================================
##
## variant.S
##
## MIPS RM7000 variant code
##
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
##=============================================================================
#######DESCRIPTIONBEGIN####
##
## Author(s): nickg
## Contributors:nickg
## Date: 2000-05-15
## Purpose: MIPS RM7000 variant code
## Description: Variant specific code for RM7000 CPU.
##
######DESCRIPTIONEND####
##
##=============================================================================
 
# Nothing at the moment.
##-----------------------------------------------------------------------------
## end of variant.S
/v2_0/src/mips_rm7000.ld
0,0 → 1,373
//===========================================================================
//
// MLT linker script for MIPS RM7000
//
//===========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//===========================================================================
 
#include <pkgconf/system.h>
 
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips",
"elf32-littlemips")
/* The preprocessor defines mips, but we know we're mips :-) */
#undef mips
OUTPUT_ARCH(mips:5000)
 
STARTUP(vectors.o)
ENTRY(reset_vector)
#if defined(EXTRAS)
INPUT(extras.o)
#endif
#if (__GNUC__ >= 3)
GROUP(libtarget.a libgcc.a libsupc++.a)
#else
GROUP(libtarget.a libgcc.a)
#endif
 
/* FIXME: The MLT should pass in the required alignment since it must be
* the same as the VMA's alignment. As a result of this bug, all the
* ROM mlt files have alignment 8, when some should have alignment 4
* (902557-CR)
*/
#define ALIGN_LMA 8
#define FOLLOWING(_section_) AT ((LOADADDR (_section_) + SIZEOF (_section_) + ALIGN_LMA - 1) & ~ (ALIGN_LMA - 1))
#define LMA_EQ_VMA
#define FORCE_OUTPUT . = .
 
#define SECTIONS_BEGIN
 
#if defined(CYG_HAL_STARTUP_RAM)
 
/* this version for RAM startup */
#define SECTION_rom_vectors(_region_, _vma_, _lma_) \
.rom_vectors _vma_ : _lma_ \
{ KEEP (*(.utlb_vector)) \
. = ALIGN(0x80); KEEP(*(.other_vector)) \
/* debug and reset vector not used in RAM version */ \
KEEP(*(.debug_vector)) \
KEEP (*(.reset_vector)) } \
> _region_
 
#elif defined(CYG_HAL_STARTUP_ROM)
 
/* this version for ROM startup */
#define SECTION_rom_vectors(_region_, _vma_, _lma_) \
.rom_vectors _vma_ : _lma_ \
{ KEEP (*(.reset_vector)) \
. = ALIGN(0x100); KEEP (*(.utlb_vector)) \
. = ALIGN(0x80); KEEP(*(.other_vector)) \
. = ALIGN(0x100); KEEP(*(.debug_vector)) } \
> _region_
 
#endif /* ROM startup version of ROM vectors */
 
#define SECTION_ROMISC(_region_, _vma_, _lma_) \
.interp _vma_ : _lma_ { *(.interp) } > _region_ \
.hash : FOLLOWING(.interp) { *(.hash) } > _region_ \
.dynsym : FOLLOWING(.hash) { *(.dynsym) } > _region_ \
.dynstr : FOLLOWING(.dynsym) { *(.dynstr) } > _region_ \
.gnu.version : FOLLOWING(.dynstr) { *(.gnu.version) } > _region_ \
.gnu.version_d : FOLLOWING(.gnu.version) { *(.gnu.version_d) } > _region_ \
.gnu.version_r : FOLLOWING(.gnu.version_d) { *(.gnu.version_r) } > _region_ \
.plt : FOLLOWING(.gnu.version_r) { *(.plt) } > _region_
 
#define SECTION_RELOCS(_region_, _vma_, _lma_) \
.rel.text : \
{ \
*(.rel.text) \
*(.rel.text.*) \
*(.rel.gnu.linkonce.t*) \
} > _region_ \
.rela.text : \
{ \
*(.rela.text) \
*(.rela.text.*) \
*(.rela.gnu.linkonce.t*) \
} > _region_ \
.rel.data : \
{ \
*(.rel.data) \
*(.rel.data.*) \
*(.rel.gnu.linkonce.d*) \
} > _region_ \
.rela.data : \
{ \
*(.rela.data) \
*(.rela.data.*) \
*(.rela.gnu.linkonce.d*) \
} > _region_ \
.rel.rodata : \
{ \
*(.rel.rodata) \
*(.rel.rodata.*) \
*(.rel.gnu.linkonce.r*) \
} > _region_ \
.rela.rodata : \
{ \
*(.rela.rodata) \
*(.rela.rodata.*) \
*(.rela.gnu.linkonce.r*) \
} > _region_ \
.rel.got : { *(.rel.got) } > _region_ \
.rela.got : { *(.rela.got) } > _region_ \
.rel.ctors : { *(.rel.ctors) } > _region_ \
.rela.ctors : { *(.rela.ctors) } > _region_ \
.rel.dtors : { *(.rel.dtors) } > _region_ \
.rela.dtors : { *(.rela.dtors) } > _region_ \
.rel.init : { *(.rel.init) } > _region_ \
.rela.init : { *(.rela.init) } > _region_ \
.rel.fini : { *(.rel.fini) } > _region_ \
.rela.fini : { *(.rela.fini) } > _region_ \
.rel.bss : { *(.rel.bss) } > _region_ \
.rela.bss : { *(.rela.bss) } > _region_ \
.rel.plt : { *(.rel.plt) } > _region_ \
.rela.plt : { *(.rela.plt) } > _region_ \
.rel.dyn : { *(.rel.dyn) } > _region_
 
#define SECTION_init(_region_, _vma_, _lma_) \
.init _vma_ : _lma_ \
{ \
FORCE_OUTPUT; KEEP (*(.init)) \
} > _region_ =0
 
#define SECTION_text(_region_, _vma_, _lma_) \
.text _vma_ : _lma_ \
{ \
_stext = .; _ftext = . ; \
*(.text) \
*(.text.*) \
*(.stub) \
*(.gnu.warning) \
*(.gnu.linkonce.t*) \
*(.mips16.fn.*) *(.mips16.call.*) \
} > _region_ =0 \
_etext = .; PROVIDE (etext = .);
 
#define SECTION_fini(_region_, _vma_, _lma_) \
.fini _vma_ : _lma_ \
{ \
FORCE_OUTPUT; KEEP (*(.fini)) \
} > _region_ =0
 
#define SECTION_rodata(_region_, _vma_, _lma_) \
.rodata _vma_ : _lma_ \
{ \
FORCE_OUTPUT; *(.rodata) *(.rodata.*) *(.gnu.linkonce.r*) \
} > _region_
 
#define SECTION_rodata1(_region_, _vma_, _lma_) \
.rodata1 _vma_ : _lma_ \
{ \
FORCE_OUTPUT; *(.rodata1) *(.rodata1.*) \
} > _region_
 
#define SECTION_vsr_table(_region_, _vma_, _lma_) \
.vsr_table _vma_ : _lma_ \
{ \
FORCE_OUTPUT; *(.vsr_table) \
} > _region_
 
#define SECTION_data(_region_, _vma_, _lma_) \
.data _vma_ : _lma_ \
{ \
__ram_data_start = ABSOLUTE (.); _fdata = . ; \
*(.data) *(.data.*) *(.gnu.linkonce.d*) \
*( .2ram.*) \
. = ALIGN (8); \
SORT(CONSTRUCTORS) \
} > _region_ \
__rom_data_start = LOADADDR(.data);
 
#define SECTION_data1(_region_, _vma_, _lma_) \
.data1 _vma_ : _lma_ \
{ \
FORCE_OUTPUT; *(.data1) *(.data1.*) \
} > _region_
 
#define SECTION_eh_frame(_region_, _vma_, _lma_) \
.eh_frame _vma_ : _lma_ \
{ \
FORCE_OUTPUT; *(.eh_frame) \
} > _region_
 
#define SECTION_gcc_except_table(_region_, _vma_, _lma_) \
.gcc_except_table _vma_ : _lma_ \
{ \
FORCE_OUTPUT; *(.gcc_except_table) \
} > _region_
 
 
/* FIXME: We shouldn't need to define __CTOR_LIST__/__CTOR_END__
and __DTOR_LIST__/__DTOR_END__ except by the PROVIDE lines.
However this doesn't work for old (99r1-era) toolchains, so
leave it for now. */
 
/* The KEEP(*_ctors.o(.ctors)) rule is included to prevent
constructors from libgcc.a from turning up in the image.
They are NULL anyway. */
 
#define SECTION_ctors(_region_, _vma_, _lma_) \
.ctors _vma_ : _lma_ \
{ \
FORCE_OUTPUT; \
KEEP (*crtbegin.o(.ctors)) \
KEEP (*_ctors.o(.ctors)) \
__CTOR_LIST__ = .; \
PROVIDE (__CTOR_LIST__ = .); \
KEEP (*(.ctors)); \
KEEP (*(SORT(.ctors.*))) \
__CTOR_END__ = .; \
PROVIDE (__CTOR_END__ = .); \
} > _region_
 
#define SECTION_dtors(_region_, _vma_, _lma_) \
.dtors _vma_ : _lma_ \
{ \
FORCE_OUTPUT; \
KEEP (*crtbegin.o(.dtors)) \
__DTOR_LIST__ = .; \
PROVIDE (__DTOR_LIST__ = .); \
KEEP (*(SORT(.dtors.*))) \
__DTOR_END__ = .; \
KEEP (*(.dtors)); \
PROVIDE (__DTOR_END__ = .); \
} > _region_
 
#define SECTION_devtab(_region_, _vma_, _lma_) \
.devtab _vma_ : _lma_ \
{ \
FORCE_OUTPUT; \
KEEP(*( SORT (.ecos.table.*))) ; \
} > _region_
 
#define SECTION_got(_region_, _vma_, _lma_) \
_gp = ALIGN(16) + 0x7ff0; \
.got _vma_ : _lma_ \
{ \
FORCE_OUTPUT; *(.got.plt) *(.got) \
} > _region_
 
#define SECTION_dynamic(_region_, _vma_, _lma_) \
.dynamic _vma_ : _lma_ \
{ \
FORCE_OUTPUT; *(.dynamic) \
} > _region_
 
/* We want the small data sections together, so single-instruction offsets
can access them all, and initialized data all before uninitialized, so
we can shorten the on-disk segment size. */
 
#define SECTION_sdata(_region_, _vma_, _lma_) \
.sdata _vma_ : _lma_ \
{ \
FORCE_OUTPUT; *(.sdata) *(.sdata.*) *(.gnu.linkonce.s*) \
} > _region_
 
#define SECTION_lit8(_region_, _vma_, _lma_) \
.lit8 _vma_ : _lma_ \
{ \
FORCE_OUTPUT; *(.lit8) \
} > _region_
 
#define SECTION_lit4(_region_, _vma_, _lma_) \
.lit4 : FOLLOWING(.lit8) \
{ \
FORCE_OUTPUT; *(.lit4) \
} > _region_ \
__ram_data_end = .; _edata = . ; \
PROVIDE (edata = .);
 
#define SECTION_sbss(_region_, _vma_, _lma_) \
__bss_start = .; _fbss = .; \
.sbss _vma_ : _lma_ \
{ \
FORCE_OUTPUT; *(.dynsbss) *(.sbss) *(.sbss.*) *(.scommon) \
} > _region_
 
#define SECTION_bss(_region_, _vma_, _lma_) \
.bss _vma_ : _lma_ \
{ \
*(.dynbss) *(.bss) *(.bss.*) *(COMMON) \
} > _region_ \
__bss_end = .;
 
/* The /DISCARD/ section ensures that the output will not contain a
* .mdebug section as it confuses GDB. This is a workaround for CR 100804.
*/
 
#define SECTIONS_END . = ALIGN(4); _end = .; PROVIDE (end = .); \
/* Stabs debugging sections. */ \
.stab 0 : { *(.stab) } \
.stabstr 0 : { *(.stabstr) } \
.stab.excl 0 : { *(.stab.excl) } \
.stab.exclstr 0 : { *(.stab.exclstr) } \
.stab.index 0 : { *(.stab.index) } \
.stab.indexstr 0 : { *(.stab.indexstr) } \
.comment 0 : { *(.comment) } \
/* DWARF debug sections. \
Symbols in the DWARF debugging sections are relative to \
the beginning of the section so we begin them at 0. */ \
/* DWARF 1 */ \
.debug 0 : { *(.debug) } \
.line 0 : { *(.line) } \
/* GNU DWARF 1 extensions */ \
.debug_srcinfo 0 : { *(.debug_srcinfo) } \
.debug_sfnames 0 : { *(.debug_sfnames) } \
/* DWARF 1.1 and DWARF 2 */ \
.debug_aranges 0 : { *(.debug_aranges) } \
.debug_pubnames 0 : { *(.debug_pubnames) } \
/* DWARF 2 */ \
.debug_info 0 : { *(.debug_info) } \
.debug_abbrev 0 : { *(.debug_abbrev) } \
.debug_line 0 : { *(.debug_line) } \
.debug_frame 0 : { *(.debug_frame) } \
.debug_str 0 : { *(.debug_str) } \
.debug_loc 0 : { *(.debug_loc) } \
.debug_macinfo 0 : { *(.debug_macinfo) } \
/* SGI/MIPS DWARF 2 extensions */ \
.debug_weaknames 0 : { *(.debug_weaknames) } \
.debug_funcnames 0 : { *(.debug_funcnames) } \
.debug_typenames 0 : { *(.debug_typenames) } \
.debug_varnames 0 : { *(.debug_varnames) } \
/* These must appear regardless of . */ \
.gptab.sdata : { *(.gptab.data) *(.gptab.sdata) } \
.gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) } \
/DISCARD/ 0 : { *(.mdebug) }
 
#include CYGHWR_MEMORY_LAYOUT_LDI
 
// 0-0x200 reserved for vectors
hal_vsr_table = 0x80000200;
hal_virtual_vector_table = 0x80000300;

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