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    /openrisc/trunk/rtos/ecos-2.0/packages/hal/mips/rm7000
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Rev 27 → Rev 174

/ocelot/v2_0/cdl/hal_mips_rm7000_ocelot.cdl
0,0 → 1,397
# ====================================================================
#
# hal_mips_rm7000_ocelot.cdl
#
# RM7000/OCELOT board HAL package configuration data
#
# ====================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
# ====================================================================
######DESCRIPTIONBEGIN####
#
# Author(s): jskov
# Original data: bartv
# Contributors:
# Date: 2000-05-15
#
#####DESCRIPTIONEND####
#
# ====================================================================
 
cdl_package CYGPKG_HAL_MIPS_RM7000_OCELOT {
display "QED Ocelot board"
parent CYGPKG_HAL_MIPS
requires CYGPKG_HAL_MIPS_RM7000
define_header hal_mips_rm7000_ocelot.h
include_dir cyg/hal
description "
The Ocelot HAL package should be used when targetting the
actual hardware."
 
compile platform.S plf_misc.c plf_stub.c ns16552.c
 
implements CYGINT_HAL_DEBUG_GDB_STUBS
implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
 
define_proc {
puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_mips_rm7000.h>"
puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_mips_rm7000_ocelot.h>"
 
puts $::cdl_header "#define CYGHWR_HAL_MIPS_WARMSTART_COLDSTART"
}
 
cdl_component CYG_HAL_STARTUP {
display "Startup type"
flavor data
legal_values {"RAM" "ROM"}
default_value {"RAM"}
no_define
define -file system.h CYG_HAL_STARTUP
description "
When targetting the Ocelot board it is possible to build
the system for either RAM bootstrap or ROM bootstrap. RAM
bootstrap generally requires that the board
is equipped with ROMs containing a suitable ROM monitor or
equivalent software that allows GDB to download the eCos
application on to the board. The ROM bootstrap typically
requires that the eCos application be blown into EPROMs or
equivalent technology."
}
 
cdl_option CYGHWR_HAL_MIPS_RM7000_OCELOT_ENDIAN {
display "Board endian mode"
flavor data
legal_values {"big" "little"}
default_value {"big"}
no_define
description "
The Ocelot platform can be used in either big or
little endian mode. This option select which. The board
will also need to be reconfigured if this option changes."
}
cdl_option CYGHWR_HAL_MIPS_RM7000_OCELOT_ENDIAN_SET {
display "Communicate endian setting to variant HAL"
active_if {CYGHWR_HAL_MIPS_RM7000_OCELOT_ENDIAN == "big"}
calculated 1
implements CYGINT_HAL_MIPS_MSBFIRST
}
 
cdl_option CYGHWR_HAL_MIPS_RM7000_OCELOT_PCI_MEM_MAP_BASE {
display "Base of memory accessible via PCI space"
flavor data
legal_values { 0xf200000 0xf300000 0xf400000 0xf500000
0xf600000 0xf700000 0xf800000 0xf900000
0xfa00000 0xfb00000 0xfc00000 0xfd00000
0xfe00000 0xff00000
}
default_value 0x0ff00000
active_if CYGPKG_IO_PCI
description "
This option determines the base of the Ocelot memory which
can be accessed via the PCI bus. The default is to allow
access to the upper 1MB of a 256MB system.
NB: We advise *against* changing this option.
The value MUST match the base address of the section
'pci_window' in the Memory Layout Tool else this memory area
will be consumed by the malloc heap.
This error condition can only be detected at runtime in
current versions of the configuration tools.
CLI users can edit include/pkgconf/mlt_mips_rm7000_ocelot_*.h
and include/pkgconf/mlt_mips_rm7000_ocelot_*.ldi to achieve the
same effects as moving that region in the MLT."
}
 
cdl_option CYGHWR_HAL_MIPS_RM7000_OCELOT_PCI_MEM_MAP_SIZE {
display "Size of memory accessible via PCI space"
flavor data
legal_values { 0x100000 0x200000 0x300000 0x400000
0x500000 0x600000 0x700000 0x800000
}
default_value 0x00100000
active_if CYGPKG_IO_PCI
description "
This option determines the size of the Ocelot memory which
can be accessed via the PCI bus. The default is to allow
access to the upper 1MB of a 256MB system.
NB: We advise *against* changing this option.
The value MUST match the size of the section 'pci_window' in the
Memory Layout Tool else this memory area will be consumed by the
malloc heap.
Further caveats in the PCI base option."
}
 
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
display "Number of communication channels on the board"
flavor data
calculated 2
}
 
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
display "Debug serial port"
active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
flavor data
legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
default_value 0
description "
The Ocelot board has two separate serial ports. This option
chooses which of these ports will be used to connect to a host
running GDB."
}
 
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
display "Diagnostic serial port"
active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
flavor data
legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
default_value 0
description "
The Ocelot board has two separate serial ports. This option
chooses which of these ports will be used for diagnostic output."
}
 
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CHANNELS_DEFAULT_BAUD {
display "Default baud rate used for serial ports"
flavor data
legal_values 9600 19200 38400 115200
default_value 38400
description "
This option selects the baud rate used for the serial ports."
}
 
# The "-o file" is a workaround for CR100958 - without it the
# output file would end up in the source directory under CygWin.
# n.b. grep does not behave itself under win32
make -priority 1 {
<PREFIX>/include/cyg/hal/plf_defs.inc : <PACKAGE>/src/plf_mk_defs.c
$(CC) $(CFLAGS) $(INCLUDE_PATH) -Wp,-MD,plf_defs.tmp -o plf_mk_defs.tmp -S $<
fgrep .equ plf_mk_defs.tmp | sed s/#// > $@
@echo $@ ": \\" > $(notdir $@).deps
@tail +2 plf_defs.tmp >> $(notdir $@).deps
@echo >> $(notdir $@).deps
@rm plf_defs.tmp plf_mk_defs.tmp
}
 
cdl_option CYGHWR_HAL_MIPS_RM7000_CPU_CLOCK {
display "CPU clock speed"
flavor data
legal_values { 300000000 400000000 500000000 600000000 }
default_value 300000000
description "
The CPU clock speed in Hz."
}
 
# Real-time clock/counter specifics
cdl_component CYGNUM_HAL_RTC_CONSTANTS {
display "Real-time clock constants."
flavor none
cdl_option CYGNUM_HAL_RTC_NUMERATOR {
display "Real-time clock numerator"
flavor data
calculated 1000000000
}
cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
display "Real-time clock denominator"
flavor data
calculated 100
}
cdl_option CYGNUM_HAL_RTC_PERIOD {
display "Real-time clock period"
flavor data
calculated { (CYGHWR_HAL_MIPS_RM7000_CPU_CLOCK / 2) / CYGNUM_HAL_RTC_DENOMINATOR }
description "
The count and compare registers of the RM7000 are used
to drive the eCos kernel RTC. The count register
increments at half the CPU clock speed."
}
}
 
cdl_component CYGBLD_GLOBAL_OPTIONS {
display "Global build options"
flavor none
parent CYGPKG_NONE
description "
Global build options including control over
compiler flags, linker flags and choice of toolchain."
 
 
cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
display "Global command prefix"
flavor data
no_define
default_value { "mipsisa32-elf" }
# default_value { "mips-tx49-elf" }
# default_value { "mips64vr5000-elf" }
# default_value { "mips64vr4300-elf" }
description "
This option specifies the command prefix used when
invoking the build tools."
}
 
cdl_option CYGBLD_GLOBAL_CFLAGS {
display "Global compiler flags"
flavor data
no_define
# -mabi=eabi -mips2
default_value { CYGPKG_HAL_MIPS_MSBFIRST ? "-G0 -mips2 -EB -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" : "-G0 -mips2 -EL -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
description "
This option controls the global compiler flags which
are used to compile all packages by
default. Individual packages may define
options which override these global flags."
}
 
cdl_option CYGBLD_GLOBAL_LDFLAGS {
display "Global linker flags"
flavor data
no_define
# -mabi=eabi -mips2
default_value { CYGPKG_HAL_MIPS_MSBFIRST ? "-G0 -g -mips32 -EB -nostdlib -Wl,--gc-sections -Wl,-static" : "-g -mips2 -EL -mabi=eabi -nostdlib -Wl,--gc-sections -Wl,-static" }
description "
This option controls the global linker flags. Individual
packages may define options which override these global flags."
}
 
cdl_option CYGBLD_BUILD_GDB_STUBS {
display "Build GDB stub ROM image"
default_value 0
requires { CYG_HAL_STARTUP == "ROM" }
requires CYGSEM_HAL_ROM_MONITOR
requires CYGBLD_BUILD_COMMON_GDB_STUBS
requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
requires ! CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
no_define
description "
This option enables the building of the GDB stubs for the
board. The common HAL controls takes care of most of the
build process, but the final conversion from ELF image to
SREC data is handled by the platform CDL, allowing
relocation of the data if necessary."
 
make -priority 320 {
<PREFIX>/bin/gdb_module.srec : <PREFIX>/bin/gdb_module.img
}
}
}
 
cdl_component CYGHWR_MEMORY_LAYOUT {
display "Memory layout"
flavor data
no_define
calculated { CYG_HAL_STARTUP == "RAM" ? "mips_rm7000_ocelot_ram" : \
"mips_rm7000_ocelot_rom" }
 
cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
display "Memory layout linker script fragment"
flavor data
no_define
define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_mips_rm7000_ocelot_ram.ldi>" : \
"<pkgconf/mlt_mips_rm7000_ocelot_rom.ldi>" }
}
 
cdl_option CYGHWR_MEMORY_LAYOUT_H {
display "Memory layout header file"
flavor data
no_define
define -file system.h CYGHWR_MEMORY_LAYOUT_H
calculated { CYG_HAL_STARTUP == "RAM" ? "<pkgconf/mlt_mips_rm7000_ocelot_ram.h>" : \
"<pkgconf/mlt_mips_rm7000_ocelot_rom.h>" }
}
}
 
cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
display "Work with a ROM monitor"
flavor booldata
legal_values { "GDB_stubs" }
default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
parent CYGPKG_HAL_ROM_MONITOR
requires { CYG_HAL_STARTUP == "RAM" }
description "
Support can be enabled for GDB stubs.
This support changes various eCos semantics such as the encoding
of diagnostic output, or the overriding of hardware interrupt
vectors.
\"GDB_stubs\" provides support when GDB stubs are
included in the ROM monitor or boot ROM, allowing debugging
via GDB."
}
 
cdl_option CYGSEM_HAL_ROM_MONITOR {
display "Behave as a ROM monitor"
flavor bool
default_value 0
parent CYGPKG_HAL_ROM_MONITOR
requires { CYG_HAL_STARTUP == "ROM" }
description "
Enable this option if this program is to be used as a ROM monitor,
i.e. applications will be loaded into RAM on the board, and this
ROM monitor may process exceptions or interrupts generated from the
application. This enables features such as utilizing a separate
interrupt stack when exceptions are generated."
}
 
cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
display "Redboot HAL options"
flavor none
no_define
parent CYGPKG_REDBOOT
active_if CYGPKG_REDBOOT
description "
This option lists the target's requirements for a valid Redboot
configuration."
 
cdl_option CYGBLD_BUILD_REDBOOT_BIN {
display "Build Redboot ROM binary image"
active_if CYGBLD_BUILD_REDBOOT
default_value 1
no_define
description "This option enables the conversion of the Redboot ELF
image to the various relocated SREC images needed
for flash updating."
 
make -priority 325 {
<PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
$(OBJCOPY) --strip-unneeded $< $(@:.bin=.img)
$(OBJCOPY) -O srec $(@:.bin=.img) $(@:.bin=.srec)
$(OBJCOPY) -O binary $(@:.bin=.img) $@
}
}
}
}
/ocelot/v2_0/include/plf_intr.h
0,0 → 1,137
#ifndef CYGONCE_HAL_PLF_INTR_H
#define CYGONCE_HAL_PLF_INTR_H
 
//==========================================================================
//
// plf_intr.h
//
// Ocelot Interrupt and clock support
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
// Contributors: jskov, nickg
// Date: 2000-05-09
// Purpose: Define Interrupt support
// Description: The macros defined here provide the HAL APIs for handling
// interrupts and the clock for the REF4955 board.
//
// Usage:
// #include <cyg/hal/plf_intr.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h>
 
//--------------------------------------------------------------------------
// Interrupt vectors.
 
#ifndef CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
 
// The first 10 correspond to the interrupt lines in the status/cause regs
#define CYGNUM_HAL_INTERRUPT_ETH0 0
#define CYGNUM_HAL_INTERRUPT_ETH1 1
#define CYGNUM_HAL_INTERRUPT_UART1 2
#define CYGNUM_HAL_INTERRUPT_21555 3
#define CYGNUM_HAL_INTERRUPT_GALILEO 4
#define CYGNUM_HAL_INTERRUPT_COMPARE 5
#define CYGNUM_HAL_INTERRUPT_PMC1 6
#define CYGNUM_HAL_INTERRUPT_PMC2 7
#define CYGNUM_HAL_INTERRUPT_CPCI 8
#define CYGNUM_HAL_INTERRUPT_UART2 9
 
// PCI interrupts are hardwired for the devices connected to the bus
#define CYGNUM_HAL_INTERRUPT_PCI_INTA CYGNUM_HAL_INTERRUPT_GALILEO
#define CYGNUM_HAL_INTERRUPT_PCI_INTB CYGNUM_HAL_INTERRUPT_ETH0
#define CYGNUM_HAL_INTERRUPT_PCI_INTC CYGNUM_HAL_INTERRUPT_GALILEO
#define CYGNUM_HAL_INTERRUPT_PCI_INTD CYGNUM_HAL_INTERRUPT_GALILEO
 
// Min/Max ISR numbers and how many there are
#define CYGNUM_HAL_ISR_MIN CYGNUM_HAL_INTERRUPT_ETH0
#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_UART2
#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX - CYGNUM_HAL_ISR_MIN + 1)
 
// The vector used by the Real time clock
#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_COMPARE
 
#define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
 
#endif
 
//--------------------------------------------------------------------------
// Interrupt controller information
 
// V320USC
#define CYGARC_REG_INT_STAT 0xb80000ec
 
#define CYGARC_REG_INT_CFG0 0xb80000e0
#define CYGARC_REG_INT_CFG1 0xb80000e4
#define CYGARC_REG_INT_CFG2 0xb80000e8
#define CYGARC_REG_INT_CFG3 0xb8000158
 
#define CYGARC_REG_INT_CFG_INT0 0x00000100
#define CYGARC_REG_INT_CFG_INT1 0x00000200
#define CYGARC_REG_INT_CFG_INT2 0x00000400
#define CYGARC_REG_INT_CFG_INT3 0x00000800
 
 
// FPGA
#define CYGARC_REG_PCI_STAT 0xb5300000
#define CYGARC_REG_PCI_MASK 0xb5300030
 
#define CYGARC_REG_IO_STAT 0xb5300010
#define CYGARC_REG_IO_MASK 0xb5300040
 
 
//----------------------------------------------------------------------------
// Reset.
// Uses Secondary Reset Bit in 21555. Don't know where it is mapped though.
#define CYGARC_REG_BOARD_RESET 0x????????
 
#define HAL_PLATFORM_RESET() /* HAL_WRITE_UINT8(CYGARC_REG_BOARD_RESET,1) */
 
#define HAL_PLATFORM_RESET_ENTRY 0xbfc00000
 
//--------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_PLF_INTR_H
// End of plf_intr.h
/ocelot/v2_0/include/plf_stub.h
0,0 → 1,85
#ifndef CYGONCE_HAL_PLF_STUB_H
#define CYGONCE_HAL_PLF_STUB_H
 
//=============================================================================
//
// plf_stub.h
//
// Platform header for GDB stub support.
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
// Contributors:jskov
// Date: 2000-05-15
// Purpose: Platform HAL stub support for Ocelot board.
// Usage: #include <cyg/hal/plf_stub.h>
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
 
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 
#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM
 
#include <cyg/hal/mips-stub.h> // architecture stub support
 
//----------------------------------------------------------------------------
// Define some platform specific communication details. This is mostly
// handled by hal_if now, but we need to make sure the comms tables are
// properly initialized.
 
externC void cyg_hal_plf_comms_init(void);
 
#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init()
 
#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud))
#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0
#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT
 
//----------------------------------------------------------------------------
// Stub initializer.
extern void hal_plf_stub_init( void );
#define HAL_STUB_PLATFORM_INIT() hal_plf_stub_init();
 
#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
//-----------------------------------------------------------------------------
#endif // CYGONCE_HAL_PLF_STUB_H
// End of plf_stub.h
/ocelot/v2_0/include/pkgconf/mlt_mips_rm7000_ocelot_rom.h
0,0 → 1,40
// eCos memory layout - Fri Jan 19 11:28:42 2001
 
// This is a generated file - do not edit
 
#ifndef __ASSEMBLER__
#include <cyg/infra/cyg_type.h>
#include <stddef.h>
 
#endif
#define CYGMEM_REGION_ram (0x80000000)
#define CYGMEM_REGION_ram_SIZE (0x10000000)
#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
#define CYGMEM_REGION_rom (0xbfc00000)
#define CYGMEM_REGION_rom_SIZE (0x80000)
#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__reserved_vectors) [];
#endif
#define CYGMEM_SECTION_reserved_vectors (CYG_LABEL_NAME (__reserved_vectors))
#define CYGMEM_SECTION_reserved_vectors_SIZE (0x200)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__reserved_vsr_table) [];
#endif
#define CYGMEM_SECTION_reserved_vsr_table (CYG_LABEL_NAME (__reserved_vsr_table))
#define CYGMEM_SECTION_reserved_vsr_table_SIZE (0x100)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__reserved_virtual_table) [];
#endif
#define CYGMEM_SECTION_reserved_virtual_table (CYG_LABEL_NAME (__reserved_virtual_table))
#define CYGMEM_SECTION_reserved_virtual_table_SIZE (0x100)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__heap1) [];
#endif
#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
#define CYGMEM_SECTION_heap1_SIZE (0x8ff00000 - (size_t) CYG_LABEL_NAME (__heap1))
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__pci_window) [];
#endif
#define CYGMEM_SECTION_pci_window (CYG_LABEL_NAME (__pci_window))
#define CYGMEM_SECTION_pci_window_SIZE (0x100000)
/ocelot/v2_0/include/pkgconf/mlt_mips_rm7000_ocelot_rom.ldi
0,0 → 1,44
// eCos memory layout - Fri Jan 19 11:28:42 2001
 
// This is a generated file - do not edit
 
#include <cyg/infra/cyg_type.inc>
 
MEMORY
{
ram : ORIGIN = 0x80000000, LENGTH = 0x10000000
rom : ORIGIN = 0xbfc00000, LENGTH = 0x80000
}
 
SECTIONS
{
SECTIONS_BEGIN
SECTION_rom_vectors (rom, 0xbfc00000, LMA_EQ_VMA)
SECTION_ROMISC (rom, ALIGN (0x8), LMA_EQ_VMA)
SECTION_RELOCS (rom, ALIGN (0x8), LMA_EQ_VMA)
SECTION_init (rom, ALIGN (0x8), LMA_EQ_VMA)
SECTION_text (rom, ALIGN (0x8), LMA_EQ_VMA)
SECTION_fini (rom, ALIGN (0x8), LMA_EQ_VMA)
SECTION_rodata (rom, ALIGN (0x8), LMA_EQ_VMA)
SECTION_rodata1 (rom, ALIGN (0x8), LMA_EQ_VMA)
CYG_LABEL_DEFN(__reserved_vectors) = 0x80000000; . = CYG_LABEL_DEFN(__reserved_vectors) + 0x200;
CYG_LABEL_DEFN(__reserved_vsr_table) = ALIGN (0x10); . = CYG_LABEL_DEFN(__reserved_vsr_table) + 0x100;
CYG_LABEL_DEFN(__reserved_virtual_table) = ALIGN (0x10); . = CYG_LABEL_DEFN(__reserved_virtual_table) + 0x100;
SECTION_data (ram, ALIGN (0x10), FOLLOWING (.rodata1))
SECTION_data1 (ram, ALIGN (0x8), FOLLOWING (.data))
SECTION_eh_frame (ram, ALIGN (0x8), FOLLOWING (.data1))
SECTION_gcc_except_table (ram, ALIGN (0x8), FOLLOWING (.eh_frame))
SECTION_ctors (ram, ALIGN (0x8), FOLLOWING (.gcc_except_table))
SECTION_dtors (ram, ALIGN (0x8), FOLLOWING (.ctors))
SECTION_devtab (ram, ALIGN (0x8), FOLLOWING (.dtors))
SECTION_got (ram, ALIGN (0x8), FOLLOWING (.devtab))
SECTION_dynamic (ram, ALIGN (0x8), FOLLOWING (.got))
SECTION_sdata (ram, ALIGN (0x8), FOLLOWING (.dynamic))
SECTION_lit8 (ram, ALIGN (0x8), FOLLOWING (.sdata))
SECTION_lit4 (ram, ALIGN (0x8), FOLLOWING (.lit8))
SECTION_sbss (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
CYG_LABEL_DEFN(__pci_window) = 0x8ff00000; . = CYG_LABEL_DEFN(__pci_window) + 0x100000;
SECTIONS_END
}
/ocelot/v2_0/include/pkgconf/mlt_mips_rm7000_ocelot_ram.h
0,0 → 1,42
// eCos memory layout - Fri Jan 19 11:27:35 2001
 
// This is a generated file - do not edit
 
#ifndef __ASSEMBLER__
#include <cyg/infra/cyg_type.h>
#include <stddef.h>
 
#endif
#define CYGMEM_REGION_ram (0x80000000)
#define CYGMEM_REGION_ram_SIZE (0x10000000)
#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__reserved_vectors) [];
#endif
#define CYGMEM_SECTION_reserved_vectors (CYG_LABEL_NAME (__reserved_vectors))
#define CYGMEM_SECTION_reserved_vectors_SIZE (0x200)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__reserved_vsr_table) [];
#endif
#define CYGMEM_SECTION_reserved_vsr_table (CYG_LABEL_NAME (__reserved_vsr_table))
#define CYGMEM_SECTION_reserved_vsr_table_SIZE (0x100)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__reserved_virtual_table) [];
#endif
#define CYGMEM_SECTION_reserved_virtual_table (CYG_LABEL_NAME (__reserved_virtual_table))
#define CYGMEM_SECTION_reserved_virtual_table_SIZE (0x100)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__reserved_for_rom) [];
#endif
#define CYGMEM_SECTION_reserved_for_rom (CYG_LABEL_NAME (__reserved_for_rom))
#define CYGMEM_SECTION_reserved_for_rom_SIZE (0x1fc00)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__heap1) [];
#endif
#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
#define CYGMEM_SECTION_heap1_SIZE (0x8ff00000 - (size_t) CYG_LABEL_NAME (__heap1))
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__pci_window) [];
#endif
#define CYGMEM_SECTION_pci_window (CYG_LABEL_NAME (__pci_window))
#define CYGMEM_SECTION_pci_window_SIZE (0x100000)
/ocelot/v2_0/include/pkgconf/mlt_mips_rm7000_ocelot_ram.ldi
0,0 → 1,44
// eCos memory layout - Fri Jan 19 11:27:35 2001
 
// This is a generated file - do not edit
 
#include <cyg/infra/cyg_type.inc>
 
MEMORY
{
ram : ORIGIN = 0x80000000, LENGTH = 0x10000000
}
 
SECTIONS
{
SECTIONS_BEGIN
CYG_LABEL_DEFN(__reserved_vectors) = 0x80000000; . = CYG_LABEL_DEFN(__reserved_vectors) + 0x200;
CYG_LABEL_DEFN(__reserved_vsr_table) = ALIGN (0x10); . = CYG_LABEL_DEFN(__reserved_vsr_table) + 0x100;
CYG_LABEL_DEFN(__reserved_virtual_table) = ALIGN (0x10); . = CYG_LABEL_DEFN(__reserved_virtual_table) + 0x100;
CYG_LABEL_DEFN(__reserved_for_rom) = ALIGN (0x10); . = CYG_LABEL_DEFN(__reserved_for_rom) + 0x1fc00;
SECTION_rom_vectors (ram, ALIGN (0x10), LMA_EQ_VMA)
SECTION_ROMISC (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_RELOCS (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_init (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_rodata (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_rodata1 (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_data (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_data1 (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_eh_frame (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_ctors (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_dtors (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_devtab (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_got (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_dynamic (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_sdata (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_lit8 (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_lit4 (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_sbss (ram, ALIGN (0x8), LMA_EQ_VMA)
SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
CYG_LABEL_DEFN(__pci_window) = 0x8ff00000; . = CYG_LABEL_DEFN(__pci_window) + 0x100000;
SECTIONS_END
}
/ocelot/v2_0/include/pkgconf/mlt_mips_rm7000_ocelot_rom.mlt
0,0 → 1,30
version 0
region ram 80000000 10000000 0 !
region rom bfc00000 80000 1 !
section reserved_vectors 200 1 0 0 1 1 1 1 80000000 80000000 reserved_vsr_table reserved_vsr_table !
section reserved_vsr_table 100 10 0 0 0 1 0 1 reserved_virtual_table reserved_virtual_table !
section reserved_virtual_table 100 10 0 0 0 1 0 0 data !
section data 0 10 1 1 0 1 0 1 data1 data1 !
section data1 0 8 1 1 0 1 0 1 eh_frame eh_frame !
section eh_frame 0 8 1 1 0 1 0 1 gcc_except_table gcc_except_table !
section gcc_except_table 0 8 1 1 0 1 0 1 ctors ctors !
section ctors 0 8 1 1 0 1 0 1 dtors dtors !
section dtors 0 8 1 1 0 1 0 1 devtab devtab !
section devtab 0 8 1 1 0 1 0 1 got got !
section got 0 8 1 1 0 1 0 1 dynamic dynamic !
section dynamic 0 8 1 1 0 1 0 1 sdata sdata !
section sdata 0 8 1 1 0 1 0 1 lit8 lit8 !
section lit8 0 8 1 1 0 1 0 1 lit4 lit4 !
section lit4 0 8 1 1 0 1 0 0 sbss !
section sbss 0 8 0 1 0 1 0 1 bss bss !
section bss 0 8 0 1 0 1 0 1 heap1 heap1 !
section heap1 0 8 0 0 0 0 0 0 !
section pci_window 100000 1 0 0 1 0 1 0 8ff00000 8ff00000 !
section rom_vectors 0 1 0 1 1 1 1 1 bfc00000 bfc00000 ROMISC ROMISC !
section ROMISC 0 8 0 1 0 1 0 1 RELOCS RELOCS !
section RELOCS 0 8 0 1 0 1 0 1 init init !
section init 0 8 0 1 0 1 0 1 text text !
section text 0 8 0 1 0 1 0 1 fini fini !
section fini 0 8 0 1 0 1 0 1 rodata rodata !
section rodata 0 8 0 1 0 1 0 1 rodata1 rodata1 !
section rodata1 0 8 0 1 0 0 0 1 data !
/ocelot/v2_0/include/pkgconf/mlt_mips_rm7000_ocelot_ram.mlt
0,0 → 1,30
version 0
region ram 80000000 10000000 0 !
section reserved_vectors 200 1 0 0 1 1 1 1 80000000 80000000 reserved_vsr_table reserved_vsr_table !
section reserved_vsr_table 100 10 0 0 0 1 0 1 reserved_virtual_table reserved_virtual_table !
section reserved_virtual_table 100 10 0 0 0 1 0 1 reserved_for_rom reserved_for_rom !
section reserved_for_rom 1fc00 10 0 0 0 1 0 1 rom_vectors rom_vectors !
section rom_vectors 0 10 0 1 0 1 0 1 ROMISC ROMISC !
section ROMISC 0 4 0 1 0 1 0 1 RELOCS RELOCS !
section RELOCS 0 4 0 1 0 1 0 1 init init !
section init 0 4 0 1 0 1 0 1 text text !
section text 0 4 0 1 0 1 0 1 fini fini !
section fini 0 4 0 1 0 1 0 1 rodata rodata !
section rodata 0 8 0 1 0 1 0 1 rodata1 rodata1 !
section rodata1 0 8 0 1 0 1 0 1 data data !
section data 0 8 0 1 0 1 0 1 data1 data1 !
section data1 0 8 0 1 0 1 0 1 eh_frame eh_frame !
section eh_frame 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
section gcc_except_table 0 4 0 1 0 1 0 1 ctors ctors !
section ctors 0 4 0 1 0 1 0 1 dtors dtors !
section dtors 0 4 0 1 0 1 0 1 devtab devtab !
section devtab 0 4 0 1 0 1 0 1 got got !
section got 0 4 0 1 0 1 0 1 dynamic dynamic !
section dynamic 0 4 0 1 0 1 0 1 sdata sdata !
section sdata 0 4 0 1 0 1 0 1 lit8 lit8 !
section lit8 0 8 0 1 0 1 0 1 lit4 lit4 !
section lit4 0 8 0 1 0 1 0 1 sbss sbss !
section sbss 0 8 0 1 0 1 0 1 bss bss !
section bss 0 8 0 1 0 1 0 1 heap1 heap1 !
section heap1 0 8 0 0 0 0 0 0 !
section pci_window 100000 1 0 0 1 0 1 0 8ff00000 8ff00000 !
/ocelot/v2_0/include/plf_cache.h
0,0 → 1,64
#ifndef CYGONCE_PLF_CACHE_H
#define CYGONCE_PLF_CACHE_H
 
//=============================================================================
//
// plf_cache.h
//
// HAL cache control API
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors:nickg
// Date: 1998-02-17
// Purpose: Cache control API
// Description: The macros defined here provide the HAL APIs for handling
// cache control operations.
// Usage:
// #include <cyg/hal/plf_cache.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
//-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_PLF_CACHE_H
// End of plf_cache.h
 
/ocelot/v2_0/include/platform.inc
0,0 → 1,235
#ifndef CYGONCE_HAL_PLATFORM_INC
#define CYGONCE_HAL_PLATFORM_INC
##=============================================================================
##
## platform.inc
##
## Ocelot board assembler header file
##
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
##=============================================================================
#######DESCRIPTIONBEGIN####
##
## Author(s): nickg
## Contributors:nickg,jskov
## Date: 2000-05-15
## Purpose: Ocelot board definitions.
## Description: This file contains various definitions and macros that are
## useful for writing assembly code for the Ocelot board.
## Usage:
## #include <cyg/hal/platform.inc>
## ...
##
##
######DESCRIPTIONEND####
##
##=============================================================================
 
#include <cyg/hal/mips.inc>
#include <cyg/hal/plf_defs.inc>
 
 
#------------------------------------------------------------------------------
# Macro for copying vectors to RAM if necessary.
#if !defined(CYGSEM_HAL_USE_ROM_MONITOR)
 
.macro hal_vectors_init
# If we don~t play nice with a ROM monitor, copy the required
# vectors into the proper location.
la t0,0x80000000 # dest addr
la t1,utlb_vector # source addr
la t3,utlb_vector_end # end dest addr
1:
lw v0,0(t1) # get word
addi t1,t1,4
sw v0,0(t0) # write word
addi t0,t0,4
bne t1,t3,1b
nop
 
la t0,0x80000180 # dest addr
la t1,other_vector # source addr
la t3,other_vector_end # end dest addr
1:
lw v0,0(t1) # get word
addi t1,t1,4
sw v0,0(t0) # write word
addi t0,t0,4
bne t1,t3,1b
nop
 
.set mips3 # Set ISA to MIPS 3 to allow cache insns
# Now clear the region in the caches
la t0,0x80000000 # dest addr
ori t1,t0,0x200 # source addr
1: cache 0x01,0x0000(t0) # Flush word from data cache
cache 0x01,0x1000(t0)
cache 0x01,0x2000(t0)
cache 0x01,0x3000(t0)
nop
cache 0x00,0x0000(t0) # Invalidate icache for word
cache 0x00,0x1000(t0)
cache 0x00,0x2000(t0)
cache 0x00,0x3000(t0)
nop
addi t0,t0,0x20
bne t0,t1,1b
nop
.set mips0 # reset ISA to default
 
.endm
 
#else
 
.macro hal_vectors_init
.endm
 
#endif
 
#------------------------------------------------------------------------------
# Monitor initialization.
#ifndef CYGPKG_HAL_MIPS_MON_DEFINED
 
#if defined(CYG_HAL_STARTUP_ROM) || \
( defined(CYG_HAL_STARTUP_RAM) && \
!defined(CYGSEM_HAL_USE_ROM_MONITOR))
# If we are starting up from ROM, or we are starting in
# RAM and NOT using a ROM monitor, initialize the VSR table.
 
.macro hal_mon_init
hal_vectors_init
# Set default exception VSR for all vectors
ori a0,zero,CYGNUM_HAL_VSR_COUNT
la a1,__default_exception_vsr
la a2,hal_vsr_table
1: sw a1,0(a2)
addi a2,a2,4
addi a0,a0,-1
bne a0,zero,1b
nop
 
# Now set special VSRs
la a0,hal_vsr_table
# Set interrupt VSR
la a1,__default_interrupt_vsr
sw a1,CYGNUM_HAL_VECTOR_INTERRUPT*4(a0)
# Add special handler on breakpoint vector to allow GDB and
# GCC to both use 'break' without conflicts.
la a1,__break_vsr_springboard
sw a1,CYGNUM_HAL_VECTOR_BREAKPOINT*4(a0)
# Set exception handler on special vectors
# FIXME: Should use proper definitions
la a1,__default_exception_vsr
sw a1,32*4(a0) # debug
sw a1,33*4(a0) # utlb
sw a1,34*4(a0) # nmi
.endm
#elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR)
 
# Initialize the VSR table entries
# We only take control of the interrupt vector,
# the rest are left to the ROM for now...
 
.macro hal_mon_init
hal_vectors_init
# Set interrupt VSR
la a0,hal_vsr_table
la a1,__default_interrupt_vsr
sw a1,CYGNUM_HAL_VECTOR_INTERRUPT*4(a0)
.endm
 
#else
 
.macro hal_mon_init
hal_vectors_init
.endm
 
#endif
 
#define CYGPKG_HAL_MIPS_MON_DEFINED
#endif
 
#------------------------------------------------------------------------------
 
#if !defined(CYG_HAL_STARTUP_RAM)
.macro hal_memc_init
// Only initialize the SDRAM controller when running in ROM
.extern hal_memc_setup
lar t0,hal_memc_setup
jalr t0
nop
 
// FIXME: Clear reset status byte
.endm
#define CYGPKG_HAL_MIPS_MEMC_DEFINED
#endif
 
#------------------------------------------------------------------------------
# Decide whether the VSR table is defined externally, or is to be defined
# here.
 
## ISR tables are defined in platform.S
#define CYG_HAL_MIPS_ISR_TABLES_DEFINED
 
## VSR table is at a fixed RAM address defined by the linker script
#define CYG_HAL_MIPS_VSR_TABLE_DEFINED
 
##-----------------------------------------------------------------------------
#ifdef CYG_STARTUP_ROM
 
## Initial SR value for use in ROM:
## CP0 usable
## Vectors in RAM
## FP registers are 32 bit
## All hw ints disabled
#define INITIAL_SR 0x30000000
 
#else
 
## Initial SR value for use standalone:
## CP0 usable
## Vectors to RAM
## FP registers are 32 bit
## All hw ints disabled
#define INITIAL_SR 0x30000000
 
#endif
 
#------------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_PLATFORM_INC
# end of platform.inc
/ocelot/v2_0/include/hal_diag.h
0,0 → 1,92
#ifndef CYGONCE_HAL_HAL_DIAG_H
#define CYGONCE_HAL_HAL_DIAG_H
 
//=============================================================================
//
// hal_diag.h
//
// HAL Support for Kernel Diagnostic Routines
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
// Contributors:jskov, nickg
// Date: 2000-05-15
// Purpose: HAL Support for Kernel Diagnostic Routines
// Description: Diagnostic routines for use during kernel development.
// Usage: #include <cyg/hal/hal_diag.h>
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h>
 
#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
 
#include <cyg/hal/hal_if.h>
 
#define HAL_DIAG_INIT() hal_if_diag_init()
#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_)
#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_)
 
#else // everything by steam
 
//-----------------------------------------------------------------------------
// functions implemented in hal_diag.c
 
externC void hal_diag_init(void);
 
externC void hal_diag_write_char(char c);
 
externC void hal_diag_read_char(char *c);
 
//-----------------------------------------------------------------------------
 
#define HAL_DIAG_INIT() hal_diag_init()
 
#define HAL_DIAG_WRITE_CHAR(_c_) hal_diag_write_char(_c_)
 
#define HAL_DIAG_READ_CHAR(_c_) hal_diag_read_char(&_c_)
 
#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
 
//-----------------------------------------------------------------------------
// end of hal_diag.h
#endif // CYGONCE_HAL_HAL_DIAG_H
/ocelot/v2_0/include/plf_io.h
0,0 → 1,356
#ifndef CYGONCE_PLF_IO_H
#define CYGONCE_PLF_IO_H
 
//=============================================================================
//
// plf_io.h
//
// Platform specific IO support
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): hmt, jskov, nickg
// Contributors: hmt, jskov, nickg
// Date: 1999-08-09
// Purpose: Ocelot/Galileo GT-64120A PCI IO support macros
// Description:
// Usage: #include <cyg/hal/plf_io.h>
//
// Note: Based on information in
// "Galileo GT 64120A System Controller For
// RC4650/4700/5000 and RM526X/527X/7000 CPUs"
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/hal/hal_arch.h> // address macros
#include <cyg/hal/hal_io.h> // IO macros
#include <cyg/hal/hal_intr.h> // Interrupt vectors
 
//-----------------------------------------------------------------------------
// PCI access registers
 
//#define HAL_PCI_ADDRESS_WINDOW_1 0xAF000014
//#define HAL_PCI_ADDRESS_WINDOW_2 0xAF000018
//#define HAL_PCI_IO_WINDOW 0xAF000024
#define HAL_PCI_CONFIG_SPACE_DATA 0xb4000cfc
#define HAL_PCI_CONFIG_SPACE_ADDR 0xb4000cf8
//#define HAL_PCI_ENABLE_REG 0xAF000074
 
//-----------------------------------------------------------------------------
// Mappings for PCI memory and IO spaces
 
// These are the offsets programmed into the Galileo for setting up the
// CPU->PCI space mapping. These are put high to allow for 256MB RAM in
// kseg0/1 - but we'll probably have to put the RAM in kuseg anyway to get
// it all mapped (512MB). These mappings leave enough space for the
// PCI devices on the Ocelot regardless though.
//
// Note that the CPU addresses are going directly to the PCI bus, so
// the IO/MEM bases are the matching CPU address space locations, not
// zero.
 
#define HAL_OCELOT_PCI_IO_BASE 0x10000000
#define HAL_OCELOT_PCI_IO_SIZE 0x01000000 // 16 MB
#define HAL_OCELOT_PCI_MEM0_BASE 0x12000000
#define HAL_OCELOT_PCI_MEM0_SIZE 0x01000000 // 16 MB
#define HAL_OCELOT_PCI_MEM1_BASE 0x13000000
#define HAL_OCELOT_PCI_MEM1_SIZE 0x01000000 // 16 MB
 
// This is where the PCI spaces are mapped in the CPU's (virtual)
// address space. These are the uncached addresses.
#define HAL_PCI_PHYSICAL_MEMORY_BASE CYGARC_UNCACHED_ADDRESS(0)
#define HAL_PCI_PHYSICAL_IO_BASE CYGARC_UNCACHED_ADDRESS(0)
 
// Map PCI device resources starting from these addresses in PCI space.
#define HAL_PCI_ALLOC_BASE_MEMORY HAL_OCELOT_PCI_MEM0_BASE
#define HAL_PCI_ALLOC_BASE_IO HAL_OCELOT_PCI_IO_BASE
 
 
// Uncached controller base
#define HAL_GALILEO_CONTROLLER_BASE 0xb4000000
 
//-----------------------------------------------------------------------------
 
#define HAL_GALILEO_PUTREG(r,d) \
HAL_WRITE_UINT32((HAL_GALILEO_CONTROLLER_BASE + (r)), \
((((d) & 0xff) << 24) | (((d) & 0xff00) << 8) | (((d) & 0xff0000) >> 8) | (((d) >> 24) & 0xff)))
#define HAL_GALILEO_GETREG(r) \
({ cyg_uint32 d; HAL_READ_UINT32((HAL_GALILEO_CONTROLLER_BASE + (r)), d);\
(((d & 0xff) << 24) | ((d & 0xff00) << 8) | ((d & 0xff0000) >> 8) | ((d >> 24) & 0xff)); })
 
// PCI config reads are special: all devices but the Galileo itself
// are in big-endian mode. Fiddling the endian configs did not seem
// to make a difference.
#define HAL_GALILEO_PUTPCI(bus, devfn, r, data) \
CYG_MACRO_START \
if (0 == bus && 0 == devfn) \
HAL_GALILEO_PUTREG(r, data); \
else \
HAL_WRITE_UINT32((HAL_GALILEO_CONTROLLER_BASE + (r)), data); \
CYG_MACRO_END
 
#define HAL_GALILEO_GETPCI(bus, devfn, r, data) \
CYG_MACRO_START \
if (0 == bus && 0 == devfn) \
data = HAL_GALILEO_GETREG(r); \
else \
HAL_READ_UINT32((HAL_GALILEO_CONTROLLER_BASE + (r)), data); \
CYG_MACRO_END
 
 
extern cyg_uint32 cyg_hal_plf_pci_cfg_read_dword (cyg_uint32 bus,
cyg_uint32 devfn,
cyg_uint32 offset);
extern cyg_uint16 cyg_hal_plf_pci_cfg_read_word (cyg_uint32 bus,
cyg_uint32 devfn,
cyg_uint32 offset);
extern cyg_uint8 cyg_hal_plf_pci_cfg_read_byte (cyg_uint32 bus,
cyg_uint32 devfn,
cyg_uint32 offset);
extern void cyg_hal_plf_pci_cfg_write_dword (cyg_uint32 bus,
cyg_uint32 devfn,
cyg_uint32 offset,
cyg_uint32 val);
extern void cyg_hal_plf_pci_cfg_write_word (cyg_uint32 bus,
cyg_uint32 devfn,
cyg_uint32 offset,
cyg_uint16 val);
extern void cyg_hal_plf_pci_cfg_write_byte (cyg_uint32 bus,
cyg_uint32 devfn,
cyg_uint32 offset,
cyg_uint8 val);
 
//-----------------------------------------------------------------------------
 
// Initialize the PCI bus.
externC void cyg_hal_plf_pci_init(void);
#define HAL_PCI_INIT() cyg_hal_plf_pci_init()
 
// Read a value from the PCI configuration space of the appropriate
// size at an address composed from the bus, devfn and
// offset.
#define HAL_PCI_CFG_READ_UINT8( __bus, __devfn, __offset, __val ) \
__val = cyg_hal_plf_pci_cfg_read_byte((__bus), (__devfn), (__offset))
#define HAL_PCI_CFG_READ_UINT16( __bus, __devfn, __offset, __val ) \
__val = cyg_hal_plf_pci_cfg_read_word((__bus), (__devfn), (__offset))
 
#define HAL_PCI_CFG_READ_UINT32( __bus, __devfn, __offset, __val ) \
__val = cyg_hal_plf_pci_cfg_read_dword((__bus), (__devfn), (__offset))
 
// Write a value to the PCI configuration space of the appropriate
// size at an address composed from the bus, devfn and offset.
#define HAL_PCI_CFG_WRITE_UINT8( __bus, __devfn, __offset, __val ) \
cyg_hal_plf_pci_cfg_write_byte((__bus), (__devfn), (__offset), (__val))
 
#define HAL_PCI_CFG_WRITE_UINT16( __bus, __devfn, __offset, __val ) \
cyg_hal_plf_pci_cfg_write_word((__bus), (__devfn), (__offset), (__val))
 
#define HAL_PCI_CFG_WRITE_UINT32( __bus, __devfn, __offset, __val ) \
cyg_hal_plf_pci_cfg_write_dword((__bus), (__devfn), (__offset), (__val))
 
 
//-----------------------------------------------------------------------------
// Resources
 
// Translate the PCI interrupt requested by the device (INTA#, INTB#,
// INTC# or INTD#) to the associated CPU interrupt (i.e., HAL vector).
// We don't actually know what the mappings are at present for this
// board. The following is therefore just a temporary guess until
// we can find out.
 
#define HAL_PCI_TRANSLATE_INTERRUPT( __bus, __devfn, __vec, __valid) \
CYG_MACRO_START \
cyg_uint8 __req; \
HAL_PCI_CFG_READ_UINT8(__bus, __devfn, CYG_PCI_CFG_INT_PIN, __req); \
if (0 != __req) { \
CYG_ADDRWORD __translation[4] = { \
CYGNUM_HAL_INTERRUPT_PCI_INTA, /* INTA# */ \
CYGNUM_HAL_INTERRUPT_PCI_INTB, /* INTB# */ \
CYGNUM_HAL_INTERRUPT_PCI_INTC, /* INTC# */ \
CYGNUM_HAL_INTERRUPT_PCI_INTD };/* INTD# */ \
\
__vec = __translation[(((__req-1)+CYG_PCI_DEV_GET_DEV(__devfn))&3)]; \
\
__valid = true; \
} else { \
/* Device will not generate interrupt requests. */ \
__valid = false; \
} \
CYG_MACRO_END
 
// Galileo GT64120 on MIPS Ocelot requires special processing.
// First, it will hang when accessing device 31 on the local bus.
// Second, we need to ignore the GT64120 so we can set it up
// outside the generic PCI library.
#define HAL_PCI_IGNORE_DEVICE(__bus, __dev, __fn) \
((__bus) == 0 && ((__dev) == 0 || (__dev) == 31))
 
 
//-----------------------------------------------------------------------------
// PCI / Galileo register definitions
#define HAL_GALILEO_PCI0_CONFIG_ADDR_ConfigEn BIT31
#define HAL_GALILEO_PCI0_STATUS_COMMAND_REGNUM 0x04
#define HAL_GALILEO_PCI0_BIST_REGNUM 0x0C
#define HAL_GALILEO_PCI0_SCS32_BASE_REGNUM 0x14
#define HAL_GALILEO_PCI0_CONFIG_MEMEn 0x2
#define HAL_GALILEO_PCI0_CONFIG_MasEn 0x4
#define HAL_GALILEO_PCI0_CONFIG_SErrEn 0x100
#define HAL_GALILEO_PCI0_LAT_TIMER_VAL 0x800
#define HAL_GALILEO_PCI0_TIMEOUT_RETRY_VALUE 0x00ffffff
 
#define HAL_GALILEO_PCI_INTERNAL_COMMAND_OFFSET 0xC00
#define HAL_GALILEO_PCI0_TIMEOUT_RETRY_OFFSET 0xc04
#define HAL_GALILEO_PCI0_SCS10_SIZE_OFFSET 0xc08
#define HAL_GALILEO_PCI0_SCS32_SIZE_OFFSET 0xc0c
#define HAL_GALILEO_PCI0_SCS20_SIZE_OFFSET 0xc10
#define HAL_GALILEO_PCI0_CS3_SIZE_OFFSET 0xc14
#define HAL_GALILEO_BAR_ENA_OFFSET 0xc3c
# define HAL_GALILEO_BAR_ENA_SWCS3 (1 << 0)
# define HAL_GALILEO_BAR_ENA_SWCS32 (1 << 1)
# define HAL_GALILEO_BAR_ENA_SWCS10 (1 << 2)
# define HAL_GALILEO_BAR_ENA_IO (1 << 3)
# define HAL_GALILEO_BAR_ENA_MEM (1 << 4)
# define HAL_GALILEO_BAR_ENA_CS3 (1 << 5)
# define HAL_GALILEO_BAR_ENA_CS20 (1 << 6)
# define HAL_GALILEO_BAR_ENA_SCS32 (1 << 7)
# define HAL_GALILEO_BAR_ENA_SCS10 (1 << 8)
#define HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET 0xcf8
# define HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE (1 << 31)
#define HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET 0xcfc
 
#define HAL_OCELOT_NULL_DEVNUM 0x0
 
// GALILEO Interrupts
#define HAL_GALILEO_IRQ_CAUSE_OFFSET 0xc18
# define HAL_GALILEO_IRQCAUSE_INTSUM (1 << 0)
# define HAL_GALILEO_IRQCAUSE_MEMOUT (1 << 1)
# define HAL_GALILEO_IRQCAUSE_DMAOUT (1 << 2)
# define HAL_GALILEO_IRQCAUSE_CPUOUT (1 << 3)
# define HAL_GALILEO_IRQCAUSE_DMA0 (1 << 4)
# define HAL_GALILEO_IRQCAUSE_DMA1 (1 << 5)
# define HAL_GALILEO_IRQCAUSE_DMA2 (1 << 6)
# define HAL_GALILEO_IRQCAUSE_DMA3 (1 << 7)
# define HAL_GALILEO_IRQCAUSE_T0 (1 << 8)
# define HAL_GALILEO_IRQCAUSE_T1 (1 << 9)
# define HAL_GALILEO_IRQCAUSE_T2 (1 << 10)
# define HAL_GALILEO_IRQCAUSE_T3 (1 << 11)
# define HAL_GALILEO_IRQCAUSE_MASRD (1 << 12)
# define HAL_GALILEO_IRQCAUSE_SLVWR (1 << 13)
# define HAL_GALILEO_IRQCAUSE_MASWR (1 << 14)
# define HAL_GALILEO_IRQCAUSE_SLVRD (1 << 15)
# define HAL_GALILEO_IRQCAUSE_AERR (1 << 16)
# define HAL_GALILEO_IRQCAUSE_MERR (1 << 17)
# define HAL_GALILEO_IRQCAUSE_MASABT (1 << 18)
# define HAL_GALILEO_IRQCAUSE_TARABT (1 << 19)
# define HAL_GALILEO_IRQCAUSE_RETRY (1 << 20)
# define HAL_GALILEO_IRQCAUSE_CPUSUM (1 << 30)
# define HAL_GALILEO_IRQCAUSE_PCISUM (1 << 31)
#define HAL_GALILEO_HIRQ_CAUSE_OFFSET 0xc98
#define HAL_GALILEO_CPUIRQ_MASK_OFFSET 0xc1c
#define HAL_GALILEO_CPUHIRQ_MASK_OFFSET 0xc9c
 
/* Galileo Memory Controller registers */
#define HAL_GALILEO_SDRAM_DUPLICATE_BANK_ADDR BIT20
#define HAL_GALILEO_SDRAM_BANK_INTERLEAVE_DIS BIT14
#define HAL_GALILEO_CPU_DECODE_SHIFT 21
#define HAL_GALILEO_DEV_DECODE_SHIFT 20
#define HAL_GALILEO_SDRAM_SRAS_TO_SCAS_DELAY_3C BIT10
#define HAL_GALILEO_SDRAM_WIDTH_64BIT BIT6
#define HAL_GALILEO_SDRAM_SRAS_PRECHARGE_3C BIT3
#define HAL_GALILEO_SDRAM_BANK0_CASLAT_2 BIT0
#define HAL_GALILEO_SDRAM_BANK0_SZ_64M BIT11
#define HAL_GALILEO_SDRAM_NUM_BANKS_4 BIT5
#define HAL_GALILEO_SDRAM_BANK0_PARITY BIT8
#define HAL_GALILEO_SDRAM_CFG_RAM_WIDTH BIT15
#define HAL_GALILEO_PCI0_CONFIG_ADDR_ConfigEn BIT31
#define HAL_GALILEO_PCI0_STATUS_COMMAND_REGNUM 0x04
#define HAL_GALILEO_PCI0_BIST_REGNUM 0x0C
#define HAL_GALILEO_PCI0_SCS32_BASE_REGNUM 0x14
#define HAL_GALILEO_PCI0_CONFIG_MEMEn 0x2
#define HAL_GALILEO_PCI0_CONFIG_MasEn 0x4
#define HAL_GALILEO_PCI0_CONFIG_SErrEn 0x100
#define HAL_GALILEO_PCI0_LAT_TIMER_VAL 0x800
#define HAL_GALILEO_PCI0_TIMEOUT_RETRY_VALUE 0x00ffffff
 
#define HAL_GALILEO_SDRAM_BANK0_OFFSET 0x44c
#define HAL_GALILEO_SDRAM_BANK2_OFFSET 0x454
#define HAL_GALILEO_SDRAM_CONFIG_OFFSET 0x448
 
#define HAL_GALILEO_SCS10_LD_OFFSET 0x008
#define HAL_GALILEO_SCS10_HD_OFFSET 0x010
#define HAL_GALILEO_SCS32_LD_OFFSET 0x018
#define HAL_GALILEO_SCS32_HD_OFFSET 0x020
#define HAL_GALILEO_CS20_LD_OFFSET 0x028
#define HAL_GALILEO_CS20_HD_OFFSET 0x030
#define HAL_GALILEO_PCIIO_LD_OFFSET 0x048
#define HAL_GALILEO_PCIIO_HD_OFFSET 0x050
#define HAL_GALILEO_PCIMEM0_LD_OFFSET 0x058
#define HAL_GALILEO_PCIMEM0_HD_OFFSET 0x060
#define HAL_GALILEO_PCIMEM1_LD_OFFSET 0x080
#define HAL_GALILEO_PCIMEM1_HD_OFFSET 0x088
#define HAL_GALILEO_PCI1IO_LD_OFFSET 0x090
#define HAL_GALILEO_PCI1IO_HD_OFFSET 0x098
#define HAL_GALILEO_PCI1MEM0_LD_OFFSET 0x0a0
#define HAL_GALILEO_PCI1MEM0_HD_OFFSET 0x0a8
#define HAL_GALILEO_PCI1MEM1_LD_OFFSET 0x0b0
#define HAL_GALILEO_PCI1MEM1_HD_OFFSET 0x0b8
#define HAL_GALILEO_PCIIO_REMAP_OFFSET 0x0f0
#define HAL_GALILEO_PCIMEM0_REMAP_OFFSET 0x0f8
#define HAL_GALILEO_PCIMEM1_REMAP_OFFSET 0x100
#define HAL_GALILEO_SCS0_LD_OFFSET 0x400
#define HAL_GALILEO_SCS0_HD_OFFSET 0x404
#define HAL_GALILEO_SCS1_LD_OFFSET 0x408
#define HAL_GALILEO_SCS1_HD_OFFSET 0x40c
#define HAL_GALILEO_SCS2_LD_OFFSET 0x410
#define HAL_GALILEO_SCS2_HD_OFFSET 0x414
#define HAL_GALILEO_SCS3_LD_OFFSET 0x418
#define HAL_GALILEO_SCS3_HD_OFFSET 0x41c
#define HAL_GALILEO_CS0_LD_OFFSET 0x420
#define HAL_GALILEO_CS0_HD_OFFSET 0x424
#define HAL_GALILEO_CS1_LD_OFFSET 0x428
#define HAL_GALILEO_CS1_HD_OFFSET 0x42c
#define HAL_GALILEO_CS2_LD_OFFSET 0x430
#define HAL_GALILEO_CS2_HD_OFFSET 0x434
#define HAL_GALILEO_CPU_DECODE_SHIFT 21
 
//-----------------------------------------------------------------------------
// end of plf_io.h
#endif // CYGONCE_PLF_IO_H
/ocelot/v2_0/ChangeLog
0,0 → 1,234
2001-08-31 David Woodhouse <dwmw2@redhat.com>
 
* cfl/hal_mips_rm7000_ocelot.cdl: Fix compiler options to use
-mips2 for BE build, and make the LE options match the BE options
in all but endianness.
 
2001-08-09 Jonathan Larmour <jlarmour@redhat.com>
 
* include/plf_intr.h: Move HAL_INTERRUPT_ interrupt controller
access macros to variant HAL as they are generic.
 
2001-08-08 Chris Morrow <cmorrow@YottaYotta.com>
 
* include/plf_intr.h (HAL_INTERRUPT_MASK): Use correct comparison
for determining when to use interrupt control register.
Also use cfc rather than mfc insns. Also simplify a fraction.
(HAL_INTERRUPT_UNMASK): Ditto.
 
2001-08-03 Jesper Skov <jskov@redhat.com>
 
* cdl/hal_mips_rm7000_ocelot.cdl: Removed obsolete and wrong
gdb_module build runes.
 
2001-06-22 Jesper Skov <jskov@redhat.com>
 
* misc/redboot_RAM.ecm: Force 32k stack.
* misc/redboot_ROM.ecm: Same.
 
2001-06-08 David Woodhouse <dwmw2@redhat.com>
 
* src/platform.S: Change CS bank 3 parameters to 8-bit.
 
2001-05-23 Jesper Skov <jskov@redhat.com>
 
* misc/redboot_RAM.ecm: Use generic AMD driver.
* misc/redboot_ROM.ecm: Same.
 
2001-03-08 Jesper Skov <jskov@redhat.com>
 
* cdl/hal_mips_rm7000_ocelot.cdl: Removed
CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT_GUARANTEED which is now the
default.
 
2001-02-23 Jesper Skov <jskov@redhat.com>
 
* include/plf_cache.h: Removed HAL_FLASH_CACHES_WANT_OPTIMAL. It
is now the default.
 
2001-02-08 Jesper Skov <jskov@redhat.com>
 
* cdl/hal_mips_rm7000_ocelot.cdl: Respect channel configuration
constraints.
 
* src/ns16552.c: Replace CYGSEM_HAL_DIAG_MANGLER_None with
CYGDBG_HAL_DIAG_TO_DEBUG_CHAN.
 
2001-02-01 Jesper Skov <jskov@redhat.com>
 
* src/platform.S: Handle interrupt chaining.
* include/platform.inc: Same.
* include/plf_intr.h: Same.
* src/plf_mk_defs.c: Same.
 
2001-01-31 Jesper Skov <jskov@redhat.com>
 
* src/ns16552.c: Replaced CYGDBG_HAL_DIAG_DISABLE_GDB_PROTOCOL
with CYGSEM_HAL_DIAG_MANGLER_None
 
2001-01-26 Jesper Skov <jskov@redhat.com>
 
* src/ns16552.c: Removed CYGSEM_HAL_VIRTUAL_VECTOR_DIAG check.
* include/plf_stub.h: Reset macros moved
* include/plf_intr.h: to this file.
 
2001-01-24 Jesper Skov <jskov@redhat.com>
 
* misc/redboot_RAM.ecm: Enable ethernet.
* misc/redboot_ROM.ecm: Same.
 
* include/plf_intr.h: PCI interrupt B is wired to i82559.
 
2001-01-19 Jesper Skov <jskov@redhat.com>
 
* cdl/hal_mips_rm7000_ocelot.cdl: Updated PCI space options
accordingly.
 
* src/platform.S: Add endian handling of memory init code.
 
* include/pkgconf/mlt_mips_rm7000_ocelot_rom.h: Update address
space to 256MB. Add space for PCI access.
* include/pkgconf/mlt_mips_rm7000_ocelot_rom.mlt: Same.
* include/pkgconf/mlt_mips_rm7000_ocelot_rom.ldi: Same.
* include/pkgconf/mlt_mips_rm7000_ocelot_ram.h: Same.
* include/pkgconf/mlt_mips_rm7000_ocelot_ram.mlt: Same.
* include/pkgconf/mlt_mips_rm7000_ocelot_ram.ldi: Same.
 
2001-01-15 Jesper Skov <jskov@redhat.com>
 
* src/plf_misc.c: Enable PCI access to memory.
* include/plf_io.h: Clean up PCI space mappings.
 
* src/plf_misc.c: The Galileo PCI config is in little-endian mode
while all other devices are in big-endian mode. Cruft to deal with
that.
* include/plf_io.h: Same.
 
2001-01-12 Jesper Skov <jskov@redhat.com>
 
* include/plf_io.h: Spacious PCI mappings.
* src/plf_misc.c (cyg_hal_plf_pci_init): Removed REMAP settings.
 
* include/plf_io.h: PCI memory changes.
* src/plf_misc.c (cyg_hal_plf_pci_init): Same. Doesn't seem to
make much of a difference though.
 
* cdl/hal_mips_rm7000_ocelot.cdl: New toolchain again.
 
2001-01-10 Jesper Skov <jskov@redhat.com>
 
* src/platform.S: Snuffed some more code from Mark to set the RAM
up properly. Not tested, and may not work with the full 512MB
[there was a mention of an Galileo errata]. We'll see.
 
* include/pkgconf/mlt_mips_rm7000_ocelot_ram.h: Hacked to provide
PCI window [no .mlt update since it'll all have to change for
fixed memory init anyway].
* include/pkgconf/mlt_mips_rm7000_ocelot_ram.ldi: Same.
 
* cdl/hal_mips_rm7000_ocelot.cdl: Added PCI memory window
options. Changed tools (again) which required some option hacking
as well. Fixed CPU clock / RTC rate issue.
 
* src/platform.S: Removed PCI init code.
 
* include/plf_io.h: Replace PCI macros with functions.
Added Galileo definitions.
* src/plf_misc.c: PCI functions. Code written by Mark
Salter.
* cdl/hal_mips_rm7000_ocelot.cdl: Change tool prefix.
 
2000-12-08 Jesper Skov <jskov@redhat.com>
 
* src/platform.S (hal_memc_setup_table): Only do one PCI access
retry.
 
2000-12-07 Jesper Skov <jskov@redhat.com>
 
* src/platform.S: Named PCI config registers.
 
* include/plf_intr.h: Added bogus PCI vectors.
 
* include/plf_io.h: Added, cloned from VRC4373 file. Pretty bogus
though. Probably need timeout support like the vrc4373 as well.
 
2000-12-06 Jesper Skov <jskov@redhat.com>
 
* cdl/hal_mips_rm7000_ocelot.cdl: Appears to only run at 150MHz.
Don't relocate RedBoot ELF image.
 
* include/pkgconf/mlt_mips_rm7000_ocelot_ram.h: Changed to 16MB
size. Need to look into why the full 256/512MB is not accessible.
* include/pkgconf/mlt_mips_rm7000_ocelot_ram.ldi: Same.
* include/pkgconf/mlt_mips_rm7000_ocelot_ram.mlt: Same.
* include/pkgconf/mlt_mips_rm7000_ocelot_rom.h: Same.
* include/pkgconf/mlt_mips_rm7000_ocelot_rom.ldi: Same.
* include/pkgconf/mlt_mips_rm7000_ocelot_rom.mlt: Same.
 
* misc/redboot_RAM.ecm: Added.
* misc/redboot_ROM.ecm: Added.
 
* cdl/hal_mips_rm7000_ocelot.cdl: Produce .srec and .img files.
 
* include/plf_cache.h (HAL_FLASH_CACHES_WANT_OPTIMAL): Defined.
 
2000-12-04 Jesper Skov <jskov@redhat.com>
 
* include/pkgconf/mlt_mips_rm7000_ocelot_ram.h: Proper sizes.
* include/pkgconf/mlt_mips_rm7000_ocelot_ram.ldi: Same.
* include/pkgconf/mlt_mips_rm7000_ocelot_ram.mlt: Same.
* include/pkgconf/mlt_mips_rm7000_ocelot_rom.h: Same.
* include/pkgconf/mlt_mips_rm7000_ocelot_rom.ldi: Same.
* include/pkgconf/mlt_mips_rm7000_ocelot_rom.mlt: Same.
 
* src/platform.S (hal_memc_setup_table): Fixed so it sets up SDRAM
correctly (only 256MB, though, I think - only uses banks 0 and 2).
 
2000-12-01 Jesper Skov <jskov@redhat.com>
 
* src/platform.S: Initialization code. Still not working.
 
* cdl/hal_mips_rm7000_ocelot.cdl: Added CPU clock and RedBoot
options.
 
2000-11-30 Jesper Skov <jskov@redhat.com>
 
* src/ns16552.c: Use uncached address space.
 
* Cloned from ref4955. Still stuff to clean out and stuff to add.
 
//===========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//===========================================================================
/ocelot/v2_0/src/plf_stub.c
0,0 → 1,70
//=============================================================================
//
// plf_stub.c
//
// Platform specific code for GDB stub support.
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
// Contributors:jskov
// Date: 2000-05-15
// Purpose: Platform specific code for GDB stub support.
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
 
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 
#include <cyg/hal/hal_stub.h>
 
#include <cyg/hal/hal_io.h> // HAL IO macros
 
//-----------------------------------------------------------------------------
// Stub init
 
void
hal_plf_stub_init(void)
{
}
 
#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
//-----------------------------------------------------------------------------
// End of plf_stub.c
/ocelot/v2_0/src/ns16552.c
0,0 → 1,595
//=============================================================================
//
// ns16552.c
//
// Simple driver for the NS16652 serial controller
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg, gthomas
// Contributors:nickg, gthomas, jskov
// Date: 1998-03-02
// Description: Simple HAL driver for the NS16552 serial controller
// Note: To drop into a new HAL, you should only have to change the
// few parameters here at the top.
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h> // base types
 
#include <cyg/infra/cyg_trac.h> // tracing macros
#include <cyg/infra/cyg_ass.h> // assertion macros
 
#include <cyg/hal/hal_arch.h> // basic machine info
#include <cyg/hal/hal_intr.h> // interrupt macros
#include <cyg/hal/hal_io.h> // IO macros
#include <cyg/hal/hal_diag.h>
#include <cyg/hal/drv_api.h>
#include <cyg/hal/hal_if.h> // interface API
#include <cyg/hal/hal_misc.h> // Helper functions
 
//-----------------------------------------------------------------------------
// Make changes here
#include <pkgconf/hal_mips_rm7000_ocelot.h> // board specifics
 
#define NS_SERIAL_A_BASE 0xbd000020
#define NS_SERIAL_A_IRQ CYGNUM_HAL_INTERRUPT_UART1
#define NS_SERIAL_B_BASE 0xbd000000
#define NS_SERIAL_B_IRQ CYGNUM_HAL_INTERRUPT_UART2
 
#define NS_CLOCK 20000000
 
// Fill in extra code as required
#define NS_EXTRA_INIT() \
CYG_MACRO_START \
CYG_MACRO_END
 
//-----------------------------------------------------------------------------
 
 
#define CYG_DEVICE_SERIAL_BAUD_MSB (((NS_CLOCK / (16*(CYGNUM_HAL_VIRTUAL_VECTOR_CHANNELS_DEFAULT_BAUD))) >> 8) & 0xff)
#define CYG_DEVICE_SERIAL_BAUD_LSB ((NS_CLOCK / (16*(CYGNUM_HAL_VIRTUAL_VECTOR_CHANNELS_DEFAULT_BAUD))) & 0xff)
 
// Define the serial registers.
#define CYG_DEV_RBR 0x00 // receiver buffer register, read, dlab = 0
#define CYG_DEV_THR 0x00 // transmitter holding register, write, dlab = 0
#define CYG_DEV_DLL 0x00 // divisor latch (LS), read/write, dlab = 1
#define CYG_DEV_IER 0x04 // interrupt enable register, read/write, dlab = 0
#define CYG_DEV_DLM 0x04 // divisor latch (MS), read/write, dlab = 1
#define CYG_DEV_IIR 0x08 // interrupt identification register, read, dlab = 0
#define CYG_DEV_FCR 0x08 // fifo control register, write, dlab = 0
#define CYG_DEV_LCR 0x0C // line control register, read/write
#define CYG_DEV_MCR 0x10 // modem control register, read/write
#define CYG_DEV_LSR 0x14 // line status register, read
#define CYG_DEV_MSR 0x18 // modem status register, read
 
// Interrupt Enable Register
#define SIO_IER_RCV 0x01
#define SIO_IER_XMT 0x02
#define SIO_IER_LS 0x04
#define SIO_IER_MS 0x08
 
// The line status register bits.
#define SIO_LSR_DR 0x01 // data ready
#define SIO_LSR_OE 0x02 // overrun error
#define SIO_LSR_PE 0x04 // parity error
#define SIO_LSR_FE 0x08 // framing error
#define SIO_LSR_BI 0x10 // break interrupt
#define SIO_LSR_THRE 0x20 // transmitter holding register empty
#define SIO_LSR_TEMT 0x40 // transmitter register empty
#define SIO_LSR_ERR 0x80 // any error condition
 
// The modem status register bits.
#define SIO_MSR_DCTS 0x01 // delta clear to send
#define SIO_MSR_DDSR 0x02 // delta data set ready
#define SIO_MSR_TERI 0x04 // trailing edge ring indicator
#define SIO_MSR_DDCD 0x08 // delta data carrier detect
#define SIO_MSR_CTS 0x10 // clear to send
#define SIO_MSR_DSR 0x20 // data set ready
#define SIO_MSR_RI 0x40 // ring indicator
#define SIO_MSR_DCD 0x80 // data carrier detect
 
// The line control register bits.
#define SIO_LCR_WLS0 0x01 // word length select bit 0
#define SIO_LCR_WLS1 0x02 // word length select bit 1
#define SIO_LCR_STB 0x04 // number of stop bits
#define SIO_LCR_PEN 0x08 // parity enable
#define SIO_LCR_EPS 0x10 // even parity select
#define SIO_LCR_SP 0x20 // stick parity
#define SIO_LCR_SB 0x40 // set break
#define SIO_LCR_DLAB 0x80 // divisor latch access bit
 
// Modem Control Register
#define SIO_MCR_DTR 0x01
#define SIO_MCR_RTS 0x02
#define SIO_MCR_INT 0x08 // Enable interrupts
 
//-----------------------------------------------------------------------------
typedef struct {
cyg_uint8* base;
cyg_int32 msec_timeout;
int isr_vector;
} channel_data_t;
 
//-----------------------------------------------------------------------------
 
static void
cyg_hal_plf_serial_init_channel(void* __ch_data)
{
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
cyg_uint8 lcr;
 
// 8-1-no parity.
HAL_WRITE_UINT8(base+CYG_DEV_LCR, SIO_LCR_WLS0 | SIO_LCR_WLS1);
 
HAL_READ_UINT8(base+CYG_DEV_LCR, lcr);
lcr |= SIO_LCR_DLAB;
HAL_WRITE_UINT8(base+CYG_DEV_LCR, lcr);
HAL_WRITE_UINT8(base+CYG_DEV_DLL, CYG_DEVICE_SERIAL_BAUD_LSB);
HAL_WRITE_UINT8(base+CYG_DEV_DLM, CYG_DEVICE_SERIAL_BAUD_MSB);
lcr &= ~SIO_LCR_DLAB;
HAL_WRITE_UINT8(base+CYG_DEV_LCR, lcr);
HAL_WRITE_UINT8(base+CYG_DEV_FCR, 0x07); // Enable & clear FIFO
 
NS_EXTRA_INIT();
}
 
void
cyg_hal_plf_serial_putc(void *__ch_data, char c)
{
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
cyg_uint8 lsr;
CYGARC_HAL_SAVE_GP();
 
do {
HAL_READ_UINT8(base+CYG_DEV_LSR, lsr);
} while ((lsr & SIO_LSR_THRE) == 0);
 
HAL_WRITE_UINT8(base+CYG_DEV_THR, c);
 
CYGARC_HAL_RESTORE_GP();
}
 
static cyg_bool
cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
{
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
cyg_uint8 lsr;
 
HAL_READ_UINT8(base+CYG_DEV_LSR, lsr);
if ((lsr & SIO_LSR_DR) == 0)
return false;
 
HAL_READ_UINT8(base+CYG_DEV_RBR, *ch);
 
return true;
}
 
cyg_uint8
cyg_hal_plf_serial_getc(void* __ch_data)
{
cyg_uint8 ch;
CYGARC_HAL_SAVE_GP();
 
while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
 
CYGARC_HAL_RESTORE_GP();
return ch;
}
 
static channel_data_t ns_ser_channels[2] = {
{ (cyg_uint8*)NS_SERIAL_A_BASE, 1000, NS_SERIAL_A_IRQ },
{ (cyg_uint8*)NS_SERIAL_B_BASE, 1000, NS_SERIAL_B_IRQ }
};
 
static void
cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
cyg_uint32 __len)
{
CYGARC_HAL_SAVE_GP();
 
while(__len-- > 0)
cyg_hal_plf_serial_putc(__ch_data, *__buf++);
 
CYGARC_HAL_RESTORE_GP();
}
 
static void
cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
{
CYGARC_HAL_SAVE_GP();
 
while(__len-- > 0)
*__buf++ = cyg_hal_plf_serial_getc(__ch_data);
 
CYGARC_HAL_RESTORE_GP();
}
 
cyg_bool
cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
{
int delay_count;
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_bool res;
CYGARC_HAL_SAVE_GP();
 
delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
 
for(;;) {
res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
if (res || 0 == delay_count--)
break;
CYGACC_CALL_IF_DELAY_US(100);
}
 
CYGARC_HAL_RESTORE_GP();
return res;
}
 
static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
int ret = 0;
CYGARC_HAL_SAVE_GP();
 
switch (__func) {
case __COMMCTL_IRQ_ENABLE:
irq_state = 1;
 
HAL_WRITE_UINT8(chan->base+CYG_DEV_IER, SIO_IER_RCV);
HAL_WRITE_UINT8(chan->base+CYG_DEV_MCR, SIO_MCR_INT|SIO_MCR_DTR|SIO_MCR_RTS);
 
HAL_INTERRUPT_UNMASK(chan->isr_vector);
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
 
HAL_WRITE_UINT8(chan->base+CYG_DEV_IER, 0);
 
HAL_INTERRUPT_MASK(chan->isr_vector);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
 
va_start(ap, __func);
 
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
 
va_end(ap);
}
default:
break;
}
CYGARC_HAL_RESTORE_GP();
return ret;
}
 
static int
cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
int res = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
char c;
cyg_uint8 lsr;
CYGARC_HAL_SAVE_GP();
 
cyg_drv_interrupt_acknowledge(chan->isr_vector);
 
*__ctrlc = 0;
HAL_READ_UINT8(chan->base+CYG_DEV_LSR, lsr);
if ( (lsr & SIO_LSR_DR) != 0 ) {
 
HAL_READ_UINT8(chan->base+CYG_DEV_RBR, c);
if( cyg_hal_is_break( &c , 1 ) )
*__ctrlc = 1;
 
res = CYG_ISR_HANDLED;
}
 
CYGARC_HAL_RESTORE_GP();
return res;
}
 
static void
cyg_hal_plf_serial_init(void)
{
hal_virtual_comm_table_t* comm;
int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
 
// Disable interrupts.
HAL_INTERRUPT_MASK(ns_ser_channels[0].isr_vector);
HAL_INTERRUPT_MASK(ns_ser_channels[1].isr_vector);
 
// Init channels
cyg_hal_plf_serial_init_channel(&ns_ser_channels[0]);
cyg_hal_plf_serial_init_channel(&ns_ser_channels[1]);
 
// Setup procs in the vector table
 
// Set channel 0
CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &ns_ser_channels[0]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
 
// Set channel 1
CYGACC_CALL_IF_SET_CONSOLE_COMM(1);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &ns_ser_channels[1]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
 
// Restore original console
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
}
 
void
cyg_hal_plf_comms_init(void)
{
static int initialized = 0;
 
if (initialized)
return;
 
initialized = 1;
 
cyg_hal_plf_serial_init();
}
 
//-----------------------------------------------------------------------------
 
//=============================================================================
// Compatibility with older stubs
//=============================================================================
 
#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
 
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
#include <cyg/hal/hal_stub.h> // cyg_hal_gdb_interrupt
#endif
 
#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL==0
// This is the base address of the A-channel
#define CYG_DEV_SERIAL_BASE 0x1d000020
#define CYG_DEVICE_SERIAL_INT CYGNUM_HAL_INTERRUPT_SERIALA
#else
// This is the base address of the B-channel
#define CYG_DEV_SERIAL_BASE 0x1d000000
#define CYG_DEVICE_SERIAL_INT CYGNUM_HAL_INTERRUPT_SERIALB
#endif
 
static channel_data_t ns_ser_channel = {
(cyg_uint8*)CYG_DEV_SERIAL_BASE, 0, 0
};
 
// Assumption: all diagnostic output must be GDB packetized unless this is a ROM (i.e.
// totally stand-alone) system.
 
#if defined(CYG_HAL_STARTUP_ROM) || !defined(CYGDBG_HAL_DIAG_TO_DEBUG_CHAN)
#define HAL_DIAG_USES_HARDWARE
#endif
 
#ifndef HAL_DIAG_USES_HARDWARE
#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL)
#define HAL_DIAG_USES_HARDWARE
#endif
#endif
 
#ifdef HAL_DIAG_USES_HARDWARE
 
void hal_diag_init(void)
{
static int init = 0;
char *msg = "\n\rARM eCos\n\r";
 
if (init++) return;
 
cyg_hal_plf_serial_init_channel(&ns_ser_channel);
 
while (*msg) cyg_hal_plf_serial_putc(&ns_ser_channel, *msg++);
}
 
#ifdef DEBUG_DIAG
#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
#define DIAG_BUFSIZE 32
#else
#define DIAG_BUFSIZE 2048
#endif
static char diag_buffer[DIAG_BUFSIZE];
static int diag_bp = 0;
#endif
 
void hal_diag_write_char(char c)
{
hal_diag_init();
 
cyg_hal_plf_serial_putc(&ns_ser_channel, c);
 
#ifdef DEBUG_DIAG
diag_buffer[diag_bp++] = c;
if (diag_bp == DIAG_BUFSIZE) diag_bp = 0;
#endif
}
 
void hal_diag_read_char(char *c)
{
*c = cyg_hal_plf_serial_getc(&ns_ser_channel);
}
 
#else // HAL_DIAG relies on GDB
 
// Initialize diag port - assume GDB channel is already set up
void hal_diag_init(void)
{
if (0) cyg_hal_plf_serial_init_channel(&ns_ser_channel); // avoid warning
}
 
// Actually send character down the wire
static void
hal_diag_write_char_serial(char c)
{
hal_diag_init();
 
cyg_hal_plf_serial_putc(&ns_ser_channel, c);
}
 
static bool
hal_diag_read_serial(char *c)
{
long timeout = 1000000000; // A long time...
while (!cyg_hal_plf_serial_getc_nonblock(&ns_ser_channel, c))
if (0 == --timeout) return false;
 
return true;
}
 
void
hal_diag_read_char(char *c)
{
while (!hal_diag_read_serial(c)) ;
}
 
void
hal_diag_write_char(char c)
{
static char line[100];
static int pos = 0;
 
// No need to send CRs
if( c == '\r' ) return;
 
line[pos++] = c;
 
if( c == '\n' || pos == sizeof(line) )
{
CYG_INTERRUPT_STATE old;
 
// Disable interrupts. This prevents GDB trying to interrupt us
// while we are in the middle of sending a packet. The serial
// receive interrupt will be seen when we re-enable interrupts
// later.
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
#else
HAL_DISABLE_INTERRUPTS(old);
#endif
 
while(1)
{
static char hex[] = "0123456789ABCDEF";
cyg_uint8 csum = 0;
int i;
char c1;
hal_diag_write_char_serial('$');
hal_diag_write_char_serial('O');
csum += 'O';
for( i = 0; i < pos; i++ )
{
char ch = line[i];
char h = hex[(ch>>4)&0xF];
char l = hex[ch&0xF];
hal_diag_write_char_serial(h);
hal_diag_write_char_serial(l);
csum += h;
csum += l;
}
hal_diag_write_char_serial('#');
hal_diag_write_char_serial(hex[(csum>>4)&0xF]);
hal_diag_write_char_serial(hex[csum&0xF]);
 
// Wait for the ACK character '+' from GDB here and handle
// receiving a ^C instead. This is the reason for this clause
// being a loop.
if (!hal_diag_read_serial(&c1))
continue; // No response - try sending packet again
 
if( c1 == '+' )
break; // a good acknowledge
 
#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
cyg_drv_interrupt_acknowledge(CYG_DEVICE_SERIAL_INT);
if( c1 == 3 ) {
// Ctrl-C: breakpoint.
cyg_hal_gdb_interrupt ((target_register_t)__builtin_return_address(0));
break;
}
#endif
// otherwise, loop round again
}
pos = 0;
 
// And re-enable interrupts
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
#else
HAL_RESTORE_INTERRUPTS(old);
#endif
}
}
#endif
 
#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
 
//-----------------------------------------------------------------------------
// End of ns16552.c
/ocelot/v2_0/src/platform.S
0,0 → 1,408
##=============================================================================
##
## platform.S
##
## MIPS Ocelot platform code
##
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
##=============================================================================
#######DESCRIPTIONBEGIN####
##
## Author(s): nickg
## Contributors:nickg, jskov
## Date: 2000-05-09
## Purpose: MIPS Ocelot platform code
## Description: Platform specific code for Ocelot board.
##
######DESCRIPTIONEND####
##
##=============================================================================
 
.set noreorder
 
#include <pkgconf/system.h>
#include <pkgconf/hal.h>
 
#ifdef CYGPKG_KERNEL
# include <pkgconf/kernel.h>
#endif
#include <cyg/hal/arch.inc>
#include <cyg/hal/plf_defs.inc>
#include <cyg/hal/hal_misc.h>
 
##-----------------------------------------------------------------------------
## MEMC initialization.
 
## This code is table driven, which is somewhat more compact that coding it
## all.
## Table entries consist of an address and a value to store in that address.
## A zero address terminates the table. Two special address values modify the
## behaviour:
## DELAY_LOOP loops for the number of iterations in the value field.
## WRITE16 treats the next 2 words as an address and value to be written
## with a 16 bit write cycle.
 
#define HAL_GALILEO_CONTROLLER_BASE 0xb4000000
#define GL_CPU_CFG 0xb4000000
#define GL_CPU_CFG_WRITERATE 0x00010000
#define GL_DEV_PAR_BANK0 0xb400045c
#define GL_DEV_PAR_BANK1 0xb4000460
#define GL_DEV_PAR_BANK2 0xb4000464
#define GL_DEV_PAR_BANK3 0xb4000468
#define GL_DEV_PAR_BOOT 0xb400046c
 
#define GL_SDRAM_CFG 0xb4000448
#define GL_SDRAM_CFG_REF_INT_CNT_default 0x00000200
#define GL_SDRAM_CFG_CPU_TO_DRAM_ERR 0x00020000
#define GL_SDRAM_CFG_ECC_INT 0x00040000
#define GL_SDRAM_CFG_DUP_BA 0x00100000
#define GL_SDRAM_CFG_REG_SDRAM 0x00800000
#define GL_SDRAM_CFG_DADR_12_SEL 0x01000000
#define GL_SDRAM_CFG_init (GL_SDRAM_CFG_REF_INT_CNT_default| \
GL_SDRAM_CFG_CPU_TO_DRAM_ERR| \
GL_SDRAM_CFG_ECC_INT| \
GL_SDRAM_CFG_DUP_BA| \
GL_SDRAM_CFG_REG_SDRAM| \
GL_SDRAM_CFG_DADR_12_SEL)
 
#define GL_SDRAM_PAR_BANK0 0xb400044c
#define GL_SDRAM_PAR_BANK2 0xb4000454
#define GL_CPU_SCS10_LO 0xb4000008
#define GL_CPU_SCS10_HI 0xb4000010
#define GL_CPU_SCS32_LO 0xb4000018
#define GL_CPU_SCS32_HI 0xb4000020
 
#define GL_SDRAM_SCS0_LO 0xb4000400
#define GL_SDRAM_SCS0_HI 0xb4000404
#define GL_SDRAM_SCS1_LO 0xb4000408
#define GL_SDRAM_SCS1_HI 0xb400040c
#define GL_SDRAM_SCS2_LO 0xb4000410
#define GL_SDRAM_SCS2_HI 0xb4000414
#define GL_SDRAM_SCS3_LO 0xb4000418
#define GL_SDRAM_SCS3_HI 0xb400041c
 
#define GL_SDRAM_MODE 0xb4000474
#define GL_SDRAM_MODE_NORMAL 0x00000000
#define GL_SDRAM_MODE_ENABLE 0x00000003
 
#define PLD_BOARD_STAT 0xbc000004
#define PLD_INT_SET 0xbc00000c
#define PLD_INT_CLEAR 0xbc00000d
#define PLD_INT_SET_USER_LED 0x40
 
#define CPU_TO_LE(x) (((x & 0xff) << 24) | ((x & 0xff00) << 8) | ((x & 0xff0000) >> 8) | ((x >> 24) & 0xff))
 
#define HAL_OCELOT_RAM_BASE 0x00000000
 
#define HAL_GALILEO_CPU_DECODE_SHIFT 21
#define HAL_GALILEO_DEV_DECODE_SHIFT 20
#define HAL_GALILEO_SCS10_LD_OFFSET 0x008
#define HAL_GALILEO_SCS10_HD_OFFSET 0x010
#define HAL_GALILEO_SCS32_LD_OFFSET 0x018
#define HAL_GALILEO_SCS32_HD_OFFSET 0x020
 
#define HAL_GALILEO_SCS0_LD_OFFSET 0x400
#define HAL_GALILEO_SCS0_HD_OFFSET 0x404
#define HAL_GALILEO_SCS1_LD_OFFSET 0x408
#define HAL_GALILEO_SCS1_HD_OFFSET 0x40c
#define HAL_GALILEO_SCS2_LD_OFFSET 0x410
#define HAL_GALILEO_SCS2_HD_OFFSET 0x414
#define HAL_GALILEO_SCS3_LD_OFFSET 0x418
#define HAL_GALILEO_SCS3_HD_OFFSET 0x41c
 
#if !defined(CYG_HAL_STARTUP_RAM)
#define DELAY_LOOP 1
#define WRITE16 2
 
 
#define swap(v, t1, t2, t3) \
lui t1,0xff; \
andi t2,v,0xff00; \
and t3,v,t1; \
sll t1,v,0x18; \
srl v,v,0x18; \
or v,v,t1; \
srl t3,t3,0x08; \
sll t2,t2,0x08; \
or v,v,t3; \
or v,v,t2;
 
FUNC_START(hal_memc_setup)
lar t0,hal_memc_setup_table
la t1,0xbfc00000
la t2,DELAY_LOOP
la t3,WRITE16
1:
lw a0,0(t0) # next table entry
lw a1,4(t0) # value to write
addiu t0,8 # go to next entry
beq a0,t2,2f # Check for delay
nop
beq a0,t3,3f # Check for 16 bit write
nop
beqz a0,9f # zero terminates loop
nop
sw a1,0(a0) # write it
lw zero,0(t1) # uncached read to flush write buffer
b 1b
nop
2:
lw zero,0(t1) # uncached read to flush write buffer
bnez a1,2b # count down by value in a1
addiu a1,-1 # decrement in delay slot
b 1b # go back to loop
nop
3:
lw a3,0(t0) # get next word
addiu t0,4 # skip it
sh a3,0(a1) # store halfword
lw zero,0(t1) # uncached read to flush write buffer
b 1b
nop
9:
 
// Complete the SDRAM setup.
la t0,GL_SDRAM_MODE
la t1,CPU_TO_LE(GL_SDRAM_MODE_ENABLE)
sw t1,0(t0)
// Wait 100us after writing mode
la a1,(CYGHWR_HAL_MIPS_RM7000_CPU_CLOCK * 100 / 1000000)
 
lui a0,0xa000 // uncached bank0 device
sw zero,0(a0)
 
mtc0 zero,$9
1: mfc0 a0,$9
nop
blt a0, a1, 1b
nop
 
lui a0,0xa080 // uncached bank2 device
sw zero,0(a0)
 
mtc0 zero,$9
1: mfc0 a0,$9
nop
blt a0, a1, 1b
nop
 
la t0,GL_SDRAM_MODE
la t1,CPU_TO_LE(GL_SDRAM_MODE_NORMAL)
sw t1,0(t0)
 
// Set CPU cfg word
la a0,GL_CPU_CFG
lw a1,0(a0)
la t0,CPU_TO_LE(0x20000)
or a1,a1,t0 // disable retries
 
// CPU WriteRate - set GT to match CPU
mfc0 t0,$16
la t1, 0x0f000000
and t0, t0, t1
beqz t0,1f // defaults to zero
nop
la t0, CPU_TO_LE(GL_CPU_CFG_WRITERATE)
or a1, a1, t0
1:
sw a1,0(a0)
 
# FIXME: Hardwired for 256MB - need kuseg magic to map full 512MB.
#
# Setup SDRAM Bank 0 Address Decoding
#
la s7, HAL_GALILEO_CONTROLLER_BASE
la a0, HAL_OCELOT_RAM_BASE # Phys bottom of Bank 0
la a1, (HAL_OCELOT_RAM_BASE+128*1024*1024)
subu a1, 1 # Phys top of Bank0
 
srl t0, a0, HAL_GALILEO_CPU_DECODE_SHIFT # Setup SCS[1:0]
swap(t0,t1,t2,t3) # 1st level decoding
sw t0, HAL_GALILEO_SCS10_LD_OFFSET(s7) # (CPU Decode Region)
srl t0, a1, HAL_GALILEO_CPU_DECODE_SHIFT #
swap(t0,t1,t2,t3)
sw t0, HAL_GALILEO_SCS10_HD_OFFSET(s7) #
 
srl t0, a0, HAL_GALILEO_DEV_DECODE_SHIFT # Setup SCS0
swap(t0,t1,t2,t3) # 2nd level decoding
sw t0, HAL_GALILEO_SCS0_LD_OFFSET(s7) # (Device Sub-decode Region)
srl t0, a1, HAL_GALILEO_DEV_DECODE_SHIFT #
swap(t0,t1,t2,t3)
sw t0, HAL_GALILEO_SCS0_HD_OFFSET(s7) #
 
#
# Setup SDRAM Bank 1 Address Decoding
#
la a0, (HAL_OCELOT_RAM_BASE+128*1024*1024) # Phys bottom of Bank 1
la a1, (HAL_OCELOT_RAM_BASE+256*1024*1024)
subu a1, 1 # Phys top of Bank1
 
srl t0, a0, HAL_GALILEO_CPU_DECODE_SHIFT # Setup SCS[3:2]
swap(t0,t1,t2,t3) # 1st level decoding
sw t0, HAL_GALILEO_SCS32_LD_OFFSET(s7) # (CPU Decode Region)
srl t0, a1, HAL_GALILEO_CPU_DECODE_SHIFT #
swap(t0,t1,t2,t3)
sw t0, HAL_GALILEO_SCS32_HD_OFFSET(s7) #
 
srl t0, a0, HAL_GALILEO_DEV_DECODE_SHIFT # Setup SCS2
swap(t0,t1,t2,t3) # 2nd level decoding
sw t0, HAL_GALILEO_SCS2_LD_OFFSET(s7) # (Device Sub-decode Region)
srl t0, a1, HAL_GALILEO_DEV_DECODE_SHIFT #
swap(t0,t1,t2,t3)
sw t0, HAL_GALILEO_SCS2_HD_OFFSET(s7) #
 
jr ra
nop
 
FUNC_END(hal_memc_setup)
##-----------------------------------------------------------------------------
## The initialization table
 
hal_memc_setup_table:
 
.long DELAY_LOOP, 10000 # Wait for HW to settle
 
.long GL_DEV_PAR_BANK0, CPU_TO_LE(0x000b6b33) // PLD
.long GL_DEV_PAR_BANK1, CPU_TO_LE(0x000bad53) // NVRAM
.long GL_DEV_PAR_BANK2, CPU_TO_LE(0x000bad54) // UART
.long GL_DEV_PAR_BANK3, CPU_TO_LE(0x000fef73) // flash disk
.long GL_DEV_PAR_BOOT, CPU_TO_LE(0x144bee63) // boot flash
 
.long GL_SDRAM_CFG, CPU_TO_LE(GL_SDRAM_CFG_init)
.long GL_SDRAM_PAR_BANK0, CPU_TO_LE(0x00000c69 | 0x4000)
.long GL_SDRAM_PAR_BANK2, CPU_TO_LE(0x00000c69 | 0x4000)
 
.long GL_CPU_SCS10_LO, CPU_TO_LE(0x00000000)
.long GL_CPU_SCS10_HI, CPU_TO_LE(0x00000003)
.long GL_CPU_SCS32_LO, CPU_TO_LE(0x00000004)
.long GL_CPU_SCS32_HI, CPU_TO_LE(0x00000007)
 
.long GL_SDRAM_SCS0_LO, CPU_TO_LE(0x00000000)
.long GL_SDRAM_SCS0_HI, CPU_TO_LE(0x00000007)
.long GL_SDRAM_SCS1_LO, CPU_TO_LE(0x000000ff)
.long GL_SDRAM_SCS1_HI, CPU_TO_LE(0x00000000)
.long GL_SDRAM_SCS2_LO, CPU_TO_LE(0x00000008)
.long GL_SDRAM_SCS2_HI, CPU_TO_LE(0x0000000f)
.long GL_SDRAM_SCS3_LO, CPU_TO_LE(0x000000ff)
.long GL_SDRAM_SCS3_HI, CPU_TO_LE(0x00000000)
 
.long 0, 0
#endif // !CYG_HAL_STARTUP_RAM
##-----------------------------------------------------------------------------
## ISR tables.
.extern hal_default_isr
.data
 
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
.globl hal_interrupt_handlers
hal_interrupt_handlers:
.long hal_default_isr # chaining vector
.globl hal_interrupt_data
hal_interrupt_data:
.long 0 # chaining vector data
 
.globl hal_interrupt_objects
hal_interrupt_objects:
.long 0 # chaining vector object
 
.globl cyg_hal_interrupt_level
cyg_hal_interrupt_level:
.rept CYGNUM_HAL_ISR_COUNT
.byte 0
.endr
 
#else // CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
.globl hal_interrupt_handlers
hal_interrupt_handlers:
.long hal_default_isr
.long hal_default_isr
.long hal_default_isr
.long hal_default_isr
.long hal_default_isr
.long hal_default_isr
.long hal_default_isr
.long hal_default_isr
.long hal_default_isr
.long hal_default_isr
 
.rept CYGNUM_HAL_ISR_COUNT-10
.long hal_default_isr
.endr
.globl hal_interrupt_data
hal_interrupt_data:
.long 0
.long 0
.long 0
.long 0
.long 0
.long 0
.long 0
.long 0
.long 0
.long 0
 
.rept CYGNUM_HAL_ISR_COUNT-10
.long 0
.endr
 
.globl hal_interrupt_objects
hal_interrupt_objects:
.rept CYGNUM_HAL_ISR_COUNT
.long 0
.endr
 
.globl cyg_hal_interrupt_level
cyg_hal_interrupt_level:
.rept CYGNUM_HAL_ISR_COUNT
.byte 0
.endr
 
#endif // CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
 
##-----------------------------------------------------------------------------
## end of platform.S
/ocelot/v2_0/src/plf_mk_defs.c
0,0 → 1,91
//==========================================================================
//
// plf_mk_defs.c
//
// HAL (platform) "make defs" program
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): gthomas
// Contributors: gthomas, jskov
// Date: 2000-11-30
// Purpose: Platform dependent definition generator
// Description: This file contains code that can be compiled by the target
// compiler and used to generate machine specific definitions
// suitable for use in assembly code.
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/hal/hal_arch.h> // HAL header
#include <cyg/hal/hal_intr.h> // HAL header
#include <cyg/hal/hal_cache.h> // HAL header
#ifdef CYGPKG_KERNEL
# include <pkgconf/kernel.h>
# include <cyg/kernel/instrmnt.h>
#endif
 
/*
* This program is used to generate definitions needed by
* assembly language modules.
*
* This technique was first used in the OSF Mach kernel code:
* generate asm statements containing #defines,
* compile this file to assembler, and then extract the
* #defines from the assembly-language output.
*/
 
#define DEFINE(sym, val) \
asm volatile("\n\t.equ\t" #sym ",%0" : : "i" (val))
 
int
main(void)
{
// Some other exception related definitions
DEFINE(CYGNUM_HAL_ISR_COUNT, CYGNUM_HAL_ISR_COUNT);
DEFINE(CYGNUM_HAL_VSR_COUNT, CYGNUM_HAL_VSR_COUNT);
DEFINE(CYGNUM_HAL_VECTOR_INTERRUPT, CYGNUM_HAL_VECTOR_INTERRUPT);
DEFINE(CYGNUM_HAL_VECTOR_BREAKPOINT, CYGNUM_HAL_VECTOR_BREAKPOINT);
 
return 0;
}
 
//--------------------------------------------------------------------------
// EOF plf_mk_defs.c
/ocelot/v2_0/src/plf_misc.c
0,0 → 1,339
//==========================================================================
//
// plf_misc.c
//
// HAL platform miscellaneous functions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
// Contributors: jskov
// Date: 2000-11-30
// Purpose: HAL miscellaneous functions
// Description: This file contains miscellaneous functions provided by the
// HAL.
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h> // Base types
 
#include <cyg/hal/hal_arch.h> // architectural definitions
#include <cyg/hal/hal_intr.h> // Interrupt handling
 
#include <cyg/hal/hal_if.h> // Calling interface definitions
 
#if defined(CYGPKG_IO_PCI)
#include <cyg/io/pci_hw.h>
#include <cyg/io/pci.h>
#endif
 
//--------------------------------------------------------------------------
 
void hal_platform_init(void)
{
hal_if_init();
 
// FIXME: Set up Galileo interrupt controller?
 
// Unmask vectors which are entry points for interrupt controllers
// HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_21555);
// HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_GALILEO);
}
 
//--------------------------------------------------------------------------
// PCI support
#if defined(CYGPKG_IO_PCI)
 
static int __check_bar(cyg_uint32 addr, cyg_uint32 size)
{
int n;
 
for (n = 0; n <= 31; n++)
if (size == (1 << n)) {
/* Check that address is naturally aligned */
if (addr != (addr & ~(size-1)))
return 0;
return size - 1;
}
return 0;
}
 
 
// One-time PCI initialization.
 
void cyg_hal_plf_pci_init(void)
{
cyg_uint32 bar_ena, start10, start32, end, size;
cyg_uint8 next_bus;
 
// Program PCI window in CPU address space and CPU->PCI remap
HAL_GALILEO_PUTREG(HAL_GALILEO_PCIMEM0_LD_OFFSET,
HAL_OCELOT_PCI_MEM0_BASE >> HAL_GALILEO_CPU_DECODE_SHIFT);
HAL_GALILEO_PUTREG(HAL_GALILEO_PCIMEM0_HD_OFFSET,
(HAL_OCELOT_PCI_MEM0_BASE+HAL_OCELOT_PCI_MEM0_SIZE-1) >> HAL_GALILEO_CPU_DECODE_SHIFT);
 
HAL_GALILEO_PUTREG(HAL_GALILEO_PCIMEM1_LD_OFFSET,
HAL_OCELOT_PCI_MEM1_BASE >> HAL_GALILEO_CPU_DECODE_SHIFT);
HAL_GALILEO_PUTREG(HAL_GALILEO_PCIMEM1_HD_OFFSET,
(HAL_OCELOT_PCI_MEM1_BASE+HAL_OCELOT_PCI_MEM1_SIZE-1) >> HAL_GALILEO_CPU_DECODE_SHIFT);
 
HAL_GALILEO_PUTREG(HAL_GALILEO_PCIIO_LD_OFFSET,
HAL_OCELOT_PCI_IO_BASE >> HAL_GALILEO_CPU_DECODE_SHIFT);
HAL_GALILEO_PUTREG(HAL_GALILEO_PCIIO_HD_OFFSET,
(HAL_OCELOT_PCI_IO_BASE+HAL_OCELOT_PCI_IO_SIZE-1) >> HAL_GALILEO_CPU_DECODE_SHIFT);
 
// Setup for bus mastering
cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_COMMAND,
CYG_PCI_CFG_COMMAND_IO |
CYG_PCI_CFG_COMMAND_MEMORY |
CYG_PCI_CFG_COMMAND_MASTER |
CYG_PCI_CFG_COMMAND_PARITY |
CYG_PCI_CFG_COMMAND_SERR);
 
// Setup latency timer field
cyg_hal_plf_pci_cfg_write_byte(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_LATENCY_TIMER, 6);
 
// Disable all BARs
bar_ena = 0x1ff;
 
// Allow PCI bus to access local memory
// Check for active SCS10
start10 = HAL_GALILEO_GETREG(HAL_GALILEO_SCS10_LD_OFFSET) << HAL_GALILEO_CPU_DECODE_SHIFT;
end = ((HAL_GALILEO_GETREG(HAL_GALILEO_SCS10_HD_OFFSET) & 0x7f) + 1) << HAL_GALILEO_CPU_DECODE_SHIFT;
if (end > start10) {
if ((size = __check_bar(start10, end - start10)) != 0) {
// Enable BAR
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_SCS10_SIZE_OFFSET, size);
bar_ena &= ~HAL_GALILEO_BAR_ENA_SCS10;
}
}
 
// Check for active SCS32
start32 = HAL_GALILEO_GETREG(HAL_GALILEO_SCS32_LD_OFFSET) << HAL_GALILEO_CPU_DECODE_SHIFT;
end = ((HAL_GALILEO_GETREG(HAL_GALILEO_SCS32_HD_OFFSET) & 0x7f) + 1) << HAL_GALILEO_CPU_DECODE_SHIFT;
if (end > start32) {
if ((size = __check_bar(start32, end - start32)) != 0) {
// Enable BAR
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_SCS32_SIZE_OFFSET, size);
bar_ena &= ~HAL_GALILEO_BAR_ENA_SCS32;
}
}
 
bar_ena &= ~HAL_GALILEO_BAR_ENA_SCS10;
 
HAL_GALILEO_PUTREG(HAL_GALILEO_BAR_ENA_OFFSET, bar_ena);
 
cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_BAR_0, 0xffffffff);
 
end = cyg_hal_plf_pci_cfg_read_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_BAR_0);
cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_BAR_0, start10);
 
 
cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_BAR_1, 0xffffffff);
 
end = cyg_hal_plf_pci_cfg_read_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_BAR_1);
 
cyg_hal_plf_pci_cfg_write_dword(0, CYG_PCI_DEV_MAKE_DEVFN(0,0),
CYG_PCI_CFG_BAR_1, start32);
 
// Configure PCI bus.
next_bus = 1;
cyg_pci_configure_bus(0, &next_bus);
}
 
 
// Check for configuration error.
static int pci_config_errcheck(void)
{
cyg_uint32 irq;
 
// Check for master or target abort
irq = HAL_GALILEO_GETREG(HAL_GALILEO_IRQ_CAUSE_OFFSET);
 
if (irq & (HAL_GALILEO_IRQCAUSE_MASABT | HAL_GALILEO_IRQCAUSE_TARABT)) {
// Error. Clear bits.
HAL_GALILEO_PUTREG(HAL_GALILEO_IRQ_CAUSE_OFFSET,
~(HAL_GALILEO_IRQCAUSE_MASABT | HAL_GALILEO_IRQCAUSE_TARABT));
return 1;
}
return 0;
}
 
cyg_uint32 cyg_hal_plf_pci_cfg_read_dword (cyg_uint32 bus,
cyg_uint32 devfn,
cyg_uint32 offset)
{
cyg_uint32 config_dword;
 
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET,
HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE |
(bus << 16) | (devfn << 8) | offset);
 
HAL_GALILEO_GETPCI(bus, devfn,
HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET, config_dword);
 
if (pci_config_errcheck())
return 0xffffffff;
return config_dword;
}
 
cyg_uint16 cyg_hal_plf_pci_cfg_read_word (cyg_uint32 bus,
cyg_uint32 devfn,
cyg_uint32 offset)
{
cyg_uint32 config_dword;
cyg_uint16 config_word;
 
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET,
HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE |
(bus << 16) | (devfn << 8) | (offset & ~3));
 
HAL_GALILEO_GETPCI(bus, devfn,
HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET, config_dword);
config_word = (cyg_uint16)((config_dword >> ((offset & 3) * 8)) & 0xffff);
 
if (pci_config_errcheck())
return 0xffff;
 
return config_word;
}
 
cyg_uint8 cyg_hal_plf_pci_cfg_read_byte (cyg_uint32 bus,
cyg_uint32 devfn,
cyg_uint32 offset)
{
cyg_uint32 config_dword;
cyg_uint8 config_byte;
 
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET,
HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE |
(bus << 16) | (devfn << 8) | (offset & ~3));
 
HAL_GALILEO_GETPCI(bus, devfn,
HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET, config_dword);
config_byte = (cyg_uint8)((config_dword >> ((offset & 3) * 8)) & 0xff);
 
if (pci_config_errcheck())
return 0xff;
 
return config_byte;
}
 
void cyg_hal_plf_pci_cfg_write_dword (cyg_uint32 bus,
cyg_uint32 devfn,
cyg_uint32 offset,
cyg_uint32 data)
{
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET,
HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE |
(bus << 16) | (devfn << 8) | offset);
 
HAL_GALILEO_PUTPCI(bus, devfn,
HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET, data);
 
(void)pci_config_errcheck();
}
 
void cyg_hal_plf_pci_cfg_write_word (cyg_uint32 bus,
cyg_uint32 devfn,
cyg_uint32 offset,
cyg_uint16 data)
{
cyg_uint32 config_dword, shift;
 
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET,
HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE |
(bus << 16) | (devfn << 8) | (offset & ~3));
 
 
HAL_GALILEO_GETPCI(bus, devfn,
HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET, config_dword);
if (pci_config_errcheck())
return;
 
shift = (offset & 3) * 8;
config_dword &= ~(0xffff << shift);
config_dword |= (data << shift);
 
HAL_GALILEO_PUTPCI(bus, devfn,
HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET, config_dword);
 
(void)pci_config_errcheck();
}
 
void cyg_hal_plf_pci_cfg_write_byte (cyg_uint32 bus,
cyg_uint32 devfn,
cyg_uint32 offset,
cyg_uint8 data)
{
cyg_uint32 config_dword, shift;
 
HAL_GALILEO_PUTREG(HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET,
HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE |
(bus << 16) | (devfn << 8) | (offset & ~3));
 
HAL_GALILEO_GETPCI(bus, devfn,
HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET, config_dword);
if (pci_config_errcheck())
return;
 
shift = (offset & 3) * 8;
config_dword &= ~(0xff << shift);
config_dword |= (data << shift);
 
HAL_GALILEO_PUTPCI(bus, devfn,
HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET, config_dword);
 
(void)pci_config_errcheck();
}
 
#endif // CYGPKG_IO_PCI
 
//--------------------------------------------------------------------------
// End of plf_misc.c
/ocelot/v2_0/misc/redboot_RAM.ecm
0,0 → 1,70
cdl_savefile_version 1;
cdl_savefile_command cdl_savefile_version {};
cdl_savefile_command cdl_savefile_command {};
cdl_savefile_command cdl_configuration { description hardware template package };
cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
 
cdl_configuration eCos {
description "" ;
hardware ocelot ;
template redboot ;
package -hardware CYGPKG_HAL_MIPS v2_0 ;
package -hardware CYGPKG_HAL_MIPS_RM7000 v2_0 ;
package -hardware CYGPKG_HAL_MIPS_RM7000_OCELOT v2_0 ;
package -hardware CYGPKG_IO_PCI v2_0 ;
package -hardware CYGPKG_DEVS_FLASH_MIPS_OCELOT v2_0 ;
package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX v2_0 ;
package -hardware CYGPKG_IO_SERIAL_GENERIC_16X5X v2_0 ;
package -hardware CYGPKG_DEVS_ETH_INTEL_I82559 v2_0 ;
package -hardware CYGPKG_DEVS_ETH_MIPS_RM7000_OCELOT v2_0 ;
package -template CYGPKG_HAL v2_0 ;
package -template CYGPKG_INFRA v2_0 ;
package -template CYGPKG_REDBOOT v2_0 ;
package CYGPKG_IO_ETH_DRIVERS v2_0 ;
package CYGPKG_IO_FLASH v2_0 ;
};
 
cdl_option CYGBLD_BUILD_GDB_STUBS {
user_value 0
};
 
cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
user_value 32768
};
 
cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
user_value 0
};
 
cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
inferred_value 0
};
 
cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
inferred_value 1
};
 
cdl_option CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT {
inferred_value 1
};
 
cdl_option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT {
inferred_value 0
};
 
cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
inferred_value 0 0
};
 
cdl_component CYGBLD_BUILD_REDBOOT {
user_value 1
};
 
cdl_option CYGHWR_DEVS_FLASH_AMD_AM29F040B {
inferred_value 1
};
 
 
/ocelot/v2_0/misc/redboot_ROM.ecm
0,0 → 1,78
cdl_savefile_version 1;
cdl_savefile_command cdl_savefile_version {};
cdl_savefile_command cdl_savefile_command {};
cdl_savefile_command cdl_configuration { description hardware template package };
cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
 
cdl_configuration eCos {
description "" ;
hardware ocelot ;
template redboot ;
package -hardware CYGPKG_HAL_MIPS v2_0 ;
package -hardware CYGPKG_HAL_MIPS_RM7000 v2_0 ;
package -hardware CYGPKG_HAL_MIPS_RM7000_OCELOT v2_0 ;
package -hardware CYGPKG_IO_PCI v2_0 ;
package -hardware CYGPKG_DEVS_FLASH_MIPS_OCELOT v2_0 ;
package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX v2_0 ;
package -hardware CYGPKG_IO_SERIAL_GENERIC_16X5X v2_0 ;
package -hardware CYGPKG_DEVS_ETH_INTEL_I82559 v2_0 ;
package -hardware CYGPKG_DEVS_ETH_MIPS_RM7000_OCELOT v2_0 ;
package -template CYGPKG_HAL v2_0 ;
package -template CYGPKG_INFRA v2_0 ;
package -template CYGPKG_REDBOOT v2_0 ;
package CYGPKG_IO_ETH_DRIVERS v2_0 ;
package CYGPKG_IO_FLASH v2_0 ;
};
 
cdl_option CYGBLD_BUILD_GDB_STUBS {
user_value 0
};
 
cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
user_value 32768
};
 
cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
user_value 0
};
 
cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
inferred_value 0
};
 
cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
inferred_value 1
};
 
cdl_option CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT {
inferred_value 1
};
 
cdl_option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT {
inferred_value 0
};
 
cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
inferred_value 0 0
};
 
cdl_option CYGSEM_HAL_ROM_MONITOR {
inferred_value 1
};
 
cdl_component CYG_HAL_STARTUP {
user_value ROM
};
 
cdl_component CYGBLD_BUILD_REDBOOT {
user_value 1
};
 
cdl_option CYGHWR_DEVS_FLASH_AMD_AM29F040B {
inferred_value 1
};
 
 
/var/v2_0/cdl/hal_mips_rm7000.cdl
0,0 → 1,163
# ====================================================================
#
# hal_mips_rm7000.cdl
#
# MIPS/RM7000 variant architectural HAL package configuration data
#
# ====================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
# ====================================================================
######DESCRIPTIONBEGIN####
#
# Author(s): jskov
# Original data: bartv, nickg
# Contributors:
# Date: 2000-05-15
#
#####DESCRIPTIONEND####
#
# ====================================================================
 
cdl_package CYGPKG_HAL_MIPS_RM7000 {
display "RM7000 variant"
parent CYGPKG_HAL_MIPS
hardware
include_dir cyg/hal
define_header hal_mips_rm7000.h
description "
The RM7000 architecture HAL package provides generic support
for this processor architecture. It is also necessary to
select a specific target platform HAL package."
 
cdl_component CYGPKG_HAL_MIPS_RM7000A {
display "RM7000A microprocessor"
default_value 1
implements CYGINT_HAL_MIPS_VARIANT
description "
The RM7000A microprocessor. This is chip which in addition to
the RM7000 processor core has built in second level cache
of 256kB."
 
define_proc {
# Sizes are configurable (on the core). Should be configurable.
puts $::cdl_header "#define CYGHWR_HAL_DCACHE_SIZE 16384"
puts $::cdl_header "#define CYGHWR_HAL_ICACHE_SIZE 16384"
}
 
cdl_option CYGHWR_HAL_MIPS_64BIT {
display "Variant 64 bit architecture support"
description "
While the RM7000 is a 64bit CPU, only its 32bit mode is
currently supported in eCos."
calculated 0
}
 
# This is optional (on the core). Should be configurable.
cdl_option CYGHWR_HAL_MIPS_FPU {
display "Variant FPU support"
calculated 1
}
 
cdl_interface CYGINT_HAL_MIPS_FPU_64BIT {
display "Variant 64 bit FPU support interface"
}
 
cdl_option CYGHWR_HAL_MIPS_FPU_64BIT {
display "Variant 64 bit FPU support"
calculated { CYGINT_HAL_MIPS_FPU_64BIT == 1 ? 1 : 0 }
}
 
cdl_option CYGHWR_HAL_MIPS_FPU_32BIT {
display "Variant 32 bit FPU support"
calculated { CYGINT_HAL_MIPS_FPU_64BIT == 0 ? 1 : 0 }
}
 
# FGRn+1 is most significant part of the FGRn&FGRn+1 pair of FPRn/2
# This is true for BE mips2 mode at least. Not sure about fp64 mode
cdl_option CYGPKG_HAL_MIPS_DOUBLE_LSBFIRST {
active_if CYGHWR_HAL_MIPS_FPU_32BIT
calculated 1
}
 
cdl_interface CYGINT_HAL_MIPS_MSBFIRST {
no_define
display "CPU Variant big-endian interface"
}
 
cdl_option CYGPKG_HAL_MIPS_MSBFIRST {
display "CPU Variant big-endian"
calculated { CYGINT_HAL_MIPS_MSBFIRST == 0 ? 0 : 1 }
}
 
cdl_option CYGPKG_HAL_MIPS_LSBFIRST {
display "CPU Variant little-endian"
calculated { CYGINT_HAL_MIPS_MSBFIRST != 0 ? 0 : 1 }
}
}
 
define_proc {
puts $::cdl_header "#include <pkgconf/hal_mips.h>"
}
 
compile var_misc.c variant.S var_mk_defs.c
 
# The "-o file" is a workaround for CR100958 - without it the
# output file would end up in the source directory under CygWin.
# n.b. grep does not behave itself under win32
make -priority 1 {
<PREFIX>/include/cyg/hal/var_defs.inc : <PACKAGE>/src/var_mk_defs.c
$(CC) $(CFLAGS) $(INCLUDE_PATH) -Wp,-MD,var_defs.tmp -o var_mk_defs.tmp -S $<
fgrep .equ var_mk_defs.tmp | sed s/#// > $@
@echo $@ ": \\" > $(notdir $@).deps
@tail +2 var_defs.tmp >> $(notdir $@).deps
@echo >> $(notdir $@).deps
@rm var_defs.tmp var_mk_defs.tmp
}
 
make {
<PREFIX>/lib/target.ld: <PACKAGE>/src/mips_rm7000.ld
$(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(CFLAGS) -o $@ $<
@echo $@ ": \\" > $(notdir $@).deps
@tail +2 target.tmp >> $(notdir $@).deps
@echo >> $(notdir $@).deps
@rm target.tmp
}
 
cdl_option CYGBLD_LINKER_SCRIPT {
display "Linker script"
flavor data
no_define
calculated { "src/mips_rm7000.ld" }
}
}
/var/v2_0/include/var_cache.h
0,0 → 1,199
#ifndef CYGONCE_VAR_CACHE_H
#define CYGONCE_VAR_CACHE_H
 
//=============================================================================
//
// var_cache.h
//
// HAL cache control API
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors:nickg, jskov
// Date: 2000-05-09
// Purpose: Cache control API
// Description: The macros defined here provide the HAL APIs for handling
// cache control operations.
// Usage:
// #include <cyg/hal/imp_cache.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
#include CYGHWR_MEMORY_LAYOUT_H
 
#include <cyg/infra/cyg_type.h>
 
#include <cyg/hal/mips-regs.h>
 
#include <cyg/hal/plf_cache.h>
 
 
//=============================================================================
// Area to use for cache scrubbing. This must be a cache sized area in
// cachable space which can be cleared. Defaults to use the area reserved
// for shared PCI memory space.
#ifndef CYGHWR_HAL_MIPS_RM7000_CACHE_SCRUB_BASE
# define CYGHWR_HAL_MIPS_RM7000_CACHE_SCRUB_BASE CYGMEM_SECTION_pci_window
#endif
 
//=============================================================================
// QED RM7000A
 
#ifdef CYGPKG_HAL_MIPS_RM7000A
 
//-----------------------------------------------------------------------------
// Cache dimensions
 
// Data cache
#define HAL_DCACHE_SIZE CYGHWR_HAL_DCACHE_SIZE // size in bytes
#define HAL_DCACHE_LINE_SIZE 32 // Size of a data cache line
#define HAL_DCACHE_WAYS 4 // Associativity of the cache
 
// Instruction cache
#define HAL_ICACHE_SIZE CYGHWR_HAL_ICACHE_SIZE // size in bytes
#define HAL_ICACHE_LINE_SIZE 32 // Size of a cache line
#define HAL_ICACHE_WAYS 4 // Associativity of the cache
 
#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
 
//-----------------------------------------------------------------------------
// Global control of data cache
 
//-----------------------------------------------------------------------------
//The RM7000 mostly uses the default MIPS cache controls defined in
//hal_cache.h Here we define the cache enable and disable macros. The
//only control we appear to have is the kseg0 cache state in
//config0. So all these macros at present manipulate this.
 
#ifndef HAL_DCACHE_ENABLE_DEFINED
#define HAL_DCACHE_ENABLE() \
CYG_MACRO_START \
asm volatile ( "mfc0 $2,$16\n" \
"nop; nop; nop\n" \
"la $3,0xFFFFFFF8\n" \
"and $2,$2,$3\n" \
"ori $2,$2,3\n" \
"mtc0 $2,$16\n" \
"nop; nop; nop;\n" \
: \
: \
: "$2", "$3" \
); \
CYG_MACRO_END
#define HAL_DCACHE_ENABLE_DEFINED
#endif
 
// Disable the data cache
#ifndef HAL_DCACHE_DISABLE_DEFINED
#define HAL_DCACHE_DISABLE() \
CYG_MACRO_START \
asm volatile ( "mfc0 $2,$16\n" \
"nop; nop; nop\n" \
"la $3,0xFFFFFFF8\n" \
"and $2,$2,$3\n" \
"ori $2,$2,2\n" \
"mtc0 $2,$16\n" \
"nop; nop; nop;\n" \
: \
: \
: "$2", "$3" \
); \
CYG_MACRO_END
#define HAL_DCACHE_DISABLE_DEFINED
#endif
 
#ifndef HAL_DCACHE_IS_ENABLED_DEFINED
#define HAL_DCACHE_IS_ENABLED(_state_) \
CYG_MACRO_START \
CYG_WORD32 _cstate_; \
asm volatile ( "mfc0 %0,$16\n" \
: "=r"(_cstate_) \
); \
if( (_cstate_ & 7) == 2 ) _state_ = 0; \
else _state_ = 1; \
CYG_MACRO_END
#define HAL_DCACHE_IS_ENABLED_DEFINED
#endif
 
#ifndef HAL_ICACHE_ENABLE_DEFINED
#define HAL_ICACHE_ENABLE() HAL_DCACHE_ENABLE()
#define HAL_ICACHE_ENABLE_DEFINED
#endif
 
// Disable the instruction cache
#ifndef HAL_ICACHE_DISABLE_DEFINED
#define HAL_ICACHE_DISABLE() HAL_DCACHE_DISABLE()
#define HAL_ICACHE_DISABLE_DEFINED
#endif
 
#ifndef HAL_ICACHE_IS_ENABLED_DEFINED
#define HAL_ICACHE_IS_ENABLED(_state_) HAL_DCACHE_IS_ENABLED(_state_)
#define HAL_ICACHE_IS_ENABLED_DEFINED
#endif
 
#if 0 // FIXME: Need this for RM7000A also?
// TX49 cache instruction must not affect the line it executes out of,
// so disable instruction cache before invalidating it.
#define HAL_ICACHE_INVALIDATE_ALL_DEFINED
#define HAL_ICACHE_INVALIDATE_ALL() \
CYG_MACRO_START \
register CYG_ADDRESS _baddr_ = 0x80000000; \
register CYG_ADDRESS _addr_ = 0x80000000; \
register CYG_WORD _state_; \
_HAL_ASM_SET_MIPS_ISA(3); \
HAL_ICACHE_IS_ENABLED( _state_ ); \
HAL_ICACHE_DISABLE(); \
for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \
{ _HAL_ASM_ICACHE_ALL_WAYS(0x00, _addr_); } \
if( _state_ ) HAL_ICACHE_ENABLE(); \
_HAL_ASM_SET_MIPS_ISA(0); \
CYG_MACRO_END
#endif
 
#endif // CYGPKG_HAL_MIPS_RM7000A
 
 
//-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_VAR_CACHE_H
// End of var_cache.h
/var/v2_0/include/var_intr.h
0,0 → 1,178
#ifndef CYGONCE_HAL_VAR_INTR_H
#define CYGONCE_HAL_VAR_INTR_H
 
//==========================================================================
//
// imp_intr.h
//
// RM7000 Interrupt and clock support
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
// Contributors: jskov
// Date: 2000-05-09
// Purpose: RM7000 Interrupt support
// Description: The macros defined here provide the HAL APIs for handling
// interrupts and the clock for variants of the RM7000 MIPS
// architecture.
//
// Usage:
// #include <cyg/hal/var_intr.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/hal/plf_intr.h>
 
//--------------------------------------------------------------------------
// Interrupt controller information
 
#ifndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
#define HAL_INTERRUPT_MASK( _vector_ ) \
CYG_MACRO_START \
if( (_vector_) <= CYGNUM_HAL_INTERRUPT_COMPARE ) \
{ \
asm volatile ( \
"mfc0 $3,$12\n" \
"la $2,0x00000400\n" \
"sllv $2,$2,%0\n" \
"nor $2,$2,$0\n" \
"and $3,$3,$2\n" \
"mtc0 $3,$12\n" \
"nop; nop; nop\n" \
: \
: "r"(_vector_) \
: "$2", "$3" \
); \
} \
else \
{ \
/* int 6:9 are masked in the Interrupt Control register */ \
asm volatile ( \
"cfc0 $3,$20\n" \
"la $2,0x00000004\n" \
"sllv $2,$2,%0\n" \
"nor $2,$2,$0\n" \
"and $3,$3,$2\n" \
"ctc0 $3,$20\n" \
"nop; nop; nop\n" \
: \
: "r"((_vector_) ) \
: "$2", "$3" \
); \
} \
CYG_MACRO_END
 
#define HAL_INTERRUPT_UNMASK( _vector_ ) \
CYG_MACRO_START \
if( (_vector_) <= CYGNUM_HAL_INTERRUPT_COMPARE ) \
{ \
asm volatile ( \
"mfc0 $3,$12\n" \
"la $2,0x00000400\n" \
"sllv $2,$2,%0\n" \
"or $3,$3,$2\n" \
"mtc0 $3,$12\n" \
"nop; nop; nop\n" \
: \
: "r"(_vector_) \
: "$2", "$3" \
); \
} \
else \
{ \
/* int 6:9 are masked in the Interrupt Control register */ \
asm volatile ( \
"cfc0 $3,$20\n" \
"la $2,0x00000004\n" \
"sllv $2,$2,%0\n" \
"or $3,$3,$2\n" \
"ctc0 $3,$20\n" \
"nop; nop; nop\n" \
: \
: "r"((_vector_) ) \
: "$2", "$3" \
); \
} \
CYG_MACRO_END
 
#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
CYG_MACRO_START \
/* All 10 interrupts have pending bits in the cause register */ \
cyg_uint32 _srvector_ = _vector_; \
asm volatile ( \
"mfc0 $3,$13\n" \
"la $2,0x00000400\n" \
"sllv $2,$2,%0\n" \
"nor $2,$2,$0\n" \
"and $3,$3,$2\n" \
"mtc0 $3,$13\n" \
"nop; nop; nop\n" \
: \
: "r"(_srvector_) \
: "$2", "$3" \
); \
CYG_MACRO_END
 
#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ )
 
#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ )
 
#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
 
#endif
 
//--------------------------------------------------------------------------
// Interrupt vectors.
 
// Vectors and handling of these are defined in platform HALs since the
// CPU itself does not have a builtin interrupt controller.
 
//--------------------------------------------------------------------------
// Clock control
 
// This is handled by the default code
 
//--------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_VAR_INTR_H
// End of var_intr.h
/var/v2_0/include/var_arch.h
0,0 → 1,71
#ifndef CYGONCE_HAL_VAR_ARCH_H
#define CYGONCE_HAL_VAR_ARCH_H
 
//==========================================================================
//
// var_arch.h
//
// Architecture specific abstractions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors: nickg, jskov
// Date: 2000-05-15
// Purpose: Define architecture abstractions
// Description: This file contains any extra or modified definitions for
// this variant of the architecture.
// Usage: #include <cyg/hal/var_arch.h>
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>
 
// -------------------------------------------------------------------------
// Although the RM7000 is really a 64 bit CPU, we have defined
// target_register_t elsewhere to be 32-bits because we only support
// 32-bit mode. Registers will still be sent to GDB as 64-bit, but that's
// not relevant for CYG_HAL_GDB_REG.
 
#define CYG_HAL_GDB_REG CYG_WORD32
 
//--------------------------------------------------------------------------
#endif // CYGONCE_HAL_VAR_ARCH_H
// End of var_arch.h
/var/v2_0/include/variant.inc
0,0 → 1,180
#ifndef CYGONCE_HAL_VARIANT_INC
#define CYGONCE_HAL_VARIANT_INC
##=============================================================================
##
## variant.inc
##
## RM7000 family assembler header file
##
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
##=============================================================================
#######DESCRIPTIONBEGIN####
##
## Author(s): nickg
## Contributors:nickg, jskov
## Date: 2000-05-10
## Purpose: RM7000 family definitions.
## Description: This file contains various definitions and macros that are
## useful for writing assembly code for the RM7000 CPU family.
## Usage:
## #include <cyg/hal/variant.inc>
## ...
##
##
######DESCRIPTIONEND####
##
##=============================================================================
 
#include <pkgconf/hal.h>
#include <cyg/hal/mips.inc>
#include <cyg/hal/platform.inc>
#include <cyg/hal/var_defs.inc>
 
##-----------------------------------------------------------------------------
## Define CPU variant for architecture HAL.
#define CYG_HAL_MIPS_RM7000
 
#------------------------------------------------------------------------------
# Set up initial value for config register. Sets endian mode and
# disables the cache on kseg0.
 
#if defined(CYGPKG_HAL_MIPS_MSBFIRST)
# define INITIAL_CONFIG0 0x00008002
#elif defined(CYGPKG_HAL_MIPS_LSBFIRST)
# define INITIAL_CONFIG0 0x00000002
#else
# error MIPS endianness not set by configuration
#endif
 
#------------------------------------------------------------------------------
# Set up initial value for FPU FCR31 register. We set the FS bit to flush
# denormalized results to zero and enable div-by-zero exceptions.
 
#ifndef CYG_HAL_MIPS_FCSR_INIT
#define CYG_HAL_MIPS_FCSR_INIT 0x01000400
#endif
 
#------------------------------------------------------------------------------
# Cache macros.
#ifndef CYGPKG_HAL_MIPS_CACHE_DEFINED
 
.macro hal_cache_init
 
mfc0 v0,config0 # disable Kseg0 caching in config0 register
nop
nop
la v1,0xfffffff8
and v0,v0,v1
ori v0,v0,2
mtc0 v0,config0
nop
nop
nop
 
.set mips3 # Set ISA to MIPS 3 to allow cache insns
 
# Now ensure the caches are invalidated. The caches are NOT cleared or
# invalidated on non-power-up resets and may come up in a random state
# on power-up. Hence they may contain stale or randomly bogus data.
# Here we use the index-store-tag cache operation to clear all the
# cache tags and states to zero. This will render them all invalid on
# the RM7000.
 
mtc0 zero,taglo
mtc0 zero,taghi
 
# D-cache:
la t0,CYGHWR_HAL_MIPS_RM7000_CACHE_SCRUB_BASE
ori t1,t0,HAL_DCACHE_SIZE
1:
cache 0x09,0x0000(t0)
cache 0x09,0x1000(t0)
cache 0x09,0x2000(t0)
cache 0x09,0x3000(t0)
 
# Clear area so Icache loads below will read valid
# instructions.
sw zero,0x00(t0)
sw zero,0x04(t0)
sw zero,0x08(t0)
sw zero,0x0c(t0)
sw zero,0x10(t0)
sw zero,0x14(t0)
sw zero,0x18(t0)
sw zero,0x1c(t0)
addi t0,t0,0x20
sub v0,t1,t0
bgez v0,1b
nop
 
# I-cache:
la a0,CYGHWR_HAL_MIPS_RM7000_CACHE_SCRUB_BASE
ori a1,a0,HAL_ICACHE_SIZE
1:
cache 0x08,0x0000(a0)
cache 0x08,0x1000(a0)
cache 0x08,0x2000(a0)
cache 0x08,0x3000(a0)
 
# Needs extra scrubbing due to RM7000A erratum #31
cache 0x14,0x0000(a0)
cache 0x14,0x1000(a0)
cache 0x14,0x2000(a0)
cache 0x14,0x3000(a0)
cache 0x08,0x0000(a0)
cache 0x08,0x1000(a0)
cache 0x08,0x2000(a0)
cache 0x08,0x3000(a0)
 
addi a0,a0,0x20
sub v0,a1,a0
bgez v0,1b
nop
 
.set mips0 # reset ISA to default
 
.endm
 
#define CYGPKG_HAL_MIPS_CACHE_DEFINED
 
#endif
 
#------------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_VARIANT_INC
# end of variant.inc
/var/v2_0/ChangeLog
0,0 → 1,106
2003-04-10 Nick Garnett <nickg@balti.calivar.com>
 
* src/mips_rm7000.ld:
Added libsupc++.a to GROUP() directive for GCC versions later than
3.0.
 
2003-04-09 Jonathan Larmour <jifl@eCosCentric.com>
 
* src/mips_rm7000.ld:
Fix .gnulinkonce.s -> .gnu.linkonce.s typo.
 
2001-08-09 Jonathan Larmour <jlarmour@redhat.com>
 
* include/var_intr.h: Move HAL_INTERRUPT_ interrupt controller
access macros here from Ocelot HAL.
 
2001-06-25 Jesper Skov <jskov@redhat.com>
 
* include/var_cache.h: Default definition for
CYGHWR_HAL_MIPS_RM7000_CACHE_SCRUB_BASE.
* src/var_mk_defs.c: export CYGHWR_HAL_MIPS_RM7000_CACHE_SCRUB_BASE.
* include/variant.inc: Use CYGHWR_HAL_MIPS_RM7000_CACHE_SCRUB_BASE.
 
2001-06-08 Jesper Skov <jskov@redhat.com>
 
* include/variant.inc: Scrub cache according to erratum #31.
 
* src/var_mk_defs.c: Added.
 
* cdl/hal_mips_rm7000.cdl: Make var_defs.inc.
 
2001-05-23 Jesper Skov <jskov@redhat.com>
 
* src/mips_rm7000.ld: Added .2ram handling.
 
2001-01-26 Jesper Skov <jskov@redhat.com>
 
* include/variant.inc: Remove hal_intc_decode macro since it's a
change needed in arch.
 
2001-01-25 Jesper Skov <jskov@redhat.com>
 
* include/variant.inc: Added hal_intc_decode macro which masks the
cause register with the status register. Works around what would
appear to be a HW bug.
2001-01-19 Jesper Skov <jskov@redhat.com>
 
* src/var_misc.c (hal_variant_init): Enable caches.
 
* include/variant.inc: Fixed typos in icache clear code.
 
2001-01-10 Jesper Skov <jskov@redhat.com>
 
* cdl/hal_mips_rm7000.cdl: Fix typo.
 
2000-12-07 Jesper Skov <jskov@redhat.com>
 
* src/var_misc.c (hal_variant_init): Disable caches until flash
stuff is working.
 
2000-12-06 Jesper Skov <jskov@redhat.com>
 
* src/mips_rm7000.ld: Include extras.o regardless of CYGPKG_IO
presence.
 
* src/var_misc.c: Enable caches.
 
2000-11-30 Jesper Skov <jskov@redhat.com>
 
* Cloned from hal/mips/tx49
 
//===========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//===========================================================================
/var/v2_0/src/var_mk_defs.c
0,0 → 1,90
//==========================================================================
//
// var_mk_defs.c
//
// HAL (variant) "make defs" program
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): gthomas
// Contributors: gthomas, jskov
// Date: 2001-06-08
// Purpose: Variant dependent definition generator
// Description: This file contains code that can be compiled by the target
// compiler and used to generate machine specific definitions
// suitable for use in assembly code.
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/hal/hal_arch.h> // HAL header
#include <cyg/hal/hal_intr.h> // HAL header
#include <cyg/hal/hal_cache.h> // HAL header
#ifdef CYGPKG_KERNEL
# include <pkgconf/kernel.h>
# include <cyg/kernel/instrmnt.h>
#endif
 
/*
* This program is used to generate definitions needed by
* assembly language modules.
*
* This technique was first used in the OSF Mach kernel code:
* generate asm statements containing #defines,
* compile this file to assembler, and then extract the
* #defines from the assembly-language output.
*/
 
#define DEFINE(sym, val) \
asm volatile("\n\t.equ\t" #sym ",%0" : : "i" (val))
 
int
main(void)
{
// Cache stuff
DEFINE(HAL_DCACHE_SIZE, HAL_DCACHE_SIZE);
DEFINE(HAL_ICACHE_SIZE, HAL_ICACHE_SIZE);
DEFINE(CYGHWR_HAL_MIPS_RM7000_CACHE_SCRUB_BASE, CYGHWR_HAL_MIPS_RM7000_CACHE_SCRUB_BASE);
 
return 0;
}
 
//--------------------------------------------------------------------------
// EOF var_mk_defs.c
/var/v2_0/src/var_misc.c
0,0 → 1,80
//==========================================================================
//
// var_misc.c
//
// HAL implementation miscellaneous functions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors: nickg, jlarmour
// Date: 1999-01-21
// Purpose: HAL miscellaneous functions
// Description: This file contains miscellaneous functions provided by the
// HAL.
//
//####DESCRIPTIONEND####
//
//========================================================================*/
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h> // Base types
#include <cyg/infra/cyg_trac.h> // tracing macros
#include <cyg/infra/cyg_ass.h> // assertion macros
 
#include <cyg/hal/hal_intr.h>
#include <cyg/hal/hal_cache.h>
 
/*------------------------------------------------------------------------*/
// Array which stores the configured priority levels for the configured
// interrupts.
 
volatile CYG_BYTE hal_interrupt_level[CYGNUM_HAL_ISR_COUNT];
 
/*------------------------------------------------------------------------*/
 
void hal_variant_init(void)
{
// The RM7000 only has an enable that works on both caches. So we
// only need to enable one of them for both to work.
//HAL_DCACHE_ENABLE();
HAL_ICACHE_ENABLE();
}
 
/*------------------------------------------------------------------------*/
/* End of var_misc.c */
/var/v2_0/src/variant.S
0,0 → 1,57
##=============================================================================
##
## variant.S
##
## MIPS RM7000 variant code
##
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
##=============================================================================
#######DESCRIPTIONBEGIN####
##
## Author(s): nickg
## Contributors:nickg
## Date: 2000-05-15
## Purpose: MIPS RM7000 variant code
## Description: Variant specific code for RM7000 CPU.
##
######DESCRIPTIONEND####
##
##=============================================================================
 
# Nothing at the moment.
##-----------------------------------------------------------------------------
## end of variant.S
/var/v2_0/src/mips_rm7000.ld
0,0 → 1,373
//===========================================================================
//
// MLT linker script for MIPS RM7000
//
//===========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//===========================================================================
 
#include <pkgconf/system.h>
 
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips",
"elf32-littlemips")
/* The preprocessor defines mips, but we know we're mips :-) */
#undef mips
OUTPUT_ARCH(mips:5000)
 
STARTUP(vectors.o)
ENTRY(reset_vector)
#if defined(EXTRAS)
INPUT(extras.o)
#endif
#if (__GNUC__ >= 3)
GROUP(libtarget.a libgcc.a libsupc++.a)
#else
GROUP(libtarget.a libgcc.a)
#endif
 
/* FIXME: The MLT should pass in the required alignment since it must be
* the same as the VMA's alignment. As a result of this bug, all the
* ROM mlt files have alignment 8, when some should have alignment 4
* (902557-CR)
*/
#define ALIGN_LMA 8
#define FOLLOWING(_section_) AT ((LOADADDR (_section_) + SIZEOF (_section_) + ALIGN_LMA - 1) & ~ (ALIGN_LMA - 1))
#define LMA_EQ_VMA
#define FORCE_OUTPUT . = .
 
#define SECTIONS_BEGIN
 
#if defined(CYG_HAL_STARTUP_RAM)
 
/* this version for RAM startup */
#define SECTION_rom_vectors(_region_, _vma_, _lma_) \
.rom_vectors _vma_ : _lma_ \
{ KEEP (*(.utlb_vector)) \
. = ALIGN(0x80); KEEP(*(.other_vector)) \
/* debug and reset vector not used in RAM version */ \
KEEP(*(.debug_vector)) \
KEEP (*(.reset_vector)) } \
> _region_
 
#elif defined(CYG_HAL_STARTUP_ROM)
 
/* this version for ROM startup */
#define SECTION_rom_vectors(_region_, _vma_, _lma_) \
.rom_vectors _vma_ : _lma_ \
{ KEEP (*(.reset_vector)) \
. = ALIGN(0x100); KEEP (*(.utlb_vector)) \
. = ALIGN(0x80); KEEP(*(.other_vector)) \
. = ALIGN(0x100); KEEP(*(.debug_vector)) } \
> _region_
 
#endif /* ROM startup version of ROM vectors */
 
#define SECTION_ROMISC(_region_, _vma_, _lma_) \
.interp _vma_ : _lma_ { *(.interp) } > _region_ \
.hash : FOLLOWING(.interp) { *(.hash) } > _region_ \
.dynsym : FOLLOWING(.hash) { *(.dynsym) } > _region_ \
.dynstr : FOLLOWING(.dynsym) { *(.dynstr) } > _region_ \
.gnu.version : FOLLOWING(.dynstr) { *(.gnu.version) } > _region_ \
.gnu.version_d : FOLLOWING(.gnu.version) { *(.gnu.version_d) } > _region_ \
.gnu.version_r : FOLLOWING(.gnu.version_d) { *(.gnu.version_r) } > _region_ \
.plt : FOLLOWING(.gnu.version_r) { *(.plt) } > _region_
 
#define SECTION_RELOCS(_region_, _vma_, _lma_) \
.rel.text : \
{ \
*(.rel.text) \
*(.rel.text.*) \
*(.rel.gnu.linkonce.t*) \
} > _region_ \
.rela.text : \
{ \
*(.rela.text) \
*(.rela.text.*) \
*(.rela.gnu.linkonce.t*) \
} > _region_ \
.rel.data : \
{ \
*(.rel.data) \
*(.rel.data.*) \
*(.rel.gnu.linkonce.d*) \
} > _region_ \
.rela.data : \
{ \
*(.rela.data) \
*(.rela.data.*) \
*(.rela.gnu.linkonce.d*) \
} > _region_ \
.rel.rodata : \
{ \
*(.rel.rodata) \
*(.rel.rodata.*) \
*(.rel.gnu.linkonce.r*) \
} > _region_ \
.rela.rodata : \
{ \
*(.rela.rodata) \
*(.rela.rodata.*) \
*(.rela.gnu.linkonce.r*) \
} > _region_ \
.rel.got : { *(.rel.got) } > _region_ \
.rela.got : { *(.rela.got) } > _region_ \
.rel.ctors : { *(.rel.ctors) } > _region_ \
.rela.ctors : { *(.rela.ctors) } > _region_ \
.rel.dtors : { *(.rel.dtors) } > _region_ \
.rela.dtors : { *(.rela.dtors) } > _region_ \
.rel.init : { *(.rel.init) } > _region_ \
.rela.init : { *(.rela.init) } > _region_ \
.rel.fini : { *(.rel.fini) } > _region_ \
.rela.fini : { *(.rela.fini) } > _region_ \
.rel.bss : { *(.rel.bss) } > _region_ \
.rela.bss : { *(.rela.bss) } > _region_ \
.rel.plt : { *(.rel.plt) } > _region_ \
.rela.plt : { *(.rela.plt) } > _region_ \
.rel.dyn : { *(.rel.dyn) } > _region_
 
#define SECTION_init(_region_, _vma_, _lma_) \
.init _vma_ : _lma_ \
{ \
FORCE_OUTPUT; KEEP (*(.init)) \
} > _region_ =0
 
#define SECTION_text(_region_, _vma_, _lma_) \
.text _vma_ : _lma_ \
{ \
_stext = .; _ftext = . ; \
*(.text) \
*(.text.*) \
*(.stub) \
*(.gnu.warning) \
*(.gnu.linkonce.t*) \
*(.mips16.fn.*) *(.mips16.call.*) \
} > _region_ =0 \
_etext = .; PROVIDE (etext = .);
 
#define SECTION_fini(_region_, _vma_, _lma_) \
.fini _vma_ : _lma_ \
{ \
FORCE_OUTPUT; KEEP (*(.fini)) \
} > _region_ =0
 
#define SECTION_rodata(_region_, _vma_, _lma_) \
.rodata _vma_ : _lma_ \
{ \
FORCE_OUTPUT; *(.rodata) *(.rodata.*) *(.gnu.linkonce.r*) \
} > _region_
 
#define SECTION_rodata1(_region_, _vma_, _lma_) \
.rodata1 _vma_ : _lma_ \
{ \
FORCE_OUTPUT; *(.rodata1) *(.rodata1.*) \
} > _region_
 
#define SECTION_vsr_table(_region_, _vma_, _lma_) \
.vsr_table _vma_ : _lma_ \
{ \
FORCE_OUTPUT; *(.vsr_table) \
} > _region_
 
#define SECTION_data(_region_, _vma_, _lma_) \
.data _vma_ : _lma_ \
{ \
__ram_data_start = ABSOLUTE (.); _fdata = . ; \
*(.data) *(.data.*) *(.gnu.linkonce.d*) \
*( .2ram.*) \
. = ALIGN (8); \
SORT(CONSTRUCTORS) \
} > _region_ \
__rom_data_start = LOADADDR(.data);
 
#define SECTION_data1(_region_, _vma_, _lma_) \
.data1 _vma_ : _lma_ \
{ \
FORCE_OUTPUT; *(.data1) *(.data1.*) \
} > _region_
 
#define SECTION_eh_frame(_region_, _vma_, _lma_) \
.eh_frame _vma_ : _lma_ \
{ \
FORCE_OUTPUT; *(.eh_frame) \
} > _region_
 
#define SECTION_gcc_except_table(_region_, _vma_, _lma_) \
.gcc_except_table _vma_ : _lma_ \
{ \
FORCE_OUTPUT; *(.gcc_except_table) \
} > _region_
 
 
/* FIXME: We shouldn't need to define __CTOR_LIST__/__CTOR_END__
and __DTOR_LIST__/__DTOR_END__ except by the PROVIDE lines.
However this doesn't work for old (99r1-era) toolchains, so
leave it for now. */
 
/* The KEEP(*_ctors.o(.ctors)) rule is included to prevent
constructors from libgcc.a from turning up in the image.
They are NULL anyway. */
 
#define SECTION_ctors(_region_, _vma_, _lma_) \
.ctors _vma_ : _lma_ \
{ \
FORCE_OUTPUT; \
KEEP (*crtbegin.o(.ctors)) \
KEEP (*_ctors.o(.ctors)) \
__CTOR_LIST__ = .; \
PROVIDE (__CTOR_LIST__ = .); \
KEEP (*(.ctors)); \
KEEP (*(SORT(.ctors.*))) \
__CTOR_END__ = .; \
PROVIDE (__CTOR_END__ = .); \
} > _region_
 
#define SECTION_dtors(_region_, _vma_, _lma_) \
.dtors _vma_ : _lma_ \
{ \
FORCE_OUTPUT; \
KEEP (*crtbegin.o(.dtors)) \
__DTOR_LIST__ = .; \
PROVIDE (__DTOR_LIST__ = .); \
KEEP (*(SORT(.dtors.*))) \
__DTOR_END__ = .; \
KEEP (*(.dtors)); \
PROVIDE (__DTOR_END__ = .); \
} > _region_
 
#define SECTION_devtab(_region_, _vma_, _lma_) \
.devtab _vma_ : _lma_ \
{ \
FORCE_OUTPUT; \
KEEP(*( SORT (.ecos.table.*))) ; \
} > _region_
 
#define SECTION_got(_region_, _vma_, _lma_) \
_gp = ALIGN(16) + 0x7ff0; \
.got _vma_ : _lma_ \
{ \
FORCE_OUTPUT; *(.got.plt) *(.got) \
} > _region_
 
#define SECTION_dynamic(_region_, _vma_, _lma_) \
.dynamic _vma_ : _lma_ \
{ \
FORCE_OUTPUT; *(.dynamic) \
} > _region_
 
/* We want the small data sections together, so single-instruction offsets
can access them all, and initialized data all before uninitialized, so
we can shorten the on-disk segment size. */
 
#define SECTION_sdata(_region_, _vma_, _lma_) \
.sdata _vma_ : _lma_ \
{ \
FORCE_OUTPUT; *(.sdata) *(.sdata.*) *(.gnu.linkonce.s*) \
} > _region_
 
#define SECTION_lit8(_region_, _vma_, _lma_) \
.lit8 _vma_ : _lma_ \
{ \
FORCE_OUTPUT; *(.lit8) \
} > _region_
 
#define SECTION_lit4(_region_, _vma_, _lma_) \
.lit4 : FOLLOWING(.lit8) \
{ \
FORCE_OUTPUT; *(.lit4) \
} > _region_ \
__ram_data_end = .; _edata = . ; \
PROVIDE (edata = .);
 
#define SECTION_sbss(_region_, _vma_, _lma_) \
__bss_start = .; _fbss = .; \
.sbss _vma_ : _lma_ \
{ \
FORCE_OUTPUT; *(.dynsbss) *(.sbss) *(.sbss.*) *(.scommon) \
} > _region_
 
#define SECTION_bss(_region_, _vma_, _lma_) \
.bss _vma_ : _lma_ \
{ \
*(.dynbss) *(.bss) *(.bss.*) *(COMMON) \
} > _region_ \
__bss_end = .;
 
/* The /DISCARD/ section ensures that the output will not contain a
* .mdebug section as it confuses GDB. This is a workaround for CR 100804.
*/
 
#define SECTIONS_END . = ALIGN(4); _end = .; PROVIDE (end = .); \
/* Stabs debugging sections. */ \
.stab 0 : { *(.stab) } \
.stabstr 0 : { *(.stabstr) } \
.stab.excl 0 : { *(.stab.excl) } \
.stab.exclstr 0 : { *(.stab.exclstr) } \
.stab.index 0 : { *(.stab.index) } \
.stab.indexstr 0 : { *(.stab.indexstr) } \
.comment 0 : { *(.comment) } \
/* DWARF debug sections. \
Symbols in the DWARF debugging sections are relative to \
the beginning of the section so we begin them at 0. */ \
/* DWARF 1 */ \
.debug 0 : { *(.debug) } \
.line 0 : { *(.line) } \
/* GNU DWARF 1 extensions */ \
.debug_srcinfo 0 : { *(.debug_srcinfo) } \
.debug_sfnames 0 : { *(.debug_sfnames) } \
/* DWARF 1.1 and DWARF 2 */ \
.debug_aranges 0 : { *(.debug_aranges) } \
.debug_pubnames 0 : { *(.debug_pubnames) } \
/* DWARF 2 */ \
.debug_info 0 : { *(.debug_info) } \
.debug_abbrev 0 : { *(.debug_abbrev) } \
.debug_line 0 : { *(.debug_line) } \
.debug_frame 0 : { *(.debug_frame) } \
.debug_str 0 : { *(.debug_str) } \
.debug_loc 0 : { *(.debug_loc) } \
.debug_macinfo 0 : { *(.debug_macinfo) } \
/* SGI/MIPS DWARF 2 extensions */ \
.debug_weaknames 0 : { *(.debug_weaknames) } \
.debug_funcnames 0 : { *(.debug_funcnames) } \
.debug_typenames 0 : { *(.debug_typenames) } \
.debug_varnames 0 : { *(.debug_varnames) } \
/* These must appear regardless of . */ \
.gptab.sdata : { *(.gptab.data) *(.gptab.sdata) } \
.gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) } \
/DISCARD/ 0 : { *(.mdebug) }
 
#include CYGHWR_MEMORY_LAYOUT_LDI
 
// 0-0x200 reserved for vectors
hal_vsr_table = 0x80000200;
hal_virtual_vector_table = 0x80000300;

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