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    /openrisc/trunk/rtos/ecos-2.0/packages/hal/mips/tx39
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Rev 27 → Rev 174

/v2_0/cdl/hal_mips_tx39.cdl
0,0 → 1,129
# ====================================================================
#
# hal_mips_tx39.cdl
#
# MIPS/TX39 variant architectural HAL package configuration data
#
# ====================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
# ====================================================================
######DESCRIPTIONBEGIN####
#
# Author(s): jskov
# Original data: bartv, nickg
# Contributors:
# Date: 1999-11-02
#
#####DESCRIPTIONEND####
#
# ====================================================================
 
cdl_package CYGPKG_HAL_MIPS_TX39 {
display "TX39 variant"
parent CYGPKG_HAL_MIPS
hardware
include_dir cyg/hal
define_header hal_mips_tx39.h
description "
The TX39 architecture HAL package provides generic support
for this processor architecture. It is also necessary to
select a specific target platform HAL package."
 
cdl_component CYGPKG_HAL_MIPS_TX3904 {
display "TX3904 microprocessor"
default_value 1
implements CYGINT_HAL_MIPS_VARIANT
description "
The TMPR3904F microprocessor. This is an embedded part that in
addition to the TX39 processor core has built in peripherals
such as memory controllers, DMA controllers, serial ports and
timers/counters."
 
cdl_option CYGHWR_HAL_MIPS_FPU {
display "Variant FPU support"
calculated 0
}
 
cdl_option CYGPKG_HAL_MIPS_MSBFIRST {
display "CPU Variant big-endian"
calculated 1
}
}
 
define_proc {
puts $::cdl_header "#include <pkgconf/hal_mips.h>"
}
 
cdl_option CYGHWR_HAL_MIPS_CPU_FREQ_ACTUAL {
display "Actual CPU frequency"
calculated (CYGHWR_HAL_MIPS_CPU_FREQ == 50 ? 49152000 : \
CYGHWR_HAL_MIPS_CPU_FREQ == 66 ? 66355200 : 0 )
flavor data
legal_values { 49152000 66355200 }
description "
Only the frequencies 50MHz and 66MHz are supported for this
CPU variant."
}
 
cdl_option CYGHWR_HAL_MIPS_TX3904_TRR_REQUIRES_SYNC {
display "Workaround for TX3904 Timer TRR register problem"
flavor bool
default_value { (CYGHWR_HAL_MIPS_CPU_FREQ == 50) ? 1 : 0 }
description "
Early versions of the TX3904 CPU have a bug such that if
coprocessor 0 (CP0) is busy outputting write buffer data, reads
of the clock would return bad values. This option enables a
workaround by not reading the clock until the write buffer
is empty."
}
 
compile hal_diag.c var_misc.c variant.S
 
make {
<PREFIX>/lib/target.ld: <PACKAGE>/src/mips_tx39.ld
$(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(CFLAGS) -o $@ $<
@echo $@ ": \\" > $(notdir $@).deps
@tail +2 target.tmp >> $(notdir $@).deps
@echo >> $(notdir $@).deps
@rm target.tmp
}
 
cdl_option CYGBLD_LINKER_SCRIPT {
display "Linker script"
flavor data
no_define
calculated { "src/mips_tx39.ld" }
}
 
}
/v2_0/include/var_cache.h
0,0 → 1,315
#ifndef CYGONCE_IMP_CACHE_H
#define CYGONCE_IMP_CACHE_H
 
//=============================================================================
//
// imp_cache.h
//
// HAL cache control API
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors: nickg
// Date: 1998-02-17
// Purpose: Cache control API
// Description: The macros defined here provide the HAL APIs for handling
// cache control operations.
// Usage:
// #include <cyg/hal/imp_cache.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>
 
#include <cyg/hal/plf_cache.h>
 
//=============================================================================
// Toshiba TX3904
 
#ifdef CYGPKG_HAL_MIPS_TX3904
 
//-----------------------------------------------------------------------------
// Cache dimensions
 
// Data cache
#define HAL_DCACHE_SIZE 1024 // Size of data cache in bytes
#define HAL_DCACHE_LINE_SIZE 4 // Size of a data cache line
#define HAL_DCACHE_WAYS 2 // Associativity of the cache
 
// Instruction cache
#define HAL_ICACHE_SIZE 4096 // Size of cache in bytes
#define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
#define HAL_ICACHE_WAYS 1 // Associativity of the cache
 
#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
 
//-----------------------------------------------------------------------------
// Global control of data cache
 
// Enable the data cache
// This uses a bit in the config register, which is TX39 specific.
#define HAL_DCACHE_ENABLE_DEFINED
#define HAL_DCACHE_ENABLE() \
{ \
asm volatile ("mfc0 $2,$3;" \
"ori $2,$2,0x0010;" \
"mtc0 $2,$3;" \
: \
: \
: "$2" \
); \
\
}
 
// Disable the data cache
#define HAL_DCACHE_DISABLE_DEFINED
#define HAL_DCACHE_DISABLE() \
{ \
asm volatile ("mfc0 $2,$3;" \
"la $3,0xFFFFFFEF;" \
"and $2,$2,$3;" \
"mtc0 $2,$3;" \
: \
: \
: "$2", "$3" \
); \
\
}
 
 
// Invalidate the entire cache
// The TX39 only has hit-invalidate on the DCACHE, not
// index-invalidate, so we cannot just empty the cache out without
// knowing what is in it. This is annoying. So, the best we can do is
// fill the cache with data that is unlikely to be there
// otherwise. Hence we read bytes from the ROM space since this is
// most likely to be code, and will not get out of sync even if it is not.
#define HAL_DCACHE_INVALIDATE_ALL_DEFINED
#define HAL_DCACHE_INVALIDATE_ALL() \
{ \
volatile CYG_BYTE *addr = (CYG_BYTE *)(0x9fc00000); \
volatile CYG_BYTE tmp = 0; \
int i; \
for( i = 0; i < (HAL_DCACHE_SIZE*2); i += HAL_DCACHE_LINE_SIZE ) \
{ \
tmp = addr[i]; \
} \
}
 
// Synchronize the contents of the cache with memory.
#define HAL_DCACHE_SYNC_DEFINED
#define HAL_DCACHE_SYNC() HAL_DCACHE_INVALIDATE_ALL()
 
// Set the data cache refill burst size
//#define HAL_DCACHE_BURST_SIZE(_size_)
 
// Set the data cache write mode
//#define HAL_DCACHE_WRITE_MODE( _mode_ )
 
//#define HAL_DCACHE_WRITETHRU_MODE 0
//#define HAL_DCACHE_WRITEBACK_MODE 1
 
// Load the contents of the given address range into the data cache
// and then lock the cache so that it stays there.
#define HAL_DCACHE_LOCK_DEFINED
#define HAL_DCACHE_LOCK(_base_, _size_) \
{ \
asm volatile ("mfc0 $2,$7;" \
"ori $2,$2,0x0100;" \
"mtc0 $2,$7;" \
: \
: \
: "$2" \
); \
}
 
// Undo a previous lock operation
#define HAL_DCACHE_UNLOCK_DEFINED
#define HAL_DCACHE_UNLOCK(_base_, _size_) \
{ \
asm volatile ("mfc0 $2,$7;" \
"la $3,0xFFFFFEFF;" \
"and $2,$2,$3;" \
"mtc0 $2,$7;" \
: \
: \
: "$2", "$3" \
); \
}
 
// Unlock entire cache
#define HAL_DCACHE_UNLOCK_ALL_DEFINED
#define HAL_DCACHE_UNLOCK_ALL() HAL_DCACHE_UNLOCK(0,HAL_DCACHE_SIZE)
 
 
//-----------------------------------------------------------------------------
// Data cache line control
 
// Allocate cache lines for the given address range without reading its
// contents from memory.
//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
 
// Write dirty cache lines to memory and invalidate the cache entries
// for the given address range.
//#define HAL_DCACHE_FLUSH( _base_ , _size_ )
#define HAL_DCACHE_FLUSH_DEFINED // Ensure no default definition
 
// Write dirty cache lines to memory for the given address range.
//#define HAL_DCACHE_STORE( _base_ , _size_ )
#define HAL_DCACHE_STORE_DEFINED // Disable default definition
 
//-----------------------------------------------------------------------------
// Global control of Instruction cache
 
// Enable the instruction cache
// This uses a bit in the config register, which is TX39 specific.
#define HAL_ICACHE_ENABLE_DEFINED
#define HAL_ICACHE_ENABLE() \
{ \
asm volatile ("mfc0 $2,$3;" \
"ori $2,$2,0x0020;" \
"mtc0 $2,$3;" \
: \
: \
: "$2" \
); \
\
}
 
// Disable the instruction cache
#define HAL_ICACHE_DISABLE_DEFINED
#define HAL_ICACHE_DISABLE() \
{ \
asm volatile ("mfc0 $2,$3;" \
"la $3,0xFFFFFFDF;" \
"and $2,$2,$3;" \
"mtc0 $2,$3;" \
"j 1f;" \
"nop;" \
".balign 16,0;" \
"1:;" \
: \
: \
: "$2", "$3" \
); \
\
}
 
// Load the contents of the given address range into the instruction cache
// and then lock the cache so that it stays there.
#define HAL_ICACHE_LOCK_DEFINED
#define HAL_ICACHE_LOCK(_base_, _size_) \
{ \
asm volatile ("mfc0 $2,$7;" \
"ori $2,$2,0x0200;" \
"mtc0 $2,$7;" \
: \
: \
: "$2" \
); \
}
 
// Undo a previous lock operation
#define HAL_ICACHE_UNLOCK_DEFINED
#define HAL_ICACHE_UNLOCK(_base_, _size_) \
{ \
asm volatile ("mfc0 $2,$7;" \
"la $3,0xFFFFFDFF;" \
"and $2,$2,$3;" \
"mtc0 $2,$7;" \
: \
: \
: "$2", "$3" \
); \
}
 
// Unlock entire cache
#define HAL_ICACHE_UNLOCK_ALL_DEFINED
#define HAL_ICACHE_UNLOCK_ALL() HAL_ICACHE_UNLOCK(0, HAL_ICACHE_SIZE)
 
//-----------------------------------------------------------------------------
// Instruction cache line control
// On the TX39, the instruction cache must be disabled to use the index-invalidate
// cache operation.
 
// Invalidate the entire cache
// This uses the index-invalidate cache operation.
#define HAL_ICACHE_INVALIDATE_ALL_DEFINED
#define HAL_ICACHE_INVALIDATE_ALL() \
{ \
register CYG_ADDRESS _baddr_ = 0x80000000; \
register CYG_ADDRESS _addr_ = 0x80000000; \
register CYG_WORD _state_; \
HAL_ICACHE_IS_ENABLED(_state_); \
HAL_ICACHE_DISABLE(); \
for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE ) \
{ \
asm volatile ("cache 0x00,0(%0)" : : "r"(_addr_) ); \
} \
if( _state_ ) HAL_ICACHE_ENABLE(); \
}
 
// Invalidate cache lines in the given range without writing to memory.
// This uses the index-invalidate cache operation since the TX39 does not
// have hit-invalidate on the instruction cache.
#define HAL_ICACHE_INVALIDATE_DEFINED
#define HAL_ICACHE_INVALIDATE( _base_ , _asize_ ) \
{ \
register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_); \
register CYG_WORD _size_ = (_asize_); \
register CYG_WORD _state_; \
HAL_ICACHE_IS_ENABLED(_state_); \
HAL_ICACHE_DISABLE(); \
for( ; _addr_ <= _addr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE ) \
{ \
asm volatile ("cache 0,0(%0)" : : "r"(_addr_) ); \
} \
if( _state_ ) HAL_ICACHE_ENABLE(); \
}
 
#endif // CYGPKG_HAL_MIPS_TX3904
 
//-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_IMP_CACHE_H
// End of imp_cache.h
/v2_0/include/var_intr.h
0,0 → 1,318
#ifndef CYGONCE_HAL_IMP_INTR_H
#define CYGONCE_HAL_IMP_INTR_H
 
//==========================================================================
//
// imp_intr.h
//
// TX39 Interrupt and clock support
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors: nickg, jskov,
// gthomas, jlarmour
// Date: 1999-02-16
// Purpose: TX39 Interrupt support
// Description: The macros defined here provide the HAL APIs for handling
// interrupts and the clock for variants of the TX39 MIPS
// architecture.
//
// Usage:
// #include <cyg/hal/imp_intr.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h>
 
#include <cyg/hal/plf_intr.h>
 
//--------------------------------------------------------------------------
// Interrupt vectors.
 
#ifndef CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
 
// These are decoded via the IP bits of the cause
// register when an external interrupt is delivered.
 
#define CYGNUM_HAL_INTERRUPT_1 0
#define CYGNUM_HAL_INTERRUPT_2 1
#define CYGNUM_HAL_INTERRUPT_3 2
#define CYGNUM_HAL_INTERRUPT_4 3
#define CYGNUM_HAL_INTERRUPT_5 4
#define CYGNUM_HAL_INTERRUPT_6 5
#define CYGNUM_HAL_INTERRUPT_7 6
#define CYGNUM_HAL_INTERRUPT_DMAC1_CH3 7
#define CYGNUM_HAL_INTERRUPT_DMAC1_CH2 8
#define CYGNUM_HAL_INTERRUPT_DMAC0_CH1 9
#define CYGNUM_HAL_INTERRUPT_DMAC0_CH0 10
#define CYGNUM_HAL_INTERRUPT_SIO_0 11
#define CYGNUM_HAL_INTERRUPT_SIO_1 12
#define CYGNUM_HAL_INTERRUPT_TMR_0 13
#define CYGNUM_HAL_INTERRUPT_TMR_1 14
#define CYGNUM_HAL_INTERRUPT_TMR_2 15
#define CYGNUM_HAL_INTERRUPT_0 16
 
// Min/Max ISR numbers and how many there are
#define CYGNUM_HAL_ISR_MIN 0
#define CYGNUM_HAL_ISR_MAX 16
#define CYGNUM_HAL_ISR_COUNT 17
 
// The vector used by the Real time clock
#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TMR_0
 
#define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
 
#endif
 
//--------------------------------------------------------------------------
// Interrupt controller access.
 
#ifndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
 
#if defined(CYGPKG_HAL_MIPS_TX3904)
 
#define CYG_HAL_MIPS_TX3904_ILR0 0xFFFFC010
#define CYG_HAL_MIPS_TX3904_CConR 0xFFFFE000
 
// Array which stores the configured priority levels for the configured
// interrupts.
externC volatile CYG_BYTE hal_interrupt_level[CYGNUM_HAL_ISR_COUNT];
 
 
#define HAL_INTERRUPT_MASK( _vector_ ) \
{ \
HAL_IO_REGISTER _reg_ = CYG_HAL_MIPS_TX3904_ILR0; \
CYG_WORD32 _ilr_; \
_reg_ += (_vector_)&0xC; \
HAL_READ_UINT32( _reg_, _ilr_ ); \
_ilr_ &= ~(7 << (((_vector_)&0x3)<<3)); \
HAL_WRITE_UINT32( _reg_, _ilr_ ); \
}
 
#define HAL_INTERRUPT_UNMASK( _vector_ ) \
{ \
HAL_IO_REGISTER _reg_ = CYG_HAL_MIPS_TX3904_ILR0; \
CYG_WORD32 _ilr_; \
_reg_ += (_vector_)&0xC; \
HAL_READ_UINT32( _reg_, _ilr_ ); \
_ilr_ |= hal_interrupt_level[_vector_] << (((_vector_)&0x3)<<3); \
HAL_WRITE_UINT32( _reg_, _ilr_ ); \
}
 
#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
{ \
if( _vector_ <= CYGNUM_HAL_INTERRUPT_7 || \
_vector_ == CYGNUM_HAL_INTERRUPT_0 ) \
{ \
cyg_uint32 _v_ = _vector_ + 1; \
cyg_uint8 _reg_; \
\
/* adjust vector to bit offset in CConR */ \
if( _v_ == CYGNUM_HAL_INTERRUPT_0 + 1 ) _v_ = 0; \
\
/* get CConR */ \
HAL_READ_UINT8( CYG_HAL_MIPS_TX3904_CConR+1, _reg_ ); \
\
/* clear old value and set new */ \
_reg_ &= ~(7 << 5); \
_reg_ |= _v_ << 5; \
HAL_WRITE_UINT8( CYG_HAL_MIPS_TX3904_CConR+1, _reg_); \
} \
}
 
#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \
{ \
if( _vector_ <= CYGNUM_HAL_INTERRUPT_7 || \
_vector_ == CYGNUM_HAL_INTERRUPT_0 ) \
{ \
cyg_uint32 _v_ = _vector_ + 1; \
cyg_uint32 _val_ = 0; \
cyg_uint16 _reg_; \
\
/* adjust vector to bit offset in CConR */ \
if( _v_ == CYGNUM_HAL_INTERRUPT_0 + 1 ) _v_ = 0; \
_v_ <<= 1; \
\
/* set bits according to requirements */ \
if( _up_ ) _val_ |= 1; \
if( !(_level_) ) _val_ |= 2; \
\
/* get CConR */ \
HAL_READ_UINT16( CYG_HAL_MIPS_TX3904_CConR+2, _reg_ ); \
\
/* clear old value and set new */ \
_reg_ &= ~(3 << _v_); \
_reg_ |= _val_ << _v_; \
HAL_WRITE_UINT16( CYG_HAL_MIPS_TX3904_CConR+2, _reg_ ); \
} \
}
 
#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \
{ \
HAL_IO_REGISTER _reg_ = CYG_HAL_MIPS_TX3904_ILR0; \
CYG_WORD32 _ilr_; \
_reg_ += (_vector_)&0xC; \
HAL_READ_UINT32( _reg_, _ilr_ ); \
_ilr_ |= (_level_) << (((_vector_)&0x3)<<3); \
HAL_WRITE_UINT32( _reg_, _ilr_ ); \
hal_interrupt_level[_vector_] = _level_; \
}
 
#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
 
#else
 
#error Unspecified TX39 variant
 
#endif
 
#endif
 
//--------------------------------------------------------------------------
// Clock control
 
#ifndef CYGHWR_HAL_CLOCK_CONTROL_DEFINED
 
#if defined(CYGPKG_HAL_MIPS_TX3904)
 
#define CYG_HAL_MIPS_TX3904_TIMER_BASE 0xFFFFF000
#define CYG_HAL_MIPS_TX3904_TIMER_CR (CYG_HAL_MIPS_TX3904_TIMER_BASE + 0x00)
#define CYG_HAL_MIPS_TX3904_TIMER_SR (CYG_HAL_MIPS_TX3904_TIMER_BASE + 0x04)
#define CYG_HAL_MIPS_TX3904_TIMER_CPR (CYG_HAL_MIPS_TX3904_TIMER_BASE + 0x08)
#define CYG_HAL_MIPS_TX3904_TIMER_IMR (CYG_HAL_MIPS_TX3904_TIMER_BASE + 0x10)
#define CYG_HAL_MIPS_TX3904_TIMER_DR (CYG_HAL_MIPS_TX3904_TIMER_BASE + 0x20)
#define CYG_HAL_MIPS_TX3904_TIMER_RR (CYG_HAL_MIPS_TX3904_TIMER_BASE + 0xF0)
 
#define HAL_CLOCK_INITIALIZE( _period_ ) \
{ \
HAL_WRITE_UINT32( CYG_HAL_MIPS_TX3904_TIMER_DR, 0x00000003 ); \
HAL_WRITE_UINT32( CYG_HAL_MIPS_TX3904_TIMER_CPR, _period_ ); \
HAL_WRITE_UINT32( CYG_HAL_MIPS_TX3904_TIMER_SR, 0x00000000 ); \
HAL_WRITE_UINT32( CYG_HAL_MIPS_TX3904_TIMER_IMR, 0x00008001 ); \
HAL_WRITE_UINT32( CYG_HAL_MIPS_TX3904_TIMER_CR, 0x000000C0 ); \
}
 
#define HAL_CLOCK_RESET( _vector_, _period_ ) \
{ \
HAL_WRITE_UINT32( CYG_HAL_MIPS_TX3904_TIMER_SR, 0x00000000 ); \
}
 
#if defined(CYGHWR_HAL_MIPS_TX3904_TRR_REQUIRES_SYNC) && \
!defined(CYGPKG_HAL_MIPS_SIM)
 
// We need to sync and check the coprocessor 0 condition - this
// indicates whether data is present in the write buffer. We need to
// wait until the data to be written is flushed out. This works
// around a tx39 bug. gcc will insert a NOP after the asm insns.
 
# define HAL_CLOCK_READ( _pvalue_ ) \
CYG_MACRO_START \
asm volatile ( \
"sync; nop; 1: ; bc0f 1b" \
: \
: \
: "$0" \
); \
HAL_READ_UINT32( CYG_HAL_MIPS_TX3904_TIMER_RR, *(_pvalue_) ); \
CYG_MACRO_END
 
#else
 
# define HAL_CLOCK_READ( _pvalue_ ) \
CYG_MACRO_START \
HAL_READ_UINT32( CYG_HAL_MIPS_TX3904_TIMER_RR, *(_pvalue_) ); \
CYG_MACRO_END
 
#endif
 
#if defined(CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY) && \
!defined(HAL_CLOCK_LATENCY)
#define HAL_CLOCK_LATENCY( _pvalue_ ) HAL_CLOCK_READ(_pvalue_)
#endif
 
#define CYGHWR_HAL_CLOCK_CONTROL_DEFINED
 
#else
 
#error Unspecified TX39 variant
 
#endif
 
#endif
 
//--------------------------------------------------------------------------
// Timeout exception support. This is TX39 specific.
 
#if defined(CYGPKG_HAL_MIPS_TX3904)
 
#define HAL_TX39_DEBUG_TOE_ENABLE() \
{ \
HAL_IO_REGISTER _reg_ = CYG_HAL_MIPS_TX3904_CConR; \
CYG_WORD32 _cconr_; \
HAL_READ_UINT32( _reg_, _cconr_); \
_cconr_ |= 0x04000000; \
HAL_WRITE_UINT32( _reg_, _cconr_); \
}
 
#define HAL_TX39_DEBUG_TOE_DISABLE() \
{ \
HAL_IO_REGISTER _reg_ = CYG_HAL_MIPS_TX3904_CConR; \
CYG_WORD32 _cconr_; \
HAL_READ_UINT32( _reg_, _cconr_); \
_cconr_ &= 0xFBFFFFFF; \
HAL_WRITE_UINT32( _reg_, _cconr_); \
}
 
#else
 
#define HAL_TX39_DEBUG_TOE_ENABLE()
 
#define HAL_TX39_DEBUG_TOE_DISABLE()
 
#endif
 
 
//--------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_IMP_INTR_H
// End of imp_intr.h
/v2_0/include/var_arch.h
0,0 → 1,73
#ifndef CYGONCE_HAL_VAR_ARCH_H
#define CYGONCE_HAL_VAR_ARCH_H
 
//==========================================================================
//
// var_arch.h
//
// Architecture specific abstractions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors: nickg
// Date: 1999-02-17
// Purpose: Define architecture abstractions
// Description: This file contains any extra or modified definitions for
// this variant of the architecture.
// Usage: #include <cyg/hal/var_arch.h>
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>
 
#ifdef CYGSEM_HAL_USE_ROM_MONITOR_CygMon
externC int
hal_diag_irq_check(int vector);
 
#define HAL_DIAG_IRQ_CHECK(_vector_, _ret_) \
CYG_MACRO_START \
_ret_ = hal_diag_irq_check((_vector_)); \
CYG_MACRO_END
#endif
 
//--------------------------------------------------------------------------
#endif // CYGONCE_HAL_VAR_ARCH_H
// End of var_arch.h
/v2_0/include/variant.inc
0,0 → 1,281
#ifndef CYGONCE_HAL_VARIANT_INC
#define CYGONCE_HAL_VARIANT_INC
##=============================================================================
##
## variant.inc
##
## TX39 family assembler header file
##
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
##=============================================================================
#######DESCRIPTIONBEGIN####
##
## Author(s): nickg
## Contributors: nickg
## Date: 1999-04-06
## Purpose: TX39 family definitions.
## Description: This file contains various definitions and macros that are
## useful for writing assembly code for the TX39 CPU family.
## Usage:
## #include <cyg/hal/variant.inc>
## ...
##
##
######DESCRIPTIONEND####
##
##=============================================================================
 
#include <pkgconf/hal.h>
#include <cyg/hal/mips.inc>
 
#include <cyg/hal/platform.inc>
 
##-----------------------------------------------------------------------------
## Define CPU variant for architecture HAL.
#define CYG_HAL_MIPS_R3000A
#define CYG_HAL_MIPS_R3900
 
##-----------------------------------------------------------------------------
## Indicate that the ISR tables are defined in variant.S
 
#define CYG_HAL_MIPS_ISR_TABLES_DEFINED
 
##-----------------------------------------------------------------------------
## TX39 Memory controller.
 
#ifndef CYGPKG_HAL_MIPS_MEMC_DEFINED
 
## ROM timing characteristics are dependent on the clock speed.
#if (CYGHWR_HAL_MIPS_CPU_FREQ == 50)
#define ROM_CCR0_INIT 0x00000420
#define DRAM_DREFC_INIT 0x00000180
#define DRAM_DWR0_INIT 0x00111111
#elif (CYGHWR_HAL_MIPS_CPU_FREQ == 66)
#define ROM_CCR0_INIT 0x00000520
#define DRAM_DREFC_INIT 0x00000200
#define DRAM_DWR0_INIT 0x00332222
#else
#error Unsupported clock frequency
#endif
 
## DRAM configuration is dependent on the DRAM device used.
## for 16MByte (4MBit (x4bit) x 8) 0x08024030
## for 4MByte (1MBit (x4bit) x 8) 0x08013020
## for 8MByte (1MBit (x4bit) x 8 x 2 banks) 0x08013020
 
#if defined CYGHWR_HAL_TX39_JMR3904_DRAM_CONFIG_INIT
#define DRAM_CONFIG_INIT CYGHWR_HAL_TX39_JMR3904_DRAM_CONFIG_INIT
#else
#define DRAM_CONFIG_INIT 0x08024030
#endif
 
## Enabling timeout exceptions can result in bogus exceptions under the
## following conditions:
## o half speed bus mode (JMR board uses this mode)
## o code resides on 0 wait SRAM
## o I- and D- caches are enabled
## o a very narrow timing condition of cache refill cycle (not
## descibed here)
## The simple solution is to configure 1 cycle wait state SRAM rather
## than zero.
 
#ifdef CYGHWR_HAL_MIPS_TX39_JMR3904_ENABLE_TOE
#define SRAM_WAIT_INIT 0x00000100
#else
#define SRAM_WAIT_INIT 0x00000000
#endif
 
.macro hal_memc_init
 
# These mappings need to be set up before we
# can use the stack and make calls to other
# functions
 
# If we have been started from Cygmon, it should have
# already done a lot of this, but it should do no harm
# to reinitialize the following registers.
# SCS0,1 base addr of ISA & PCI
la v0,0xffffe010
la v1,0x20201410
sw v1,0(v0)
 
la v0,0xffffe014
la v1,0xfffffcfc
sw v1,0(v0)
 
# ROM configuration
.set at
la v0,0xffff9000
lw v1,0(v0)
and v1,v1,0xffff0004 # keep hardware defaults
or v1,ROM_CCR0_INIT # install our values
sw v1,0(v0)
.set noat
 
# SRAM config
la v0,0xffff9100
la v1,SRAM_WAIT_INIT
sw v1,0(v0)
 
# ISA bus setup
la v0,0xb2100000
la v1,4
sb v1,0(v0)
# Clear IMR (to cope with JMON)
la v0,0xffffc004
la v1,0x00000000
sw v1,0(v0)
 
hal_memc_init_dram
.endm
 
 
.macro hal_memc_init_dram
# DRAM Configuration
la v0, 0xffff8000
la v1, DRAM_CONFIG_INIT
sw v1, 0(v0)
# DBMR0
la v0, 0xffff8004
la v1, 0x00000000
sw v1, 0(v0)
# DWR0
la v0, 0xffff8008
la v1, DRAM_DWR0_INIT
sw v1, 0(v0)
# DREFC - Depends on clock requency
la v0, 0xffff8800
la v1, DRAM_DREFC_INIT
sw v1, 0(v0)
.endm
 
#define CYGPKG_HAL_MIPS_MEMC_DEFINED
#endif
##-----------------------------------------------------------------------------
## TX39 interrupt handling.
 
#ifndef CYGPKG_HAL_MIPS_INTC_DEFINED
 
#ifdef CYGPKG_HAL_MIPS_TX3904
 
# Set all ILRX registers to 0, masking all external interrupts.
.macro hal_intc_init
 
#ifndef CYG_HAL_STARTUP_RAM
la v0,0xFFFFC010
move v1,zero
sw v1,0(v0)
sw v1,4(v0)
sw v1,8(v0)
sw v1,12(v0)
#endif
.endm
 
.macro hal_intc_decode vnum
mfc0 v1,cause # get cause register
nop
srl v1,v1,10 # shift IP bits to ls bits
andi v1,v1,0x7F # isolate IP bits
la v0,hal_intc_translation_table # address of translation table
add v0,v0,v1 # offset of index byte
lb \vnum,0(v0) # load it
.endm
 
#ifndef CYGPKG_HAL_MIPS_INTC_TRANSLATE_DEFINED
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
.macro hal_intc_translate inum,vnum
move \vnum,zero # Just vector zero is supported
.endm
#else
.macro hal_intc_translate inum,vnum
move \vnum,\inum # Vector == interrupt number
.endm
#endif
#endif
 
# This table translates from the 6 bit value supplied in the IP bits
# of the cause register into a 0..16 offset into the ISR tables.
.macro hal_intc_decode_data
hal_intc_translation_table:
.byte 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
.byte 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
.byte 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16
.byte 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16
.endm
 
#define CYGPKG_HAL_MIPS_INTC_DEFINED
 
#else
 
#error Unknown TX39 variant
 
#endif
 
#endif
 
#------------------------------------------------------------------------------
# Diagnostics macros.
#if 0
#ifndef CYGPKG_HAL_MIPS_DIAG_DEFINED
 
# Set up PIO0 for debugging output
.macro hal_diag_init
la v0,0xfffff500
la v1,0xff
sb v1,0(v0)
la v1,0
sb v1,4(v0)
.endm
 
#define CYGPKG_HAL_MIPS_DIAG_DEFINED
#endif
#endif
 
#------------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_VARIANT_INC
# end of variant.inc
/v2_0/ChangeLog
0,0 → 1,230
2003-04-10 Nick Garnett <nickg@balti.calivar.com>
 
* src/mips_tx39.ld:
Added libsupc++.a to GROUP() directive for GCC versions later than
3.0.
 
2003-04-09 Jonathan Larmour <jifl@eCosCentric.com>
 
* src/mips_tx39.ld:
Fix .gnulinkonce.s -> .gnu.linkonce.s typo.
 
2000-10-20 Jesper Skov <jskov@redhat.com>
 
* include/var_cache.h (HAL_DCACHE_INVALIDATE_ALL): Move volatile
keyword before type.
 
2000-08-03 Jonathan Larmour <jlarmour@redhat.co.uk>
 
* src/mips_tx39.ld: Revert below change. It was correct before.
 
2000-06-21 Nick Garnett <nickg@cygnus.co.uk>
 
* src/mips_tx39.ld:
Added underscore to _stext and _etext.
Switched to new table definition mechanism.
 
2000-06-06 Jesper Skov <jskov@redhat.com>
 
* include/var_intr.h (HAL_INTERRUPT_ACKNOWLEDGE,
HAL_INTERRUPT_CONFIGURE): Change the right bits.
(Haruki Kashiwaya)
 
2000-04-06 Jonathan Larmour <jlarmour@redhat.co.uk>
 
* src/mips_tx39.ld: Define __CTOR_LIST__, __CTOR_END__, __DTOR_LIST__,
__DTOR_END__ regardless, for compatibility with old toolchains
 
2000-04-04 Jonathan Larmour <jlarmour@redhat.co.uk>
 
* src/mips_tx39.ld: Make sure some potentially empty sections are
output. Replace __rom_data_start which was accidentally removed.
Split lit section into lit8 and lit4.
 
2000-03-16 Jonathan Larmour <jlarmour@redhat.co.uk>
 
* src/mips_tx39.ld: Update from latest "mips-tx39-elf-ld --verbose"
output so that it properly reflects what the tools expect
 
2000-02-23 Jonathan Larmour <jlarmour@redhat.co.uk>
 
* include/var_intr.h: CYG_HAL_MIPS_SIM -> CYGPKG_HAL_MIPS_SIM
 
2000-02-16 Jesper Skov <jskov@redhat.com>
 
* cdl/hal_mips_tx39.cdl: removed fix me.
 
2000-01-28 Gary Thomas <gthomas@cygnus.co.uk>
 
* src/mips_tx39.ld: Add support for network package.
 
1999-12-21 Jonathan Larmour <jlarmour@cygnus.co.uk>
 
* include/var_arch.h: Rename CYG_HAL_USE_ROM_MONITOR_CYGMON ->
CYGSEM_HAL_USE_ROM_MONITOR_CygMon
 
* src/hal_diag.c: Likewise. Also CYG_HAL_USE_ROM_MONITOR ->
CYGSEM_HAL_USE_ROM_MONITOR throughout
 
* include/pkgconf/hal_mips_tx39.h: Fix typo
 
* cdl/hal_mips_tx39.cdl: Some cosmetic layout changes and fixed typos
Ensure we "puts" to correct CDL header
Add CYGHWR_HAL_MIPS_TX3904_TRR_REQUIRES_SYNC which for some reason
wasn't brought over from ~CDL
 
1999-12-02 John Dallaway <jld@cygnus.co.uk>
 
* cdl/hal_mips_tx39.cdl:
 
Use the <PACKAGE> token in custom rules.
 
1999-12-01 John Dallaway <jld@cygnus.co.uk>
 
* cdl/hal_mips_tx39.cdl:
 
Use the <PREFIX> token in custom rules.
 
1999-11-04 John Dallaway <jld@cygnus.co.uk>
 
* cdl/hal_mips_tx39.cdl:
 
Output custom rule dependency information to .deps files in
the current directory.
 
Dispense with the need to create a 'src' sub-directory.
 
1999-11-02 Jesper Skov <jskov@cygnus.co.uk>
 
* cdl/hal_mips_tx39.cdl: Added.
 
1999-10-26 Nick Garnett <nickg@cygnus.co.uk>
 
* include/variant.inc: Added implementations of hal_intc_translate
macro.
 
1999-10-06 Jonathan Larmour <jlarmour@cygnus.co.uk>
 
* src/PKGconf.mak: Don't create extras.o here any more
 
1999-10-05 Nick Garnett <nickg@cygnus.co.uk>
 
* include/pkgconf/hal_mips_tx39.h: Added define of
CYGPKG_HAL_MIPS_MSBFIRST.
 
1999-09-17 Jonathan Larmour <jlarmour@cygnus.co.uk>
 
* src/hal_diag.c: Only avoid SERIAL0 if CYG_HAL_USE_ROM_MONITOR_CYGMON
since we default to assuming Cygmon
 
* include/variant.inc (hal_memc_init): Don't make conditional on
ROM startup - makes sense anyway so that users can change amount
of memory in system
(hal_memc_init_dram): Likewise
 
* include/var_arch.h (HAL_DIAG_IRQ_CHECK): Give extra return parameter
rather than relying on this being an expression which evaluates
1999-09-16 Hugo Tyson <hmt@cygnus.co.uk>
 
This set of changes with matching ones in arch comes from Mark
Salter's work to make jmr3904 CygMon talk Ethernet.
 
* include/variant.inc: Do not re-initialize and disable all
interrupts if RAM start, this stops networked CygMon working.
Likewise don't re-init memory.
 
* src/hal_diag.c: Add alternate hal_diag...() routines that talk
via CygMon so that ethernet debugging works.
 
* include/var_arch.h: If CYG_HAL_USE_ROM_MONITOR, export macro for
polling unknown interrupts in CygMon, HAL_DIAG_IRQ_CHECK.
1999-08-25 Nick Garnett <nickg@cygnus.co.uk>
 
* include/variant.inc: Added clock-speed dependent values for the
DRAM DWR0 register. Values as suggested by Toshiba in PR20094.
Added improved work-around for TOE problem suggested by Toshiba
in PR20233.
Some code rearranged to eliminate assembler warning messages.
Some general tidying.
 
* include/var_cache.h (HAL_ICACHE_DISABLE): Added jump to aligned
label after disable to avoid potential race with cache. Suggested
by Toshiba in PR20091.
 
1999-06-18 Nick Garnett <nickg@cygnus.co.uk>
 
* include/var_intr.h: Added TX39 specific variant of
HAL_CLOCK_LATENCY().
 
* include/var_cache.h: Added TX39 specific implementation of
HAL_ICACHE_INVALIDATE_ALL().
 
1999-06-16 Jesper Skov <jskov@cygnus.co.uk>
CR 100804 workaround
* src/mips_tx39.ld: Suppress .mdebug in the final output.
 
1999-06-02 Jonathan Larmour <jlarmour@cygnus.co.uk>
 
* src/mips_tx39.ld:
Add .ctors and .dtors sections as required by new compilers, but
keep around old SORT(CONSTRUCTORS) for use by old compilers.
 
1999-05-27 Nick Garnett <nickg@cygnus.co.uk>
 
* src/hal_diag.c (hal_diag_write_char): Tidied away defunct code
and made use of HAL support for user break detection and delivery.
 
1999-05-14 Nick Garnett <nickg@cygnus.co.uk>
 
* src/var_misc.c: Added definition of hal_interrupt_level[].
 
* include/variant.inc:
* src/variant.S:
Added these files. They contain stuff that was previously in the
jmr3904 platform files.
 
* src/PKGconf.mak (COMPILE): Added variant.S
 
1999-05-13 Nick Garnett <nickg@cygnus.co.uk>
 
Imported whole directory tree into main trunk of repository.
1999-05-11 Nick Garnett <nickg@cygnus.co.uk>
 
* include/imp_cache.h
* include/imp_intr.h
* include/impl.h
* src/imp_misc.c:
* include/var_cache.h
* include/var_intr.h
* include/variant.inc
* src/var_misc.c:
Changed references to "imp" and "implementation" to "var" and
"variant" respectively.
 
* include/var_arch.h
File added.
* include/pkgconf/hal_tx39.h:
* include/pkgconf/hal_mips_tx39.h:
File hal_tx39.h renamed to match name synthesized by pkgconf.tcl.
 
1999-04-22 Nick Garnett <nickg@cygnus.co.uk>
 
* include/imp_cache.h: Move cache enables and disables here from
hal_cache.h since they are tx39 specific.
 
1999-04-21 Nick Garnett <nickg@cygnus.co.uk>
 
* src/imp_misc.c: Added this file to contain
hal_implementation_init().
 
* src/PKGconf.mak (COMPILE): Added imp_misc.c.
 
1999-04-13 Nick Garnett <nickg@cygnus.co.uk>
 
* include/pkgconf/hal_tx39.h: Removed superfluous variant level
from configuration data.
 
/v2_0/src/var_misc.c
0,0 → 1,75
//==========================================================================
//
// var_misc.c
//
// HAL implementation miscellaneous functions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors: nickg, jlarmour
// Date: 1999-01-21
// Purpose: HAL miscellaneous functions
// Description: This file contains miscellaneous functions provided by the
// HAL.
//
//####DESCRIPTIONEND####
//
//========================================================================*/
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h> // Base types
#include <cyg/infra/cyg_trac.h> // tracing macros
#include <cyg/infra/cyg_ass.h> // assertion macros
 
#include <cyg/hal/hal_intr.h>
 
/*------------------------------------------------------------------------*/
// Array which stores the configured priority levels for the configured
// interrupts.
 
volatile CYG_BYTE hal_interrupt_level[CYGNUM_HAL_ISR_COUNT];
 
/*------------------------------------------------------------------------*/
 
void hal_variant_init(void)
{
}
 
/*------------------------------------------------------------------------*/
/* End of var_misc.c */
/v2_0/src/variant.S
0,0 → 1,108
##=============================================================================
##
## variant.S
##
## MIPS JMR-TX3904 variant code
##
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
##=============================================================================
#######DESCRIPTIONBEGIN####
##
## Author(s): nickg
## Contributors: nickg
## Date: 1999-04-20
## Purpose: MIPS JMR-TX3904 variant code
## Description: Variant specific code for JMR-TX3904 board.
##
##
##
##
######DESCRIPTIONEND####
##
##=============================================================================
 
#include <pkgconf/system.h>
#include <pkgconf/hal.h>
 
#ifdef CYGPKG_KERNEL
# include <pkgconf/kernel.h>
#endif
#include <cyg/hal/arch.inc>
##-----------------------------------------------------------------------------
# Interrupt vector tables.
# These tables contain the isr, data and object pointers used to deliver
# interrupts to user code.
.extern hal_default_isr
.data
 
.globl hal_interrupt_handlers
hal_interrupt_handlers:
.long hal_default_isr
.long hal_default_isr
.long hal_default_isr
.long hal_default_isr
.long hal_default_isr
.long hal_default_isr
.long hal_default_isr
.long hal_default_isr
.long hal_default_isr
.long hal_default_isr
.long hal_default_isr
.long hal_default_isr
.long hal_default_isr
.long hal_default_isr
.long hal_default_isr
.long hal_default_isr
.long hal_default_isr
 
.globl hal_interrupt_data
hal_interrupt_data:
.rept 17
.long 0
.endr
 
.globl hal_interrupt_objects
hal_interrupt_objects:
.rept 17
.long 0
.endr
 
##-----------------------------------------------------------------------------
## end of variant.S
/v2_0/src/hal_diag.c
0,0 → 1,760
/*=============================================================================
//
// hal_diag.c
//
// HAL diagnostic output code
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors: nickg
// Date: 1998-03-02
// Purpose: HAL diagnostic output
// Description: Implementations of HAL diagnostic output support.
//
//####DESCRIPTIONEND####
//
//===========================================================================*/
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h> // base types
#include <cyg/infra/cyg_trac.h> // tracing macros
#include <cyg/infra/cyg_ass.h> // assertion macros
 
#include <cyg/hal/hal_arch.h>
#include <cyg/hal/hal_diag.h>
 
#include <cyg/hal/hal_intr.h>
 
#include <cyg/hal/hal_io.h>
 
/*---------------------------------------------------------------------------*/
 
//#define CYG_KERNEL_DIAG_LCD
#define CYG_KERNEL_DIAG_SERIAL0 // For ROM start but see immediately below:
 
#if defined(CYGSEM_HAL_USE_ROM_MONITOR_CygMon)
#undef CYG_KERNEL_DIAG_SERIAL0
#undef CYG_KERNEL_DIAG_LCD
#define CYG_KERNEL_DIAG_CYGMON
#define CYG_KERNEL_DIAG_GDB
 
#endif
 
/*---------------------------------------------------------------------------*/
 
static cyg_uint8 leds = 0;
 
void hal_diag_led(int x)
{
// return;
leds ^= x;
HAL_WRITE_UINT8( 0xfffff504, leds);
 
#if 0
{
int i;
 
for( i = 0; i < 0x00020000; i++ );
}
#endif
}
 
/*---------------------------------------------------------------------------*/
 
#if defined(CYG_KERNEL_DIAG_SERIAL0) || defined(CYG_KERNEL_DIAG_CYGMON)
 
#define DIAG_BASE 0xfffff300
#define DIAG_SLCR (DIAG_BASE+0x00)
#define DIAG_SLSR (DIAG_BASE+0x04)
#define DIAG_SLDICR (DIAG_BASE+0x08)
#define DIAG_SLDISR (DIAG_BASE+0x0C)
#define DIAG_SFCR (DIAG_BASE+0x10)
#define DIAG_SBRG (DIAG_BASE+0x14)
#define DIAG_TFIFO (DIAG_BASE+0x20)
#define DIAG_RFIFO (DIAG_BASE+0x30)
 
#define BRG_T0 0x0000
#define BRG_T2 0x0100
#define BRG_T4 0x0200
#define BRG_T5 0x0300
 
 
void hal_diag_init()
{
#if defined(CYGSEM_HAL_USE_ROM_MONITOR)
// If we are using the ROM monitor, it has already
// initialized the serial line.
#else
//hal_diag_led(0x10);
HAL_WRITE_UINT16( DIAG_SLCR , 0x0020 );
 
HAL_WRITE_UINT16( DIAG_SLDICR , 0x0000 );
HAL_WRITE_UINT16( DIAG_SFCR , 0x0000 );
 
#if CYGHWR_HAL_MIPS_CPU_FREQ == 50
// HAL_WRITE_UINT16( DIAG_SBRG , BRG_T2 | 20 ); // 9600 bps
// HAL_WRITE_UINT16( DIAG_SBRG , BRG_T2 | 10 ); // 19200 bps
HAL_WRITE_UINT16( DIAG_SBRG , BRG_T2 | 5 ); // 38400 bps
#elif CYGHWR_HAL_MIPS_CPU_FREQ == 66
// HAL_WRITE_UINT16( DIAG_SBRG , BRG_T2 | 27 ); // 9600 bps
// HAL_WRITE_UINT16( DIAG_SBRG , BRG_T0 | 54 ); // 19200 bps
HAL_WRITE_UINT16( DIAG_SBRG , BRG_T0 | 27 ); // 38400 bps
#else
#error Unsupported CPU frequency
#endif
//hal_diag_led(0x10);
#endif
}
 
void hal_diag_write_char_serial0( char c)
{
CYG_WORD16 disr;
//hal_diag_led(0x20);
 
for(;;)
{
HAL_READ_UINT16( DIAG_SLDISR , disr );
 
if( disr & 0x0002 ) break;
}
 
disr = disr & ~0x0002;
HAL_WRITE_UINT8( DIAG_TFIFO, c );
 
HAL_WRITE_UINT16( DIAG_SLDISR , disr );
 
//hal_diag_led(0x20);
}
 
void hal_diag_drain_serial0(void)
{
CYG_WORD16 disr;
for(;;)
{
HAL_READ_UINT16( DIAG_SLDISR , disr );
 
if( disr & 0x0002 ) break;
}
 
disr = disr & ~0x0002;
HAL_WRITE_UINT16( DIAG_SLDISR , disr );
}
 
void hal_diag_read_char_serial0(char *c)
{
CYG_WORD16 disr;
//hal_diag_led(0x40);
for(;;)
{
HAL_READ_UINT16( DIAG_SLDISR , disr );
 
if( disr & 0x0001 ) break;
}
 
disr = disr & ~0x0001;
HAL_READ_UINT8( DIAG_RFIFO, *c );
HAL_WRITE_UINT16( DIAG_SLDISR , disr );
 
//hal_diag_led(0x40);
}
 
 
#if defined(CYG_KERNEL_DIAG_CYGMON)
void hal_diag_dumb_write_char(char c)
#else
void hal_diag_write_char(char c)
#endif
{
#ifdef CYG_KERNEL_DIAG_GDB
#if 0 //defined(CYGSEM_HAL_USE_ROM_MONITOR)
 
typedef void rom_write_fn(char c);
rom_write_fn *fn = ((rom_write_fn **)0x80000100)[63];
 
fn(c);
#else
static char line[100];
static int pos = 0;
// register volatile cyg_uint16 *volatile tty_status = SERIAL1_SR;
 
// No need to send CRs
if( c == '\r' ) return;
 
line[pos++] = c;
 
if( c == '\n' || pos == sizeof(line) )
{
 
// Disable interrupts. This prevents GDB trying to interrupt us
// while we are in the middle of sending a packet. The serial
// receive interrupt will be seen when we re-enable interrupts
// later.
CYG_INTERRUPT_STATE oldstate;
HAL_DISABLE_INTERRUPTS(oldstate);
while(1)
{
static char hex[] = "0123456789ABCDEF";
cyg_uint8 csum = 0;
int i;
char c1;
hal_diag_write_char_serial0('$');
hal_diag_write_char_serial0('O');
csum += 'O';
for( i = 0; i < pos; i++ )
{
char ch = line[i];
char h = hex[(ch>>4)&0xF];
char l = hex[ch&0xF];
hal_diag_write_char_serial0(h);
hal_diag_write_char_serial0(l);
csum += h;
csum += l;
}
hal_diag_write_char_serial0('#');
hal_diag_write_char_serial0(hex[(csum>>4)&0xF]);
hal_diag_write_char_serial0(hex[csum&0xF]);
 
hal_diag_read_char_serial0( &c1 );
 
if( c1 == '+' ) break;
 
{
extern void cyg_hal_user_break(CYG_ADDRWORD *regs);
extern cyg_bool cyg_hal_is_break(char *buf, int size);
if( cyg_hal_is_break( &c1 , 1 ) )
cyg_hal_user_break( NULL );
}
break;
}
pos = 0;
 
// Wait for all data from serial line to drain
// and clear ready-to-send indication.
hal_diag_drain_serial0();
// And re-enable interrupts
HAL_RESTORE_INTERRUPTS( oldstate );
}
#endif
#else
hal_diag_write_char_serial0(c);
#endif
}
 
 
void hal_diag_read_char(char *c)
{
for(;;)
{
#if defined(CYG_KERNEL_DIAG_GDB) && defined(CYGSEM_HAL_USE_ROM_MONITOR)
 
typedef void rom_read_fn(char *c);
rom_read_fn *fn = ((rom_read_fn **)0x80000100)[62];
 
fn(c);
#else
hal_diag_read_char_serial0(c);
 
#endif
 
#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
if( *c == 3 )
{
// Ctrl-C: breakpoint.
extern void breakpoint(void);
breakpoint();
continue;
}
#elif defined(CYGSEM_HAL_USE_ROM_MONITOR)
if( *c == 3 )
{
// Ctrl-C: breakpoint.
 
// HAL_BREAKPOINT(_breakinst);
typedef void bpt_fn(void);
bpt_fn *bfn = ((bpt_fn **)0x80000100)[61];
 
bfn();
continue;
}
#endif
 
break;
}
}
 
#endif // defined(CYG_KERNEL_DIAG_SERIAL0) || defined(CYG_KERNEL_DIAG_CYGMON)
 
 
#if defined(CYG_KERNEL_DIAG_CYGMON) // only
 
/* This code has been imported from the BSP module. The definitions have
* been left as-is, even though there was scope for doing more, to avoid
* too much drift from the original sources
*/
 
struct bsp_comm_procs {
void *ch_data;
void (*__write)(void *ch_data, const char *buf, int len);
int (*__read)(void *ch_data, char *buf, int len);
void (*__putc)(void *ch_data, char ch);
int (*__getc)(void *ch_data);
int (*__control)(void *ch_data, int func, ...);
};
 
// This is pointed to by entry BSP_NOTVEC_BSP_COMM_PROCS:
typedef struct {
int version; /* version number for future expansion */
void *__ictrl_table;
void *__exc_table;
void *__dbg_vector;
void *__kill_vector;
struct bsp_comm_procs *__console_procs;
struct bsp_comm_procs *__debug_procs;
void *__flush_dcache;
void *__flush_icache;
void *__cpu_data;
void *__board_data;
void *__sysinfo;
int (*__set_debug_comm)(int __comm_id);
int (*__set_console_comm)(int __comm_id);
int (*__set_serial_baud)(int __comm_id, int baud);
void *__dbg_data;
void (*__reset)(void);
int __console_interrupt_flag;
} bsp_shared_t;
 
/*
* Core Exception vectors.
*/
#define BSP_EXC_INT 0
#define BSP_EXC_TLBMOD 1
#define BSP_EXC_TLBL 2
#define BSP_EXC_TLBS 3
#define BSP_EXC_ADEL 4
#define BSP_EXC_ADES 5
#define BSP_EXC_IBE 6
#define BSP_EXC_DBE 7
#define BSP_EXC_SYSCALL 8
#define BSP_EXC_BREAK 9
#define BSP_EXC_ILL 10
#define BSP_EXC_CPU 11
#define BSP_EXC_OV 12
#define BSP_EXC_TRAP 13
#define BSP_EXC_VCEI 14
#define BSP_EXC_FPE 15
#define BSP_EXC_RSV16 16
#define BSP_EXC_RSV17 17
#define BSP_EXC_RSV18 18
#define BSP_EXC_RSV19 19
#define BSP_EXC_RSV20 20
#define BSP_EXC_RSV21 21
#define BSP_EXC_RSV22 22
#define BSP_EXC_WATCH 23
#define BSP_EXC_RSV24 24
#define BSP_EXC_RSV25 25
#define BSP_EXC_RSV26 26
#define BSP_EXC_RSV27 27
#define BSP_EXC_RSV28 28
#define BSP_EXC_RSV29 29
#define BSP_EXC_RSV30 30
#define BSP_EXC_VCED 31
/* tx39 debug exception */
#define BSP_EXC_DEBUG 32
#define BSP_EXC_TLB 33
#define BSP_EXC_NMI 34
/*
* Hack for eCos on tx39 to set an async breakpoint.
*/
#define BSP_VEC_BP_HOOK 35
 
#define BSP_EXC_XTLB 36
#define BSP_EXC_CACHE 37
 
#define BSP_MAX_EXCEPTIONS 38
 
/*
* Another hack for tx39 eCos compatibility.
*/
#if defined(__CPU_R3900__)
#define BSP_VEC_MT_DEBUG 15
#else
#define BSP_VEC_MT_DEBUG 38
#endif
 
#define BSP_VEC_STUB_ENTRY 39
#define BSP_VEC_BSPDATA 40
#define BSP_VEC_MAGIC 41
#define BSP_VEC_IRQ_CHECK 42
 
#define BSP_VEC_PAD 43
#define NUM_VTAB_ENTRIES 44
 
 
#define BSP_MAGIC_VAL 0x55aa4321
 
#define SYS_interrupt 1000
 
// These vectors should be called with:
//
// k0 - Exception Number
 
#define CYGMON_VECTOR_TABLE_BASE 0x80000100
#define CYGMON_VECTOR_TABLE ((CYG_ADDRESS *)CYGMON_VECTOR_TABLE_BASE)
 
#if 0 // UNUSED
static int
hal_bsp_set_debug_comm(int arg)
{
bsp_shared_t *shared;
 
shared = (bsp_shared_t *)
(CYGMON_VECTOR_TABLE[ BSP_VEC_BSPDATA ]);
 
if (0 != shared->__set_debug_comm) {
return (*(shared->__set_debug_comm))(arg);
}
return 0;
}
 
static int
hal_bsp_set_console_comm(int arg)
{
bsp_shared_t *shared;
 
shared = (bsp_shared_t *)
(CYGMON_VECTOR_TABLE[ BSP_VEC_BSPDATA ]);
 
if (0 != shared->__set_console_comm) {
return (*(shared->__set_console_comm))(arg);
}
return 0;
}
#endif // 0 UNUSED
 
static void bsp_trap(int trap_num);
 
static int
hal_bsp_console_write(const void *p, int len)
{
bsp_shared_t *shared;
struct bsp_comm_procs *com;
int magic;
 
/*hal_bsp_set_console_comm(0);*/
 
/* If this is not a BSP-based CygMon, return 0 */
magic = (int)(CYGMON_VECTOR_TABLE[ BSP_VEC_MAGIC ]);
if (magic != BSP_MAGIC_VAL)
return 0;
 
shared = (bsp_shared_t *)
(CYGMON_VECTOR_TABLE[ BSP_VEC_BSPDATA ]);
 
com = shared->__console_procs;
 
if (0 != com) {
shared->__console_interrupt_flag = 0;
com->__write(com->ch_data, p, len);
if (shared->__console_interrupt_flag) {
/* debug interrupt; stop here */
bsp_trap(SYS_interrupt);
}
 
return 1;
}
return 0;
}
 
static void
bsp_trap(int trap_num)
{
asm("syscall\n");
}
 
 
static void
hal_dumb_serial_write(const char *p, int len)
{
int i;
for ( i = 0 ; i < len; i++ ) {
hal_diag_dumb_write_char(p[i]);
}
}
 
void hal_diag_write_char(char c)
{
static char line[100];
static int pos = 0;
 
// No need to send CRs
if( c == '\r' ) return;
 
line[pos++] = c;
 
if( c == '\n' || pos == sizeof(line) ) {
CYG_INTERRUPT_STATE old;
 
// Disable interrupts. This prevents GDB trying to interrupt us
// while we are in the middle of sending a packet. The serial
// receive interrupt will be seen when we re-enable interrupts
// later.
HAL_DISABLE_INTERRUPTS(old);
if ( ! hal_bsp_console_write( line, pos ) )
// then there is no function registered, just spew it out serial
hal_dumb_serial_write( line, pos );
pos = 0;
 
// And re-enable interrupts
HAL_RESTORE_INTERRUPTS(old);
 
}
}
 
int
hal_diag_irq_check(int vector)
{
typedef int irq_check_fn(int irq_nr);
irq_check_fn *fn = (irq_check_fn *)(CYGMON_VECTOR_TABLE[ BSP_VEC_IRQ_CHECK ]);
int magic;
 
/* If this is not a BSP-based CygMon, return 0 */
magic = (int)(CYGMON_VECTOR_TABLE[ BSP_VEC_MAGIC ]);
if (magic != BSP_MAGIC_VAL)
return 0;
 
#if defined(CYGPKG_HAL_MIPS_TX3904)
/* convert vector to BSP irq number */
if (vector == 16)
vector = 2;
else
vector += 3;
#endif
 
return fn(vector);
}
 
#endif // defined(CYG_KERNEL_DIAG_CYGMON) *only*
 
/*---------------------------------------------------------------------------*/
 
#if defined(CYGPKG_HAL_MIPS_TX39_JMR3904) && defined(CYG_KERNEL_DIAG_LCD)
 
/* ----------------------------------------------------------- */
#define ISA_BASE 0xA0000000
#define LCD_DATA *(volatile unsigned char*)(0x13400000+ISA_BASE)
#define LCD_CMD *(volatile unsigned char*)(0x13000000+ISA_BASE)
 
#define DISPCLR 0x01 /* Display Clear */
#define ECURINC 0x06 /* Cursor Increment */
#define DISPCONT 0x08 /* Display Control */
#define BLINK 0x01 /* Blink */
#define CURON 0x02 /* Cursor ON */
#define DISPON 0x04 /* Display ON */
#define INITCMD 0x38 /* Initial Command */
#define DDRAM 0x80 /* DDRAM address */
#define LCDBUSY 0x80 /* Busy */
 
/* ----------------------------------------------------------- */
 
/* */
/* JMZ-LCD202 LCD Display Unit */
/* - Sample Program (for JMR-TX3904) - */
/* */
 
static void readyLCD(){
while(LCD_CMD & LCDBUSY);
}
 
static void outLCD(unsigned char d){
readyLCD();
LCD_DATA = d;
}
 
static void outLCD_CMD(unsigned char d){
readyLCD();
LCD_CMD = d;
}
 
static void INIT_LCD(){
outLCD_CMD(INITCMD);
outLCD_CMD(DISPCONT);
outLCD_CMD(DISPCLR);
outLCD_CMD(ECURINC);
outLCD_CMD(DISPCONT|BLINK|CURON|DISPON);
}
 
#if 0
static void MAIN(){
int i;
static char c[]="JMZ-LCD202 LCD UNIT";
static char d[]="Display Test Sample";
 
INIT_LCD();
outLCD_CMD(DDRAM);
for (i=0;i<20;i++) outLCD(c[i]);
outLCD_CMD(DDRAM+0x40);
for (i=0;i<20;i++) outLCD(d[i]);
}
#endif
 
#define LCD_LINE0 0x00
#define LCD_LINE1 0x40
 
#define LCD_LINE_LENGTH 20
 
static char lcd_line0[LCD_LINE_LENGTH+1];
static char lcd_line1[LCD_LINE_LENGTH+1];
static char *lcd_line[2] = { lcd_line0, lcd_line1 };
static int lcd_curline = 0;
static int lcd_linepos = 0;
 
static void lcd_dis(int add, char *string);
 
void hal_diag_init()
{
int i;
//hal_diag_led(0x10);
 
INIT_LCD();
 
lcd_curline = 0;
lcd_linepos = 0;
 
for( i = 0; i < LCD_LINE_LENGTH; i++ )
lcd_line[0][i] = lcd_line[1][i] = ' ';
 
lcd_line[0][LCD_LINE_LENGTH] = lcd_line[1][LCD_LINE_LENGTH] = 0;
 
lcd_dis( LCD_LINE0, lcd_line[0] );
lcd_dis( LCD_LINE1, lcd_line[1] );
 
#if 0
{
int i;
static char c[]="JMZ-LCD202 LCD UNIT";
static char d[]="Display Test Sample";
 
outLCD_CMD(DDRAM);
for (i=0;i<20;i++) outLCD(c[i]);
outLCD_CMD(DDRAM+0x40);
for (i=0;i<20;i++) outLCD(d[i]);
}
#endif
//hal_diag_led(0x10);
}
 
/* this routine writes the string to the LCD */
/* display after setting the address to add */
static void lcd_dis(int add, char *string)
{
int i;
outLCD_CMD(DDRAM+add);
 
for (i=0 ; i<LCD_LINE_LENGTH ; i++) outLCD(string[i]);
}
 
void hal_diag_write_char( char c)
{
int i;
 
//hal_diag_led(0x20);
// Truncate long lines
if( lcd_linepos >= LCD_LINE_LENGTH ) return;
 
// ignore CR
if( c == '\r' ) return;
if( c == '\n' )
{
lcd_dis( LCD_LINE0, &lcd_line[lcd_curline^1][0] );
lcd_dis( LCD_LINE1, &lcd_line[lcd_curline][0] );
 
// Do a line feed
lcd_curline ^= 1;
lcd_linepos = 0;
for( i = 0; i < LCD_LINE_LENGTH; i++ )
lcd_line[lcd_curline][i] = ' ';
 
return;
}
 
lcd_line[lcd_curline][lcd_linepos++] = c;
//hal_diag_led(0x20);
}
 
void hal_diag_read_char(char *c)
{
//hal_diag_led(0x40);
 
//hal_diag_led(0x40);
}
 
 
#endif
 
 
/*---------------------------------------------------------------------------*/
/* End of hal_diag.c */
/v2_0/src/mips_tx39.ld
0,0 → 1,384
//===========================================================================
//
// MLT linker script for MIPS TX39
//
//===========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//===========================================================================
 
#include <pkgconf/system.h>
 
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips",
"elf32-littlemips")
/* The preprocessor defines mips, but we know we're mips :-) */
#undef mips
OUTPUT_ARCH(mips:3000)
 
STARTUP(vectors.o)
ENTRY(reset_vector)
#ifdef EXTRAS
INPUT(extras.o)
#endif
#if (__GNUC__ >= 3)
GROUP(libtarget.a libgcc.a libsupc++.a)
#else
GROUP(libtarget.a libgcc.a)
#endif
 
/* FIXME: The MLT should pass in the required alignment since it must be
* the same as the VMA's alignment. As a result of this bug, all the JMR3904
* ROM mlt files have alignment 8, when some should have alignment 4
* (902557-CR)
*/
#define ALIGN_LMA 8
#define FOLLOWING(_section_) AT ((LOADADDR (_section_) + SIZEOF (_section_) + ALIGN_LMA - 1) & ~ (ALIGN_LMA - 1))
#define LMA_EQ_VMA
#define FORCE_OUTPUT . = .
 
#define SECTIONS_BEGIN
 
#if defined(CYG_HAL_STARTUP_RAM)
 
/* this version for RAM startup */
#define SECTION_rom_vectors(_region_, _vma_, _lma_) \
.rom_vectors _vma_ : _lma_ \
{ KEEP (*(.utlb_vector)) \
. = ALIGN(0x80); KEEP(*(.other_vector)) \
/* debug and reset vector not used in RAM version */ \
KEEP(*(.debug_vector)) \
KEEP (*(.reset_vector)) } \
> _region_
 
#elif defined(CYG_HAL_STARTUP_ROM)
 
/* this version for ROM startup */
#define SECTION_rom_vectors(_region_, _vma_, _lma_) \
.rom_vectors _vma_ : _lma_ \
{ KEEP (*(.reset_vector)) \
. = ALIGN(0x100); KEEP (*(.utlb_vector)) \
. = ALIGN(0x80); KEEP(*(.other_vector)) \
. = ALIGN(0x100); KEEP(*(.debug_vector)) } \
> _region_
 
#endif /* ROM startup version of ROM vectors */
 
#define SECTION_ROMISC(_region_, _vma_, _lma_) \
.interp _vma_ : _lma_ { *(.interp) } > _region_ \
.hash : FOLLOWING(.interp) { *(.hash) } > _region_ \
.dynsym : FOLLOWING(.hash) { *(.dynsym) } > _region_ \
.dynstr : FOLLOWING(.dynsym) { *(.dynstr) } > _region_ \
.gnu.version : FOLLOWING(.dynstr) { *(.gnu.version) } > _region_ \
.gnu.version_d : FOLLOWING(.gnu.version) { *(.gnu.version_d) } > _region_ \
.gnu.version_r : FOLLOWING(.gnu.version_d) { *(.gnu.version_r) } > _region_ \
.plt : FOLLOWING(.gnu.version_r) { *(.plt) } > _region_
 
#define SECTION_RELOCS(_region_, _vma_, _lma_) \
.rel.text : \
{ \
*(.rel.text) \
*(.rel.text.*) \
*(.rel.gnu.linkonce.t*) \
} > _region_ \
.rela.text : \
{ \
*(.rela.text) \
*(.rela.text.*) \
*(.rela.gnu.linkonce.t*) \
} > _region_ \
.rel.data : \
{ \
*(.rel.data) \
*(.rel.data.*) \
*(.rel.gnu.linkonce.d*) \
} > _region_ \
.rela.data : \
{ \
*(.rela.data) \
*(.rela.data.*) \
*(.rela.gnu.linkonce.d*) \
} > _region_ \
.rel.rodata : \
{ \
*(.rel.rodata) \
*(.rel.rodata.*) \
*(.rel.gnu.linkonce.r*) \
} > _region_ \
.rela.rodata : \
{ \
*(.rela.rodata) \
*(.rela.rodata.*) \
*(.rela.gnu.linkonce.r*) \
} > _region_ \
.rel.got : { *(.rel.got) } > _region_ \
.rela.got : { *(.rela.got) } > _region_ \
.rel.ctors : { *(.rel.ctors) } > _region_ \
.rela.ctors : { *(.rela.ctors) } > _region_ \
.rel.dtors : { *(.rel.dtors) } > _region_ \
.rela.dtors : { *(.rela.dtors) } > _region_ \
.rel.init : { *(.rel.init) } > _region_ \
.rela.init : { *(.rela.init) } > _region_ \
.rel.fini : { *(.rel.fini) } > _region_ \
.rela.fini : { *(.rela.fini) } > _region_ \
.rel.bss : { *(.rel.bss) } > _region_ \
.rela.bss : { *(.rela.bss) } > _region_ \
.rel.plt : { *(.rel.plt) } > _region_ \
.rela.plt : { *(.rela.plt) } > _region_ \
.rel.dyn : { *(.rel.dyn) } > _region_
 
#define SECTION_init(_region_, _vma_, _lma_) \
.init _vma_ : _lma_ \
{ \
FORCE_OUTPUT; KEEP (*(.init)) \
} > _region_ =0
 
#define SECTION_text(_region_, _vma_, _lma_) \
.text _vma_ : _lma_ \
{ \
_stext = .; _ftext = . ; \
*(.text) \
*(.text.*) \
*(.stub) \
*(.gnu.warning) \
*(.gnu.linkonce.t*) \
*(.mips16.fn.*) *(.mips16.call.*) \
} > _region_ =0 \
_etext = .; PROVIDE (etext = .);
 
#define SECTION_fini(_region_, _vma_, _lma_) \
.fini _vma_ : _lma_ \
{ \
FORCE_OUTPUT; KEEP (*(.fini)) \
} > _region_ =0
 
#define SECTION_rodata(_region_, _vma_, _lma_) \
.rodata _vma_ : _lma_ \
{ \
FORCE_OUTPUT; *(.rodata) *(.rodata.*) *(.gnu.linkonce.r*) \
} > _region_
 
#define SECTION_rodata1(_region_, _vma_, _lma_) \
.rodata1 _vma_ : _lma_ \
{ \
FORCE_OUTPUT; *(.rodata1) *(.rodata1.*) \
} > _region_
 
#define SECTION_vsr_table(_region_, _vma_, _lma_) \
.vsr_table _vma_ : _lma_ \
{ \
FORCE_OUTPUT; *(.vsr_table) \
} > _region_
 
#define SECTION_data(_region_, _vma_, _lma_) \
.data _vma_ : _lma_ \
{ \
__ram_data_start = ABSOLUTE (.); _fdata = . ; \
*(.data) *(.data.*) *(.gnu.linkonce.d*) \
. = ALIGN (8); \
SORT(CONSTRUCTORS) \
} > _region_ \
__rom_data_start = LOADADDR(.data);
 
#define SECTION_data1(_region_, _vma_, _lma_) \
.data1 _vma_ : _lma_ \
{ \
FORCE_OUTPUT; *(.data1) *(.data1.*) \
} > _region_
 
#define SECTION_eh_frame(_region_, _vma_, _lma_) \
.eh_frame _vma_ : _lma_ \
{ \
FORCE_OUTPUT; *(.eh_frame) \
} > _region_
 
#define SECTION_gcc_except_table(_region_, _vma_, _lma_) \
.gcc_except_table _vma_ : _lma_ \
{ \
FORCE_OUTPUT; *(.gcc_except_table) \
} > _region_
 
 
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
 
/* We don't want to include the .ctors section from
the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
 
/* FIXME: We shouldn't need to define __CTOR_LIST__/__CTOR_END__
and __DTOR_LIST__/__DTOR_END__ except by the PROVIDE lines.
However this doesn't work for old (99r1-era) toolchains, so
leave it for now. */
 
#define SECTION_ctors(_region_, _vma_, _lma_) \
.ctors _vma_ : _lma_ \
{ \
FORCE_OUTPUT; \
KEEP (*crtbegin.o(.ctors)) \
__CTOR_LIST__ = .; \
PROVIDE (__CTOR_LIST__ = .); \
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) \
KEEP (*(SORT(.ctors.*))) \
KEEP (*(.ctors)) \
__CTOR_END__ = .; \
PROVIDE (__CTOR_END__ = .); \
} > _region_
 
#define SECTION_dtors(_region_, _vma_, _lma_) \
.dtors _vma_ : _lma_ \
{ \
FORCE_OUTPUT; \
KEEP (*crtbegin.o(.dtors)) \
__DTOR_LIST__ = .; \
PROVIDE (__DTOR_LIST__ = .); \
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) \
KEEP (*(SORT(.dtors.*))) \
KEEP (*(.dtors)) \
__DTOR_END__ = .; \
PROVIDE (__DTOR_END__ = .); \
} > _region_
 
#define SECTION_devtab(_region_, _vma_, _lma_) \
.devtab _vma_ : _lma_ \
{ \
FORCE_OUTPUT; \
KEEP(*( SORT (.ecos.table.*))) ; \
} > _region_
 
#define SECTION_got(_region_, _vma_, _lma_) \
_gp = ALIGN(16) + 0x7ff0; \
.got _vma_ : _lma_ \
{ \
FORCE_OUTPUT; *(.got.plt) *(.got) \
} > _region_
 
#define SECTION_dynamic(_region_, _vma_, _lma_) \
.dynamic _vma_ : _lma_ \
{ \
FORCE_OUTPUT; *(.dynamic) \
} > _region_
 
/* We want the small data sections together, so single-instruction offsets
can access them all, and initialized data all before uninitialized, so
we can shorten the on-disk segment size. */
 
#define SECTION_sdata(_region_, _vma_, _lma_) \
.sdata _vma_ : _lma_ \
{ \
FORCE_OUTPUT; *(.sdata) *(.sdata.*) *(.gnu.linkonce.s*) \
} > _region_
 
#define SECTION_lit8(_region_, _vma_, _lma_) \
.lit8 _vma_ : _lma_ \
{ \
FORCE_OUTPUT; *(.lit8) \
} > _region_
 
#define SECTION_lit4(_region_, _vma_, _lma_) \
.lit4 : FOLLOWING(.lit8) \
{ \
FORCE_OUTPUT; *(.lit4) \
} > _region_ \
__ram_data_end = .; _edata = . ; \
PROVIDE (edata = .);
 
#define SECTION_sbss(_region_, _vma_, _lma_) \
__bss_start = .; _fbss = .; \
.sbss _vma_ : _lma_ \
{ \
FORCE_OUTPUT; *(.dynsbss) *(.sbss) *(.sbss.*) *(.scommon) \
} > _region_
 
#define SECTION_bss(_region_, _vma_, _lma_) \
.bss _vma_ : _lma_ \
{ \
*(.dynbss) *(.bss) *(.bss.*) *(COMMON) \
} > _region_ \
__bss_end = .;
 
/* The /DISCARD/ section ensures that the output will not contain a
* .mdebug section as it confuses GDB. This is a workaround for CR 100804.
*/
 
#define SECTIONS_END . = ALIGN(4); _end = .; PROVIDE (end = .); \
/* Stabs debugging sections. */ \
.stab 0 : { *(.stab) } \
.stabstr 0 : { *(.stabstr) } \
.stab.excl 0 : { *(.stab.excl) } \
.stab.exclstr 0 : { *(.stab.exclstr) } \
.stab.index 0 : { *(.stab.index) } \
.stab.indexstr 0 : { *(.stab.indexstr) } \
.comment 0 : { *(.comment) } \
/* DWARF debug sections. \
Symbols in the DWARF debugging sections are relative to \
the beginning of the section so we begin them at 0. */ \
/* DWARF 1 */ \
.debug 0 : { *(.debug) } \
.line 0 : { *(.line) } \
/* GNU DWARF 1 extensions */ \
.debug_srcinfo 0 : { *(.debug_srcinfo) } \
.debug_sfnames 0 : { *(.debug_sfnames) } \
/* DWARF 1.1 and DWARF 2 */ \
.debug_aranges 0 : { *(.debug_aranges) } \
.debug_pubnames 0 : { *(.debug_pubnames) } \
/* DWARF 2 */ \
.debug_info 0 : { *(.debug_info) } \
.debug_abbrev 0 : { *(.debug_abbrev) } \
.debug_line 0 : { *(.debug_line) } \
.debug_frame 0 : { *(.debug_frame) } \
.debug_str 0 : { *(.debug_str) } \
.debug_loc 0 : { *(.debug_loc) } \
.debug_macinfo 0 : { *(.debug_macinfo) } \
/* SGI/MIPS DWARF 2 extensions */ \
.debug_weaknames 0 : { *(.debug_weaknames) } \
.debug_funcnames 0 : { *(.debug_funcnames) } \
.debug_typenames 0 : { *(.debug_typenames) } \
.debug_varnames 0 : { *(.debug_varnames) } \
/* These must appear regardless of . */ \
.gptab.sdata : { *(.gptab.data) *(.gptab.sdata) } \
.gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) } \
/DISCARD/ 0 : { *(.mdebug) }
 
#include CYGHWR_MEMORY_LAYOUT_LDI
 
#ifndef CYGPKG_HAL_MIPS_SIM
hal_vsr_table = 0x80000100;
#endif

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