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    /openrisc/trunk/rtos/ecos-2.0/packages/hal/mips/upd985xx
    from Rev 27 to Rev 174
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  •

Rev 27 → Rev 174

/v2_0/cdl/hal_mips_upd985xx.cdl
0,0 → 1,228
# ====================================================================
#
# hal_mips_upd985xx.cdl
#
# MIPS/UPD985XX variant architectural HAL package configuration data
#
# ====================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
# ====================================================================
######DESCRIPTIONBEGIN####
#
# Author(s): hmt, jskov
# Original data: nickg
# Contributors:
# Date: 2001-05-24
#
#####DESCRIPTIONEND####
#
# ====================================================================
 
cdl_package CYGPKG_HAL_MIPS_UPD985XX {
display "UPD985XX variant"
parent CYGPKG_HAL_MIPS
implements CYGINT_HAL_MIPS_VARIANT
hardware
include_dir cyg/hal
define_header hal_mips_upd985xx.h
description "
The UPD985XX variant HAL package provides generic support
for this NEC system-on-chip processor architecture, uPD985xx.
It is also necessary to
select a specific target platform HAL package."
 
implements CYGINT_HAL_DEBUG_GDB_STUBS
implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
 
implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
implements CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
 
implements CYGINT_HAL_MIPS_STUB_REPRESENT_32BIT_AS_64BIT
 
implements CYGINT_HAL_MIPS_INTERRUPT_RETURN_KEEP_SR_IM
 
# The way the arbitration ISR is attached does not work with chained interrupts
requires ! CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
 
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
display "Number of communication channels on the board"
flavor data
calculated 1
}
 
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
display "Debug serial port"
active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
flavor data
legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
default_value 0
description "
There is only one serial port. This option
chooses which port will be used to connect to a host
running GDB."
}
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
display "Diagnostic serial port"
active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
flavor data
legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
default_value 0
description "
There is only one serial port. This option
chooses which port will be used for diagnostic output."
}
cdl_option CYGHWR_HAL_MIPS_UPD985XX_DIAG_BAUD {
display "Diagnostic Serial Port Baud Rate"
flavor data
legal_values 9600 19200 38400 115200
default_value 38400
define CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD
description "
This option selects the baud rate used for the diagnostic port.
Note: this must match the value chosen for the GDB port if the
diagnostic and GDB port are the same."
}
cdl_option CYGHWR_HAL_MIPS_UPD985XX_GDB_BAUD {
display "GDB Serial Port Baud Rate"
active_if { CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL != \
CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL }
flavor data
legal_values 9600 19200 38400 115200
default_value 38400
description "
This option controls the baud rate used for the GDB connection."
}
 
cdl_component CYGPKG_HAL_MIPS_UPD985XX_HARDWARE_BUGS {
display "Workarounds for uPD98503 hardware bugs "
flavor bool
default_value 1
description "
This component controls whether code workarounds for the
hardware bugs in the uPD98503 System Controller and IBUS are included.
Please refer to the manufacturer's
Behaviour Analysis Report to make your decision about which of
these options to enable or disable.
The default is to enable all workarounds for best reliability.
Please refer to the
USB and Ethernet devices for controls for subsystem specific
workarounds such as U3 and U4 in the USB; or E1,E2,E3 and E8 in
the ethernet."
 
cdl_option CYGOPT_HAL_MIPS_UPD985XX_HARDWARE_BUGS_S1 {
display "S1 - CPU to IBUS write restriction"
active_if { CYGPKG_DEVS_USB_UPD985XX || CYGPKG_DEVS_ETH_MIPS_UPD985XX }
flavor bool
default_value 1
# require either the workaround, or not the package ;
requires { CYGIMP_DEVS_USB_UPD985XX_IBUS_WRITE_LIMIT || !CYGPKG_DEVS_USB_UPD985XX }
requires { CYGOPT_DEVS_ETH_MIPS_UPD985XX_HARDWARE_BUGS_S1 || !CYGPKG_DEVS_ETH_MIPS_UPD985XX}
description "
This workaround is actually implemented in the Ethernet and USB
drivers; this option is a short cut to enable those options when
those packages are included in the build."
}
cdl_option CYGOPT_HAL_MIPS_UPD985XX_HARDWARE_BUGS_S2 {
display "S2 - Interrupt Mask restriction"
flavor bool
default_value 1
description "
Problem 'S2' is that masking an interrupt source at the same
instant that the interrupt 'fires' can lock up the system.
This workaround enables code which never masks an interrupt
once it has been unmasked, and silently fields any interrupts
which occur when that interrupt is soft-masked. When the
interrupt is unmasked by the application, then passing on the
interrupt is once more permitted, and any stored-up interrupt
will have its ISR called, otherwise interrupts would be
lost; they would not pend until the interrupt is unmasked.
This tactic is only possible due to the edge-triggered nature
of the interrupt controller in this device."
}
}
 
cdl_option CYGHWR_HAL_MIPS_64BIT {
display "Variant 64 bit architecture support"
calculated 0
description "
While the vr4100 is a 64bit CPU core, only its 32bit mode is
currently supported in eCos."
}
 
cdl_option CYGHWR_HAL_MIPS_FPU {
display "Variant FPU support"
calculated 0
}
 
cdl_option CYGHWR_HAL_MIPS_FPU_64BIT {
display "Variant 64 bit FPU support"
calculated 0
}
 
cdl_option CYGPKG_HAL_MIPS_LSBFIRST {
display "CPU Variant little-endian"
calculated 1
}
 
cdl_option CYGPKG_HAL_MIPS_MSBFIRST {
display "CPU Variant big-endian"
calculated { ! CYGPKG_HAL_MIPS_LSBFIRST }
}
 
define_proc {
puts $::cdl_header "#include <pkgconf/hal_mips.h>"
}
 
compile variant.S var_misc.c hal_diag.c
 
make {
<PREFIX>/lib/target.ld: <PACKAGE>/src/hal_mips_upd985xx.ld
$(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(CFLAGS) -o $@ $<
@echo $@ ": \\" > $(notdir $@).deps
@tail +2 target.tmp >> $(notdir $@).deps
@echo >> $(notdir $@).deps
@rm target.tmp
}
 
cdl_option CYGBLD_LINKER_SCRIPT {
display "Linker script"
flavor data
no_define
calculated { "src/hal_mips_upd985xx.ld" }
}
 
}
/v2_0/include/var_cache.h
0,0 → 1,173
#ifndef CYGONCE_VAR_CACHE_H
#define CYGONCE_VAR_CACHE_H
//=============================================================================
//
// var_cache.h
//
// HAL cache control API
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): hmt, nickg
// Contributors: nickg
// Date: 2001-05-24
// Purpose: Cache control API
// Description: The macros defined here provide the HAL APIs for handling
// cache control operations.
// Usage:
// #include <cyg/hal/var_cache.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>
 
#include <cyg/hal/plf_cache.h>
 
//-----------------------------------------------------------------------------
// Cache sizes.
 
// Data cache
#define HAL_DCACHE_SIZE (8*1024) // Size of data cache in bytes
#define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
#define HAL_DCACHE_WAYS 1 // Associativity of the cache
 
// Instruction cache
#define HAL_ICACHE_SIZE (16*1024) // Size of cache in bytes
#define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
#define HAL_ICACHE_WAYS 1 // Associativity of the cache
 
#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
 
//-----------------------------------------------------------------------------
// The uPD985xx mostly uses the default MIPS cache controls defined in
// hal_cache.h Here we define the cache enable and disable macros. The only
// control we appear to have is the kseg0 cache state in config0. So all
// these macros at present manipulate this.
 
#ifndef HAL_DCACHE_ENABLE_DEFINED
#define HAL_DCACHE_ENABLE() \
CYG_MACRO_START \
asm volatile ( "mfc0 $2,$16\n" \
"nop; nop; nop\n" \
"la $3,0xFFFFFFF8\n" \
"and $2,$2,$3\n" \
"ori $2,$2,3\n" \
"mtc0 $2,$16\n" \
"nop; nop; nop; nop;\n" \
"nop; nop; nop; nop;\n" \
"nop; nop; nop; nop;\n" \
"nop; nop; nop; nop;\n" \
: \
: \
: "$2", "$3" \
); \
CYG_MACRO_END
#define HAL_DCACHE_ENABLE_DEFINED
#endif
 
// Disable the data cache
#ifndef HAL_DCACHE_DISABLE_DEFINED
#define HAL_DCACHE_DISABLE() \
CYG_MACRO_START \
asm volatile ( "mfc0 $2,$16\n" \
"nop; nop; nop\n" \
"la $3,0xFFFFFFF8\n" \
"and $2,$2,$3\n" \
"ori $2,$2,2\n" \
"mtc0 $2,$16\n" \
"nop; nop; nop; nop;\n" \
"nop; nop; nop; nop;\n" \
"nop; nop; nop; nop;\n" \
"nop; nop; nop; nop;\n" \
: \
: \
: "$2", "$3" \
); \
CYG_MACRO_END
#define HAL_DCACHE_DISABLE_DEFINED
#endif
 
#ifndef HAL_DCACHE_IS_ENABLED_DEFINED
#define HAL_DCACHE_IS_ENABLED(_state_) \
CYG_MACRO_START \
CYG_WORD32 _cstate_; \
asm volatile ( "mfc0 %0,$16\n" \
"nop; nop; nop\n" \
: "=r"(_cstate_) \
); \
if( (_cstate_ & 7) == 2 ) _state_ = 0; \
else _state_ = 1; \
CYG_MACRO_END
#define HAL_DCACHE_IS_ENABLED_DEFINED
#endif
 
#ifndef HAL_ICACHE_ENABLE_DEFINED
#define HAL_ICACHE_ENABLE() HAL_DCACHE_ENABLE()
#define HAL_ICACHE_ENABLE_DEFINED
#endif
 
// Disable the instruction cache
#ifndef HAL_ICACHE_DISABLE_DEFINED
#define HAL_ICACHE_DISABLE() HAL_DCACHE_DISABLE()
#define HAL_ICACHE_DISABLE_DEFINED
#endif
 
#ifndef HAL_ICACHE_IS_ENABLED_DEFINED
#define HAL_ICACHE_IS_ENABLED(_state_) HAL_DCACHE_IS_ENABLED(_state_)
#define HAL_ICACHE_IS_ENABLED_DEFINED
#endif
 
//-----------------------------------------------------------------------------
// The VR4300 has no cache locking facility so we define the guard macros
// to disable the definitions in hal_arch.h.
 
#define HAL_DCACHE_LOCK_DEFINED
#define HAL_DCACHE_UNLOCK_DEFINED
#define HAL_DCACHE_UNLOCK_ALL_DEFINED
 
#define HAL_ICACHE_LOCK_DEFINED
#define HAL_ICACHE_UNLOCK_DEFINED
 
//-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_VAR_CACHE_H
// End of var_cache.h
/v2_0/include/plf_stub.h
0,0 → 1,80
#ifndef CYGONCE_HAL_PLF_STUB_H
#define CYGONCE_HAL_PLF_STUB_H
//=============================================================================
//
// plf_stub.h
//
// Platform header for GDB stub support.
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): hmt, jskov
// Contributors:jskov
// Date: 2001-05-25
// Purpose: Platform HAL stub support for MIPS/uUPD985xx devices.
// Usage: #include <cyg/hal/plf_stub.h>
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
 
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 
#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM
 
#include <cyg/hal/mips-stub.h> // architecture stub support
 
//----------------------------------------------------------------------------
// Define serial stuff.
externC void cyg_hal_plf_comms_init(void);
 
#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init()
#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud))
#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0
#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT
 
//----------------------------------------------------------------------------
// Stub initializer.
 
#define HAL_STUB_PLATFORM_INIT() /* nothing */
 
#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
//-----------------------------------------------------------------------------
#endif // CYGONCE_HAL_PLF_STUB_H
// End of plf_stub.h
/v2_0/include/var_intr.h
0,0 → 1,380
#ifndef CYGONCE_HAL_VAR_INTR_H
#define CYGONCE_HAL_VAR_INTR_H
//==========================================================================
//
// var_intr.h
//
// VR4300 Interrupt and clock support
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): hmt, nickg
// Contributors: nickg, jskov,
// gthomas, jlarmour
// Date: 2001-05-24
// Purpose: uPD985xx Interrupt support
// Description: The macros defined here provide the HAL APIs for handling
// interrupts and the clock for variants of the NEC uPD985xx
// architecture.
//
// Usage:
// #include <cyg/hal/var_intr.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#include <cyg/hal/var_arch.h>
#include <cyg/hal/plf_intr.h>
 
//--------------------------------------------------------------------------
// Interrupt controller stuff.
 
#ifndef CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
// Interrupts dealt with via the status and cause registers
// must be numbered in bit order:
#define CYGNUM_HAL_INTERRUPT_STATUS_CAUSE_LOW (0)
// The first two are the "software interrupts" - you just set a bit.
#define CYGNUM_HAL_INTERRUPT_SOFT_ZERO (0)
#define CYGNUM_HAL_INTERRUPT_SOFT_ONE (1)
#define CYGNUM_HAL_INTERRUPT_FREE_TWO (2)
#define CYGNUM_HAL_INTERRUPT_USB (3)
#define CYGNUM_HAL_INTERRUPT_ETHER (4)
#define CYGNUM_HAL_INTERRUPT_FREE_FIVE (5)
#define CYGNUM_HAL_INTERRUPT_SYSCTL (6)
#define CYGNUM_HAL_INTERRUPT_COMPARE (7)
 
// Number 6 "SYSCTL" is all external sources in the system controller and
// will normally be decoded into one of 8-12 instead. If you use number 6
// directly, then this will disable *all* system controller sources.
// Startup code will ensure number 6 is unmasked by default, and it will
// have an arbitration routine installed to call all of the subsequent
// interrupts from the S_ISR register. This has to be an external routine
// because the S_ISR register is read-clear, and the interrupt sources are
// edge-triggered so they do not re-assert themselves - so we must address
// multiple sources per actual interrupt, in a loop.
 
#define CYGNUM_HAL_INTERRUPT_SYSCTL_LOW (8)
#define CYGNUM_HAL_INTERRUPT_SYSCTL_HI (12)
 
#define CYGNUM_HAL_INTERRUPT_TM0 (8) // TIMER CH0 interrupt.
#define CYGNUM_HAL_INTERRUPT_TM1 (9) // TIMER CH1 interrupt.
#define CYGNUM_HAL_INTERRUPT_UART (10) // UART interrupt.
#define CYGNUM_HAL_INTERRUPT_EXT (11) // External Interrupt.
#define CYGNUM_HAL_INTERRUPT_WU (12) // Wakeup Interrupt.
 
#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART
 
// Min/Max ISR numbers and how many there are
#define CYGNUM_HAL_ISR_MIN 0
#define CYGNUM_HAL_ISR_MAX 12
#define CYGNUM_HAL_ISR_COUNT 13
 
// The vector used by the Real time clock. The default here is to use
// interrupt 5, which is connected to the counter/comparator registers
// in many MIPS variants.
 
#ifndef CYGNUM_HAL_INTERRUPT_RTC
#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_COMPARE
#endif
 
#define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
 
#endif // CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
 
#ifndef __ASSEMBLER__
 
// ------------------------------------------------------------------------
 
// This is placed in memory at a fixed location because we must share it
// with RedBoot, along with the VSR table and Virtual Vector table.
// It has to be an array to get the correct code generation to access it
// over all that distance.
externC volatile cyg_uint32 hal_interrupt_sr_mask_shadow_base[];
#define hal_interrupt_sr_mask_shadow (hal_interrupt_sr_mask_shadow_base[0])
 
// We have to have local versions of these to preserve the mask bits in the
// SR correctly when an interrupt occurs within one of these code sequences
// which are doing a read-modify-write to the main interrupt bit of the SR.
 
// Disable, it doesn't matter what the SR IM bits are - but it is possible
// for control to return with interrupts enabled if a context switch occurs
// away from the thread that disabled interrupts. Therefore we also make
// sure the contents of the SR match the shadow variable at the end.
 
#define HAL_DISABLE_INTERRUPTS(_old_) \
CYG_MACRO_START \
register int _tmp; \
asm volatile ( \
"mfc0 $8,$12; nop;" \
"move %0,$8;" \
"and $8,$8,0xfffffffe;" \
"mtc0 $8,$12;" \
"nop; nop; nop;" \
: "=r"(_tmp) \
: \
: "$8" \
); \
/* interrupts disabled so can now inject the correct IM bits */ \
(_old_) = _tmp & 1; \
_tmp &= 0xffff00fe; \
_tmp |= (hal_interrupt_sr_mask_shadow & 0xff00); \
asm volatile ( \
"mtc0 %0,$12;" \
"nop; nop; nop;" \
: \
: "r"(_tmp) \
); \
CYG_MACRO_END
 
// Enable and restore, we must pick up hal_interrupt_sr_mask_shadow because
// it contains the truth. This is also for the convenience of the
// mask/unmask macros below.
#define HAL_ENABLE_INTERRUPTS() HAL_RESTORE_INTERRUPTS(1)
 
#define HAL_RESTORE_INTERRUPTS(_old_) \
CYG_MACRO_START \
asm volatile ( \
"mfc0 $8,$12; nop;" \
"or $8,$8,%0;" /* inject IE bit */ \
"and $8,$8,0xffff00ff;" /* clear IM bits */ \
"or $8,$8,%1;" /* insert true IM */ \
"mtc0 $8,$12;" \
"nop; nop; nop;" \
: \
: "r"((_old_) & 1),"r"(hal_interrupt_sr_mask_shadow & 0xff00) \
: "$8" \
); \
CYG_MACRO_END
 
#define HAL_QUERY_INTERRUPTS( _state_ ) \
CYG_MACRO_START \
asm volatile ( \
"mfc0 %0,$12; nop;" \
"and %0,%0,0x1;" \
: "=r"(_state_) \
); \
CYG_MACRO_END
 
#define CYGHWR_HAL_INTERRUPT_ENABLE_DISABLE_RESTORE_DEFINED
 
// ------------------------------------------------------------------------
 
// For the bits which are in the SR, we only need to diddle the shadow
// variable; restore interrupts will pick that up at the end of the macro.
// Neat, huh.
 
#ifndef CYGOPT_HAL_MIPS_UPD985XX_HARDWARE_BUGS_S2
// Vanilla versions here: trick versions with the workaround follow:
 
#define HAL_INTERRUPT_MASK( _vector_ ) \
CYG_MACRO_START \
register int _intstate; \
register int _shift; \
HAL_DISABLE_INTERRUPTS( _intstate ); \
if ( CYGNUM_HAL_INTERRUPT_SYSCTL_LOW > (_vector_) ) { \
/* mask starts at bit 8 */ \
_shift = 8 + (_vector_) - CYGNUM_HAL_INTERRUPT_STATUS_CAUSE_LOW; \
hal_interrupt_sr_mask_shadow &=~(1 << _shift); \
} \
else { \
_shift = (_vector_) - CYGNUM_HAL_INTERRUPT_SYSCTL_LOW; \
*S_IMR &=~(1 << _shift); \
} \
HAL_RESTORE_INTERRUPTS( _intstate ); \
CYG_MACRO_END
 
 
#define HAL_INTERRUPT_UNMASK( _vector_ ) \
CYG_MACRO_START \
register int _intstate; \
register int _shift; \
HAL_DISABLE_INTERRUPTS( _intstate ); \
if ( CYGNUM_HAL_INTERRUPT_SYSCTL_LOW > (_vector_) ) { \
/* mask starts at bit 8 */ \
_shift = 8 + (_vector_) - CYGNUM_HAL_INTERRUPT_STATUS_CAUSE_LOW; \
hal_interrupt_sr_mask_shadow |= (1 << _shift); \
} \
else { \
_shift = (_vector_) - CYGNUM_HAL_INTERRUPT_SYSCTL_LOW; \
*S_IMR |= (1 << _shift); \
} \
HAL_RESTORE_INTERRUPTS( _intstate ); \
CYG_MACRO_END
 
 
#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
CYG_MACRO_START \
register int _intstate; \
HAL_DISABLE_INTERRUPTS( _intstate ); \
/* Default clears the bit in the cause register. But VR4120 doc */ \
/* says this is a NOP so we ignore low numbered sources except the */ \
/* software interrupt bits. */ \
if ( CYGNUM_HAL_INTERRUPT_SYSCTL_LOW <= (_vector_) || \
CYGNUM_HAL_INTERRUPT_SYSCTL == (_vector_) ) { \
register int i; \
i = *S_ISR; /* This is read-clear! */ \
} \
else if ( CYGNUM_HAL_INTERRUPT_SOFT_ZERO == (_vector_) || \
CYGNUM_HAL_INTERRUPT_SOFT_ONE == (_vector_) ) { \
/* These two are acknowledged by writing the bit to zero in */ \
/* the cause register. NB not the status register! */ \
asm volatile ( \
"mfc0 $3,$13\n" \
"la $2,0x00000100\n" \
"sllv $2,$2,%0\n" \
"andi $2,$2,0x0300\n" \
"nor $2,$2,$0\n" \
"and $3,$3,$2\n" \
"mtc0 $3,$13\n" \
"nop; nop; nop\n" \
: \
: "r"((_vector_)-CYGNUM_HAL_INTERRUPT_STATUS_CAUSE_LOW) \
: "$2", "$3" \
); \
} \
HAL_RESTORE_INTERRUPTS( _intstate ); \
CYG_MACRO_END
 
#else // DEFINED: CYGOPT_HAL_MIPS_UPD985XX_HARDWARE_BUGS_S2
 
#ifdef __cplusplus
extern "C" {
#endif
extern void cyg_hal_interrupt_unmask( int vec );
extern void cyg_hal_interrupt_mask( int vec );
extern void cyg_hal_interrupt_acknowledge( int vec );
#ifdef __cplusplus
} /* extern "C" */
#endif
 
#define HAL_INTERRUPT_MASK( _vector_ ) \
CYG_MACRO_START \
register int _intstate; \
register int _shift; \
HAL_DISABLE_INTERRUPTS( _intstate ); \
if ( CYGNUM_HAL_INTERRUPT_SYSCTL_LOW > (_vector_) ) { \
/* mask starts at bit 8 */ \
_shift = 8 + (_vector_) - CYGNUM_HAL_INTERRUPT_STATUS_CAUSE_LOW; \
hal_interrupt_sr_mask_shadow &=~(1 << _shift); \
} \
else { \
cyg_hal_interrupt_mask( (_vector_) ); \
} \
HAL_RESTORE_INTERRUPTS( _intstate ); \
CYG_MACRO_END
 
 
#define HAL_INTERRUPT_UNMASK( _vector_ ) \
CYG_MACRO_START \
register int _intstate; \
register int _shift; \
HAL_DISABLE_INTERRUPTS( _intstate ); \
if ( CYGNUM_HAL_INTERRUPT_SYSCTL_LOW > (_vector_) ) { \
/* mask starts at bit 8 */ \
_shift = 8 + (_vector_) - CYGNUM_HAL_INTERRUPT_STATUS_CAUSE_LOW; \
hal_interrupt_sr_mask_shadow |= (1 << _shift); \
} \
else { \
cyg_hal_interrupt_unmask( (_vector_) ); \
} \
HAL_RESTORE_INTERRUPTS( _intstate ); \
CYG_MACRO_END
 
 
#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
CYG_MACRO_START \
register int _intstate; \
HAL_DISABLE_INTERRUPTS( _intstate ); \
/* Default clears the bit in the cause register. But VR4120 doc */ \
/* says this is a NOP so we ignore low numbered sources except the */ \
/* software interrupt bits. */ \
if ( CYGNUM_HAL_INTERRUPT_SYSCTL_LOW <= (_vector_) || \
CYGNUM_HAL_INTERRUPT_SYSCTL == (_vector_) ) { \
cyg_hal_interrupt_acknowledge( (_vector_) ); \
} \
else if ( CYGNUM_HAL_INTERRUPT_SOFT_ZERO == (_vector_) || \
CYGNUM_HAL_INTERRUPT_SOFT_ONE == (_vector_) ) { \
/* These two are acknowledged by writing the bit to zero in */ \
/* the cause register. NB not the status register! */ \
asm volatile ( \
"mfc0 $3,$13\n" \
"la $2,0x00000100\n" \
"sllv $2,$2,%0\n" \
"andi $2,$2,0x0300\n" \
"nor $2,$2,$0\n" \
"and $3,$3,$2\n" \
"mtc0 $3,$13\n" \
"nop; nop; nop\n" \
: \
: "r"((_vector_)-CYGNUM_HAL_INTERRUPT_STATUS_CAUSE_LOW) \
: "$2", "$3" \
); \
} \
HAL_RESTORE_INTERRUPTS( _intstate ); \
CYG_MACRO_END
 
#endif // CYGOPT_HAL_MIPS_UPD985XX_HARDWARE_BUGS_S2
 
#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ )
 
#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ )
 
#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
 
//--------------------------------------------------------------------------
// Useful for debugging...
 
#define HAL_READ_INTR_REGS( _status, _cause ) \
{ \
asm volatile ( \
"mfc0 %0,$12; nop;" \
: "=r"(_status) \
); \
asm volatile ( \
"mfc0 %0,$13; nop;" \
: "=r"(_cause) \
); \
}
 
//--------------------------------------------------------------------------
#endif // ! __ASSEMBLER__
 
#endif // ifndef CYGONCE_HAL_VAR_INTR_H
// End of var_intr.h
/v2_0/include/var_arch.h
0,0 → 1,374
#ifndef CYGONCE_HAL_VAR_ARCH_H
#define CYGONCE_HAL_VAR_ARCH_H
//==========================================================================
//
// var_arch.h
//
// Architecture specific abstractions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): hmt, nickg
// Contributors: nickg
// Date: 2001-05-24
// Purpose: Define architecture abstractions
// Description: This file contains any extra or modified definitions for
// this variant of the architecture.
// Usage: #include <cyg/hal/var_arch.h>
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
 
// -------------------------------------------------------------------------
// Although the VR4100 is really a 64 bit CPU, we have defined
// target_register_t elsewhere to be 32-bits because we only support
// 32-bit mode. Registers will still be sent to GDB as 64-bit, but that's
// not relevant for CYG_HAL_GDB_REG.
 
#define CYG_HAL_GDB_REG CYG_WORD32
 
//--------------------------------------------------------------------------
// Now defines for all the system controller registers
//
// These all exist at base 0x1000_0000 in physical memory.
 
#define MIPS_KSEG0_BASE (0x80000000u)
#define MIPS_KSEG1_BASE (0xA0000000u)
 
#define UPD985XX_SYSTEM_BASE (0x10000000u)
 
#define MIPS_IO_BASE (MIPS_KSEG1_BASE + UPD985XX_SYSTEM_BASE)
 
#define UPD985XX_SYSCTL_OFF (0x0000u)
#define UPD985XX_SYSUSB_OFF (0x1000u)
#define UPD985XX_SYSETH_OFF (0x2000u)
 
#define UPD985XX_SYSCTL_REG( n ) ((volatile unsigned int *)\
(MIPS_IO_BASE + UPD985XX_SYSCTL_OFF + (unsigned)(n)))
#define UPD985XX_SYSUSB_REG( n ) ((volatile unsigned int *)\
(MIPS_IO_BASE + UPD985XX_SYSUSB_OFF + (unsigned)(n)))
#define UPD985XX_SYSETH_REG( n ) ((volatile unsigned int *)\
(MIPS_IO_BASE + UPD985XX_SYSETH_OFF + (unsigned)(n)))
 
// This for the few that we need in assembly
#define UPD985XX_SYSCTL_ADDR( n ) (0xb0000000 + (n))
 
// (the noise at the end of these lines is the default value)
#define S_GMR UPD985XX_SYSCTL_REG( 0x00) // General Mode Register 00000000H
#define S_GSR UPD985XX_SYSCTL_REG( 0x04) // General Status Register unknown
#define S_ISR UPD985XX_SYSCTL_REG( 0x08) // Interrupt Status Register 00000000H
#define S_IMR UPD985XX_SYSCTL_REG( 0x0C) // Interrupt Mask Register 00000000H
#define S_NSR UPD985XX_SYSCTL_REG( 0x10) // NMI Status Register 00000000H
#define S_NMR UPD985XX_SYSCTL_REG( 0x14) // NMI Mask Register 00000000H
#define S_VER UPD985XX_SYSCTL_REG( 0x18) // Version Register 00000301H
// N/A UPD985XX_SYSCTL_REG( 0x1C) reserved 00000000H
#define S_GIOER UPD985XX_SYSCTL_REG( 0x20) // GPIO Output Enable Register 00000000H
#define S_GOPR UPD985XX_SYSCTL_REG( 0x24) // GPIO Output (Write) Register 00000000H
#define S_GIPR UPD985XX_SYSCTL_REG( 0x28) // GPIO Input (Read) Register 00000000H
// N/A UPD985XX_SYSCTL_REG( 0x2C) // Reserved unknown
#define S_WRCR UPD985XX_SYSCTL_REG( 0x30) // Warm Reset Control Register 00000000H
#define S_WRSR UPD985XX_SYSCTL_REG( 0x34) // Warm Reset Status Register 00000000H
#define S_PWCR UPD985XX_SYSCTL_REG( 0x38) // Power Control Register 00000000H
#define S_PWSR UPD985XX_SYSCTL_REG( 0x3C) // Power Control Status Register 00000000H
// N/A UPD985XX_SYSCTL_REG( 0x40) Reserved unknown
#define ITCNTR UPD985XX_SYSCTL_REG( 0x4C) // IBUS Timeout Timer Control Register 00000000H
#define ITSETR UPD985XX_SYSCTL_REG( 0x50) // IBUS Timeout Timer Set Register 80000000H
// N/A UPD985XX_SYSCTL_REG( 0x54) Reserved unknown
// UPD985XX_SYSCTL_REG( 0x7F)
#define UARTRBR UPD985XX_SYSCTL_REG( 0x80) // UART, Receiver Buffer Register [DLAB=0,READ] unknown
#define UARTTHR UPD985XX_SYSCTL_REG( 0x80) // UART, Transmitter Holding Register [DLAB=0,WRITE] unknown
#define UARTDLL UPD985XX_SYSCTL_REG( 0x80) // UART, Divisor Latch LSB Register [DLAB=1] unknown
#define UARTIER UPD985XX_SYSCTL_REG( 0x84) // UART, Interrupt Enable Register [DLAB=0] unknown
#define UARTDLM UPD985XX_SYSCTL_REG( 0x84) // UART, Divisor Latch MSB Register [DLAB=1] unknown
#define UARTIIR UPD985XX_SYSCTL_REG( 0x88) // UART, Interrupt ID Register [READ] unknown
// The uPD985xx devices do not support UART FIFOs.
#define UARTFCR UPD985XX_SYSCTL_REG( 0x88) // UART, FIFO control Register [WRITE]
#define UARTLCR UPD985XX_SYSCTL_REG( 0x8C) // UART, Line control Register unknown
#define UARTMCR UPD985XX_SYSCTL_REG( 0x90) // UART, Modem Control Register unknown
#define UARTLSR UPD985XX_SYSCTL_REG( 0x94) // UART, Line status Register unknown
#define UARTMSR UPD985XX_SYSCTL_REG( 0x98) // UART, Modem Status Register unknown
#define UARTSCR UPD985XX_SYSCTL_REG( 0x9C) // UART, Scratch Register unknown
#define DSUCNTR UPD985XX_SYSCTL_REG( 0xA0) // DSU Control Register 00000000H
#define DSUSETR UPD985XX_SYSCTL_REG( 0xA4) // DSU Dead Time Set Register 80000000H
#define DSUCLRR UPD985XX_SYSCTL_REG( 0xA8) // DSU Clear Register 00000000H
#define DSUTIMR UPD985XX_SYSCTL_REG( 0xAC) // DSU Elapsed Time Register 00000000H
#define TMMR UPD985XX_SYSCTL_REG( 0xB0) // Timer Mode Register 00000000H
#define TM0CSR UPD985XX_SYSCTL_REG( 0xB4) // Timer CH0 Count Set Register 00000000H
#define TM1CSR UPD985XX_SYSCTL_REG( 0xB8) // Timer CH1 Count Set Register 00000000H
#define TM0CCR UPD985XX_SYSCTL_REG( 0xBC) // Timer CH0 Current Count Register FFFFFFFFH
#define TM1CCR UPD985XX_SYSCTL_REG( 0xC0) // Timer CH1 Current Count Register FFFFFFFFH
// N/A UPD985XX_SYSCTL_REG( 0xC4) Reserved unknown
// UPD985XX_SYSCTL_REG( 0xCF)
#define ECCR UPD985XX_SYSCTL_REG( 0xD0) // EEPROM Command Control Register 00000000H
#define ERDR UPD985XX_SYSCTL_REG( 0xD4) // EEPROM Read Data Register 80000000H
#define MACAR1 UPD985XX_SYSCTL_REG( 0xD8) // MAC Address Register 1 00000000H
#define MACAR2 UPD985XX_SYSCTL_REG( 0xDC) // MAC Address Register 2 00000000H
#define MACAR3 UPD985XX_SYSCTL_REG( 0xE0) // MAC Address Register 3 00000000H
// N/A UPD985XX_SYSCTL_REG( 0xE4) Reserved unknown
// UPD985XX_SYSCTL_REG( 0xFF)
#define RMMDR UPD985XX_SYSCTL_REG(0x100) // Boot ROM Mode Register 00000000H
#define RMATR UPD985XX_SYSCTL_REG(0x104) // Boot ROM Access Timing Register 00000000H
#define SDMDR UPD985XX_SYSCTL_REG(0x108) // SDRAM Mode Register 00000330H
#define SDTSR UPD985XX_SYSCTL_REG(0x10C) // SDRAM Type Selection Register 00000000H
#define SDPTR UPD985XX_SYSCTL_REG(0x110) // SDRAM Precharge Timing Register 00000142H
// N/A UPD985XX_SYSCTL_REG(0x114) ---- ---- Reserved unknown
// UPD985XX_SYSCTL_REG(0x11B)
#define SDRMR UPD985XX_SYSCTL_REG(0x11C) // SDRAM Refresh Mode Register 00000200H
#define SDRCR UPD985XX_SYSCTL_REG(0x120) // SDRAM Refresh Timer Count Register 00000200H
#define MBCR UPD985XX_SYSCTL_REG(0x124) // Memory Bus Control Register 00000000H
#define MESR UPD985XX_SYSCTL_REG(0x128) // Memory Error Status Register 00000000H
#define MEAR UPD985XX_SYSCTL_REG(0x12C) // Memory Error Address Register 00000000H
 
// The few that we need from assembly
#define S_ISR_ADR UPD985XX_SYSCTL_ADDR( 0x08) // Interrupt Status Register 00000000H
#define S_IMR_ADR UPD985XX_SYSCTL_ADDR( 0x0C) // Interrupt Mask Register 00000000H
 
#define RMMDR_ADR UPD985XX_SYSCTL_ADDR(0x100) // Boot ROM Mode Register 00000000H
#define RMATR_ADR UPD985XX_SYSCTL_ADDR(0x104) // Boot ROM Access Timing Register 00000000H
#define SDMDR_ADR UPD985XX_SYSCTL_ADDR(0x108) // SDRAM Mode Register 00000330H
#define SDTSR_ADR UPD985XX_SYSCTL_ADDR(0x10C) // SDRAM Type Selection Register 00000000H
#define SDPTR_ADR UPD985XX_SYSCTL_ADDR(0x110) // SDRAM Precharge Timing Register 00000142H
 
#define SDRMR_ADR UPD985XX_SYSCTL_ADDR(0x11C) // SDRAM Refresh Mode Register 00000200H
#define SDRCR_ADR UPD985XX_SYSCTL_ADDR(0x120) // SDRAM Refresh Timer Count Register 00000200H
#define MBCR_ADR UPD985XX_SYSCTL_ADDR(0x124) // Memory Bus Control Register 00000000H
#define MESR_ADR UPD985XX_SYSCTL_ADDR(0x128) // Memory Error Status Register 00000000H
#define MEAR_ADR UPD985XX_SYSCTL_ADDR(0x12C) // Memory Error Address Register 00000000H
 
// ---------------------------------------------------------------------------
// Contents of all these glorious registers:
 
// --------- general ---------
// S_GMR General Mode Register 00000000H
#define S_GMR_CRST 1 // Cold Reset
#define S_GMR_IAEN 2 // IBUS Arbiter Enable
#define S_GMR_MPFD 4 // Memory-to-CPU Prefetch FIFO disable
#define S_GMR_UCSEL 8 // UART Source Clock Selection (0 = CPU, 1 = ext)
#define S_GMR_HSWP (1<<8) // HIF Block Data swap function disable
#define S_GMR_MSWP (1<<9) // MIF Block Data swap function disable
 
// S_GSR General Status Register
#define S_GSR_ENDCEN 1
#define S_GSR_CCLKSEL 2
 
// S_ISR Interrupt Status Register 00000000H
#define S_ISR_TM0IS (1<<0) // TIMER CH0 interrupt.
#define S_ISR_TM1IS (1<<1) // TIMER CH1 interrupt.
#define S_ISR_UARTIS (1<<2) // UART interrupt.
#define S_ISR_EXTIS (1<<3) // External Interrupt.
#define S_ISR_WUIS (1<<4) // Wakeup Interrupt.
 
// S_IMR Interrupt Mask Register 00000000H
// see S_ISR; write a 1 to unmask, 0 to mask.
 
// S_NSR NMI Status Register 00000000H
// S_NMR NMI Mask Register 00000000H
 
// S_VER Version Register 00000301H
 
// --------- GPIO ---------
// S_GIOER GPIO Output Enable Register 00000000H
// S_GOPR GPIO Output (Write) Register 00000000H
// S_GIPR GPIO Input (Read) Register 00000000H
// 16-bit regsiters that do the utterly obvious thing.
 
// --------- reset ---------
// S_WRCR Warm Reset Control Register 00000000H
#define S_WRCR_USBWR (1<<0) // Warm Reset request for USB Controller
#define S_WRCR_MACWR (1<<1) // Warm Reset request for Ethernet Controller
#define S_WRCR_UARTWR (1<<4) // Warm Reset request for UART
 
// S_WRSR Warm Reset Status Register 00000000H
// See S_WRCR; 1 <=> Ready, 0 <=> performing warm reset.
 
// --------- power control of USB/ETH peripherals ---------
// S_PWCR Power Control Register 00000000H
// S_PWSR Power Control Status Register 00000000H
 
// --------- bus timouts ---------
// ITCNTR IBUS Timeout Timer Control Register 00000000H
// ITSETR IBUS Timeout Timer Set Register 80000000H
 
// --------- UART ---------
// UARTRBR UART, Receiver Buffer Register [DLAB=0,READ]
// UARTTHR UART, Transmitter Holding Register [DLAB=0,WRITE]
// UARTDLL UART, Divisor Latch LSB Register [DLAB=1]
// The external (18.432MHz) clock is not present. See S_GMR_UCSEL.
// See also UARTDLM below. So we use the internal 50MHz clock.
 
//#define UARTCLOCK (18432000)
#define UARTCLOCK (50 * 1000 * 1000)
#define UARTDLL_VAL( _baud_ ) ((UARTCLOCK / 16) / (_baud_) )
 
// UARTIER UART, Interrupt Enable Register [DLAB=0]
#define UARTIER_ERBFI (1<<0) // UART Receive data Buffer Full Interrupt
#define UARTIER_ERBEI (1<<1) // UART Transmitter Buffer empty Interrupt
#define UARTIER_ERBLI (1<<2) // UART Line status Interrupts
#define UARTIER_ERBMI (1<<3) // UART Modem status Interrupts
 
// UARTDLM UART, Divisor Latch MSB Register [DLAB=1]
#define UARTDLM_ANY_BAUD (0)
#define UARTDLM_VAL( _baud_ ) (UARTDLL_VAL( _baud_ ) >> 8)
 
// UARTIIR UART, Interrupt ID Register [READ]
#define UARTIIR_INTPENDL (1<<0) // No Pending interrupts
 
// mask to give one of:
#define UARTIIR_UIID_MASK (7<<1) // Indicates the priority level of pending interrupt.
 
#define UARTIIR_RXERROR (3<<1) // Receiver Line Error
#define UARTIIR_RXD_AVAIL (2<<1) // Received data available
#define UARTIIR_CHAR_TO (6<<1) // Character timeout
#define UARTIIR_TX_EMPTY (1<<1) // Transmitter Register Empty
#define UARTIIR_MODEM (0<<1) // Modem Status: CTS_L, DSR_L or DCD_L
 
// UARTFCR UART, FIFO control Register [WRITE]
// ...is not supported. But nontheless it appears necessary to write it.
#define UARTFCR_16550_MODE (6) // and clear the FIFOs.
 
// UARTLCR UART, Line control Register
// Word length
#define UARTLCR_8 (0x03)
#define UARTLCR_7 (0x02)
// Stop bits
#define UARTLCR_STB1 (0x00)
#define UARTLCR_STB2 (0x04)
// Parity
#define UARTLCR_NOP (0x00)
#define UARTLCR_EP (0x18)
#define UARTLCR_OP (0x08)
 
// Just predefine the pattern for 8-N-1...
#define UARTLCR_8N1 (0x03)
 
// Divisor latch access bit; or this with one of the above.
#define UARTLCR_DLAB (0x80)
 
// UARTMCR UART, Modem Control Register
#define UARTMCR_DTR (1<<0) // Data Terminal Ready.
#define UARTMCR_RTS (1<<1) // Request To Send.
 
// UARTLSR UART, Line status Register
#define UARTLSR_DR (1<<0) // Receive-Data Ready.
#define UARTLSR_OE (1<<1) // Receive-Data Overrun Error.
#define UARTLSR_PE (1<<2) // Receive-Data Parity Error.
#define UARTLSR_FE (1<<3) // Receive-Data Framing Error.
#define UARTLSR_BI (1<<4) // Break Interrupt.
#define UARTLSR_THRE (1<<5) // Transmitter Holding Register Empty.
#define UARTLSR_TEMT (1<<6) // Transmitter Empty.
#define UARTLSR_RFERR (1<<7) // Receiver FIFO Error.
 
// UARTMSR UART, Modem Status Register
#define UARTMSR_DCTS (1<<0) // Delta Clear To Send.
#define UARTMSR_DDSR (1<<1) // Delta Data Set Ready.
#define UARTMSR_TERI (1<<2) // Trailing Edge Ring Indicato
#define UARTMSR_DDCD (1<<3) // Delta Data Carrier Detect.
#define UARTMSR_CTS (1<<4) // Clear To Send.
#define UARTMSR_DSR (1<<5) // Data Set Ready.
#define UARTMSR_RI (1<<6) // Ring Indicator.
#define UARTMSR_DCD (1<<7) // Data Carrier Detect.
 
// UARTSCR UART, Scratch Register unknown
 
 
// --------- watchdog aka dead man's switch ---------
// DSUCNTR DSU Control Register 00000000H
// DSUSETR DSU Dead Time Set Register 80000000H
// DSUCLRR DSU Clear Register 00000000H
// DSUTIMR DSU Elapsed Time Register 00000000H
 
// --------- additional timers ---------
// TMMR Timer Mode Register 00000000H
// TM0CSR Timer CH0 Count Set Register 00000000H
// TM1CSR Timer CH1 Count Set Register 00000000H
// TM0CCR Timer CH0 Current Count Register FFFFFFFFH
// TM1CCR Timer CH1 Current Count Register FFFFFFFFH
 
// --------- serial eeprom ---------
// ECCR EEPROM Command Control Register 00000000H
// ERDR EEPROM Read Data Register 80000000H
// MACAR1 MAC Address Register 1 00000000H
// MACAR2 MAC Address Register 2 00000000H
// MACAR3 MAC Address Register 3 00000000H
 
// --------- memory control ---------
// RMMDR Boot ROM Mode Register 00000000H
// RMATR Boot ROM Access Timing Register 00000000H
#define RMMDR_FLASH_WRITE_ENABLE (0x100)
 
#define RMMDR_28F640 (0)
#define RMMDR_28F320 (0)
#define RMMDR_29LV160_120 (3) // sic. from customer doc
#define RMMDR_29LV160_90 (3) // even though "3" is a reserved value
#define RMMDR_29LV160_70 (3) // maybe it means "1".
 
#define RMATR_28F640 (5)
#define RMATR_28F320 (4)
#define RMATR_29LV160_120 (5)
#define RMATR_29LV160_90 (4)
#define RMATR_29LV160_70 (3)
 
// SDMDR SDRAM Mode Register 00000330H
// SDTSR SDRAM Type Selection Register 00000000H
// SDPTR SDRAM Precharge Timing Register 00000142H
// SDRMR SDRAM Refresh Mode Register 00000200H
// SDRCR SDRAM Refresh Timer Count Register 00000200H
 
#if 1
// initial settings from customer doc.
#define SDMDR_INIT (0x230) // 230 from the hardware, 330 from doc
#define SDTSR_INIT (0x180 | 0x20 | 0x1)
#define SDPTR_INIT (0x111)
#define SDRMR_INIT (0x600)
#else
// optimized setting "don't be used before qualification"
#define SDMDR_INIT (0x120)
#define SDTSR_INIT (0x180 | 0x20 | 0x1)
#define SDPTR_INIT (0x100)
#define SDRMR_INIT (0x600)
#endif
 
// These are used for decoding SEGV types.
// MBCR Memory Bus Control Register 00000000H
// MESR Memory Error Status Register 00000000H
// MEAR Memory Error Address Register 00000000H
 
// --------------------------------------------------------------------------
#endif // CYGONCE_HAL_VAR_ARCH_H
// End of var_arch.h
/v2_0/include/variant.inc
0,0 → 1,549
#ifndef CYGONCE_HAL_VARIANT_INC
#define CYGONCE_HAL_VARIANT_INC
//#=============================================================================
//#
//# variant.inc
//#
//# UPD985XX assembler header file
//#
//#=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//#=============================================================================
//######DESCRIPTIONBEGIN####
//#
//# Author(s): hmt, nickg
//# Contributors: nickg
//# Date: 2001-05-24
//# Purpose: UPD985XX definitions.
//# Description: This file contains various definitions and macros that are
//# useful for writing assembly code for the UPD985XX CPU.
//# Usage:
//# #include <cyg/hal/variant.inc>
//# ...
//#
//#
//#####DESCRIPTIONEND####
//#
//#=============================================================================
 
.set mips3
 
#include <cyg/hal/mips.inc>
 
#include <cyg/hal/platform.inc>
 
#include <pkgconf/hal.h>
 
#include CYGBLD_HAL_PLATFORM_H
 
#include <cyg/hal/arch.inc>
 
#include <cyg/hal/var_arch.h>
#include <cyg/hal/var_intr.h>
 
// ------------------------------------------------------------------------
// Basic LED and poke-uart level debugging stuff.
 
#if 0
.macro DELAY dd
la k0,\dd
98: addiu k0,k0,-1
bnez k0,98b
nop
.endm
 
.macro LED nn
la k1,0xb0000000
la k0,0xfdff
sw k0,0x20(k1)
nop
nop
nop
la t0,\nn
99:
la k0,0x100
sw k0,0x24(k1)
 
DELAY 0x40000
 
la k0,0x000
sw k0,0x24(k1)
DELAY 0x30000
 
addi t0,t0,-1
bnez t0,99b
nop
 
DELAY 0xd0000
 
.endm
 
.macro PRINT nn
la k1,0xb0000000
DELAY 0x10000
la k0, '.'
sw k0,0x80(k1)
DELAY 0x10000
la k0, 0xf & ((\nn) >> 4)
addi k0,k0,'0'
sw k0,0x80(k1)
DELAY 0x10000
la k0, 0xf & ((\nn))
addi k0,k0,'0'
sw k0,0x80(k1)
DELAY 0x10000
la k0, '.'
sw k0,0x80(k1)
.endm
 
.macro DEBUG nn
#LED \nn
PRINT \nn
.endm
 
#else
 
.macro DEBUG nn
.endm
 
#endif
 
##-----------------------------------------------------------------------------
## configure the architecture HAL to define the right things.
 
## ISR tables are larger than the defaults defined in vectors.S
## We define our own in var_misc.c
#define CYG_HAL_MIPS_ISR_TABLES_DEFINED
 
## VSR table is at a fixed RAM address defined by the linker script
#define CYG_HAL_MIPS_VSR_TABLE_DEFINED
 
//------------------------------------------------------------------------------
// Set up initial value for config register. Sets endian mode and
// disables the cache on kseg0.
 
#if defined(CYGPKG_HAL_MIPS_MSBFIRST)
# define INITIAL_CONFIG0 ***!!!Nope, it should be little-endian!!!***
#elif defined(CYGPKG_HAL_MIPS_LSBFIRST)
# define INITIAL_CONFIG0 0x00000002
#else
# error MIPS endianness not set by configuration
#endif
 
//------------------------------------------------------------------------------
// Initial SR value for use standalone and with GDB_stubs:
// CP0 usable
// Vectors to RAM
// All hw ints disabled
 
#define INITIAL_SR 0x10000000
 
#------------------------------------------------------------------------------
# Cache macros.
 
#ifndef CYGPKG_HAL_MIPS_CACHE_DEFINED
 
.macro hal_cache_init
 
mfc0 v0,config0 # disable Kseg0 caching in config0 register
nop
nop
la v1,0xfffffff8
and v0,v0,v1
ori v0,v0,2
mtc0 v0,config0
nop
nop
nop
 
// If we invalidate the caches in RAM startup, this destroys
// network debugging == the network device.
// Don~t fully understand why, but this exclusion fixes it.
// Invalidating caches could destroy other RedBoot state so we
// shouldn~t do it anyway.
#ifndef CYG_HAL_STARTUP_RAM
 
.set mips3 # Set ISA to MIPS 3 to allow cache insns
 
// Now ensure the caches are invalidated. The caches are NOT cleared or
// invalidated on non-power-up resets and may come up in a random state
// on power-up. Hence they may contain stale or randomly bogus data.
// Here we use the index-store-tag cache operation to clear all the cache
// tags and states to zero. This will render them all invalid on the
// VR4300.
 
# D-cache:
la t0,0x80000000
addi t1,t0,0x2000
1:
mtc0 zero,$28
mtc0 zero,$29
cache 0x09,0(t0)
addi t0,t0,0x10
sub v0,t1,t0
bgez v0,1b
nop
 
# I-cache:
la a0,0x80000000
addi a1,a0,0x4000
1:
mtc0 zero,$28
mtc0 zero,$29
cache 0x08,0(a0)
addi a0,a0,0x20
sub v0,a1,a0
bgez v0,1b
nop
 
.set mips0 # reset ISA to default
 
#endif
 
.endm
 
#define CYGPKG_HAL_MIPS_CACHE_DEFINED
 
#endif
 
//-----------------------------------------------------------------------------
// Load Address and Relocate. This macro is used in code that may be
// linked to execute out of RAM but is actually executed from ROM. The
// code that initializes the memory controller and copies the ROM
// contents to RAM must work in this way, for example. This macro is used
// in place of an "la" macro instruction when loading code and data
// addresses. There are two versions of the macro here. The first
// assumes that we are executing in the ROM space at 0xbfc00000 and are
// linked to run in the RAM space at 0x80000000. It simply adds the
// difference between the two to the loaded address. The second is more
// code, but will execute correctly at either location since it
// calculates the difference at runtime. The second variant is enabled
// by default.
 
 
#ifdef CYG_HAL_STARTUP_ROMRAM
 
#if 0
.macro lar reg,addr
.set noat
la \reg,\addr
la $at,0x3fc00000
addu \reg,\reg,$at
.set at
.endm
#else
.macro lar reg,addr
.set noat
move $at,ra # save ra
la \reg,\addr # get address into register
la ra,x\@ # get linked address of label
subiu \reg,\reg,ra # subtract it from value
bal x\@ # branch and link to label
nop # to get current actual address
x\@:
addiu \reg,\reg,ra # add actual address
move ra,$at # restore ra
.set at
.endm
 
#endif
 
#define CYGPKG_HAL_MIPS_LAR_DEFINED
 
#endif
//----------------------------------------------------------------------------
// MMU macros.
// The MMU must be set up on this board before we can access any external devices,
// including the memory controller, so we have no RAM to work with yet.
// Since the setup code must work only in registers, we do not do a subroutine
// linkage here, instead the setup code knows to jump back here when finished.
#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
 
// There is none. We can access all areas via kseg[01] so we are happy
// with no MMU setup.
 
// NO #define CYGPKG_HAL_MIPS_MMU_DEFINED
 
#endif
 
//----------------------------------------------------------------------------
// MEMC macros.
//
.macro hal_memc_init
 
#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
 
.extern hal_memc_setup
lar k0,hal_memc_setup
jalr k0
nop
 
#endif
 
#if defined(CYG_HAL_STARTUP_ROMRAM)
 
# Having got the RAM working, we must now relocate the Entire
# ROM into it and then continue execution from RAM.
 
la t0,0x80000000 # dest addr
la t1,0xbfc00000 # source addr
la t3,__ram_data_end # end dest addr
1:
lw v0,0(t1) # get word
addiu t1,t1,4
sw v0,0(t0) # write word
addiu t0,t0,4
bne t0,t3,1b
nop
 
la v0,2f # RAM address to go to
jr v0
nop
2:
# We are now executing out of RAM!
 
#endif
 
.endm
 
#define CYGPKG_HAL_MIPS_MEMC_DEFINED
 
#------------------------------------------------------------------------------
# Interrupt controller initialization.
 
#ifndef CYGPKG_HAL_MIPS_INTC_DEFINED
 
#ifndef CYGPKG_HAL_MIPS_INTC_INIT_DEFINED
# initialize all interrupts to disabled
.macro hal_intc_init
mfc0 v0,status
nop
lui v1,0xFFFF
ori v1,v1,0x00FF
and v0,v0,v1 # clear the IntMask bits
mtc0 v0,status
nop
nop
nop
.endm
#endif
 
#ifndef CYGPKG_HAL_MIPS_INTC_DECODE_DEFINED
.macro hal_intc_decode vnum
mfc0 v1,status # get status register (interrupt mask)
nop # delay slot
mfc0 v0,cause # get cause register
nop # delay slot
and v0,v0,v1 # apply interrupt mask
andi v1,v0,0x0300 # test for soft interrupt bits
beqz v1, 43f # neither of them
srl v1,v1,8 # shift interrupt bits down
addi v1,v1,-1 # now have 1,2,3 in v1 -> 0,1,2
andi \vnum,v1,1 # -> 0,1,0 is the right answer
b 44f
nop
43:
srl v0,v0,10 # shift interrupt bits down
andi v0,v0,0x3f # isolate 6 interrupt bits
la v1,hal_intc_translation_table
add v0,v0,v1 # index into table
lb \vnum,0(v0) # pick up vector number
addi \vnum,\vnum,2 # offset soft intrs
44: nop
.endm
#endif
 
#ifndef CYGPKG_HAL_MIPS_INTC_TRANSLATE_DEFINED
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
.macro hal_intc_translate inum,vnum
move \vnum,zero # Just vector zero is supported
.endm
#else
.macro hal_intc_translate inum,vnum
move \vnum,\inum # Vector == interrupt number
.endm
#endif
#endif
 
.macro hal_intc_decode_data
hal_intc_translation_table:
.byte 0, 0, 1, 0
.byte 2, 0, 1, 0
.byte 3, 0, 1, 0
.byte 2, 0, 1, 0
.byte 4, 0, 1, 0
.byte 2, 0, 1, 0
.byte 3, 0, 1, 0
.byte 2, 0, 1, 0
.byte 5, 0, 1, 0
.byte 2, 0, 1, 0
.byte 3, 0, 1, 0
.byte 2, 0, 1, 0
.byte 4, 0, 1, 0
.byte 2, 0, 1, 0
.byte 3, 0, 1, 0
.byte 2, 0, 1, 0
.endm
 
#define CYGPKG_HAL_MIPS_INTC_DEFINED
 
#endif // CYGPKG_HAL_MIPS_INTC_DEFINED
 
 
#------------------------------------------------------------------------------
# Monitor initialization.
 
 
# Macro for copying vectors to RAM if necessary.
#if !defined(CYGSEM_HAL_USE_ROM_MONITOR)
 
.macro hal_vectors_init
 
# If we don~t play nice with a ROM monitor, copy the required
# vectors into the proper location.
la t0,0x80000000 # dest addr
la t1,utlb_vector # source addr
la t3,utlb_vector_end # end dest addr
1:
lw v0,0(t1) # get word
addi t1,t1,4
sw v0,0x0000(t0) # write word to utlb vec
sw v0,0x0080(t0) # and also to xtlb vector (64-bit)
addi t0,t0,4 # (no harm done)
bne t1,t3,1b
nop
 
la t0,0x80000000 # dest addr page base
la t1,other_vector # source addr
la t3,other_vector_end # end dest addr
1:
lw v0,0(t1) # get word
addi t1,t1,4
sw v0,0x0180(t0) # write word to other vector
addi t0,t0,4
bne t1,t3,1b
nop
 
// We are running uncached here anyhow, so no need to flush caches
 
.endm
 
#else
 
.macro hal_vectors_init
.endm
 
#endif
 
 
#ifndef CYGPKG_HAL_MIPS_MON_DEFINED
 
#if defined(CYG_HAL_STARTUP_ROM) || \
( defined(CYG_HAL_STARTUP_RAM) && \
!defined(CYGSEM_HAL_USE_ROM_MONITOR))
# If we are starting up from ROM, or we are starting in
# RAM and NOT using a ROM monitor, initialize the VSR table.
 
.macro hal_mon_init
 
hal_vectors_init
 
# Set default exception VSR for all vectors
ori a0,zero,64 // not CYGNUM_HAL_VSR_COUNT at all
la a1,__default_exception_vsr
la a2,hal_vsr_table
1: sw a1,0(a2)
addi a2,a2,4
addi a0,a0,-1
bne a0,zero,1b
nop
 
# Now set special VSRs
 
# FIXME: Should use proper definitions
 
la a0,hal_vsr_table
# Set interrupt VSR
la a1,__default_interrupt_vsr
sw a1,0*4(a0) // CYGNUM_HAL_VECTOR_INTERRUPT
# Add special handler on breakpoint vector to allow GDB and
# GCC to both use 'break' without conflicts.
la a1,__break_vsr_springboard
sw a1,9*4(a0) // CYGNUM_HAL_VECTOR_BREAKPOINT
 
# Set exception handler on special vectors
// but these are already set up above:
// la a1,__default_exception_vsr
// sw a1,32*4(a0) # debug
// sw a1,33*4(a0) # utlb
// sw a1,34*4(a0) # nmi
.endm
#elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR)
 
# Initialize the VSR table entries
# We only take control of the interrupt vector,
# the rest are left to the ROM for now...
 
.macro hal_mon_init
hal_vectors_init
# Set interrupt VSR
la a0,hal_vsr_table
la a1,__default_interrupt_vsr
sw a1,0*4(a0) // CYGNUM_HAL_VECTOR_INTERRUPT
.endm
 
#else
 
.macro hal_mon_init
hal_vectors_init
.endm
 
#endif
 
#define CYGPKG_HAL_MIPS_MON_DEFINED
#endif
 
#------------------------------------------------------------------------------
# Diagnostic macros
 
 
#------------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_VARIANT_INC
# end of variant.inc
/v2_0/include/hal_diag.h
0,0 → 1,89
#ifndef CYGONCE_HAL_HAL_DIAG_H
#define CYGONCE_HAL_HAL_DIAG_H
/*=============================================================================
//
// hal_diag.h
//
// HAL Support for Kernel Diagnostic Routines
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): hmt, nickg
// Contributors: nickg
// Date: 2001-05-25
// Purpose: HAL Support for Kernel Diagnostic Routines
// Description: Diagnostic routines for use during kernel development.
// Usage: #include <cyg/hal/hal_diag.h>
//
//####DESCRIPTIONEND####
//
//===========================================================================*/
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h>
 
#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
 
#include <cyg/hal/hal_if.h>
 
#define HAL_DIAG_INIT() hal_if_diag_init()
#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_)
#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_)
 
#else // everything by steam
 
/*---------------------------------------------------------------------------*/
/* functions implemented in hal_diag.c */
 
externC void hal_diag_init(void);
 
externC void hal_diag_write_char(char c);
 
externC void hal_diag_read_char(char *c);
 
/*---------------------------------------------------------------------------*/
 
#define HAL_DIAG_INIT() hal_diag_init()
#define HAL_DIAG_WRITE_CHAR(_c_) hal_diag_write_char(_c_)
#define HAL_DIAG_READ_CHAR(_c_) hal_diag_read_char(&_c_)
 
#endif // ! CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
 
/*---------------------------------------------------------------------------*/
/* end of hal_diag.h */
#endif /* CYGONCE_HAL_HAL_DIAG_H */
/v2_0/src/var_misc.c
0,0 → 1,224
//==========================================================================
//
// var_misc.c
//
// HAL CPU variant miscellaneous functions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): hmt, nickg
// Contributors: nickg, jlarmour
// Date: 2001-05-24
// Purpose: HAL miscellaneous functions
// Description: This file contains miscellaneous functions provided by the
// HAL.
//
//####DESCRIPTIONEND####
//
//========================================================================*/
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h> // Base types
#include <cyg/infra/cyg_trac.h> // tracing macros
#include <cyg/infra/cyg_ass.h> // assertion macros
 
#include <cyg/hal/hal_arch.h> // everything...
#include <cyg/hal/hal_cache.h> // HAL_ICACHE_ENABLE();
#include <cyg/hal/hal_if.h> // hal_if_init();
#include <cyg/hal/hal_intr.h> // HAL_INTERRUPT_UNMASK()
#include <cyg/hal/hal_arbiter.h> // hal_call_isr()
 
/*------------------------------------------------------------------------*/
/* Variant specific initialization routine. */
 
volatile CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
volatile CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_ISR_COUNT];
volatile CYG_ADDRESS hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT];
 
// ------------------------------------------------------------------------
// An ISR for decoding and calling the additional S_ISR external interrupt
// sources; this has to be an external routine because the S_ISR register
// is read-clear, and the interrupt sources are edge-triggered so they do
// not re-assert themselves - so we must address multiple sources per
// actual interrupt.
 
static cyg_uint32 _arbitration_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);
 
#ifndef CYGOPT_HAL_MIPS_UPD985XX_HARDWARE_BUGS_S2
static cyg_uint32 _arbitration_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data)
{
cyg_uint32 s_isr;
int bit, vecnum;
cyg_uint32 isr_ret = 0;
// decode interrupt source and for each active source call the ISR
s_isr = *S_ISR; // Read once only
s_isr &= *S_IMR; // Keep unmasked bits
 
for ( bit = 1, vecnum = CYGNUM_HAL_INTERRUPT_SYSCTL_LOW;
vecnum <= CYGNUM_HAL_INTERRUPT_SYSCTL_HI;
bit <<= 1, vecnum++ )
if ( bit & s_isr )
isr_ret |= hal_call_isr( vecnum );
return isr_ret & ~CYG_ISR_CALL_DSR; // Since we have no DSR.
}
#endif // NOT defined CYGOPT_HAL_MIPS_UPD985XX_HARDWARE_BUGS_S2
 
// ------------------------------------------------------------------------
 
void hal_variant_init(void)
{
int i;
for ( i = 0; i < CYGNUM_HAL_ISR_COUNT; i++ ) {
hal_interrupt_handlers [i] = (CYG_ADDRESS)&hal_default_isr;
hal_interrupt_data [i] = 0;
hal_interrupt_objects [i] = 0;
}
 
// Interrupt mask shadow variable initialization
hal_interrupt_sr_mask_shadow = 0;
 
// Enable the IBUS arbiter so that internal devices can work
// (Ie. USB and ether)
*S_GMR |= S_GMR_IAEN;
 
// Enable writing to the flash device per se (ie. no SEGV)
*RMMDR |= RMMDR_FLASH_WRITE_ENABLE;
 
// Mask off external interrupt sources and clear any pending.
*S_IMR = 0;
i = *S_ISR;
// Enable sysctl interrupt (in status reg) for those external sources.
// "True" enable is in the external control reg, handled generically
// by HAL_INTERRUPT_UNMASK for those vector numbers.
HAL_INTERRUPT_ATTACH( CYGNUM_HAL_INTERRUPT_SYSCTL, &_arbitration_isr, 0, 0);
HAL_INTERRUPT_UNMASK( CYGNUM_HAL_INTERRUPT_SYSCTL );
 
#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
hal_if_init();
#endif
 
// The uPD985xx only has an enable that works on both caches. So we
// only need to enable one of them for both to work.
HAL_DCACHE_ENABLE();
// HAL_ICACHE_ENABLE();
}
 
// ------------------------------------------------------------------------
//
// Routines to handle soft-masking and calling pent-up interrupts.
//
 
#ifdef CYGOPT_HAL_MIPS_UPD985XX_HARDWARE_BUGS_S2
 
// Assume all these are called with interrupts disabled globally
 
// We deal in vector numbers throughout: these contain "true" vector
// number shifts, whereas we have to shift hardware regs before use.
static int once_mask = 0; // Those unmasked ever
static int soft_mask = 0; // Those unmasked right now
static int pent_mask = 0; // Those pending right now
 
void cyg_hal_interrupt_mask( int vec )
{
CYG_ASSERT( CYGNUM_HAL_INTERRUPT_SYSCTL_LOW <= vec, "vec underflow" );
CYG_ASSERT( CYGNUM_HAL_INTERRUPT_SYSCTL_HI >= vec, "vec overflow" );
// We only manipulate the soft mask - NEVER the S_IMR.
soft_mask &=~ (1<<vec);
}
 
void cyg_hal_interrupt_unmask( int vec )
{
CYG_ASSERT( CYGNUM_HAL_INTERRUPT_SYSCTL_LOW <= vec, "vec underflow" );
CYG_ASSERT( CYGNUM_HAL_INTERRUPT_SYSCTL_HI >= vec, "vec overflow" );
// If this is the very first time of unmasking, unmask in the S_IMR &c
// also.
if ( 0 == ( (1<<vec) & once_mask ) ) {
once_mask |= (1<<vec);
*S_IMR |= (1 << ((vec - CYGNUM_HAL_INTERRUPT_SYSCTL_LOW)));
}
// We manipulate the soft mask and call any pent-up interrupt
soft_mask |= (1<<vec);
if ( (1<<vec) & pent_mask ) {
pent_mask &=~ (1<<vec); // "Acknowledge" the pent-up interrupt
hal_call_isr( vec ); // this does it all!
}
}
 
void cyg_hal_interrupt_acknowledge( int vec )
{
CYG_ASSERT( CYGNUM_HAL_INTERRUPT_SYSCTL_LOW <= vec ||
CYGNUM_HAL_INTERRUPT_SYSCTL == vec, "vec underflow" );
CYG_ASSERT( CYGNUM_HAL_INTERRUPT_SYSCTL_HI >= vec, "vec overflow" );
// (no harm done if this is CYGNUM_HAL_INTERRUPT_SYSCTL)
pent_mask &=~ (1<<vec); // "Acknowledge" the pent-up interrupt
}
 
 
static cyg_uint32 _arbitration_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data)
{
cyg_uint32 s_isr;
int vecnum;
cyg_uint32 isr_ret = 0;
// decode interrupt source and for each active source call the ISR
s_isr = *S_ISR; // Read once only
 
s_isr <<= CYGNUM_HAL_INTERRUPT_SYSCTL_LOW;
// Ignore the hardware mask; use the soft mask
 
// Any that are set in S_ISR and masked out in soft_mask become
// pending:
pent_mask |= (s_isr & ~soft_mask);
 
s_isr &= soft_mask; // Keep unmasked bits
 
for ( vecnum = CYGNUM_HAL_INTERRUPT_SYSCTL_LOW;
vecnum <= CYGNUM_HAL_INTERRUPT_SYSCTL_HI;
vecnum++ )
if ( (1<<vecnum) & s_isr )
isr_ret |= hal_call_isr( vecnum );
return isr_ret & ~CYG_ISR_CALL_DSR; // Since we have no DSR.
}
 
#endif // CYGOPT_HAL_MIPS_UPD985XX_HARDWARE_BUGS_S2
 
/*------------------------------------------------------------------------*/
/* End of var_misc.c */
/v2_0/src/variant.S
0,0 → 1,162
##=============================================================================
##
## variant.S
##
## MIPS uPD9875xx device code
##
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
##=============================================================================
#######DESCRIPTIONBEGIN####
##
## Author(s): hmt, nickg
## Contributors:nickg
## Date: 2001-05-25
## Purpose: NEC MIPS uPD985xx device code
## Description: Device specific code
##
##
##
##
######DESCRIPTIONEND####
##
##=============================================================================
 
#include <pkgconf/system.h>
#include <pkgconf/hal.h>
 
#ifdef CYGPKG_KERNEL
# include <pkgconf/kernel.h>
#endif
#include <cyg/hal/arch.inc>
 
#include <cyg/hal/var_arch.h>
 
##-----------------------------------------------------------------------------
## MMU setup.
## Some of this code is taken from the PMON sources, hence it does not fully
## conform to our normal coding conventions.
 
#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
 
// There is none. We can access all areas via kseg[01] so we are happy
// with no MMU setup.
 
#endif
##-----------------------------------------------------------------------------
## MEMC initialization.
## This also initializes the PCI bus and ISA bus bridge, so at the end of this
## we should have full access to all the memory and devices we need.
## This code is table driven, which is somewhat more compact that coding it all.
## Table entries consist of an address and a value to store in that address.
## A zero address terminates the table. Two special address values modify the
## behaviour:
## DELAY_LOOP loops for the number of iterations in the value field.
## WRITE16 treats the next 2 words as an address and value to be written
## with a 16 bit write cycle.
#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
#define DELAY_LOOP 1
#define WRITE16 2
 
FUNC_START(hal_memc_setup)
 
lar t0,hal_memc_setup_table
la t1,0xbfc00000
la t2,DELAY_LOOP
la t3,WRITE16
1:
lw a0,0(t0) # next table entry
lw a1,4(t0) # value to write
addiu t0,8 # go to next entry
beq a0,t2,2f # Check for delay
nop
beq a0,t3,3f # Check for 16 bit write
nop
beqz a0,9f # zero terminates loop
nop
sw a1,0(a0) # write it
lw zero,0(t1) # uncached read to flush write buffer
b 1b
nop
2:
lw zero,0(t1) # uncached read to flush write buffer
bnez a1,2b # count down by value in a1
addiu a1,-1 # decrement in delay slot
b 1b # go back to loop
nop
3:
lw a3,0(t0) # get next word
addiu t0,4 # skip it
sh a3,0(a1) # store halfword
lw zero,0(t1) # uncached read to flush write buffer
b 1b
nop
9:
jr ra
nop
 
FUNC_END(hal_memc_setup)
 
##-----------------------------------------------------------------------------
##-----------------------------------------------------------------------------
## The initialization table
hal_memc_setup_table:
.long DELAY_LOOP, 0x00010000 # Wait for HW to settle
 
.long RMMDR_ADR, RMMDR_28F640
.long RMATR_ADR, RMATR_28F640
 
.long DELAY_LOOP, 0x00010000 # Wait for HW to settle
.long SDMDR_ADR, SDMDR_INIT
.long SDTSR_ADR, SDTSR_INIT
.long SDPTR_ADR, SDPTR_INIT
.long SDRMR_ADR, SDRMR_INIT
.long DELAY_LOOP, 0x00010000 # Wait for HW to settle
.long 0, 0
 
 
#endif
##-----------------------------------------------------------------------------
## end of platform.S
/v2_0/src/hal_mips_upd985xx.ld
0,0 → 1,207
//===========================================================================
//
// MLT linker script for NEC MIPS uPD985xx
//
//===========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//===========================================================================
 
#include <pkgconf/system.h>
 
STARTUP(vectors.o)
ENTRY(reset_vector)
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-littlemips")
#ifdef EXTRAS
INPUT(extras.o)
#endif
#if (__GNUC__ >= 3)
GROUP(libtarget.a libgcc.a libsupc++.a)
#else
GROUP(libtarget.a libgcc.a)
#endif
 
#define ALIGN_LMA 8
#define FOLLOWING(_section_) AT ((LOADADDR (_section_) + SIZEOF (_section_) + ALIGN_LMA - 1) & ~ (ALIGN_LMA - 1))
#define LMA_EQ_VMA
#define FORCE_OUTPUT . = .
 
#define SECTIONS_BEGIN
 
#if defined(CYG_HAL_STARTUP_RAM)
 
/* this version for RAM startup */
#define SECTION_rom_vectors(_region_, _vma_, _lma_) \
.rom_vectors _vma_ : _lma_ \
{ KEEP (*(.utlb_vector)) \
. = ALIGN(0x80); KEEP(*(.other_vector)) \
/* debug and reset vector not used in RAM version */ \
KEEP (*(.reset_vector)) } \
> _region_
 
#elif defined(CYG_HAL_STARTUP_ROM)
 
/* this version for ROM startup */
#define SECTION_rom_vectors(_region_, _vma_, _lma_) \
.rom_vectors _vma_ : _lma_ \
{ KEEP (*(.reset_vector)) \
. = ALIGN(0x100); KEEP (*(.utlb_vector)) \
. = ALIGN(0x80); KEEP(*(.other_vector)) \
} > _region_
 
#elif defined(CYG_HAL_STARTUP_ROMRAM)
 
/* this version for ROMRAM startup. These are actually a */
/* combination of the ROM and RAM vector locations since the code */
/* starts off in ROM and transfers to RAM during startup. */
#define SECTION_rom_vectors(_region_, _vma_, _lma_) \
.rom_vectors _vma_ : _lma_ \
{ \
KEEP (*(.reset_vector)) \
. = ALIGN(0x100); \
KEEP (*(.utlb_vector)) \
. = ALIGN(0x80); \
KEEP(*(.other_vector)) \
. = ALIGN(0x800); \
} > _region_ =0
 
#endif /* ROMRAM startup version of ROM vectors */
 
#define SECTION_text(_region_, _vma_, _lma_) \
.text _vma_ : _lma_ \
{ _stext = ABSOLUTE(.); \
*(.text*) *(.gnu.warning) *(.gnu.linkonce*) *(.init) } \
> _region_ \
_etext = .; PROVIDE (etext = .);
 
#define SECTION_fini(_region_, _vma_, _lma_) \
.fini _vma_ : _lma_ \
{ FORCE_OUTPUT; *(.fini) } \
> _region_
 
#define SECTION_ctors(_region_, _vma_, _lma_) \
.ctors _vma_ : _lma_ \
{ \
__CTOR_LIST__ = ABSOLUTE (.); \
KEEP(*(.ctors)) \
KEEP(*(SORT(.ctors.*))) \
__CTOR_END__ = ABSOLUTE (.); \
} > _region_
 
#define SECTION_dtors(_region_, _vma_, _lma_) \
.dtors _vma_ : _lma_ \
{ \
__DTOR_LIST__ = ABSOLUTE (.); \
KEEP(*(SORT(.dtors.*))) \
KEEP(*(.dtors)) \
__DTOR_END__ = ABSOLUTE (.); \
} > _region_
 
#define SECTION_rodata(_region_, _vma_, _lma_) \
.rodata _vma_ : _lma_ \
{ FORCE_OUTPUT; *(.rodata*) } \
> _region_
 
#define SECTION_vsr_table(_region_, _vma_, _lma_) \
.vsr_table _vma_ : _lma_ \
{ FORCE_OUTPUT; *(.vsr_table) } \
> _region_
 
#define SECTION_rodata1(_region_, _vma_, _lma_) \
.rodata1 _vma_ : _lma_ \
{ FORCE_OUTPUT; *(.rodata1) } \
> _region_
 
#define SECTION_fixup(_region_, _vma_, _lma_) \
.fixup _vma_ : _lma_ \
{ FORCE_OUTPUT; *(.fixup) } \
> _region_
 
#define SECTION_rel__dyn(_region_, _vma_, _lma_) \
.rel.dyn _vma_ : _lma_ \
{ FORCE_OUTPUT; *(.rel.dyn) } \
> _region_
 
#define SECTION_gcc_except_table(_region_, _vma_, _lma_) \
.gcc_except_table _vma_ : _lma_ \
{ FORCE_OUTPUT; *(.gcc_except_table) } \
> _region_
 
#define SECTION_data(_region_, _vma_, _lma_) \
.data _vma_ : _lma_ \
{ __ram_data_start = ABSOLUTE (.); \
*(.data*) *(.data1) \
_GOT1_START_ = ABSOLUTE (.); *(.got1) _GOT1_END_ = ABSOLUTE (.); \
_GOT2_START_ = ABSOLUTE (.); *(.got2) _GOT2_END_ = ABSOLUTE (.); \
. = ALIGN (8); \
KEEP(*( SORT (.ecos.table.*))) ; \
. = ALIGN (8); \
_GOT_START = ABSOLUTE (.); _gp = ABSOLUTE (.); __global = _gp; _GLOBAL_OFFSET_TABLE_ = ABSOLUTE (.); _SDA_BASE_ = ABSOLUTE (.); \
*(.got.plt) *(.got) _GOT_END_ = ABSOLUTE (.); \
*(.dynamic) *(.lit8) *(.lit4) *(.sdata*) *(.sbss*) *(.eh_frame) } \
> _region_ \
__rom_data_start = LOADADDR (.data); \
__ram_data_end = .; PROVIDE (__ram_data_end = .); _edata = .; PROVIDE (edata = .);
#define SECTION_bss(_region_, _vma_, _lma_) \
.bss _vma_ : _lma_ \
{ __bss_start = ABSOLUTE (.); \
*(.scommon) *(.dynbss) *(.bss) *(COMMON) \
__bss_end = ABSOLUTE (.); } \
> _region_
 
#define SECTIONS_END . = ALIGN(4); _end = .; PROVIDE (end = .); \
.debug 0 : { *(.debug) } \
.line 0 : { *(.line) } \
.debug_srcinfo 0 : { *(.debug_srcinfo) } \
.debug_sfnames 0 : { *(.debug_sfnames) } \
.debug_aranges 0 : { *(.debug_aranges) } \
.debug_pubnames 0 : { *(.debug_pubnames) } \
.debug_info 0 : { *(.debug_info) } \
.debug_abbrev 0 : { *(.debug_abbrev) } \
.debug_line 0 : { *(.debug_line) } \
.debug_frame 0 : { *(.debug_frame) } \
.debug_str 0 : { *(.debug_str) } \
.debug_loc 0 : { *(.debug_loc) } \
.debug_macinfo 0 : { *(.debug_macinfo) } \
.debug_weaknames 0 : { *(.debug_weaknames) } \
.debug_funcnames 0 : { *(.debug_funcnames) } \
.debug_typenames 0 : { *(.debug_typenames) } \
.debug_varnames 0 : { *(.debug_varnames) } \
/DISCARD/ : { *(.debug_vector) }
 
#include CYGHWR_MEMORY_LAYOUT_LDI
 
hal_vsr_table = 0x80000400;
hal_interrupt_sr_mask_shadow_base = 0x80000500;
hal_virtual_vector_table = 0x80000600;
/v2_0/src/hal_diag.c
0,0 → 1,401
/*=============================================================================
//
// hal_diag.c
//
// HAL diagnostic output code
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): hmt, nickg
// Contributors: nickg
// Date: 2001-05-25
// Purpose: HAL diagnostic output
// Description: Implementations of HAL diagnostic output support.
//
//####DESCRIPTIONEND####
//
//===========================================================================*/
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h> // base types
#include <cyg/infra/cyg_trac.h> // tracing macros
#include <cyg/infra/cyg_ass.h> // assertion macros
 
#include <cyg/hal/hal_arch.h> // which includes var_arch => UART.
#include <cyg/hal/hal_diag.h>
#include <cyg/hal/hal_intr.h>
#include <cyg/hal/hal_io.h>
#include <cyg/hal/drv_api.h>
#include <cyg/hal/hal_if.h> // interface API
#include <cyg/hal/hal_misc.h> // Helper functions
 
/*---------------------------------------------------------------------------*/
//#define CYG_KERNEL_DIAG_GDB
 
#if defined(CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs)
 
#define CYG_KERNEL_DIAG_GDB
 
#endif
 
/*---------------------------------------------------------------------------*/
static inline
void hal_uart_setbaud( int baud )
{
// now set the baud rate
*UARTLCR |= UARTLCR_DLAB;
*UARTDLM = UARTDLM_VAL( baud );
*UARTDLL = UARTDLL_VAL( baud );
*UARTLCR &=~UARTLCR_DLAB;
}
 
void hal_uart_init(void)
{
// Ensure that we use the internal clock
*S_GMR &=~S_GMR_UCSEL;
 
*UARTFCR = UARTFCR_16550_MODE;
*UARTLCR = UARTLCR_8N1;
*UARTIER = UARTIER_ERBFI; // rx interrupts enabled for CTRL-C
 
hal_uart_setbaud( CYGHWR_HAL_MIPS_UPD985XX_DIAG_BAUD );
}
 
void hal_uart_write_char(char c)
{
while ( 0 == (UARTLSR_THRE & *UARTLSR) )
/* do nothing */ ;
 
*UARTTHR = (unsigned int)c;
 
// Ensure that this write does not provoke a spurious interrupt.
HAL_INTERRUPT_ACKNOWLEDGE( CYGHWR_HAL_GDB_PORT_VECTOR );
}
 
void hal_uart_read_char(char *c)
{
while ( 0 == (UARTLSR_DR & *UARTLSR) )
/* do nothing */ ;
 
*c = (char)*UARTRBR;
 
// Ensure that this read does not provoke a spurious interrupt.
HAL_INTERRUPT_ACKNOWLEDGE( CYGHWR_HAL_GDB_PORT_VECTOR );
}
 
int hal_uart_read_char_nonblock(char *c)
{
if ( 0 == (UARTLSR_DR & *UARTLSR) )
return 0;
 
*c = (char)*UARTRBR;
 
// Ensure that this read does not provoke a spurious interrupt.
HAL_INTERRUPT_ACKNOWLEDGE( CYGHWR_HAL_GDB_PORT_VECTOR );
 
return 1;
}
 
 
/*---------------------------------------------------------------------------*/
 
#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
 
#include <cyg/hal/hal_if.h>
 
// This is lame, duplicating all these wrappers with slightly different details.
// All this should be in hal_if.c
static void
cyg_hal_plf_serial_putc(void* __ch_data, cyg_uint8 c)
{
CYGARC_HAL_SAVE_GP();
hal_uart_write_char( (char)c );
CYGARC_HAL_RESTORE_GP();
}
 
static cyg_uint8
cyg_hal_plf_serial_getc(void* __ch_data)
{
cyg_uint8 result;
CYGARC_HAL_SAVE_GP();
hal_uart_read_char( (char *)&result );
CYGARC_HAL_RESTORE_GP();
return result;
}
 
static int
cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8 *pc)
{
return hal_uart_read_char_nonblock( (char *)pc );
}
 
static void
cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
cyg_uint32 __len)
{
CYGARC_HAL_SAVE_GP();
 
while(__len-- > 0)
cyg_hal_plf_serial_putc(__ch_data, *__buf++);
 
CYGARC_HAL_RESTORE_GP();
}
 
static void
cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
{
CYGARC_HAL_SAVE_GP();
 
while(__len-- > 0)
*__buf++ = cyg_hal_plf_serial_getc(__ch_data);
 
CYGARC_HAL_RESTORE_GP();
}
 
static int chan__msec_timeout = 0;
static int chan__irq_state = 0;
static int chan__baud_rate = CYGHWR_HAL_MIPS_UPD985XX_DIAG_BAUD;
 
cyg_bool
cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
{
int delay_count;
cyg_bool res;
CYGARC_HAL_SAVE_GP();
 
delay_count = chan__msec_timeout * 10; // delay in .1 ms steps
 
for(;;) {
res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
if (res || 0 >= delay_count--)
break;
CYGACC_CALL_IF_DELAY_US(100);
}
 
CYGARC_HAL_RESTORE_GP();
return res;
}
 
static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
int ret = -1;
va_list ap;
 
CYGARC_HAL_SAVE_GP();
va_start(ap, __func);
 
switch (__func) {
case __COMMCTL_GETBAUD:
ret = chan__baud_rate;
break;
case __COMMCTL_SETBAUD:
ret = 0;
chan__baud_rate = va_arg(ap, cyg_int32);
hal_uart_setbaud( chan__baud_rate );
break;
case __COMMCTL_IRQ_ENABLE:
ret = chan__irq_state;
chan__irq_state = 1;
HAL_INTERRUPT_UNMASK( CYGHWR_HAL_GDB_PORT_VECTOR );
break;
case __COMMCTL_IRQ_DISABLE:
ret = chan__irq_state;
chan__irq_state = 0;
HAL_INTERRUPT_MASK( CYGHWR_HAL_GDB_PORT_VECTOR );
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = CYGHWR_HAL_GDB_PORT_VECTOR;
break;
case __COMMCTL_SET_TIMEOUT:
ret = chan__msec_timeout;
chan__msec_timeout = va_arg(ap, cyg_uint32);
break;
default:
break;
}
va_end(ap);
CYGARC_HAL_RESTORE_GP();
return ret;
}
 
static int
cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
int ret = 0;
char c;
 
*__ctrlc = 0;
 
if ( hal_uart_read_char_nonblock( &c ) ) {
if ( cyg_hal_is_break( &c , 1 ) )
*__ctrlc = 1;
ret = CYG_ISR_HANDLED;
}
 
return ret;
}
 
static void
cyg_hal_plf_serial_init(void)
{
hal_virtual_comm_table_t* comm;
int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
 
// Init channels
CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, comm);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
// Restore original console
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
}
 
void
cyg_hal_plf_comms_init(void)
{
static int initialized = 0;
 
if (initialized)
return;
 
initialized = 1;
 
hal_uart_init();
cyg_hal_plf_serial_init();
}
 
#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
 
// ------------------------------------------------------------------------
 
void hal_diag_init(void)
{
hal_uart_init();
}
 
void hal_diag_read_char(char *c)
{
hal_uart_read_char(c);
}
 
extern cyg_bool cyg_hal_is_break(char *buf, int size);
extern void cyg_hal_user_break(CYG_ADDRWORD *regs);
 
void hal_diag_write_char(char c)
{
#ifdef CYG_KERNEL_DIAG_GDB
static char line[100];
static int pos = 0;
 
// No need to send CRs
if( c == '\r' ) return;
 
line[pos++] = c;
 
if( c == '\n' || pos == sizeof(line) )
{
 
// Disable interrupts. This prevents GDB trying to interrupt us
// while we are in the middle of sending a packet. The serial
// receive interrupt will be seen when we re-enable interrupts
// later.
CYG_INTERRUPT_STATE oldstate;
HAL_DISABLE_INTERRUPTS(oldstate);
while(1)
{
static char hex[] = "0123456789ABCDEF";
cyg_uint8 csum = 0;
int i;
char c1;
hal_uart_write_char('$');
hal_uart_write_char('O');
csum += 'O';
for( i = 0; i < pos; i++ )
{
char ch = line[i];
char h = hex[(ch>>4)&0xF];
char l = hex[ch&0xF];
hal_uart_write_char(h);
hal_uart_write_char(l);
csum += h;
csum += l;
}
hal_uart_write_char('#');
hal_uart_write_char(hex[(csum>>4)&0xF]);
hal_uart_write_char(hex[csum&0xF]);
 
hal_uart_read_char( &c1 );
 
if( c1 == '+' ) break;
 
if( cyg_hal_is_break( &c1 , 1 ) )
cyg_hal_user_break( NULL );
 
}
pos = 0;
 
// Disabling the interrupts for an extended period of time
// can provoke a spurious interrupt.
 
// Ensure that this write does not provoke a spurious interrupt.
HAL_INTERRUPT_ACKNOWLEDGE( CYGHWR_HAL_GDB_PORT_VECTOR );
 
// And re-enable interrupts
HAL_RESTORE_INTERRUPTS( oldstate );
}
#else
hal_uart_write_char(c);
#endif
}
 
/*---------------------------------------------------------------------------*/
/* End of hal_diag.c */
/v2_0/ChangeLog
0,0 → 1,370
2003-04-10 Nick Garnett <nickg@balti.calivar.com>
 
* src/hal_mips_upd985xx.ld:
Added libsupc++.a to GROUP() directive for GCC versions later than
3.0.
 
2002-04-02 Hugo Tyson <hmt@redhat.com>
2002-04-02 Anssi Pulkkinen <anssi.pulkkinen@ascom.com>
 
* src/var_misc.c (cyg_hal_interrupt_acknowledge): Remove the read
of the read-clear ISR register - it loses other pending interrupt
sources. Thanks to ASCOM for spotting this. It should have been
removed when the soft-copy and arbitration ISR were added, because
those changes mean the hardware register would already be cleared
down.
 
2002-01-22 Hugo Tyson <hmt@redhat.com>
 
* cdl/hal_mips_upd985xx.cdl: CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
must not be enabled because the way the arbitration ISR is
attached does not work with chained interrupts.
 
2001-10-30 Jonathan Larmour <jlarmour@redhat.com>
 
* cdl/hal_mips_upd985xx.cdl (CYGHWR_HAL_MIPS_UPD985XX_DIAG_BAUD):
This is the same as CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD
which RedBoot uses, so define it.
And also reimplement CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
as this is what makes it work.
 
2001-10-30 Hugo Tyson <hmt@redhat.com>
 
* cdl/hal_mips_upd985xx.cdl: Platform does *not* implement VV baud
operations, in fact the implements
CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT prevents it building.
 
2001-10-09 Hugo Tyson <hmt@redhat.com>
 
* cdl/hal_mips_upd985xx.cdl (..._MIPS_UPD985XX_HARDWARE_BUGS...):
New CDL options to control workarounds for System Controller bugs
S1 and S2. Shorthand for S1 requires the fixes elsewhere. That
for S2 selects alternate versions of the interrupt code.
 
* include/var_intr.h (HAL_INTERRUPT_ACKNOWLEDGE,...): Alternative
versions which call the new routines in src/var_misc.c to deal
with System Controller interrupts.
 
* src/var_misc.c (cyg_hal_interrupt_unmask,...): New routines to
manage the System Controller interrupts by software rather than
S_ISR/S_IMR. We never mask an interrupt once unmasked, but let
the interrupt happen, fielding it silently. When/if it becomes
unmasked, then we call the ISR &c.
 
2001-08-17 Jonathan Larmour <jlarmour@redhat.com>
 
* cdl/hal_mips_upd985xx.cdl: Platform implements VV baud operations.
 
2001-08-08 Hugo Tyson <hmt@redhat.com>
 
* include/variant.inc (hal_intc_decode): Do not decode the S_ISR
interrupts after all - they must be handled by arbitration. So
any S_ISR interrupt is reported as CYGNUM_HAL_INTERRUPT_SYSCTL -
Who are they? They are *all* number 6.
 
* src/var_misc.c (_arbitration_isr): New routine to arbitrate
between - and call all of - the interrupt sources that hang off
the system controller S_ISR register, because the S_ISR register
is read-clear, and the interrupt sources are edge-triggered so
they do not re-assert themselves - so we must address multiple
sources per actual interrupt.
(hal_variant_init): Install _arbitration_isr() on the SYSCTL
interrupt at startup.
 
* include/var_intr.h: Commented the change in interrupt usage -
the SYSCTL is occupied from time zero.
 
2001-08-01 Hugo Tyson <hmt@redhat.com>
 
* src/hal_mips_upd985xx.ld (hal_interrupt_sr_mask_shadow_base):
This must be placed statically so it is shared with RedBoot. And
it must be an array so that we can address it from afar.
 
* include/var_intr.h (HAL_DISABLE_INTERRUPTS): Implement this
macro and its fellows as well as the individual MASK/UNMASK
routines; these work together to keep the SR IM bits "true" to
what is intended by means of a shadow variable. Otherwise a race
condition in the vanilla HAL_DISABLE_INTERRUPTS() can discard an
interrupt mask change made by an ISR.
(hal_interrupt_sr_mask_shadow): declare this and define it to
entry zero of hal_interrupt_sr_mask_shadow_base[].
* src/var_misc.c (hal_interrupt_sr_mask_shadow): initialize this
new variable.
 
* cdl/hal_mips_upd985xx.cdl (CYGPKG_HAL_MIPS_UPD985XX): set
CYGINT_HAL_MIPS_INTERRUPT_RETURN_KEEP_SR_IM because we use bits
within the SR for interrupt control.
 
2001-07-25 Hugo Tyson <hmt@redhat.com>
 
* include/var_intr.h (CYGNUM_HAL_INTERRUPT_SOFT_ZERO)
(CYGNUM_HAL_INTERRUPT_SOFT_ONE): New interrupt numbers for
software interrupts 0 and 1. Also mask, unmask, and ack them
correctly; ack clears the R/W bit in the cause regsiter.
 
* include/variant.inc (hal_intc_decode) : Decode Software
interrupts into numbers 0 and 1 - all else are moved up a bit.
 
2001-07-20 Hugo Tyson <hmt@redhat.com>
 
* cdl/hal_mips_upd985xx.cdl: Demand that CYGPKG_LIBM includes
-fno-strict-aliasing in its CFLAGS_ADD to workaround a tools issue
with access to double via pointer-to-union casts.
 
2001-07-18 Hugo Tyson <hmt@redhat.com>
 
* include/var_arch.h (UARTLCR_8N1): Add more divers definitions of
UART control bits for implementing all the controls in the serial
device that nobody ever uses.
 
2001-07-17 Hugo Tyson <hmt@redhat.com>
 
* include/variant.inc: If RAM startup, don't blow away the
contents of cache - it might contain things that matter such as
debug connection state.
 
2001-07-09 Hugo Tyson <hmt@redhat.com>
 
* include/var_arch.h (SDMDR_INIT): Change one of the numbers to
match what's in the hardware when set up by customer code.
 
* include/variant.inc: Remove dependency on temporary development
config point CYGBLD_HAL_STARTUP_ROM_POST_OMIT_INITIALIZATION - the
initialization now works OK. So hal_memc_setup_table gets called.
 
* src/variant.S (hal_memc_setup_table): ROM startup now works, so
this code now gets called.
 
2001-07-06 Hugo Tyson <hmt@redhat.com>
 
* src/hal_diag.c (hal_uart_init): Ensure that we use the internal
baud clock because there is no external one.
 
* include/var_arch.h (UARTCLOCK): Clock is now 50MHz for "new"
boards, not 18.xMHz any more.
 
2001-07-03 Hugo Tyson <hmt@redhat.com>
 
* include/var_intr.h (HAL_INTERRUPT_[UN]MASK): Better manipulate
these with interrupts disabled for atomicity.
 
2001-07-02 Bart Veer <bartv@redhat.com>
 
* src/var_misc.c (hal_variant_init):
Move the GPIO0 manipulating (flash programming voltagE)
to the platform-init.
 
2001-06-27 Hugo Tyson <hmt@redhat.com>
 
This all fixes the serial interrupt problem of 2001-06-26.
* src/var_misc.c (hal_variant_init): Initialize the system
controller's ISR/IMR registers to mask and ack all external
interrupts and then enable the underlying interrupt source that
controls them all.
Also provide hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT]; &c for
use by system in vectors.S, and initialize them.
 
* src/hal_diag.c (cyg_hal_plf_serial_isr): Do not paranoically
acknowledge spurious interrupts. No need.
 
* include/variant.inc: Add complete redefinitions of interrupt
decoding to handle extended interrupt sources from the system
controller's ISR/IMR registers.
 
* include/var_intr.h: Add complete redefinitions of interrupt
management to handle extended interrupt sources from the system
controller's ISR/IMR registers.
 
* include/var_arch.h (S_ISR_ADR): Add ISR and IMR register
addresses for use by assembly files.
 
* include/plf_stub.h: Provide proto for cyg_hal_plf_comms_init()
to reduce warning.
 
2001-06-26 Hugo Tyson <hmt@redhat.com>
 
* cdl/hal_mips_upd985xx.cdl: Remove src/var_stub.c - functionality
is duplicated in the common HAL.
 
* include/plf_stub.h: Remove a load of unneccessary cruft which is
duplicated in the common HAL.
 
* src/var_stub.c: Removed.
 
2001-06-26 Hugo Tyson <hmt@redhat.com>
 
* src/var_misc.c (hal_variant_init): Unmask the UART interrupt in
the system controller - this is before the interrupt system in the
MIPS core which is used for dynamic control.
 
Also removed a load of duplicate hal_ctrlc_isr/HAL_CTRLC_ISR stuff
that fought with the common HAL,
 
Asynchronous CTRL-C still does not work. The interrupt asserts
forever. This is similar to System Controller known bug S2
"Interrupt Mask Restriction" from the NEC docs. Hence this code
in this file:
// *******************FIXME
// This causes an interrupt loop from the UART as soon as you do IO.
// *S_IMR |= S_ISR_UARTIS; // unmask UART
// *******************NB we mask it here so that the status is in control
// ******************* of the application code whatever RedBoot does.
*S_IMR &=~S_ISR_UARTIS;
// *******************FIXME
 
* src/hal_diag.c (cyg_hal_plf_serial_isr): This now contains all
it should need to.
(cyg_hal_plf_serial_control): Ditto, all cases now supported.
 
CYGHWR_HAL_GDB_PORT_VECTOR use now unconditional, other tidyups.
Bugfix to interrupt ack in nonblocking read, it was after the
return.
* cdl/hal_mips_upd985xx.cdl: We want to support ^Cm, so do not
implement CYGINT_HAL_DEBUG_GDB_CTRLC_UNSUPPORTED.
 
* include/var_intr.h (HAL_READ_INTR_REGS): New macro, handy for
debugging MIPS. Also remove duplicate hal_ctrlc_isr/HAL_CTRLC_ISR
stuff that fought with the common HAL, just leaving
CYGHWR_HAL_GDB_PORT_VECTOR defined.
 
* src/var_stub.c (hal_var_stub_init): Use symbols for entries in
vector tables and the like.
 
2001-06-22 Hugo Tyson <hmt@redhat.com>
 
* include/variant.inc: Use the proper target-agnostic config
include CYGBLD_HAL_PLATFORM_H, and do not initialize the memory
controller if you're told not to by the platform configuration
CYGBLD_HAL_STARTUP_ROM_POST_OMIT_INITIALIZATION.
 
2001-06-22 Hugo Tyson <hmt@redhat.com>
 
* src/var_misc.c (hal_variant_init): Enable write-access to the
flash area, and power-up the programming voltage via GPIO0, so
that flash drivers can work. Also enable the IBUS Arbiter so that
internal peripherals can work.
 
* src/variant.S (hal_memc_setup): Remove hal_memc_setup for RAM
start; the work is done elsewhere.
 
* include/variant.inc (hal_memc_init): Don't call hal_memc_setup
for RAM start.
2001-06-07 Hugo Tyson <hmt@redhat.com>
 
* include/variant.inc (hal_memc_init): Always do the memc call
even in RAM start, to enable...
 
* src/variant.S (hal_memc_setup): Enable write-access to the flash
area so that flash drivers can work.
 
2001-06-06 Hugo Tyson <hmt@redhat.com>
 
* include/var_cache.h (HAL_DCACHE_ENABLE_DEFINED): Add enough NOPs
after diddling the cache-enability that it works. Also give
correct (apparantly!) figures for cache size despite the
documentation arguing with itself.
 
* src/var_misc.c (hal_variant_init): Enable the caches during
startup.
 
* include/var_arch.h: Add a very few definitions for use by
assembler code here, and tidy up a little so that it can be used
from .S files. Specifically this is to let us init the RAM and
ROM access controllers from assembly.
 
* src/variant.S:
* include/variant.inc: Cut out some stuff we don't need that I had
blindly copied from another platform. Specifically we don't need
to set up the TLB *at all* because all its space are belong, um,
all memory, IO and devices are accessible through kseg1 and kseg0.
Added initial (untested) cut at setup of RAM/ROM controllers.
 
2001-06-06 Hugo Tyson <hmt@redhat.com>
 
* cdl/hal_mips_upd985xx.cdl: Add implements statement for
CYGINT_HAL_DEBUG_GDB_STUBS_BREAK, moved from the platform HAL.
 
2001-06-05 Hugo Tyson <hmt@redhat.com>
 
* include/variant.inc: It all works rather better now... fiddling
with vector setup and cache initialization.
 
2001-06-05 Hugo Tyson <hmt@redhat.com>
 
* cdl/hal_mips_upd985xx.cdl: to make GDB stubs work, implements
CYGINT_HAL_MIPS_STUB_REPRESENT_32BIT_AS_64BIT. Commented out
implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT_NOT_GUARANTEED.
 
* include/hal_diag.h: Now it works, properly be dependent on
CYGSEM_HAL_VIRTUAL_VECTOR_DIAG.
 
* include/plf_stub.h: Choose the right init routine dependent on
CYGSEM_HAL_VIRTUAL_VECTOR_DIAG.
 
* src/hal_diag.c (hal_uart_init): Remove diagnostics and delays
from initialization.
 
* src/var_stub.c (hal_var_stub_init): Remove bogus definition of
vsr_table and leave breakpoint VSR alone, the springboard will
handle it AOK.
 
2001-06-04 Hugo Tyson <hmt@redhat.com>
 
* cdl/hal_mips_upd985xx.cdl
* include/hal_diag.h
* include/plf_stub.h
* include/var_arch.h
* include/var_cache.h
* include/var_intr.h
* include/variant.inc
* src/hal_diag.c
* src/hal_mips_upd985xx.ld
* src/var_misc.c
* src/var_stub.c
* src/variant.S
New files; initial checkin.
 
RAM startup works; kernel tests run, loaded via SRecords,
including tm_basic, clockcnv, mutex3 and the exception tests.
Virtual vector calling works, but all apps do not work with a ROM
monitor, so they are all standalone. Diag printf et all all work.
Floating point emulation works.
 
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