OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/rtos/ecos-2.0/packages/hal/mips/vr4300
    from Rev 27 to Rev 174
    ↔ Reverse comparison
  •

Rev 27 → Rev 174

/v2_0/cdl/hal_mips_vr4300.cdl
0,0 → 1,100
# ====================================================================
#
# hal_mips_vr4300.cdl
#
# MIPS/VR4300 variant architectural HAL package configuration data
#
# ====================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
# ====================================================================
######DESCRIPTIONBEGIN####
#
# Author(s): nickg
# Contributors:
# Date: 1999-11-02
#
#####DESCRIPTIONEND####
#
# ====================================================================
 
cdl_package CYGPKG_HAL_MIPS_VR4300 {
display "VR4300 variant"
parent CYGPKG_HAL_MIPS
implements CYGINT_HAL_MIPS_VARIANT
hardware
include_dir cyg/hal
define_header hal_mips_vr4300.h
description "
The VR4300 variant HAL package provides generic support
for this processor architecture. It is also necessary to
select a specific target platform HAL package."
 
cdl_option CYGHWR_HAL_MIPS_64BIT {
display "Variant 64 bit architecture support"
calculated 1
}
 
cdl_option CYGHWR_HAL_MIPS_FPU {
display "Variant FPU support"
calculated 1
}
 
cdl_option CYGHWR_HAL_MIPS_FPU_64BIT {
display "Variant 64 bit FPU support"
calculated 1
}
 
define_proc {
puts $::cdl_header "#include <pkgconf/hal_mips.h>"
}
 
compile var_misc.c
 
make {
<PREFIX>/lib/target.ld: <PACKAGE>/src/mips_vr4300.ld
$(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(CFLAGS) -o $@ $<
@echo $@ ": \\" > $(notdir $@).deps
@tail +2 target.tmp >> $(notdir $@).deps
@echo >> $(notdir $@).deps
@rm target.tmp
}
 
cdl_option CYGBLD_LINKER_SCRIPT {
display "Linker script"
flavor data
no_define
calculated { "src/mips_vr4300.ld" }
}
 
}
/v2_0/include/var_cache.h
0,0 → 1,167
#ifndef CYGONCE_VAR_CACHE_H
#define CYGONCE_VAR_CACHE_H
 
//=============================================================================
//
// var_cache.h
//
// HAL cache control API
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors: nickg
// Date: 1998-02-17
// Purpose: Cache control API
// Description: The macros defined here provide the HAL APIs for handling
// cache control operations.
// Usage:
// #include <cyg/hal/var_cache.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>
 
#include <cyg/hal/plf_cache.h>
 
//-----------------------------------------------------------------------------
// Cache sizes.
 
// Data cache
#define HAL_DCACHE_SIZE (8*1024) // Size of data cache in bytes
#define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
#define HAL_DCACHE_WAYS 1 // Associativity of the cache
 
// Instruction cache
#define HAL_ICACHE_SIZE (16*1024) // Size of cache in bytes
#define HAL_ICACHE_LINE_SIZE 32 // Size of a cache line
#define HAL_ICACHE_WAYS 1 // Associativity of the cache
 
#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
 
//-----------------------------------------------------------------------------
// The VR4300 mostly uses the default MIPS cache controls defined in hal_cache.h
// Here we define the cache enable and disable macros. The only control we appear
// to have is the kseg0 cache state in config0. So all these macros at present
// manipulate this.
 
#ifndef HAL_DCACHE_ENABLE_DEFINED
#define HAL_DCACHE_ENABLE() \
CYG_MACRO_START \
asm volatile ( "mfc0 $2,$16\n" \
"nop; nop; nop\n" \
"la $3,0xFFFFFFF8\n" \
"and $2,$2,$3\n" \
"ori $2,$2,3\n" \
"mtc0 $2,$16\n" \
"nop; nop; nop;\n" \
: \
: \
: "$2", "$3" \
); \
CYG_MACRO_END
#define HAL_DCACHE_ENABLE_DEFINED
#endif
 
// Disable the data cache
#ifndef HAL_DCACHE_DISABLE_DEFINED
#define HAL_DCACHE_DISABLE() \
CYG_MACRO_START \
asm volatile ( "mfc0 $2,$16\n" \
"nop; nop; nop\n" \
"la $3,0xFFFFFFF8\n" \
"and $2,$2,$3\n" \
"ori $2,$2,2\n" \
"mtc0 $2,$16\n" \
"nop; nop; nop;\n" \
: \
: \
: "$2", "$3" \
); \
CYG_MACRO_END
#define HAL_DCACHE_DISABLE_DEFINED
#endif
 
#ifndef HAL_DCACHE_IS_ENABLED_DEFINED
#define HAL_DCACHE_IS_ENABLED(_state_) \
CYG_MACRO_START \
CYG_WORD32 _cstate_; \
asm volatile ( "mfc0 %0,$16\n" \
: "=r"(_cstate_) \
); \
if( (_cstate_ & 7) == 2 ) _state_ = 0; \
else _state_ = 1; \
CYG_MACRO_END
#define HAL_DCACHE_IS_ENABLED_DEFINED
#endif
 
#ifndef HAL_ICACHE_ENABLE_DEFINED
#define HAL_ICACHE_ENABLE() HAL_DCACHE_ENABLE()
#define HAL_ICACHE_ENABLE_DEFINED
#endif
 
// Disable the instruction cache
#ifndef HAL_ICACHE_DISABLE_DEFINED
#define HAL_ICACHE_DISABLE() HAL_DCACHE_DISABLE()
#define HAL_ICACHE_DISABLE_DEFINED
#endif
 
#ifndef HAL_ICACHE_IS_ENABLED_DEFINED
#define HAL_ICACHE_IS_ENABLED(_state_) HAL_DCACHE_IS_ENABLED(_state_)
#define HAL_ICACHE_IS_ENABLED_DEFINED
#endif
 
//-----------------------------------------------------------------------------
// The VR4300 has no cache locking facility so we define the guard macros
// to disable the definitions in hal_arch.h.
 
#define HAL_DCACHE_LOCK_DEFINED
#define HAL_DCACHE_UNLOCK_DEFINED
#define HAL_DCACHE_UNLOCK_ALL_DEFINED
 
#define HAL_ICACHE_LOCK_DEFINED
#define HAL_ICACHE_UNLOCK_DEFINED
 
//-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_VAR_CACHE_H
// End of var_cache.h
/v2_0/include/var_intr.h
0,0 → 1,98
#ifndef CYGONCE_HAL_VAR_INTR_H
#define CYGONCE_HAL_VAR_INTR_H
 
//==========================================================================
//
// var_intr.h
//
// VR4300 Interrupt and clock support
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors: nickg, jskov,
// gthomas, jlarmour
// Date: 1999-02-16
// Purpose: VR4300 Interrupt support
// Description: The macros defined here provide the HAL APIs for handling
// interrupts and the clock for variants of the NEC VR4300
// architecture.
//
// Usage:
// #include <cyg/hal/var_intr.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h>
 
#include <cyg/hal/plf_intr.h>
 
//--------------------------------------------------------------------------
// Interrupt controller access.
 
#if 0 //ndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
 
// Need info about VRC4372 to do this.
 
#define HAL_INTERRUPT_MASK( _vector_ )
 
#define HAL_INTERRUPT_UNMASK( _vector_ )
 
#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ )
 
#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ )
 
#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ )
 
#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
 
#endif
 
//--------------------------------------------------------------------------
// Clock control
 
// This is handled by the default code
 
//--------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_VAR_INTR_H
// End of var_intr.h
/v2_0/include/var_arch.h
0,0 → 1,71
#ifndef CYGONCE_HAL_VAR_ARCH_H
#define CYGONCE_HAL_VAR_ARCH_H
 
//==========================================================================
//
// var_arch.h
//
// Architecture specific abstractions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors: nickg
// Date: 1999-02-17
// Purpose: Define architecture abstractions
// Description: This file contains any extra or modified definitions for
// this variant of the architecture.
// Usage: #include <cyg/hal/var_arch.h>
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>
 
// -------------------------------------------------------------------------
// Although the VR4300 is really a 64 bit CPU, we have defined
// target_register_t elsewhere to be 32-bits because we only support
// 32-bit mode. Registers will still be sent to GDB as 64-bit, but that's
// not relevant for CYG_HAL_GDB_REG.
 
#define CYG_HAL_GDB_REG CYG_WORD64
 
//--------------------------------------------------------------------------
#endif // CYGONCE_HAL_VAR_ARCH_H
// End of var_arch.h
/v2_0/include/variant.inc
0,0 → 1,158
#ifndef CYGONCE_HAL_VARIANT_INC
#define CYGONCE_HAL_VARIANT_INC
##=============================================================================
##
## variant.inc
##
## VR4300 assembler header file
##
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
##=============================================================================
#######DESCRIPTIONBEGIN####
##
## Author(s): nickg
## Contributors: nickg
## Date: 1999-04-06
## Purpose: VR4300 definitions.
## Description: This file contains various definitions and macros that are
## useful for writing assembly code for the VR4300 CPU.
## Usage:
## #include <cyg/hal/variant.inc>
## ...
##
##
######DESCRIPTIONEND####
##
##=============================================================================
 
.set mips3
 
#include <cyg/hal/mips.inc>
 
#include <cyg/hal/platform.inc>
 
#include <pkgconf/hal.h>
 
#------------------------------------------------------------------------------
# Initial SR value
# Set the KX bit to enable 64bit accesses in kernel mode.
 
#define INITIAL_SR_VAR 0x00000080
 
#------------------------------------------------------------------------------
# Set up initial value for config register. Sets endian mode and
# disables the cache on kseg0.
 
#if defined(CYGPKG_HAL_MIPS_MSBFIRST)
# define INITIAL_CONFIG0 0x00008002
#elif defined(CYGPKG_HAL_MIPS_LSBFIRST)
# define INITIAL_CONFIG0 0x00000002
#else
# error MIPS endianness not set by configuration
#endif
 
#------------------------------------------------------------------------------
# Set up initial value for FPU FCR31 register. We set the FS bit to flush
# denormalized results to zero.
 
#ifndef CYG_HAL_MIPS_FCSR_INIT
#define CYG_HAL_MIPS_FCSR_INIT 0x01000000
#endif
 
#------------------------------------------------------------------------------
# Cache macros.
#ifndef CYGPKG_HAL_MIPS_CACHE_DEFINED
 
.macro hal_cache_init
 
#ifndef CYG_HAL_STARTUP_RAM
 
mfc0 v0,config0 # disable Kseg0 caching in config0 register
nop
nop
la v1,0xfffffff8
and v0,v0,v1
ori v0,v0,2
mtc0 v0,config0
nop
nop
nop
 
.set mips3 # Set ISA to MIPS 3 to allow cache insns
 
# Now ensure the caches are invalidated. The caches are NOT cleared or
# invalidated on non-power-up resets and may come up in a random state
# on power-up. Hence they may contain stale or randomly bogus data.
# Here we use the index-store-tag cache operation to clear all the cache
# tags and states to zero. This will render them all invalid on the
# VR4300.
 
# D-cache:
la t0,0x80000000
addi t1,t0,0x2000
1:
mtc0 zero,$28
mtc0 zero,$29
cache 0x09,0(t0)
addi t0,t0,0x10
sub v0,t1,t0
bgez v0,1b
nop # delay slot
 
# I-cache:
la a0,0x80000000
addi a1,a0,0x4000
1:
mtc0 zero,$28
mtc0 zero,$29
cache 0x08,0(a0)
addi a0,a0,0x20
sub v0,a1,a0
bgez v0,1b
nop # delay slot
 
.set mips0 # reset ISA to default
#endif
 
.endm
 
#define CYGPKG_HAL_MIPS_CACHE_DEFINED
 
#endif
 
#------------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_VARIANT_INC
# end of variant.inc
/v2_0/src/mips_vr4300.ld
0,0 → 1,214
//===========================================================================
//
// MLT linker script for MIPS VR4300
//
//===========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//===========================================================================
 
#include <pkgconf/system.h>
 
STARTUP(vectors.o)
ENTRY(reset_vector)
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-littlemips")
#ifdef EXTRAS
INPUT(extras.o)
#endif
#if (__GNUC__ >= 3)
GROUP(libtarget.a libgcc.a libsupc++.a)
#else
GROUP(libtarget.a libgcc.a)
#endif
 
#define ALIGN_LMA 8
#define FOLLOWING(_section_) AT ((LOADADDR (_section_) + SIZEOF (_section_) + ALIGN_LMA - 1) & ~ (ALIGN_LMA - 1))
#define LMA_EQ_VMA
#define FORCE_OUTPUT . = .
 
#define SECTIONS_BEGIN
 
#if defined(CYG_HAL_STARTUP_RAM)
 
/* this version for RAM startup */
#define SECTION_rom_vectors(_region_, _vma_, _lma_) \
.rom_vectors _vma_ : _lma_ \
{ KEEP (*(.utlb_vector)) \
. = ALIGN(0x80); KEEP(*(.other_vector)) \
/* debug and reset vector not used in RAM version */ \
KEEP (*(.reset_vector)) } \
> _region_
 
#elif defined(CYG_HAL_STARTUP_ROM)
 
/* this version for ROM startup */
#define SECTION_rom_vectors(_region_, _vma_, _lma_) \
.rom_vectors _vma_ : _lma_ \
{ \
KEEP (*(.reset_vector)) \
. = ALIGN(0x200); \
KEEP (*(.utlb_vector)) \
. = ALIGN(0x100); \
. = . + (0x80); \
KEEP(*(.other_vector)) \
} > _region_
 
#elif defined(CYG_HAL_STARTUP_ROMRAM)
 
/* this version for ROMRAM startup. These are actually a */
/* combination of the ROM and RAM vector locations since the code */
/* starts off in ROM and transfers to RAM during startup. */
#define SECTION_rom_vectors(_region_, _vma_, _lma_) \
.rom_vectors _vma_ : _lma_ \
{ \
KEEP (*(.reset_vector)) \
. = ALIGN(0x100); \
KEEP (*(.utlb_vector)) \
. = ALIGN(0x80); \
KEEP(*(.other_vector)) \
. = ALIGN(0x800); \
} > _region_ =0
 
#endif /* ROMRAM startup version of ROM vectors */
 
#define SECTION_text(_region_, _vma_, _lma_) \
.text _vma_ : _lma_ \
{ _stext = ABSOLUTE(.); \
*(.text*) *(.gnu.warning) *(.gnu.linkonce*) *(.init) } \
> _region_ \
_etext = .; PROVIDE (etext = .);
 
#define SECTION_fini(_region_, _vma_, _lma_) \
.fini _vma_ : _lma_ \
{ FORCE_OUTPUT; *(.fini) } \
> _region_
 
#define SECTION_ctors(_region_, _vma_, _lma_) \
.ctors _vma_ : _lma_ \
{ \
__CTOR_LIST__ = ABSOLUTE (.); \
KEEP(*(.ctors)) \
KEEP(*(SORT(.ctors.*))) \
__CTOR_END__ = ABSOLUTE (.); \
} > _region_
 
#define SECTION_dtors(_region_, _vma_, _lma_) \
.dtors _vma_ : _lma_ \
{ \
__DTOR_LIST__ = ABSOLUTE (.); \
KEEP(*(SORT(.dtors.*))) \
KEEP(*(.dtors)) \
__DTOR_END__ = ABSOLUTE (.); \
} > _region_
 
#define SECTION_rodata(_region_, _vma_, _lma_) \
.rodata _vma_ : _lma_ \
{ FORCE_OUTPUT; *(.rodata*) } \
> _region_
 
#define SECTION_vsr_table(_region_, _vma_, _lma_) \
.vsr_table _vma_ : _lma_ \
{ FORCE_OUTPUT; *(.vsr_table) } \
> _region_
 
#define SECTION_rodata1(_region_, _vma_, _lma_) \
.rodata1 _vma_ : _lma_ \
{ FORCE_OUTPUT; *(.rodata1) } \
> _region_
 
#define SECTION_fixup(_region_, _vma_, _lma_) \
.fixup _vma_ : _lma_ \
{ FORCE_OUTPUT; *(.fixup) } \
> _region_
 
#define SECTION_rel__dyn(_region_, _vma_, _lma_) \
.rel.dyn _vma_ : _lma_ \
{ FORCE_OUTPUT; *(.rel.dyn) } \
> _region_
 
#define SECTION_gcc_except_table(_region_, _vma_, _lma_) \
.gcc_except_table _vma_ : _lma_ \
{ FORCE_OUTPUT; *(.gcc_except_table) } \
> _region_
 
#define SECTION_data(_region_, _vma_, _lma_) \
.data _vma_ : _lma_ \
{ __ram_data_start = ABSOLUTE (.); \
*(.data*) *(.data1) \
*( .2ram.*) \
_GOT1_START_ = ABSOLUTE (.); *(.got1) _GOT1_END_ = ABSOLUTE (.); \
_GOT2_START_ = ABSOLUTE (.); *(.got2) _GOT2_END_ = ABSOLUTE (.); \
. = ALIGN (8); \
KEEP(*( SORT (.ecos.table.*))) ; \
. = ALIGN (8); \
_GOT_START = ABSOLUTE (.); _gp = ABSOLUTE (.); __global = _gp; _GLOBAL_OFFSET_TABLE_ = ABSOLUTE (.); _SDA_BASE_ = ABSOLUTE (.); \
*(.got.plt) *(.got) _GOT_END_ = ABSOLUTE (.); \
*(.dynamic) *(.lit8) *(.lit4) *(.sdata*) *(.sbss*) *(.eh_frame) } \
> _region_ \
__rom_data_start = LOADADDR (.data); \
__ram_data_end = .; PROVIDE (__ram_data_end = .); _edata = .; PROVIDE (edata = .);
#define SECTION_bss(_region_, _vma_, _lma_) \
.bss _vma_ : _lma_ \
{ __bss_start = ABSOLUTE (.); \
*(.scommon) *(.dynbss) *(.bss) *(COMMON) \
__bss_end = ABSOLUTE (.); } \
> _region_
 
#define SECTIONS_END . = ALIGN(4); _end = .; PROVIDE (end = .); \
.debug 0 : { *(.debug) } \
.line 0 : { *(.line) } \
.debug_srcinfo 0 : { *(.debug_srcinfo) } \
.debug_sfnames 0 : { *(.debug_sfnames) } \
.debug_aranges 0 : { *(.debug_aranges) } \
.debug_pubnames 0 : { *(.debug_pubnames) } \
.debug_info 0 : { *(.debug_info) } \
.debug_abbrev 0 : { *(.debug_abbrev) } \
.debug_line 0 : { *(.debug_line) } \
.debug_frame 0 : { *(.debug_frame) } \
.debug_str 0 : { *(.debug_str) } \
.debug_loc 0 : { *(.debug_loc) } \
.debug_macinfo 0 : { *(.debug_macinfo) } \
.debug_weaknames 0 : { *(.debug_weaknames) } \
.debug_funcnames 0 : { *(.debug_funcnames) } \
.debug_typenames 0 : { *(.debug_typenames) } \
.debug_varnames 0 : { *(.debug_varnames) } \
/DISCARD/ : { *(.debug_vector) }
 
#include CYGHWR_MEMORY_LAYOUT_LDI
 
#ifndef CYGPKG_HAL_MIPS_SIM
hal_vsr_table = 0x80000400;
hal_virtual_vector_table = 0x80000600;
#endif
 
/v2_0/src/var_misc.c
0,0 → 1,75
//==========================================================================
//
// var_misc.c
//
// HAL CPU variant miscellaneous functions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors: nickg, jlarmour
// Date: 1999-01-21
// Purpose: HAL miscellaneous functions
// Description: This file contains miscellaneous functions provided by the
// HAL.
//
//####DESCRIPTIONEND####
//
//========================================================================*/
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h> // Base types
#include <cyg/infra/cyg_trac.h> // tracing macros
#include <cyg/infra/cyg_ass.h> // assertion macros
 
#include <cyg/hal/hal_cache.h>
 
/*------------------------------------------------------------------------*/
/* Variant specific initialization routine. */
 
void hal_variant_init(void)
{
// The VR4300 only has an enable that works on both caches. So we
// only need to enable one of them for both to work.
// HAL_DCACHE_ENABLE();
HAL_ICACHE_ENABLE();
}
 
/*------------------------------------------------------------------------*/
/* End of var_misc.c */
/v2_0/ChangeLog
0,0 → 1,307
2003-04-10 Nick Garnett <nickg@balti.calivar.com>
 
* src/mips_vr4300.ld:
Added libsupc++.a to GROUP() directive for GCC versions later than
3.0.
 
2001-12-05 Nick Garnett <nickg@redhat.com>
 
* include/variant.inc: Add ifdef around cache clearing code to
only do this in non-RAM-startup configurations. If this is done in
a RAM-startup configuration, it can play merry havoc with the
state of things like RedBoot's network stack.
We now assume, for RAM applications, that our loader has
initialized the cache.
 
2001-10-12 Nick Garnett <nickg@redhat.com>
 
* src/mips_vr4300.ld (SECTION_rom_vectors): Updated this section
to make ROM startup work.
Note: this still does not fix all ROM startup problems, since the
ROM is still too slow to execute code from at anything like a
relistic speed.
 
2001-10-01 Jonathan Larmour <jlarmour@redhat.com>
 
* cdl/hal_mips_vr4300.cdl: Define endianness in platform CDL instead.
 
2001-09-10 Nick Garnett <nickg@redhat.com>
 
* src/mips_vr4300.ld: Added .2ram sections to data section needed
for FLASH support.
 
2001-09-07 Nick Garnett <nickg@redhat.com>
 
* include/variant.inc: Added definition of INITIAL_SR_VAR.
 
* include/var_arch.h (CYG_HAL_GDB_REG): Returned GDB registers to
full 64bit width.
 
* cdl/hal_mips_vr4300.cdl: Added endianness configuration.
Currently the VRC4373 platform is big endian for historical
reasons, while the VRC4375 platform is little endian.
2000-09-01 Jonathan Larmour <jlarmour@redhat.com>
 
* include/var_arch.h (CYG_HAL_GDB_REG): vr4300 GDB stubs now use
32-bits internally to represent registers
 
2000-06-21 Nick Garnett <nickg@cygnus.co.uk>
 
* src/mips_vr4300.ld:
Switched to new table definition mechanism.
 
2000-02-23 Jonathan Larmour <jlarmour@redhat.co.uk>
 
* include/var_cache.h: Don't need to conditionalize on vr4300
 
2000-02-16 Jesper Skov <jskov@redhat.com>
 
* cdl/hal_mips_vr4300.cdl: removed fix me
 
2000-01-28 Gary Thomas <gthomas@cygnus.co.uk>
 
* src/mips_vr4300.ld: Add support for network package.
 
2000-01-14 Nick Garnett <nickg@cygnus.co.uk>
 
* include/pkgconf/hal_mips_vr4300.h:
Added define for CYGHWR_HAL_MIPS_64BIT so that all vr4300 targets
save and restore 64 bit register values.
 
* cdl/hal_mips_vr4300.cdl:
Added option for CYGHWR_HAL_MIPS_64BIT so that all vr4300 targets
save and restore 64 bit register values.
 
1999-12-21 Jonathan Larmour <jlarmour@cygnus.co.uk>
 
* cdl/hal_mips_vr4300.cdl: Some cosmetic layout changes and fixed typos
Ensure we "puts" to correct CDL header
 
1999-12-02 John Dallaway <jld@cygnus.co.uk>
 
* cdl/hal_mips_vr4300.cdl:
 
Use the <PACKAGE> token in custom rules.
 
1999-12-01 John Dallaway <jld@cygnus.co.uk>
 
* cdl/hal_mips_vr4300.cdl:
 
Use the <PREFIX> token in custom rules.
 
1999-11-04 John Dallaway <jld@cygnus.co.uk>
 
* cdl/hal_mips_vr4300.cdl:
 
Output custom rule dependency information to .deps files in
the current directory.
 
Dispense with the need to create a 'src' sub-directory.
 
1999-11-02 Jesper Skov <jskov@cygnus.co.uk>
 
* cdl/hal_mips_vr4300.cdl: Added.
 
1999-10-25 Nick Garnett <nickg@cygnus.co.uk>
 
* include/var_cache.h: The single nop added on 10-21 seems to
cause exceptions on the vrc4373 board but not on others. Extended
this to three nops, which seem to work on all boards.
 
1999-10-22 Nick Garnett <nickg@cygnus.co.uk>
 
* include/var_intr.h: Removed superfluous placeholder ifdef.
 
1999-10-21 Nick Garnett <nickg@cygnus.co.uk>
 
* include/var_cache.h: Added an extra nop after reading the
config0 register. In some boards we get an exception when reloading
it if we don't have this here. Something to do with coprocessor
hazards.
 
1999-10-06 Jonathan Larmour <jlarmour@cygnus.co.uk>
 
* src/PKGconf.mak: Don't create extras.o here any more
 
1999-10-05 Nick Garnett <nickg@cygnus.co.uk>
 
* src/PKGconf.mak: Switched link command for libextras over to big
endian.
 
* include/pkgconf/hal_mips_vr4300.h: Added definition of
CYGPKG_HAL_MIPS_MSBFIRST.
 
* include/variant.inc: Set BE bit in config0 register depending on
definitions of CYGPKG_HAL_MIPS_[L|M]SBFIRST.
 
1999-09-09 Nick Garnett <nickg@cygnus.co.uk>
 
* src/mips_vr4300.ld:
Extended size of .rom_vectors section to 0x800 bytes for ROMRAM
startup so that when it is copied down into RAM, the VSR and
vector tables are zeroed automatically.
 
* include/variant.inc:
Moved cache macros here so that code to initialize the caches is
variant specific.
 
1999-09-08 Jonathan Larmour <jlarmour@cygnus.co.uk>
 
* src/mips_vr4300.ld: Discard debug vector - it doesn't exist on the
vr4300
 
1999-08-05 Jonathan Larmour <jlarmour@cygnus.co.uk>
 
* include/variant.inc: VR4300 is a mips 3 processor, so always allow
mips3 instructions
 
1999-07-15 Jonathan Larmour <jlarmour@cygnus.co.uk>
 
* include/variant.inc: Rename CYG_HAL_MIPS_FSR_INIT to
CYG_HAL_MIPS_FCSR_INIT since that's closer to its documented name
 
1999-07-09 Jonathan Larmour <jlarmour@cygnus.co.uk>
 
* include/var_cache.h: Define HAL_ICACHE_IS_ENABLED() to be the same
as HAL_DCACHE_IS_ENABLED()
 
1999-06-25 Nick Garnett <nickg@cygnus.co.uk>
 
* include/variant.inc:
Added initializer for FPU FSR register.
 
1999-06-17 Nick Garnett <nickg@cygnus.co.uk>
 
* include/var_cache.h: Added defines to disable generic code for
cache lock support in hal_cache.h. The vr4300 does not have cache
locking.
 
1999-06-17 Jesper Skov <jskov@cygnus.co.uk>
 
* src/mips_vr4300.ld: Removed below workaround.
 
1999-06-16 Jesper Skov <jskov@cygnus.co.uk>
CR 100804 workaround
* src/mips_vr4300.ld: Suppress .mdebug in the final output.
 
1999-05-28 Nick Garnett <nickg@cygnus.co.uk>
 
* src/mips_vr4300.ld:
Removed references to CYG_HAL_STARTUP_STUBS
 
1999-05-27 Nick Garnett <nickg@cygnus.co.uk>
 
* include/var_cache.h (HAL_DCACHE_IS_ENABLED): Added an
implementation of this macro.
 
1999-05-21 Nick Garnett <nickg@cygnus.co.uk>
 
* src/var_misc.c (hal_variant_init): Added enables for caches.
 
* src/mips_vr4300.ld: Added definition of SECTION_rom_vectors()
for ROMRAM and STUBS startups.
 
* include/variant.inc: Added an initial value for config0.
 
* include/var_cache.h: Added enable and disable macros for data
and instruction caches.
 
1999-05-13 Nick Garnett <nickg@cygnus.co.uk>
 
Imported whole directory tree into main trunk of repository.
 
1999-05-11 Nick Garnett <nickg@cygnus.co.uk>
 
[VR4300 branch]
* include/imp_arch.h:
* include/imp_intr.h:
* include/imp_cache.h:
* include/impl.inc:
* src/imp_misc.c:
* include/var_arch.h:
* include/var_intr.h:
* include/var_cache.h:
* include/variant.inc:
* src/var_misc.c:
* src/PKGconf.mak:
"Imp" and "Impl" files renamed to "var" and "variant" equivalents.
 
* include/pkgconf/hal_vr4300.h
* include/pkgconf/hal_mips_vr4300.h
Config file hal_vr4300.h renamed to hal_mips_vr4300.h so that it
matches the name synthesized by pkgconf.tcl.
 
* src/mips_vr4300.ld:
Moved VSR table and vector table to 0x800XXXXX.
1999-05-11 Gary Thomas <gthomas@cygnus.co.uk>
 
[VR4300 branch]
* src/mips_vr4300.ld: Change CTOR sort order - fixes problems
with uItron initialization.
 
1999-04-29 Nick Garnett <nickg@cygnus.co.uk>
 
[VR4300 branch]
* src/mips_vr4300.ld: Added definitions of hal_vsr_table and
hal_virtual_vector_table. These are currently at 0x806XXXXX but
will be moved to 0x800XXXXX when we can make proper ROMs.
 
1999-04-27 John Dallaway <jld@cygnus.co.uk>
 
[VR4300 branch]
* src/PKGconf.mak: Force generation of little-endian extras.o
 
1999-04-23 Nick Garnett <nickg@cygnus.co.uk>
 
[VR4300 branch]
* include/pkgconf/hal_vr4300.h: Added some CPU characterization
definitions for the benefit of the generic mips HAL.
 
* include/imp_arch.h: Added this file. It contains configuration
and redefinitions for stuff in hal_arch.h.
 
1999-04-21 Nick Garnett <nickg@cygnus.co.uk>
 
[VR4300 branch]
* src/imp_misc.c: Added this file to contain
hal_implementation_init().
* src/PKGconf.mak (COMPILE): Added imp_misc.c.
 
 
//===========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//===========================================================================

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.