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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/rtos/ecos-2.0/packages/hal/mips/vrc437x/v2_0/include
    from Rev 27 to Rev 174
    ↔ Reverse comparison
  •

Rev 27 → Rev 174

/plf_z8530.h
0,0 → 1,118
#ifndef CYGONCE_HAL_PLF_Z8530_H
#define CYGONCE_HAL_PLF_Z8530_H
 
//=============================================================================
//
// plf_z8530.h
//
// Platform header for Z8530 support.
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors:nickg
// Date: 1999-05-21
// Purpose: Platform HAL Z8530 support.
// Usage: #include <cyg/hal/plf_z8530.h>
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
 
/*---------------------------------------------------------------------------*/
/* Zilog Z8530 access macros. */
 
#if defined(CYGPKG_HAL_MIPS_LSBFIRST)
# define DUART_BASE 0xc1000000
#elif defined(CYGPKG_HAL_MIPS_MSBFIRST)
# define DUART_BASE 0xc1000003
#else
#error MIPS endianness not defined by configuration
#endif
 
// Address offsets for DUART channels
#define DUART_A 4
#define DUART_B 0
 
/* Require Delay between Zilog chip (Z8530 and Z8536) register access */
 
//#define ZDEL 66 /* 66 Instructions for 66Mhz */
#define ZDEL 200 /* 200 Instructions for 133Mhz */
 
#define DELAY_ZACC\
{ register int N = ZDEL; while (--N > 0); }
 
 
#define HAL_DUART_READ_CR( _chan_, _reg_, _val_) \
CYG_MACRO_START \
if( (_reg_) != 0 ) \
{ \
DELAY_ZACC; \
HAL_WRITE_UINT8( DUART_BASE+(_chan_), _reg_); \
} \
DELAY_ZACC; \
HAL_READ_UINT8( DUART_BASE+(_chan_), _val_ ); \
CYG_MACRO_END
 
#define HAL_DUART_WRITE_CR( _chan_, _reg_, _val_ ) \
CYG_MACRO_START \
if( (_reg_) != 0 ) \
{ \
DELAY_ZACC; \
HAL_WRITE_UINT8( DUART_BASE+(_chan_), _reg_); \
} \
DELAY_ZACC; \
HAL_WRITE_UINT8( DUART_BASE+(_chan_), _val_ ); \
CYG_MACRO_END
 
#define HAL_DUART_WRITE_TR( _chan_, _val_ ) \
CYG_MACRO_START \
DELAY_ZACC; \
HAL_WRITE_UINT8( DUART_BASE+(_chan_)+8, _val_ ); \
CYG_MACRO_END
 
#define HAL_DUART_READ_RR( _chan_, _val_ ) \
CYG_MACRO_START \
DELAY_ZACC; \
HAL_READ_UINT8( DUART_BASE+(_chan_)+8, _val_ ); \
CYG_MACRO_END
 
//-----------------------------------------------------------------------------
#endif // CYGONCE_HAL_PLF_Z8530_H
// End of plf_z8530.h
/plf_intr.h
0,0 → 1,319
#ifndef CYGONCE_HAL_PLF_INTR_H
#define CYGONCE_HAL_PLF_INTR_H
 
//==========================================================================
//
// plf_intr.h
//
// VRC437X Interrupt and clock support
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors: nickg, jskov,
// gthomas, jlarmour
// Date: 1999-02-16
// Purpose: Define Interrupt support
// Description: The macros defined here provide the HAL APIs for handling
// interrupts and the clock for the VRC437X board.
//
// Usage:
// #include <cyg/hal/plf_intr.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h>
 
//--------------------------------------------------------------------------
// Interrupt controller stuff.
 
// The first 6 correspond to the interrupt lines in the status/cause regs
#define CYGNUM_HAL_INTERRUPT_VRC437X 0
#define CYGNUM_HAL_INTERRUPT_IPL0 1
#define CYGNUM_HAL_INTERRUPT_IPL1 2
#define CYGNUM_HAL_INTERRUPT_IPL2 3
#define CYGNUM_HAL_INTERRUPT_POWER 4
#define CYGNUM_HAL_INTERRUPT_COMPARE 5
// The next 32 correspond to the interrupt lines in the 4372 interrupt
// controller. These are decoded from the controller when an interrupt
// on any of the IPL[0:2] lines in signalled.
#define CYGNUM_HAL_INTERRUPT_REALTIME_A 6
#define CYGNUM_HAL_INTERRUPT_REALTIME_B 7
#define CYGNUM_HAL_INTERRUPT_DUART 8
#define CYGNUM_HAL_INTERRUPT_TIMER 9
#define CYGNUM_HAL_INTERRUPT_PARALLEL 10
#define CYGNUM_HAL_INTERRUPT_PCI_INTA 11
#define CYGNUM_HAL_INTERRUPT_PCI_INTB 12
#define CYGNUM_HAL_INTERRUPT_PCI_INTC 13
#define CYGNUM_HAL_INTERRUPT_PCI_INTD 14
#define CYGNUM_HAL_INTERRUPT_INT_9 15
#define CYGNUM_HAL_INTERRUPT_INT_10 16
#define CYGNUM_HAL_INTERRUPT_INT_11 17
#define CYGNUM_HAL_INTERRUPT_INT_12 18
#define CYGNUM_HAL_INTERRUPT_INT_13 19
#define CYGNUM_HAL_INTERRUPT_DMA_0 20
#define CYGNUM_HAL_INTERRUPT_DMA_1 21
#define CYGNUM_HAL_INTERRUPT_DMA_2 22
#define CYGNUM_HAL_INTERRUPT_DMA_3 23
#define CYGNUM_HAL_INTERRUPT_TICK_0 24
#define CYGNUM_HAL_INTERRUPT_TICK_1 25
#define CYGNUM_HAL_INTERRUPT_UNUSED_20 26
#define CYGNUM_HAL_INTERRUPT_UNUSED_21 27
#define CYGNUM_HAL_INTERRUPT_IO_TIMEOUT 28
#define CYGNUM_HAL_INTERRUPT_PCI_PERR 29
#define CYGNUM_HAL_INTERRUPT_PCI_SERR 30
#define CYGNUM_HAL_INTERRUPT_PCI_SIG_TA 31
#define CYGNUM_HAL_INTERRUPT_PCI_REC_TA 32
#define CYGNUM_HAL_INTERRUPT_PCI_SIG_MA 33
#define CYGNUM_HAL_INTERRUPT_PCI_ADD 34
#define CYGNUM_HAL_INTERRUPT_PCI_RET_ERR 35
#define CYGNUM_HAL_INTERRUPT_UNUSED_30 36
#define CYGNUM_HAL_INTERRUPT_UNUSED_31 37
 
// Min/Max ISR numbers and how many there are
#define CYGNUM_HAL_ISR_MIN 0
#define CYGNUM_HAL_ISR_MAX 37
#define CYGNUM_HAL_ISR_COUNT 38
 
// The vector used by the Real time clock. The default here is to use
// interrupt 5, which is connected to the counter/comparator registers
// in many MIPS variants.
 
#ifndef CYGNUM_HAL_INTERRUPT_RTC
#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_COMPARE
#endif
 
#define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
 
//--------------------------------------------------------------------------
// Vector translation.
// For chained interrupts we only have a single vector though which all
// are passed. For unchained interrupts we have a vector per interrupt.
// Vector 0 has a special catcher ISR for spurious interrupts from the VRC437X
// and vectors 1-3 are springboards, so we chain through vector 4.
 
#if defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN)
 
#define HAL_TRANSLATE_VECTOR(_vector_,_index_) \
{ \
if ((_vector_)==0) \
(_index_) = 0; \
else \
(_index_) = 4; \
}
#endif
 
//--------------------------------------------------------------------------
// controller access code
 
#define CYGHWR_HAL_MIPS_VRC4372_BASE 0xbc000000
#define CYGHWR_HAL_MIPS_VRC4372_INTC_POL (CYGHWR_HAL_MIPS_VRC4372_BASE+0x200)
#define CYGHWR_HAL_MIPS_VRC4372_INTC_TRIG (CYGHWR_HAL_MIPS_VRC4372_BASE+0x204)
#define CYGHWR_HAL_MIPS_VRC4372_INTC_PINS (CYGHWR_HAL_MIPS_VRC4372_BASE+0x208)
#define CYGHWR_HAL_MIPS_VRC4372_INTC_MASK0 (CYGHWR_HAL_MIPS_VRC4372_BASE+0x20c)
#define CYGHWR_HAL_MIPS_VRC4372_INTC_STAT0 (CYGHWR_HAL_MIPS_VRC4372_BASE+0x210)
#define CYGHWR_HAL_MIPS_VRC4372_INTC_MASK1 (CYGHWR_HAL_MIPS_VRC4372_BASE+0x214)
#define CYGHWR_HAL_MIPS_VRC4372_INTC_STAT1 (CYGHWR_HAL_MIPS_VRC4372_BASE+0x218)
#define CYGHWR_HAL_MIPS_VRC4372_INTC_MASK2 (CYGHWR_HAL_MIPS_VRC4372_BASE+0x21c)
#define CYGHWR_HAL_MIPS_VRC4372_INTC_STAT2 (CYGHWR_HAL_MIPS_VRC4372_BASE+0x220)
 
#define CYGHWR_HAL_MIPS_VRC4372_INTC_MASK_OFF 8
 
// Array which stores the configured priority levels for the configured
// interrupts.
externC volatile CYG_BYTE cyg_hal_interrupt_level[CYGNUM_HAL_ISR_COUNT];
 
#define HAL_INTERRUPT_MASK( _vector_ ) \
CYG_MACRO_START \
if( _vector_ <= CYGNUM_HAL_INTERRUPT_COMPARE ) \
{ \
asm volatile ( \
"mfc0 $3,$12\n" \
"la $2,0x00000400\n" \
"sllv $2,$2,%0\n" \
"nor $2,$2,$0\n" \
"and $3,$3,$2\n" \
"mtc0 $3,$12\n" \
"nop; nop; nop\n" \
: \
: "r"(_vector_) \
: "$2", "$3" \
); \
} \
else \
{ \
CYG_WORD32 _mask_; \
CYG_BYTE _shift_; \
HAL_IO_REGISTER _maskreg_ = CYGHWR_HAL_MIPS_VRC4372_INTC_MASK0 + \
cyg_hal_interrupt_level[_vector_] * \
CYGHWR_HAL_MIPS_VRC4372_INTC_MASK_OFF; \
HAL_READ_UINT32( _maskreg_, _mask_ ); \
_shift_ = _vector_-CYGNUM_HAL_INTERRUPT_REALTIME_A; \
_mask_ &= ~(1<<_shift_); \
HAL_WRITE_UINT32( _maskreg_, _mask_ ); \
} \
CYG_MACRO_END
 
#define HAL_INTERRUPT_UNMASK( _vector_ ) \
CYG_MACRO_START \
if( _vector_ <= CYGNUM_HAL_INTERRUPT_COMPARE ) \
{ \
asm volatile ( \
"mfc0 $3,$12\n" \
"la $2,0x00000400\n" \
"sllv $2,$2,%0\n" \
"or $3,$3,$2\n" \
"mtc0 $3,$12\n" \
"nop; nop; nop\n" \
: \
: "r"(_vector_) \
: "$2", "$3" \
); \
} \
else \
{ \
CYG_WORD32 _mask_; \
CYG_BYTE _shift_; \
HAL_IO_REGISTER _maskreg_ = CYGHWR_HAL_MIPS_VRC4372_INTC_MASK0 + \
cyg_hal_interrupt_level[_vector_] * \
CYGHWR_HAL_MIPS_VRC4372_INTC_MASK_OFF; \
HAL_READ_UINT32( _maskreg_, _mask_ ); \
_shift_ = _vector_-CYGNUM_HAL_INTERRUPT_REALTIME_A; \
_mask_ |= 1<<_shift_; \
HAL_WRITE_UINT32( _maskreg_, _mask_ ); \
} \
CYG_MACRO_END
 
#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
CYG_MACRO_START \
CYG_WORD32 _srvector_ = _vector_; \
if( _vector_ > CYGNUM_HAL_INTERRUPT_COMPARE ) \
{ \
CYG_WORD32 _stat_; \
CYG_BYTE _shift_; \
HAL_IO_REGISTER _statreg_ = CYGHWR_HAL_MIPS_VRC4372_INTC_STAT0 +\
cyg_hal_interrupt_level[_vector_] * \
CYGHWR_HAL_MIPS_VRC4372_INTC_MASK_OFF; \
HAL_READ_UINT32( _statreg_, _stat_ ); \
_shift_ = _vector_-CYGNUM_HAL_INTERRUPT_REALTIME_A; \
_stat_ &= ~(1<<_shift_); \
HAL_WRITE_UINT32( _statreg_, _stat_ ); \
_srvector_ = cyg_hal_interrupt_level[_vector_] + \
CYGNUM_HAL_INTERRUPT_IPL0; \
} \
asm volatile ( \
"mfc0 $3,$13\n" \
"la $2,0x00000400\n" \
"sllv $2,$2,%0\n" \
"nor $2,$2,$0\n" \
"and $3,$3,$2\n" \
"mtc0 $3,$13\n" \
"nop; nop; nop\n" \
: \
: "r"(_srvector_) \
: "$2", "$3" \
); \
CYG_MACRO_END
 
#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \
CYG_MACRO_START \
if( (_vector_ >= CYGNUM_HAL_INTERRUPT_REALTIME_A) && \
(_vector_ <= CYGNUM_HAL_INTERRUPT_INT_13)) \
{ \
CYG_WORD32 mask = 1<<(_vector_-CYGNUM_HAL_INTERRUPT_REALTIME_A); \
CYG_WORD32 pol; \
CYG_WORD32 trig; \
HAL_READ_UINT32( CYGHWR_HAL_MIPS_VRC4372_INTC_POL, pol ); \
HAL_READ_UINT32( CYGHWR_HAL_MIPS_VRC4372_INTC_TRIG, trig ); \
if( _level_ ) \
{ \
pol &= ~mask; \
if( _up_ ) trig |= mask; \
else trig &= ~mask; \
} \
else \
{ \
pol |= mask; \
if( !(_up_) ) trig |= mask; \
else trig &= ~mask; \
} \
HAL_WRITE_UINT32( CYGHWR_HAL_MIPS_VRC4372_INTC_POL, pol ); \
HAL_WRITE_UINT32( CYGHWR_HAL_MIPS_VRC4372_INTC_TRIG, trig ); \
} \
CYG_MACRO_END
 
#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \
CYG_MACRO_START \
if( _vector_ > CYGNUM_HAL_INTERRUPT_COMPARE ) \
{ \
cyg_uint32 _ilevel_ = _level_; \
while( _ilevel_ > 2 ) _ilevel_ -= 2; \
cyg_hal_interrupt_level[_vector_] = _ilevel_; \
} \
CYG_MACRO_END
 
#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
 
//--------------------------------------------------------------------------
// Control-C support.
 
#if defined(CYGDBG_HAL_MIPS_DEBUG_GDB_CTRLC_SUPPORT)
 
# define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_DUART
 
externC cyg_uint32 hal_ctrlc_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);
 
#define HAL_CTRLC_ISR hal_ctrlc_isr
 
#endif
 
//----------------------------------------------------------------------------
// Reset.
 
#define HAL_PLATFORM_RESET() CYG_EMPTY_STATEMENT
 
#define HAL_PLATFORM_RESET_ENTRY 0xbfc00000
 
//--------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_PLF_INTR_H
// End of plf_intr.h
/plf_stub.h
0,0 → 1,87
#ifndef CYGONCE_HAL_PLF_STUB_H
#define CYGONCE_HAL_PLF_STUB_H
 
//=============================================================================
//
// plf_stub.h
//
// Platform header for GDB stub support.
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
// Contributors:jskov
// Date: 1999-02-12
// Purpose: Platform HAL stub support for MIPS/Vrc4373 boards.
// Usage: #include <cyg/hal/plf_stub.h>
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
 
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 
#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM
 
#include <cyg/hal/mips-stub.h> // architecture stub support
 
//----------------------------------------------------------------------------
// Define serial stuff.
extern void cyg_hal_plf_comms_init( void );
extern cyg_uint8 cyg_hal_plf_serial_getc( void *chan );
extern void cyg_hal_plf_serial_putc( void *chan, cyg_uint8 c );
 
#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init()
#define HAL_STUB_PLATFORM_GET_CHAR() cyg_hal_plf_serial_getc(0)
#define HAL_STUB_PLATFORM_PUT_CHAR(c) cyg_hal_plf_serial_putc(0,(c))
#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) CYG_UNUSED_PARAM(int, (baud))
#define HAL_STUB_PLATFORM_INTERRUPTIBLE 0
#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT
 
//----------------------------------------------------------------------------
// Stub initializer.
 
extern void hal_plf_stub_init(void);
 
#define HAL_STUB_PLATFORM_INIT() hal_plf_stub_init();
 
#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
//-----------------------------------------------------------------------------
#endif // CYGONCE_HAL_PLF_STUB_H
// End of plf_stub.h
/plf_cache.h
0,0 → 1,73
#ifndef CYGONCE_PLF_CACHE_H
#define CYGONCE_PLF_CACHE_H
 
//=============================================================================
//
// plf_cache.h
//
// HAL cache control API
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors: nickg
// Date: 1998-02-17
// Purpose: Cache control API
// Description: The macros defined here provide the HAL APIs for handling
// cache control operations.
// Usage:
// #include <cyg/hal/plf_cache.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>
 
#include <cyg/hal/plf_cache.h>
 
//=============================================================================
 
// Nothing here at present.
 
//-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_PLF_CACHE_H
// End of plf_cache.h
 
/platform.inc
0,0 → 1,680
#ifndef CYGONCE_HAL_PLATFORM_INC
#define CYGONCE_HAL_PLATFORM_INC
##=============================================================================
##
## platform.inc
##
## DDB-VRC4373 board assembler header file
##
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
##=============================================================================
#######DESCRIPTIONBEGIN####
##
## Author(s): nickg
## Contributors: nickg
## Date: 1999-04-06
## Purpose: VRC4373 board definitions.
## Description: This file contains various definitions and macros that are
## useful for writing assembly code for the VRC4373 board.
## Usage:
## #include <cyg/hal/platform.inc>
## ...
##
##
######DESCRIPTIONEND####
##
##=============================================================================
 
#include <cyg/hal/mips.inc>
 
##-----------------------------------------------------------------------------
## VRC4372 registers
#define CYGHWR_HAL_MIPS_VRC4373_BASE 0xbc000000
#define CYGHWR_HAL_MIPS_VRC4373_INTC_POL (CYGHWR_HAL_MIPS_VRC4373_BASE+0x200)
#define CYGHWR_HAL_MIPS_VRC4373_INTC_TRIG (CYGHWR_HAL_MIPS_VRC4373_BASE+0x204)
#define CYGHWR_HAL_MIPS_VRC4373_INTC_PINS (CYGHWR_HAL_MIPS_VRC4373_BASE+0x208)
#define CYGHWR_HAL_MIPS_VRC4373_INTC_MASK0 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x20c)
#define CYGHWR_HAL_MIPS_VRC4373_INTC_STAT0 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x210)
#define CYGHWR_HAL_MIPS_VRC4373_INTC_MASK1 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x214)
#define CYGHWR_HAL_MIPS_VRC4373_INTC_STAT1 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x218)
#define CYGHWR_HAL_MIPS_VRC4373_INTC_MASK2 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x21c)
#define CYGHWR_HAL_MIPS_VRC4373_INTC_STAT2 (CYGHWR_HAL_MIPS_VRC4373_BASE+0x220)
##-----------------------------------------------------------------------------
## configure the architecture HAL to define the right things.
 
## ISR tables are defined in platform.S
#define CYG_HAL_MIPS_ISR_TABLES_DEFINED
 
## VSR table is at a fixed RAM address defined by the linker script
#define CYG_HAL_MIPS_VSR_TABLE_DEFINED
 
##-----------------------------------------------------------------------------
 
#if defined(CYGSEM_HAL_USE_ROM_MONITOR_PMON)
 
## Initial SR value for use with PMON:
## CP0 usable
## Vectors to RAM
## All hw ints disabled
#define INITIAL_SR_PLF 0x10000000
 
#elif defined(CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs)
 
## Initial SR value for use with GDB stubs:
## CP0 and CP1 usable
## FP registers are 64 bit
## Vectors to RAM
## All hw ints disabled
#define INITIAL_SR_PLF 0x34000000
#else
 
## Initial SR value for use standalone:
## CP0 usable
## Vectors to RAM
## All hw ints disabled
#define INITIAL_SR_PLF 0x10000000
 
#endif
 
#------------------------------------------------------------------------------
## Load Address and Relocate. This macro is used in code that may be
## linked to execute out of RAM but is actually executed from ROM. The
## code that initializes the memory controller and copies the ROM
## contents to RAM must work in this way, for example. This macro is used
## in place of an "la" macro instruction when loading code and data
## addresses. There are two versions of the macro here. The first
## assumes that we are executing in the ROM space at 0xbfc00000 and are
## linked to run in the RAM space at 0x80000000. It simply adds the
## difference between the two to the loaded address. The second is more
## code, but will execute correctly at either location since it
## calculates the difference at runtime. The second variant is enabled
## by default.
 
 
#ifdef CYG_HAL_STARTUP_ROMRAM
 
#if 0
.macro lar reg,addr
.set noat
la \reg,\addr
la $at,0x3fc00000
addu \reg,\reg,$at
.set at
.endm
#else
.macro lar reg,addr
.set noat
move $at,ra # save ra
la \reg,\addr # get address into register
la ra,x\@ # get linked address of label
subu \reg,\reg,ra # subtract it from value
bal x\@ # branch and link to label
nop # to get current actual address
x\@:
addu \reg,\reg,ra # add actual address
move ra,$at # restore ra
.set at
.endm
 
#endif
 
#define CYGPKG_HAL_MIPS_LAR_DEFINED
 
#endif
#------------------------------------------------------------------------------
# MMU macros.
# The MMU must be set up on this board before we can access any external devices,
# including the memory controller, so we have no RAM to work with yet.
# Since the setup code must work only in registers, we do not do a subroutine
# linkage here, instead the setup code knows to jump back here when finished.
#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
 
.macro hal_mmu_init
.extern hal_mmu_setup
lar k0,hal_mmu_setup
jr k0
nop
.global hal_mmu_setup_return
hal_mmu_setup_return:
.endm
 
#define CYGPKG_HAL_MIPS_MMU_DEFINED
 
#endif
 
#------------------------------------------------------------------------------
# MEMC macros.
#
#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
 
.macro hal_memc_init
.extern hal_memc_setup
lar k0,hal_memc_setup
jalr k0
nop
 
#if defined(CYG_HAL_STARTUP_ROMRAM)
# Having got the RAM working, we must now relocate the Entire
# ROM into it and then continue execution from RAM.
 
la t0,reset_vector # dest addr
lar t1,reset_vector # source addr
la t3,__ram_data_end # end dest addr
1:
lw v0,0(t1) # get word
sw v0,0(t0) # write word
addiu t1,t1,4
addiu t0,t0,4
bne t0,t3,1b
nop
 
la v0,2f # RAM address to go to
jr v0
nop
2:
# We are now executing out of RAM!
#endif
 
.endm
 
#define CYGPKG_HAL_MIPS_MEMC_DEFINED
 
#endif
 
#------------------------------------------------------------------------------
# Interrupt controller initialization.
 
# initialize all interrupts to disabled
.macro hal_intc_init
mfc0 v0,status
nop
la v1,0xFFFF00FF
and v0,v0,v1 # clear the IntMask bits
ori v0,v0,0x3800 # set 3 IPL bits
mtc0 v0,status
nop
nop
nop
# mask them all in the VRC4372 interrupt controller too,
# and write zeros to the status registers to clear any
# pending interrupts.
la v0,CYGHWR_HAL_MIPS_VRC4373_INTC_MASK0
sw zero,0(v0)
sw zero,4(v0)
sw zero,8(v0)
sw zero,12(v0)
sw zero,16(v0)
sw zero,20(v0)
.endm
 
#define CYGPKG_HAL_MIPS_INTC_INIT_DEFINED
 
#------------------------------------------------------------------------------
# Interrupt Translator.
# This translates an interrupt number into an ISR table offset. Vector 0
# contains a special ISR for dealing with spurious interrupts from the
# Vrc437x, and vectors 1-3 contain springboards, so we chain via vector 4.
# This macro translates interrupt 0 to vector 0 and all others to vector 4.
 
#ifndef CYGPKG_HAL_MIPS_INTC_TRANSLATE_DEFINED
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
.macro hal_intc_translate inum,vnum
beqz \inum,1f # jump if interrupt is zero
move v0,zero # set v0=0 in delay slot
addi v0,v0,4 # non zero vector, inc v0
1: move \vnum,v0 # store 0 or 4 in vnum
.endm
#define CYGPKG_HAL_MIPS_INTC_TRANSLATE_DEFINED
#endif
#endif
 
#------------------------------------------------------------------------------
# Monitor initialization.
#ifndef CYGPKG_HAL_MIPS_MON_DEFINED
 
 
.macro hal_mon_init
 
hal_mon_copy_trampoline
 
hal_mon_init_vsr_table
 
.endm
 
 
#if defined(CYGSEM_HAL_USE_ROM_MONITOR_PMON)
 
# Copy the other_vector trampoline code into the RAM
# area so we intercept all interrupts.
 
.macro hal_mon_copy_trampoline
la a0,other_vector
la a1,other_vector_end
la t0,0xa0000180
1:
lw v0,0(a0)
sw v0,0(t0)
addiu a0,a0,4
bne a0,a1,1b
addiu t0,t0,4
.endm
 
 
# plant a pointer to the breakpoint springboard into the
# correct vsr table slot.
 
.macro hal_mon_init_vsr_table
.extern hal_breakpoint_springboard
la v1,hal_vsr_table
 
# Plant the interrupt VSR
la v0,__default_interrupt_vsr
sw v0,(0*4)(v1)
 
# And the breakpoint VSR
la v0,hal_breakpoint_springboard
sw v0,(9*4)(v1)
 
# Temporarily also plant all the others, so all exceptions
# go to PMON.
sw v0,(4*4)(v1)
sw v0,(5*4)(v1)
sw v0,(6*4)(v1)
sw v0,(7*4)(v1)
sw v0,(8*4)(v1)
sw v0,(10*4)(v1)
sw v0,(11*4)(v1)
sw v0,(12*4)(v1)
sw v0,(13*4)(v1)
sw v0,(14*4)(v1)
sw v0,(15*4)(v1)
 
.endm
 
#elif defined(CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs)
 
# The stubs have a trampoline of their own installed which
# already goes through the VSR table.
 
.macro hal_mon_copy_trampoline
.endm
 
# plant a pointer to the interrupt VSR handler in the
# correct vsr table slot. Leave the rest for the monitor.
 
.macro hal_mon_init_vsr_table
la v0,__default_interrupt_vsr
la v1,hal_vsr_table
sw v0,(0*4)(v1)
 
# plant a pointer to our own bus error handler. See the
# comments in platform.S.
.extern hal_bus_error_vsr
la v0,hal_bus_error_vsr
sw v0,(7*4)(v1)
 
.endm
 
#else
# The other_vector trampoline is already installed as part of
# the executable image. However, the TLB exception is, in RAM
# in the analogous place to the reset vector in ROM. In a
# ROM or ROMRAM startup we need to copy it into place.
 
#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
.macro hal_mon_copy_trampoline
la a0,utlb_vector
la a1,utlb_vector_end
la t0,0xa0000000
1:
lw v0,0(a0)
sw v0,0(t0)
sw v0,0x80(t0)
addiu a0,a0,4
bne a0,a1,1b
addiu t0,t0,4
#if defined(CYG_HAL_STARTUP_ROM)
la a0,other_vector
la a1,other_vector_end
la t0,0xa0000180
1:
lw v0,0(a0)
sw v0,0(t0)
addiu a0,a0,4
bne a0,a1,1b
addiu t0,t0,4
#endif
.endm
#else
.macro hal_mon_copy_trampoline
.endm
#endif
 
# Fill the VSR table with the default VSRs.
# If we contain the stubs, the default VSR will pass
# exceptions on to the stubs.
 
.macro hal_mon_init_vsr_table
la v0,__default_exception_vsr
la v1,hal_vsr_table
 
sw v0,(1*4)(v1)
sw v0,(2*4)(v1)
sw v0,(3*4)(v1)
sw v0,(4*4)(v1)
sw v0,(5*4)(v1)
sw v0,(6*4)(v1)
# sw v0,(7*4)(v1) # Bus error
sw v0,(8*4)(v1)
sw v0,(9*4)(v1)
sw v0,(10*4)(v1)
sw v0,(11*4)(v1)
sw v0,(12*4)(v1)
sw v0,(13*4)(v1)
sw v0,(14*4)(v1)
sw v0,(15*4)(v1)
sw v0,(23*4)(v1)
sw v0,(24*4)(v1)
# sw v0,(32*4)(v1) # debug
sw v0,(33*4)(v1) # utlb
sw v0,(34*4)(v1) # nmi
 
la v0,__default_interrupt_vsr
sw v0,(0*4)(v1)
 
# plant a pointer to our own bus error handler. See the
# comments in platform.S.
.extern hal_bus_error_vsr
la v0,hal_bus_error_vsr
sw v0,(7*4)(v1)
 
.endm
 
#endif
 
 
#define CYGPKG_HAL_MIPS_MON_DEFINED
 
#endif
 
#------------------------------------------------------------------------------
# Diagnostic macros
 
 
#ifndef CYGPKG_HAL_MIPS_DIAG_DEFINED
 
#if 0
 
# This code generates characters and hex values to a
# Grammar Engine PromICE AI interface.
 
#define AILOC 0xbfc70000
 
.macro hal_diag_init
la v0,AILOC
1:
lbu v1,3(v0)
nop ; nop ; nop
subu v1,0xCC
beqz v1,1b
nop
lbu v1,2(v0)
 
b 9f
nop
 
.global hal_diag_ai_write_char
hal_diag_ai_write_char:
 
.set noat
la v0,AILOC # v0 = AI location
1:
lbu v1,3(v0) # v1 = status register
nop ; nop ; nop
andi v1,v1,1 # v1 = TDA bit
bnez v1,1b # loop while non-zero
nop
sll a0,a0,1 # a0 = a0<<1
ori a0,a0,0x0201 # or in start and stop bits
li $at,10 # we have 10 bits to send
2:
andi v1,a0,1 # v1 = ls bit of char
add v1,v0,v1 # v1 = address of ZERO or ONE register
lbu zero,0(v1) # read it to send bit
la v1,100 # delay a bit to let PROMICE deal with it
3: bnez v1,3b # loop while non-zero
add v1,v1,-1 # decrement in delay slot
srl a0,a0,1 # a0 = a0>>1
subu $at,1 # decrement count
bnez $at,2b # loop while non-zero
nop
 
jr ra # all done, return
nop
 
.set at
 
.global hal_diag_ai_write_hex1
hal_diag_ai_write_hex1:
la v0,9
andi a0,a0,0xf
ble a0,v0,1f
nop
addi a0,a0,('A'-'9'-1)
1: addi a0,a0,'0'
b hal_diag_ai_write_char
nop
 
.global hal_diag_ai_write_hex2
hal_diag_ai_write_hex2:
move t0,ra # save ra
move t1,a0 # save arg
srl a0,a0,4 # ms nibble
bal hal_diag_ai_write_hex1
nop
move a0,t1 # retrieve a0
move ra,t0 # retrieve ra
b hal_diag_ai_write_hex1
nop
 
.global hal_diag_ai_write_hex4
hal_diag_ai_write_hex4:
move t2,ra # save ra
move t3,a0 # save arg
srl a0,a0,8 # ms byte
bal hal_diag_ai_write_hex2
nop
move a0,t3 # retrieve a0
move ra,t2 # retrieve ra
b hal_diag_ai_write_hex2
nop
 
 
.global hal_diag_ai_write_hex8
hal_diag_ai_write_hex8:
move t4,ra # save ra
move t5,a0 # save arg
srl a0,a0,16 # ms short
bal hal_diag_ai_write_hex4
nop
move a0,t5 # retrieve a0
move ra,t4 # retrieve ra
b hal_diag_ai_write_hex4
nop
 
9:
# Output a '!' to check that the interface is working
 
li a0,'!'
bal hal_diag_ai_write_char
nop
 
.endm
 
# Utility macro to emit a character
.macro hal_diag_writec char
.extern hal_diag_ai_write_char
la a0,\char
lar v0,hal_diag_ai_write_char
jalr v0
# bal hal_diag_ai_write_char
nop
.endm
 
#if 0
# This macro outputs a '+', the exception number as a
# character offset from 'A' and the exception address
# in hex.
.macro hal_diag_excpt_start
hal_diag_writec '+'
srl k0,k0,2
addi a0,k0,'A'
jal hal_diag_ai_write_char
nop
move a0,t6 # we know t6 contains the epc value
jal hal_diag_ai_write_hex8
nop
.endm
#else
.macro hal_diag_excpt_start
.endm
#endif
 
#if 0
# This macro outputs a '=' and the vector number as a
# character offset from 'A'.
.macro hal_diag_intr_start
.extern hal_diag_ai_write_char
hal_diag_writec '='
addi a0,s2,'A'
jal hal_diag_ai_write_char
nop
.endm
#else
.macro hal_diag_intr_start
.endm
#endif
 
#if 0
.macro hal_diag_restore
hal_diag_writec '^'
lw a0,mipsreg_pc(sp)
lar k0,hal_diag_ai_write_hex8
jalr k0
.endm
#else
.macro hal_diag_restore
.endm
#endif
 
#define CYGPKG_HAL_MIPS_DIAG_DEFINED
#elif 0
 
#define DELAY(n) \
li $at,n; \
9: bnez $at,9b; \
subu $at,1; \
 
/* Zilog Access Delay */
#define DELZ DELAY( (200) )
 
 
.macro hal_diag_init
la v0,0xc2000000
DELZ
lbu v1,8(v0)
andi v1,v1,0xfc
DELZ
sb v1,8(v0)
.endm
 
.macro hal_diag_excpt_start
.endm
 
.macro hal_diag_intr_start
la v0,0xc2000000
DELZ
lbu v1,8(v0)
xori v1,v1,0x01
DELZ
sb v1,8(v0)
.endm
 
.macro hal_diag_restore
la v0,0xc2000000
DELZ
lbu v1,8(v0)
xori v1,v1,0x01
DELZ
sb v1,8(v0)
 
# li a0,0x0310 # a0 = type = INTR,RAISE
# lw a1,mipsreg_sr(sp) # a1 = sr
# mfc0 a2,status
# jal cyg_instrument # call instrument function
# nop
 
.endm
 
#define CYGPKG_HAL_MIPS_DIAG_DEFINED
 
 
#endif
 
#endif
 
 
 
#------------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_PLATFORM_INC
# end of platform.inc
/hal_diag.h
0,0 → 1,92
#ifndef CYGONCE_HAL_HAL_DIAG_H
#define CYGONCE_HAL_HAL_DIAG_H
 
/*=============================================================================
//
// hal_diag.h
//
// HAL Support for Kernel Diagnostic Routines
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors: nickg
// Date: 1998-03-02
// Purpose: HAL Support for Kernel Diagnostic Routines
// Description: Diagnostic routines for use during kernel development.
// Usage: #include <cyg/hal/hal_diag.h>
//
//####DESCRIPTIONEND####
//
//===========================================================================*/
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h>
 
#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
 
#include <cyg/hal/hal_if.h>
 
#define HAL_DIAG_INIT() hal_if_diag_init()
#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_)
#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_)
 
#else // everything by steam
 
/*---------------------------------------------------------------------------*/
/* functions implemented in hal_diag.c */
 
externC void hal_diag_init(void);
 
externC void hal_diag_write_char(char c);
 
externC void hal_diag_read_char(char *c);
 
/*---------------------------------------------------------------------------*/
 
#define HAL_DIAG_INIT() hal_diag_init()
 
#define HAL_DIAG_WRITE_CHAR(_c_) hal_diag_write_char(_c_)
 
#define HAL_DIAG_READ_CHAR(_c_) hal_diag_read_char(&_c_)
 
#endif
 
/*---------------------------------------------------------------------------*/
/* end of hal_diag.h */
#endif /* CYGONCE_HAL_HAL_DIAG_H */
/plf_io.h
0,0 → 1,224
#ifndef CYGONCE_PLF_IO_H
#define CYGONCE_PLF_IO_H
 
//=============================================================================
//
// plf_io.h
//
// Platform specific IO support
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): hmt, jskov, nickg
// Contributors: hmt, jskov, nickg
// Date: 1999-08-09
// Purpose: VRC4373 PCI IO support macros
// Description:
// Usage: #include <cyg/hal/plf_io.h>
//
// Note: Based on information in
// "VRC4373 System Controller Data Sheet"
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/hal/hal_io.h> // IO macros
#include <cyg/hal/hal_intr.h> // Interrupt vectors
 
//-----------------------------------------------------------------------------
// PCI access registers
 
#define HAL_PCI_ADDRESS_WINDOW_1 0xAF000014
#define HAL_PCI_ADDRESS_WINDOW_2 0xAF000018
#define HAL_PCI_IO_WINDOW 0xAF000024
#define HAL_PCI_CONFIG_SPACE_DATA 0xAF000028
#define HAL_PCI_CONFIG_SPACE_ADDR 0xAF00002C
#define HAL_PCI_ENABLE_REG 0xAF000074
 
//-----------------------------------------------------------------------------
// Mappings for PCI memory and IO spaces
 
// This is where the PCI spaces are mapped in the CPU's (virtual)
// address space.
#define HAL_PCI_PHYSICAL_IO_BASE 0xA0000000
#define HAL_PCI_PHYSICAL_MEMORY_BASE 0xBC100000
 
//-----------------------------------------------------------------------------
 
// Initialize the PCI bus.
externC void cyg_hal_plf_pci_init(void);
#define HAL_PCI_INIT() cyg_hal_plf_pci_init()
 
// Compute address necessary to access PCI config space for the given
// bus and device.
#define HAL_PCI_CONFIG_ADDRESS( __bus, __devfn, __offset ) \
({ \
cyg_uint32 __addr; \
cyg_uint32 __dev = CYG_PCI_DEV_GET_DEV(__devfn); \
if (0 == __bus) { \
__addr = (1 << (__dev+16)); \
} else { \
/* We need better info about how to form type 1 addresses */ \
__addr = 0x800000000 | (__bus << 16) | (__dev << 11); \
} \
__addr |= CYG_PCI_DEV_GET_FN(__devfn) << 8; \
__addr |= (__offset)&~3; \
__addr; \
})
 
// The following function allows us to read locations in the PCI config
// space that we are not sure contains a valid device. Support in platform.S
// catches and fixes any bus errors caused.
externC CYG_WORD32 hal_pci_config_read(CYG_ADDRESS addr);
#define HAL_PCI_CONFIG_READ( __addr, __val ) __val = hal_pci_config_read(__addr)
 
// Read a value from the PCI configuration space of the appropriate
// size at an address composed from the bus, devfn and offset.
// We can only make 32 bit accesses to the PCI config data register, hence
// all the shifing and masking in these macros.
// Note that we may only use HAL_PCI_CONFIG_READ() here.
#define HAL_PCI_CFG_READ_UINT8( __bus, __devfn, __offset, __val ) \
CYG_MACRO_START \
CYG_WORD32 _val_; \
CYG_WORD32 _offset_ = __offset & 3; \
HAL_WRITE_UINT32(HAL_PCI_CONFIG_SPACE_ADDR, \
HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \
HAL_PCI_CONFIG_READ(HAL_PCI_CONFIG_SPACE_DATA, _val_); \
__val = (CYG_BYTE)((_val_>>(_offset_*8))&0xFF); \
CYG_MACRO_END
 
#define HAL_PCI_CFG_READ_UINT16( __bus, __devfn, __offset, __val ) \
CYG_MACRO_START \
CYG_WORD32 _val_; \
CYG_WORD32 _offset_ = __offset & 2; \
HAL_WRITE_UINT32(HAL_PCI_CONFIG_SPACE_ADDR, \
HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \
HAL_PCI_CONFIG_READ(HAL_PCI_CONFIG_SPACE_DATA, _val_); \
__val = (CYG_WORD16)((_val_>>(_offset_*8))&0xFFFF); \
CYG_MACRO_END
 
#define HAL_PCI_CFG_READ_UINT32( __bus, __devfn, __offset, __val ) \
CYG_MACRO_START \
CYG_WORD32 _val_; \
HAL_WRITE_UINT32(HAL_PCI_CONFIG_SPACE_ADDR, \
HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \
HAL_PCI_CONFIG_READ(HAL_PCI_CONFIG_SPACE_DATA, _val_); \
__val = (CYG_WORD32)_val_; \
CYG_MACRO_END
 
// Write a value to the PCI configuration space of the appropriate
// size at an address composed from the bus, devfn and offset.
// We can only make 32 bit accesses to the PCI config data register, hence
// all the shifing and masking in these macros.
// Note that we do not need to use HAL_PCI_CONFIG_READ() here since we
// should not be writing to config space locations that we do not already
// know are valid.
#define HAL_PCI_CFG_WRITE_UINT8( __bus, __devfn, __offset, __val ) \
CYG_MACRO_START \
CYG_WORD32 _val_; \
CYG_WORD32 _offset_ = __offset & 3; \
HAL_WRITE_UINT32(HAL_PCI_CONFIG_SPACE_ADDR, \
HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \
HAL_READ_UINT32(HAL_PCI_CONFIG_SPACE_DATA, _val_); \
_val_ &= ~(0xFF<<(_offset_*8)); \
_val_ |= (__val)<<(_offset_*8); \
HAL_WRITE_UINT32(HAL_PCI_CONFIG_SPACE_DATA, _val_); \
CYG_MACRO_END
 
#define HAL_PCI_CFG_WRITE_UINT16( __bus, __devfn, __offset, __val ) \
CYG_MACRO_START \
CYG_WORD32 _val_; \
CYG_WORD32 _offset_ = __offset & 2; \
HAL_WRITE_UINT32(HAL_PCI_CONFIG_SPACE_ADDR, \
HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \
HAL_READ_UINT32(HAL_PCI_CONFIG_SPACE_DATA, _val_); \
_val_ &= ~(0xFFFF<<(_offset_*8)); \
_val_ |= (__val)<<(_offset_*8); \
HAL_WRITE_UINT32(HAL_PCI_CONFIG_SPACE_DATA, _val_); \
CYG_MACRO_END
 
#define HAL_PCI_CFG_WRITE_UINT32( __bus, __devfn, __offset, __val ) \
CYG_MACRO_START \
HAL_WRITE_UINT32(HAL_PCI_CONFIG_SPACE_ADDR, \
HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \
HAL_WRITE_UINT32(HAL_PCI_CONFIG_SPACE_DATA, __val); \
CYG_MACRO_END
 
 
//-----------------------------------------------------------------------------
// Resources
 
// Map PCI device resources starting from these addresses in PCI space.
#define HAL_PCI_ALLOC_BASE_MEMORY 0
#define HAL_PCI_ALLOC_BASE_IO 0x0c000000
 
// Translate the PCI interrupt requested by the device (INTA#, INTB#,
// INTC# or INTD#) to the associated CPU interrupt (i.e., HAL vector).
// We don't actually know what the mappings are at present for this
// board. The following is therefore just a temporary guess until
// we can find out.
 
#define HAL_PCI_TRANSLATE_INTERRUPT( __bus, __devfn, __vec, __valid) \
CYG_MACRO_START \
cyg_uint8 __req; \
HAL_PCI_CFG_READ_UINT8(__bus, __devfn, CYG_PCI_CFG_INT_PIN, __req); \
if (0 != __req) { \
CYG_ADDRWORD __translation[4] = { \
CYGNUM_HAL_INTERRUPT_PCI_INTA, /* INTA# */ \
CYGNUM_HAL_INTERRUPT_PCI_INTB, /* INTB# */ \
CYGNUM_HAL_INTERRUPT_PCI_INTC, /* INTC# */ \
CYGNUM_HAL_INTERRUPT_PCI_INTD };/* INTD# */ \
\
__vec = __translation[(((__req-1)+CYG_PCI_DEV_GET_DEV(__devfn))&3)]; \
\
__valid = true; \
} else { \
/* Device will not generate interrupt requests. */ \
__valid = false; \
} \
CYG_MACRO_END
 
// Ignore all devices on not on bus 0 since those all seem to map to the
// Nile II controller itself.
#define HAL_PCI_IGNORE_DEVICE(__bus, __dev, __fn) \
((__bus) != 0)
 
//-----------------------------------------------------------------------------
// end of plf_io.h
#endif // CYGONCE_PLF_IO_H

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